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1/* Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
2 * Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
3 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
4 * Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
5 * Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
6 * Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
7 * Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
8 * Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
9 * <http://rt2x00.serialmonkey.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
a05b8c58 22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
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23 */
24
25/* Module: rt2800mmio
26 * Abstract: forward declarations for the rt2800mmio module.
27 */
28
29#ifndef RT2800MMIO_H
30#define RT2800MMIO_H
31
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32/*
33 * Queue register offset macros
34 */
35#define TX_QUEUE_REG_OFFSET 0x10
36#define TX_BASE_PTR(__x) (TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET))
37#define TX_MAX_CNT(__x) (TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET))
38#define TX_CTX_IDX(__x) (TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET))
39#define TX_DTX_IDX(__x) (TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET))
40
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41/*
42 * DMA descriptor defines.
43 */
44#define TXD_DESC_SIZE (4 * sizeof(__le32))
9732497d 45#define RXD_DESC_SIZE (4 * sizeof(__le32))
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46
47/*
48 * TX descriptor format for TX, PRIO and Beacon Ring.
49 */
50
51/*
52 * Word0
53 */
54#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
55
56/*
57 * Word1
58 */
59#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
60#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
61#define TXD_W1_BURST FIELD32(0x00008000)
62#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
63#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
64#define TXD_W1_DMA_DONE FIELD32(0x80000000)
65
66/*
67 * Word2
68 */
69#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
70
71/*
72 * Word3
73 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
74 * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
75 * 0:MGMT, 1:HCCA 2:EDCA
76 */
77#define TXD_W3_WIV FIELD32(0x01000000)
78#define TXD_W3_QSEL FIELD32(0x06000000)
79#define TXD_W3_TCO FIELD32(0x20000000)
80#define TXD_W3_UCO FIELD32(0x40000000)
81#define TXD_W3_ICO FIELD32(0x80000000)
82
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83/*
84 * RX descriptor format for RX Ring.
85 */
86
87/*
88 * Word0
89 */
90#define RXD_W0_SDP0 FIELD32(0xffffffff)
91
92/*
93 * Word1
94 */
95#define RXD_W1_SDL1 FIELD32(0x00003fff)
96#define RXD_W1_SDL0 FIELD32(0x3fff0000)
97#define RXD_W1_LS0 FIELD32(0x40000000)
98#define RXD_W1_DMA_DONE FIELD32(0x80000000)
99
100/*
101 * Word2
102 */
103#define RXD_W2_SDP1 FIELD32(0xffffffff)
104
105/*
106 * Word3
107 * AMSDU: RX with 802.3 header, not 802.11 header.
108 * DECRYPTED: This frame is being decrypted.
109 */
110#define RXD_W3_BA FIELD32(0x00000001)
111#define RXD_W3_DATA FIELD32(0x00000002)
112#define RXD_W3_NULLDATA FIELD32(0x00000004)
113#define RXD_W3_FRAG FIELD32(0x00000008)
114#define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
115#define RXD_W3_MULTICAST FIELD32(0x00000020)
116#define RXD_W3_BROADCAST FIELD32(0x00000040)
117#define RXD_W3_MY_BSS FIELD32(0x00000080)
118#define RXD_W3_CRC_ERROR FIELD32(0x00000100)
119#define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
120#define RXD_W3_AMSDU FIELD32(0x00000800)
121#define RXD_W3_HTC FIELD32(0x00001000)
122#define RXD_W3_RSSI FIELD32(0x00002000)
123#define RXD_W3_L2PAD FIELD32(0x00004000)
124#define RXD_W3_AMPDU FIELD32(0x00008000)
125#define RXD_W3_DECRYPTED FIELD32(0x00010000)
126#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
127#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
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128
129/* TX descriptor initialization */
130__le32 *rt2800mmio_get_txwi(struct queue_entry *entry);
131void rt2800mmio_write_tx_desc(struct queue_entry *entry,
132 struct txentry_desc *txdesc);
133
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134/* RX control handlers */
135void rt2800mmio_fill_rxdone(struct queue_entry *entry,
136 struct rxdone_entry_desc *rxdesc);
137
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138/* Interrupt functions */
139void rt2800mmio_txstatus_tasklet(unsigned long data);
140void rt2800mmio_pretbtt_tasklet(unsigned long data);
141void rt2800mmio_tbtt_tasklet(unsigned long data);
142void rt2800mmio_rxdone_tasklet(unsigned long data);
143void rt2800mmio_autowake_tasklet(unsigned long data);
144irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance);
145void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev,
146 enum dev_state state);
9732497d 147
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148/* Queue handlers */
149void rt2800mmio_start_queue(struct data_queue *queue);
150void rt2800mmio_kick_queue(struct data_queue *queue);
151void rt2800mmio_stop_queue(struct data_queue *queue);
152void rt2800mmio_queue_init(struct data_queue *queue);
153
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154/* Initialization functions */
155bool rt2800mmio_get_entry_state(struct queue_entry *entry);
156void rt2800mmio_clear_entry(struct queue_entry *entry);
157int rt2800mmio_init_queues(struct rt2x00_dev *rt2x00dev);
158int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev);
159
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160/* Device state switch handlers. */
161int rt2800mmio_enable_radio(struct rt2x00_dev *rt2x00dev);
162
e5553f08 163#endif /* RT2800MMIO_H */