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rt2x00: Properly reserve room for descriptors in skbs.
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
9c9a0d14
GW		 2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
34#include <linux/crc-ccitt.h>
35#include <linux/delay.h>
36#include <linux/etherdevice.h>
37#include <linux/init.h>
38#include <linux/kernel.h>
39#include <linux/module.h>
40#include <linux/pci.h>
41#include <linux/platform_device.h>
42#include <linux/eeprom_93cx6.h>
43
44#include "rt2x00.h"
45#include "rt2x00pci.h"
46#include "rt2x00soc.h"
7ef5cc92 47#include "rt2800lib.h"
b54f78a8 48#include "rt2800.h"
a9b3a9f7
ID		 49#include "rt2800pci.h"
50
a9b3a9f7
ID		 51/*
52 * Allow hardware encryption to be disabled.
53 */
54static int modparam_nohwcrypt = 1;
55module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
56MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57
a9b3a9f7
ID		 58static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
59{
60 unsigned int i;
61 u32 reg;
62
f18d4463
LC		 63 /*
64 * SOC devices don't support MCU requests.
65 */
66 if (rt2x00_is_soc(rt2x00dev))
67 return;
68
a9b3a9f7 69 for (i = 0; i < 200; i++) {
9ca21eb7 70 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 71
72 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
75 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
76 break;
77
78 udelay(REGISTER_BUSY_DELAY);
79 }
80
81 if (i == 200)
82 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
83
9ca21eb7
BZ		 84 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
85 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 86}
87
00e23ce2 88#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 89static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
90{
91 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
92
93 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
94}
95#else
96static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
97{
98}
00e23ce2 99#endif /* CONFIG_RT2800PCI_SOC */
a9b3a9f7
ID		 100
101#ifdef CONFIG_RT2800PCI_PCI
102static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
103{
104 struct rt2x00_dev *rt2x00dev = eeprom->data;
105 u32 reg;
106
9ca21eb7 107 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 108
109 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
110 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
111 eeprom->reg_data_clock =
112 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
113 eeprom->reg_chip_select =
114 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
115}
116
117static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
118{
119 struct rt2x00_dev *rt2x00dev = eeprom->data;
120 u32 reg = 0;
121
122 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
123 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
124 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
125 !!eeprom->reg_data_clock);
126 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
127 !!eeprom->reg_chip_select);
128
9ca21eb7 129 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 130}
131
132static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
133{
134 struct eeprom_93cx6 eeprom;
135 u32 reg;
136
9ca21eb7 137 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 138
139 eeprom.data = rt2x00dev;
140 eeprom.register_read = rt2800pci_eepromregister_read;
141 eeprom.register_write = rt2800pci_eepromregister_write;
142 eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
143 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
144 eeprom.reg_data_in = 0;
145 eeprom.reg_data_out = 0;
146 eeprom.reg_data_clock = 0;
147 eeprom.reg_chip_select = 0;
148
149 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
150 EEPROM_SIZE / sizeof(u16));
151}
152
a6598682
GW		 153static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
154{
30e84034 155 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 156}
157
30e84034 158static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 159{
30e84034 160 rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 161}
162#else
163static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
164{
165}
166
a6598682
GW		 167static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
168{
169 return 0;
170}
171
a9b3a9f7
ID		 172static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
173{
174}
175#endif /* CONFIG_RT2800PCI_PCI */
176
a9b3a9f7
ID		 177/*
178 * Firmware functions
179 */
180static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
181{
182 return FIRMWARE_RT2860;
183}
184
185static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
186 const u8 *data, const size_t len)
187{
188 u16 fw_crc;
189 u16 crc;
190
191 /*
192 * Only support 8kb firmware files.
193 */
194 if (len != 8192)
195 return FW_BAD_LENGTH;
196
197 /*
198 * The last 2 bytes in the firmware array are the crc checksum itself,
199 * this means that we should never pass those 2 bytes to the crc
200 * algorithm.
201 */
202 fw_crc = (data[len - 2] << 8 | data[len - 1]);
203
204 /*
205 * Use the crc ccitt algorithm.
206 * This will return the same value as the legacy driver which
207 * used bit ordering reversion on the both the firmware bytes
208 * before input input as well as on the final output.
209 * Obviously using crc ccitt directly is much more efficient.
210 */
211 crc = crc_ccitt(~0, data, len - 2);
212
213 /*
214 * There is a small difference between the crc-itu-t + bitrev and
215 * the crc-ccitt crc calculation. In the latter method the 2 bytes
216 * will be swapped, use swab16 to convert the crc to the correct
217 * value.
218 */
219 crc = swab16(crc);
220
221 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
222}
223
224static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
225 const u8 *data, const size_t len)
226{
227 unsigned int i;
228 u32 reg;
229
230 /*
231 * Wait for stable hardware.
232 */
233 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 234 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
a9b3a9f7
ID		 235 if (reg && reg != ~0)
236 break;
237 msleep(1);
238 }
239
240 if (i == REGISTER_BUSY_COUNT) {
241 ERROR(rt2x00dev, "Unstable hardware.\n");
242 return -EBUSY;
243 }
244
9ca21eb7
BZ		 245 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
246 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
a9b3a9f7
ID		 247
248 /*
249 * Disable DMA, will be reenabled later when enabling
250 * the radio.
251 */
9ca21eb7 252 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 253 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
254 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
255 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
256 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
257 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 258 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7
ID		 259
260 /*
261 * enable Host program ram write selection
262 */
263 reg = 0;
264 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9ca21eb7 265 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 266
267 /*
268 * Write firmware to device.
269 */
4f2732ce 270 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
a9b3a9f7
ID		 271 data, len);
272
9ca21eb7
BZ		 273 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
274 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7
ID		 275
276 /*
277 * Wait for device to stabilize.
278 */
279 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 280 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
a9b3a9f7
ID		 281 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
282 break;
283 msleep(1);
284 }
285
286 if (i == REGISTER_BUSY_COUNT) {
287 ERROR(rt2x00dev, "PBF system register not ready.\n");
288 return -EBUSY;
289 }
290
291 /*
292 * Disable interrupts
293 */
294 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
295
296 /*
297 * Initialize BBP R/W access agent
298 */
9ca21eb7
BZ		 299 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
300 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 301
302 return 0;
303}
304
305/*
306 * Initialization functions.
307 */
308static bool rt2800pci_get_entry_state(struct queue_entry *entry)
309{
310 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
311 u32 word;
312
313 if (entry->queue->qid == QID_RX) {
314 rt2x00_desc_read(entry_priv->desc, 1, &word);
315
316 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
317 } else {
318 rt2x00_desc_read(entry_priv->desc, 1, &word);
319
320 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
321 }
322}
323
324static void rt2800pci_clear_entry(struct queue_entry *entry)
325{
326 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
327 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
328 u32 word;
329
330 if (entry->queue->qid == QID_RX) {
331 rt2x00_desc_read(entry_priv->desc, 0, &word);
332 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
333 rt2x00_desc_write(entry_priv->desc, 0, word);
334
335 rt2x00_desc_read(entry_priv->desc, 1, &word);
336 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
337 rt2x00_desc_write(entry_priv->desc, 1, word);
338 } else {
339 rt2x00_desc_read(entry_priv->desc, 1, &word);
340 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
341 rt2x00_desc_write(entry_priv->desc, 1, word);
342 }
343}
344
345static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
346{
347 struct queue_entry_priv_pci *entry_priv;
348 u32 reg;
349
a9b3a9f7
ID		 350 /*
351 * Initialize registers.
352 */
353 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9ca21eb7
BZ		 354 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
355 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
356 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
357 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 358
359 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9ca21eb7
BZ		 360 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
361 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
362 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
363 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 364
365 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9ca21eb7
BZ		 366 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
367 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
368 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
369 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 370
371 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9ca21eb7
BZ		 372 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
373 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
374 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
375 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 376
377 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9ca21eb7
BZ		 378 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
379 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
380 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
381 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 382
383 /*
384 * Enable global DMA configuration
385 */
9ca21eb7 386 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 387 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
388 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
389 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 390 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 391
9ca21eb7 392 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 393
394 return 0;
395}
396
a9b3a9f7
ID		 397/*
398 * Device state switch handlers.
399 */
400static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
401 enum dev_state state)
402{
403 u32 reg;
404
9ca21eb7 405 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 406 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
407 (state == STATE_RADIO_RX_ON) ||
408 (state == STATE_RADIO_RX_ON_LINK));
9ca21eb7 409 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 410}
411
412static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
413 enum dev_state state)
414{
415 int mask = (state == STATE_RADIO_IRQ_ON);
416 u32 reg;
417
418 /*
419 * When interrupts are being enabled, the interrupt registers
420 * should clear the register to assure a clean state.
421 */
422 if (state == STATE_RADIO_IRQ_ON) {
9ca21eb7
BZ		 423 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
424 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 425 }
426
9ca21eb7 427 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9b3a9f7
ID		 428 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
429 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
430 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
431 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
432 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
433 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
434 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
435 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
436 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
437 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
438 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
439 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
440 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
441 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
442 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
443 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
444 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
445 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
9ca21eb7 446 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9b3a9f7
ID		 447}
448
a9b3a9f7
ID		 449static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
450{
451 u32 reg;
452 u16 word;
453
454 /*
455 * Initialize all registers.
456 */
67a4c1e2 457 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
a9b3a9f7 458 rt2800pci_init_queues(rt2x00dev) ||
fcf51541 459 rt2800_init_registers(rt2x00dev) ||
67a4c1e2 460 rt2800_wait_wpdma_ready(rt2x00dev) ||
fcf51541
BZ		 461 rt2800_init_bbp(rt2x00dev) ||
462 rt2800_init_rfcsr(rt2x00dev)))
a9b3a9f7
ID		 463 return -EIO;
464
465 /*
466 * Send signal to firmware during boot time.
467 */
3a9e5b0f 468 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
a9b3a9f7
ID		 469
470 /*
471 * Enable RX.
472 */
9ca21eb7 473 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 474 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
475 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9ca21eb7 476 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7 477
9ca21eb7 478 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 479 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
480 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
481 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
482 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 483 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 484
9ca21eb7 485 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 486 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
487 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9ca21eb7 488 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 489
490 /*
491 * Initialize LED control
492 */
493 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
3a9e5b0f 494 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
a9b3a9f7
ID		 495 word & 0xff, (word >> 8) & 0xff);
496
497 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
3a9e5b0f 498 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
a9b3a9f7
ID		 499 word & 0xff, (word >> 8) & 0xff);
500
501 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
3a9e5b0f 502 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
a9b3a9f7
ID		 503 word & 0xff, (word >> 8) & 0xff);
504
505 return 0;
506}
507
508static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
509{
510 u32 reg;
511
9ca21eb7 512 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 513 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
514 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
515 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
516 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
517 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 518 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 519
9ca21eb7
BZ		 520 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
521 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
522 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
a9b3a9f7 523
9ca21eb7 524 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
a9b3a9f7 525
9ca21eb7 526 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 527 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
528 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
529 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
530 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
531 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
532 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
533 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 534 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 535
9ca21eb7
BZ		 536 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
537 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 538
539 /* Wait for DMA, ignore error */
67a4c1e2 540 rt2800_wait_wpdma_ready(rt2x00dev);
a9b3a9f7
ID		 541}
542
543static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
544 enum dev_state state)
545{
546 /*
547 * Always put the device to sleep (even when we intend to wakeup!)
548 * if the device is booting and wasn't asleep it will return
549 * failure when attempting to wakeup.
550 */
3a9e5b0f 551 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
a9b3a9f7
ID		 552
553 if (state == STATE_AWAKE) {
3a9e5b0f 554 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
a9b3a9f7
ID		 555 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
556 }
557
558 return 0;
559}
560
561static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
562 enum dev_state state)
563{
564 int retval = 0;
565
566 switch (state) {
567 case STATE_RADIO_ON:
568 /*
569 * Before the radio can be enabled, the device first has
570 * to be woken up. After that it needs a bit of time
571 * to be fully awake and then the radio can be enabled.
572 */
573 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
574 msleep(1);
575 retval = rt2800pci_enable_radio(rt2x00dev);
576 break;
577 case STATE_RADIO_OFF:
578 /*
579 * After the radio has been disabled, the device should
580 * be put to sleep for powersaving.
581 */
582 rt2800pci_disable_radio(rt2x00dev);
583 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
584 break;
585 case STATE_RADIO_RX_ON:
586 case STATE_RADIO_RX_ON_LINK:
587 case STATE_RADIO_RX_OFF:
588 case STATE_RADIO_RX_OFF_LINK:
589 rt2800pci_toggle_rx(rt2x00dev, state);
590 break;
591 case STATE_RADIO_IRQ_ON:
592 case STATE_RADIO_IRQ_OFF:
593 rt2800pci_toggle_irq(rt2x00dev, state);
594 break;
595 case STATE_DEEP_SLEEP:
596 case STATE_SLEEP:
597 case STATE_STANDBY:
598 case STATE_AWAKE:
599 retval = rt2800pci_set_state(rt2x00dev, state);
600 break;
601 default:
602 retval = -ENOTSUPP;
603 break;
604 }
605
606 if (unlikely(retval))
607 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
608 state, retval);
609
610 return retval;
611}
612
613/*
614 * TX descriptor initialization
615 */
baaffe67
GW		 616static void rt2800pci_write_tx_datadesc(struct queue_entry* entry,
617 struct txentry_desc *txdesc)
a9b3a9f7 618{
0b8004aa 619 rt2800_write_txwi((__le32 *) entry->skb->data, txdesc);
745b1ae3
HS		 620}
621
622
623static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
624 struct sk_buff *skb,
625 struct txentry_desc *txdesc)
626{
627 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
85b7a8b3
GW		 628 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
629 __le32 *txd = entry_priv->desc;
745b1ae3
HS		 630 u32 word;
631
a9b3a9f7
ID		 632 /*
633 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
634 * must contains a TXWI structure + 802.11 header + padding + 802.11
635 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
636 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
637 * data. It means that LAST_SEC0 is always 0.
638 */
639
640 /*
641 * Initialize TX descriptor
642 */
643 rt2x00_desc_read(txd, 0, &word);
644 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
645 rt2x00_desc_write(txd, 0, word);
646
647 rt2x00_desc_read(txd, 1, &word);
648 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
649 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
650 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
651 rt2x00_set_field32(&word, TXD_W1_BURST,
652 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
85b7a8b3 653 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
a9b3a9f7
ID		 654 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
655 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
656 rt2x00_desc_write(txd, 1, word);
657
658 rt2x00_desc_read(txd, 2, &word);
659 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
85b7a8b3 660 skbdesc->skb_dma + TXWI_DESC_SIZE);
a9b3a9f7
ID		 661 rt2x00_desc_write(txd, 2, word);
662
663 rt2x00_desc_read(txd, 3, &word);
664 rt2x00_set_field32(&word, TXD_W3_WIV,
665 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
666 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
667 rt2x00_desc_write(txd, 3, word);
85b7a8b3
GW		 668
669 /*
670 * Register descriptor details in skb frame descriptor.
671 */
672 skbdesc->desc = txd;
673 skbdesc->desc_len = TXD_DESC_SIZE;
a9b3a9f7
ID		 674}
675
676/*
677 * TX data initialization
678 */
f224f4ef
GW		 679static void rt2800pci_write_beacon(struct queue_entry *entry,
680 struct txentry_desc *txdesc)
a9b3a9f7
ID		 681{
682 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
5c3b685c 683 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
a9b3a9f7
ID		 684 unsigned int beacon_base;
685 u32 reg;
686
687 /*
688 * Disable beaconing while we are reloading the beacon data,
689 * otherwise we might be sending out invalid data.
690 */
9ca21eb7 691 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
a9b3a9f7 692 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
9ca21eb7 693 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
a9b3a9f7 694
0b8004aa
GW		 695 /*
696 * Add space for the TXWI in front of the skb.
697 */
698 skb_push(entry->skb, TXWI_DESC_SIZE);
699 memset(entry->skb, 0, TXWI_DESC_SIZE);
700
5c3b685c
GW		 701 /*
702 * Register descriptor details in skb frame descriptor.
703 */
0b8004aa
GW		 704 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
705 skbdesc->desc = entry->skb->data;
5c3b685c
GW		 706 skbdesc->desc_len = TXWI_DESC_SIZE;
707
a9b3a9f7 708 /*
3b9f0ed7
GW		 709 * Add the TXWI for the beacon to the skb.
710 */
0b8004aa 711 rt2800_write_txwi((__le32 *)entry->skb->data, txdesc);
5c3b685c
GW		 712
713 /*
714 * Dump beacon to userspace through debugfs.
715 */
716 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
717
3b9f0ed7
GW		 718 /*
719 * Write entire beacon with TXWI to register.
a9b3a9f7
ID		 720 */
721 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
3b9f0ed7
GW		 722 rt2800_register_multiwrite(rt2x00dev, beacon_base,
723 entry->skb->data, entry->skb->len);
a9b3a9f7 724
d61cb266
GW		 725 /*
726 * Enable beaconing again.
727 */
728 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
729 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
730 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
731 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
732
a9b3a9f7
ID		 733 /*
734 * Clean up beacon skb.
735 */
736 dev_kfree_skb_any(entry->skb);
737 entry->skb = NULL;
738}
739
740static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
741 const enum data_queue_qid queue_idx)
742{
743 struct data_queue *queue;
744 unsigned int idx, qidx = 0;
a9b3a9f7
ID		 745
746 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
747 return;
748
749 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
750 idx = queue->index[Q_INDEX];
751
752 if (queue_idx == QID_MGMT)
753 qidx = 5;
754 else
755 qidx = queue_idx;
756
9ca21eb7 757 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
a9b3a9f7
ID		 758}
759
760static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
761 const enum data_queue_qid qid)
762{
763 u32 reg;
764
765 if (qid == QID_BEACON) {
9ca21eb7 766 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
a9b3a9f7
ID		 767 return;
768 }
769
9ca21eb7 770 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 771 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
772 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
773 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
774 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
9ca21eb7 775 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7
ID		 776}
777
778/*
779 * RX control handlers
780 */
781static void rt2800pci_fill_rxdone(struct queue_entry *entry,
782 struct rxdone_entry_desc *rxdesc)
783{
784 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 785 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
786 __le32 *rxd = entry_priv->desc;
2de64dd2
GW		 787 u32 word;
788
789 rt2x00_desc_read(rxd, 3, &word);
790
791 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
a9b3a9f7
ID		 792 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
793
78b8f3b0
GW		 794 /*
795 * Unfortunately we don't know the cipher type used during
796 * decryption. This prevents us from correct providing
797 * correct statistics through debugfs.
798 */
2de64dd2 799 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
a9b3a9f7 800
2de64dd2 801 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
a9b3a9f7
ID		 802 /*
803 * Hardware has stripped IV/EIV data from 802.11 frame during
804 * decryption. Unfortunately the descriptor doesn't contain
805 * any fields with the EIV/IV data either, so they can't
806 * be restored by rt2x00lib.
807 */
808 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
809
810 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
811 rxdesc->flags |= RX_FLAG_DECRYPTED;
812 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
813 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
814 }
815
2de64dd2 816 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
a9b3a9f7
ID		 817 rxdesc->dev_flags |= RXDONE_MY_BSS;
818
2de64dd2 819 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
a9b3a9f7 820 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7 821
a9b3a9f7 822 /*
2de64dd2 823 * Process the RXWI structure that is at the start of the buffer.
a9b3a9f7 824 */
2de64dd2 825 rt2800_process_rxwi(entry->skb, rxdesc);
a9b3a9f7
ID		 826
827 /*
828 * Set RX IDX in register to inform hardware that we have handled
829 * this entry and it is available for reuse again.
830 */
9ca21eb7 831 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
a9b3a9f7
ID		 832}
833
834/*
835 * Interrupt functions.
836 */
837static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
838{
839 struct data_queue *queue;
840 struct queue_entry *entry;
632dd959 841 __le32 *txwi;
a9b3a9f7
ID		 842 struct txdone_entry_desc txdesc;
843 u32 word;
844 u32 reg;
845 u32 old_reg;
632dd959 846 int wcid, ack, pid, tx_wcid, tx_ack, tx_pid;
a9b3a9f7
ID		 847 u16 mcs, real_mcs;
848
849 /*
850 * During each loop we will compare the freshly read
851 * TX_STA_FIFO register value with the value read from
852 * the previous loop. If the 2 values are equal then
853 * we should stop processing because the chance it
854 * quite big that the device has been unplugged and
855 * we risk going into an endless loop.
856 */
857 old_reg = 0;
858
859 while (1) {
9ca21eb7 860 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
a9b3a9f7
ID		 861 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
862 break;
863
864 if (old_reg == reg)
865 break;
866 old_reg = reg;
867
632dd959
AB		 868 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
869 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
870 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
871
a9b3a9f7
ID		 872 /*
873 * Skip this entry when it contains an invalid
874 * queue identication number.
875 */
632dd959 876 if (pid <= 0 || pid > QID_RX)
a9b3a9f7
ID		 877 continue;
878
632dd959 879 queue = rt2x00queue_get_queue(rt2x00dev, pid - 1);
a9b3a9f7
ID		 880 if (unlikely(!queue))
881 continue;
882
883 /*
632dd959
AB		 884 * Inside each queue, we process each entry in a chronological
885 * order. We first check that the queue is not empty.
a9b3a9f7 886 */
632dd959 887 if (rt2x00queue_empty(queue))
a9b3a9f7 888 continue;
632dd959 889 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
a9b3a9f7 890
632dd959
AB		 891 /* Check if we got a match by looking at WCID/ACK/PID
892 * fields */
0b8004aa 893 txwi = (__le32 *) entry->skb->data;
632dd959
AB		 894
895 rt2x00_desc_read(txwi, 1, &word);
896 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
897 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
898 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
899
900 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid))
901 WARNING(rt2x00dev, "invalid TX_STA_FIFO content\n");
a9b3a9f7
ID		 902
903 /*
904 * Obtain the status about this packet.
905 */
906 txdesc.flags = 0;
bf18723d
AB		 907 rt2x00_desc_read(txwi, 0, &word);
908 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
909 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
a9b3a9f7
ID		 910
911 /*
912 * Ralink has a retry mechanism using a global fallback
bf18723d
AB		 913 * table. We setup this fallback table to try the immediate
914 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
915 * always contains the MCS used for the last transmission, be
916 * it successful or not.
a9b3a9f7 917 */
bf18723d
AB		 918 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
919 /*
920 * Transmission succeeded. The number of retries is
921 * mcs - real_mcs
922 */
923 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
924 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
925 } else {
926 /*
927 * Transmission failed. The number of retries is
928 * always 7 in this case (for a total number of 8
929 * frames sent).
930 */
931 __set_bit(TXDONE_FAILURE, &txdesc.flags);
932 txdesc.retry = 7;
933 }
934
a9b3a9f7 935 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
bf18723d 936
a9b3a9f7 937
0b8004aa 938 rt2x00pci_txdone(entry, &txdesc);
a9b3a9f7
ID		 939 }
940}
941
4d66edc8
GW		 942static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
943{
944 struct ieee80211_conf conf = { .flags = 0 };
945 struct rt2x00lib_conf libconf = { .conf = &conf };
946
947 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
948}
949
a9b3a9f7
ID		 950static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
951{
952 struct rt2x00_dev *rt2x00dev = dev_instance;
953 u32 reg;
954
955 /* Read status and ACK all interrupts */
9ca21eb7
BZ		 956 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
957 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 958
959 if (!reg)
960 return IRQ_NONE;
961
962 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
963 return IRQ_HANDLED;
964
965 /*
966 * 1 - Rx ring done interrupt.
967 */
968 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
969 rt2x00pci_rxdone(rt2x00dev);
970
971 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
972 rt2800pci_txdone(rt2x00dev);
973
4d66edc8
GW		 974 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
975 rt2800pci_wakeup(rt2x00dev);
976
a9b3a9f7
ID		 977 return IRQ_HANDLED;
978}
979
980/*
981 * Device probe functions.
982 */
7ab71325
BZ		 983static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
984{
985 /*
986 * Read EEPROM into buffer
987 */
cea90e55 988 if (rt2x00_is_soc(rt2x00dev))
7ab71325 989 rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55
GW		 990 else if (rt2800pci_efuse_detect(rt2x00dev))
991 rt2800pci_read_eeprom_efuse(rt2x00dev);
992 else
993 rt2800pci_read_eeprom_pci(rt2x00dev);
7ab71325
BZ		 994
995 return rt2800_validate_eeprom(rt2x00dev);
996}
997
b0a1edab
BZ		 998static const struct rt2800_ops rt2800pci_rt2800_ops = {
999 .register_read = rt2x00pci_register_read,
31a4cf1f 1000 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
b0a1edab
BZ		 1001 .register_write = rt2x00pci_register_write,
1002 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1003
1004 .register_multiread = rt2x00pci_register_multiread,
1005 .register_multiwrite = rt2x00pci_register_multiwrite,
1006
1007 .regbusy_read = rt2x00pci_regbusy_read,
1008};
1009
a9b3a9f7
ID		 1010static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1011{
1012 int retval;
1013
b0a1edab
BZ		 1014 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1015
a9b3a9f7
ID		 1016 /*
1017 * Allocate eeprom data.
1018 */
1019 retval = rt2800pci_validate_eeprom(rt2x00dev);
1020 if (retval)
1021 return retval;
1022
38bd7b8a 1023 retval = rt2800_init_eeprom(rt2x00dev);
a9b3a9f7
ID		 1024 if (retval)
1025 return retval;
1026
1027 /*
1028 * Initialize hw specifications.
1029 */
4da2933f 1030 retval = rt2800_probe_hw_mode(rt2x00dev);
a9b3a9f7
ID		 1031 if (retval)
1032 return retval;
1033
1034 /*
1035 * This device has multiple filters for control frames
1036 * and has a separate filter for PS Poll frames.
1037 */
1038 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1039 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1040
1041 /*
1042 * This device requires firmware.
1043 */
cea90e55 1044 if (!rt2x00_is_soc(rt2x00dev))
a9b3a9f7
ID		 1045 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1046 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1047 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1048 if (!modparam_nohwcrypt)
1049 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1050
1051 /*
1052 * Set the rssi offset.
1053 */
1054 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1055
1056 return 0;
1057}
1058
a9b3a9f7
ID		 1059static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1060 .irq_handler = rt2800pci_interrupt,
1061 .probe_hw = rt2800pci_probe_hw,
1062 .get_firmware_name = rt2800pci_get_firmware_name,
1063 .check_firmware = rt2800pci_check_firmware,
1064 .load_firmware = rt2800pci_load_firmware,
1065 .initialize = rt2x00pci_initialize,
1066 .uninitialize = rt2x00pci_uninitialize,
1067 .get_entry_state = rt2800pci_get_entry_state,
1068 .clear_entry = rt2800pci_clear_entry,
1069 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1070 .rfkill_poll = rt2800_rfkill_poll,
1071 .link_stats = rt2800_link_stats,
1072 .reset_tuner = rt2800_reset_tuner,
1073 .link_tuner = rt2800_link_tuner,
a9b3a9f7 1074 .write_tx_desc = rt2800pci_write_tx_desc,
baaffe67
GW		 1075 .write_tx_data = rt2x00pci_write_tx_data,
1076 .write_tx_datadesc = rt2800pci_write_tx_datadesc,
a9b3a9f7
ID		 1077 .write_beacon = rt2800pci_write_beacon,
1078 .kick_tx_queue = rt2800pci_kick_tx_queue,
1079 .kill_tx_queue = rt2800pci_kill_tx_queue,
1080 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1081 .config_shared_key = rt2800_config_shared_key,
1082 .config_pairwise_key = rt2800_config_pairwise_key,
1083 .config_filter = rt2800_config_filter,
1084 .config_intf = rt2800_config_intf,
1085 .config_erp = rt2800_config_erp,
1086 .config_ant = rt2800_config_ant,
1087 .config = rt2800_config,
a9b3a9f7
ID		 1088};
1089
1090static const struct data_queue_desc rt2800pci_queue_rx = {
1091 .entry_num = RX_ENTRIES,
1092 .data_size = AGGREGATION_SIZE,
1093 .desc_size = RXD_DESC_SIZE,
1094 .priv_size = sizeof(struct queue_entry_priv_pci),
1095};
1096
1097static const struct data_queue_desc rt2800pci_queue_tx = {
1098 .entry_num = TX_ENTRIES,
1099 .data_size = AGGREGATION_SIZE,
1100 .desc_size = TXD_DESC_SIZE,
1101 .priv_size = sizeof(struct queue_entry_priv_pci),
1102};
1103
1104static const struct data_queue_desc rt2800pci_queue_bcn = {
1105 .entry_num = 8 * BEACON_ENTRIES,
1106 .data_size = 0, /* No DMA required for beacons */
1107 .desc_size = TXWI_DESC_SIZE,
1108 .priv_size = sizeof(struct queue_entry_priv_pci),
1109};
1110
1111static const struct rt2x00_ops rt2800pci_ops = {
04d0362e
GW		 1112 .name = KBUILD_MODNAME,
1113 .max_sta_intf = 1,
1114 .max_ap_intf = 8,
1115 .eeprom_size = EEPROM_SIZE,
1116 .rf_size = RF_SIZE,
1117 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1118 .extra_tx_headroom = TXWI_DESC_SIZE,
04d0362e
GW		 1119 .rx = &rt2800pci_queue_rx,
1120 .tx = &rt2800pci_queue_tx,
1121 .bcn = &rt2800pci_queue_bcn,
1122 .lib = &rt2800pci_rt2x00_ops,
1123 .hw = &rt2800_mac80211_ops,
a9b3a9f7 1124#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1125 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1126#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1127};
1128
1129/*
1130 * RT2800pci module information.
1131 */
d6e36ec1 1132#ifdef CONFIG_RT2800PCI_PCI
a3aa1884 1133static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
de1ebdce
GW		 1134 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1135 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1136 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1137 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1138 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1139 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1140 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1141 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1142 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1143 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1144 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce
GW		 1145 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1146#ifdef CONFIG_RT2800PCI_RT30XX
a9b3a9f7
ID		 1147 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1148 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1149 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce
GW		 1150 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1151#endif
1152#ifdef CONFIG_RT2800PCI_RT35XX
1153 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1154 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1155 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1156 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
6424bf70 1157 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce 1158#endif
a9b3a9f7
ID		 1159 { 0, }
1160};
d6e36ec1 1161#endif /* CONFIG_RT2800PCI_PCI */
a9b3a9f7
ID		 1162
1163MODULE_AUTHOR(DRV_PROJECT);
1164MODULE_VERSION(DRV_VERSION);
1165MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1166MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1167#ifdef CONFIG_RT2800PCI_PCI
1168MODULE_FIRMWARE(FIRMWARE_RT2860);
1169MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1170#endif /* CONFIG_RT2800PCI_PCI */
1171MODULE_LICENSE("GPL");
1172
00e23ce2 1173#ifdef CONFIG_RT2800PCI_SOC
714fa663
GW		 1174static int rt2800soc_probe(struct platform_device *pdev)
1175{
6e93d719 1176 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1177}
a9b3a9f7
ID		 1178
1179static struct platform_driver rt2800soc_driver = {
1180 .driver = {
1181 .name = "rt2800_wmac",
1182 .owner = THIS_MODULE,
1183 .mod_name = KBUILD_MODNAME,
1184 },
714fa663 1185 .probe = rt2800soc_probe,
a9b3a9f7
ID		 1186 .remove = __devexit_p(rt2x00soc_remove),
1187 .suspend = rt2x00soc_suspend,
1188 .resume = rt2x00soc_resume,
1189};
00e23ce2 1190#endif /* CONFIG_RT2800PCI_SOC */
a9b3a9f7
ID		 1191
1192#ifdef CONFIG_RT2800PCI_PCI
1193static struct pci_driver rt2800pci_driver = {
1194 .name = KBUILD_MODNAME,
1195 .id_table = rt2800pci_device_table,
1196 .probe = rt2x00pci_probe,
1197 .remove = __devexit_p(rt2x00pci_remove),
1198 .suspend = rt2x00pci_suspend,
1199 .resume = rt2x00pci_resume,
1200};
1201#endif /* CONFIG_RT2800PCI_PCI */
1202
1203static int __init rt2800pci_init(void)
1204{
1205 int ret = 0;
1206
00e23ce2 1207#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1208 ret = platform_driver_register(&rt2800soc_driver);
1209 if (ret)
1210 return ret;
1211#endif
1212#ifdef CONFIG_RT2800PCI_PCI
1213 ret = pci_register_driver(&rt2800pci_driver);
1214 if (ret) {
00e23ce2 1215#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1216 platform_driver_unregister(&rt2800soc_driver);
1217#endif
1218 return ret;
1219 }
1220#endif
1221
1222 return ret;
1223}
1224
1225static void __exit rt2800pci_exit(void)
1226{
1227#ifdef CONFIG_RT2800PCI_PCI
1228 pci_unregister_driver(&rt2800pci_driver);
1229#endif
00e23ce2 1230#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1231 platform_driver_unregister(&rt2800soc_driver);
1232#endif
1233}
1234
1235module_init(rt2800pci_init);
1236module_exit(rt2800pci_exit);
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