[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / rt2x00 / rt2800pci.h

/*
	Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
	Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
	Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
	Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
	Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
	Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
	Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
	Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
	<http://rt2x00.serialmonkey.com>

	This program is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with this program; if not, write to the
	Free Software Foundation, Inc.,
	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

/*
	Module: rt2800pci
	Abstract: Data structures and registers for the rt2800pci module.
	Supported chipsets: RT2800E & RT2800ED.
 */

#ifndef RT2800PCI_H
#define RT2800PCI_H

/*
 * PCI registers.
 */

/*
 * E2PROM_CSR: EEPROM control register.
 * RELOAD: Write 1 to reload eeprom content.
 * TYPE: 0: 93c46, 1:93c66.
 * LOAD_STATUS: 1:loading, 0:done.
 */
#define E2PROM_CSR			0x0004
#define E2PROM_CSR_DATA_CLOCK		FIELD32(0x00000001)
#define E2PROM_CSR_CHIP_SELECT		FIELD32(0x00000002)
#define E2PROM_CSR_DATA_IN		FIELD32(0x00000004)
#define E2PROM_CSR_DATA_OUT		FIELD32(0x00000008)
#define E2PROM_CSR_TYPE			FIELD32(0x00000030)
#define E2PROM_CSR_LOAD_STATUS		FIELD32(0x00000040)
#define E2PROM_CSR_RELOAD		FIELD32(0x00000080)

/*
 * Queue register offset macros
 */
#define TX_QUEUE_REG_OFFSET		0x10
#define TX_BASE_PTR(__x)		TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
#define TX_MAX_CNT(__x)			TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
#define TX_CTX_IDX(__x)			TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
#define TX_DTX_IDX(__x)			TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)

/*
 * 8051 firmware image.
 */
#define FIRMWARE_RT2860			"rt2860.bin"
#define FIRMWARE_IMAGE_BASE		0x2000

/*
 * DMA descriptor defines.
 */
#define TXD_DESC_SIZE			( 4 * sizeof(__le32) )
#define RXD_DESC_SIZE			( 4 * sizeof(__le32) )

/*
 * TX descriptor format for TX, PRIO and Beacon Ring.
 */

/*
 * Word0
 */
#define TXD_W0_SD_PTR0			FIELD32(0xffffffff)

/*
 * Word1
 */
#define TXD_W1_SD_LEN1			FIELD32(0x00003fff)
#define TXD_W1_LAST_SEC1		FIELD32(0x00004000)
#define TXD_W1_BURST			FIELD32(0x00008000)
#define TXD_W1_SD_LEN0			FIELD32(0x3fff0000)
#define TXD_W1_LAST_SEC0		FIELD32(0x40000000)
#define TXD_W1_DMA_DONE			FIELD32(0x80000000)

/*
 * Word2
 */
#define TXD_W2_SD_PTR1			FIELD32(0xffffffff)

/*
 * Word3
 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
 * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
 *       0:MGMT, 1:HCCA 2:EDCA
 */
#define TXD_W3_WIV			FIELD32(0x01000000)
#define TXD_W3_QSEL			FIELD32(0x06000000)
#define TXD_W3_TCO			FIELD32(0x20000000)
#define TXD_W3_UCO			FIELD32(0x40000000)
#define TXD_W3_ICO			FIELD32(0x80000000)

/*
 * RX descriptor format for RX Ring.
 */

/*
 * Word0
 */
#define RXD_W0_SDP0			FIELD32(0xffffffff)

/*
 * Word1
 */
#define RXD_W1_SDL1			FIELD32(0x00003fff)
#define RXD_W1_SDL0			FIELD32(0x3fff0000)
#define RXD_W1_LS0			FIELD32(0x40000000)
#define RXD_W1_DMA_DONE			FIELD32(0x80000000)

/*
 * Word2
 */
#define RXD_W2_SDP1			FIELD32(0xffffffff)

/*
 * Word3
 * AMSDU: RX with 802.3 header, not 802.11 header.
 * DECRYPTED: This frame is being decrypted.
 */
#define RXD_W3_BA			FIELD32(0x00000001)
#define RXD_W3_DATA			FIELD32(0x00000002)
#define RXD_W3_NULLDATA			FIELD32(0x00000004)
#define RXD_W3_FRAG			FIELD32(0x00000008)
#define RXD_W3_UNICAST_TO_ME		FIELD32(0x00000010)
#define RXD_W3_MULTICAST		FIELD32(0x00000020)
#define RXD_W3_BROADCAST		FIELD32(0x00000040)
#define RXD_W3_MY_BSS			FIELD32(0x00000080)
#define RXD_W3_CRC_ERROR		FIELD32(0x00000100)
#define RXD_W3_CIPHER_ERROR		FIELD32(0x00000600)
#define RXD_W3_AMSDU			FIELD32(0x00000800)
#define RXD_W3_HTC			FIELD32(0x00001000)
#define RXD_W3_RSSI			FIELD32(0x00002000)
#define RXD_W3_L2PAD			FIELD32(0x00004000)
#define RXD_W3_AMPDU			FIELD32(0x00008000)
#define RXD_W3_DECRYPTED		FIELD32(0x00010000)
#define RXD_W3_PLCP_SIGNAL		FIELD32(0x00020000)
#define RXD_W3_PLCP_RSSI		FIELD32(0x00040000)

#endif /* RT2800PCI_H */
Commit	Line	Data
a9b3a9f7	1	/*
9c9a0d14 GW	2	Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
	3	Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
	4	Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
	5	Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
	6	Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
	7	Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
	8	Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
	9	Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7 ID	10	<http://rt2x00.serialmonkey.com>
	11
	12	This program is free software; you can redistribute it and/or modify
	13	it under the terms of the GNU General Public License as published by
	14	the Free Software Foundation; either version 2 of the License, or
	15	(at your option) any later version.
	16
	17	This program is distributed in the hope that it will be useful,
	18	but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	GNU General Public License for more details.
	21
	22	You should have received a copy of the GNU General Public License
	23	along with this program; if not, write to the
	24	Free Software Foundation, Inc.,
	25	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	26	*/
	27
	28	/*
	29	Module: rt2800pci
	30	Abstract: Data structures and registers for the rt2800pci module.
	31	Supported chipsets: RT2800E & RT2800ED.
	32	*/
	33
	34	#ifndef RT2800PCI_H
	35	#define RT2800PCI_H
	36
	37	/*
b54f78a8	38	* PCI registers.
a9b3a9f7	39	*/
a9b3a9f7 ID	40
a9b3a9f7 ID	41	/*
b54f78a8 BZ	42	* E2PROM_CSR: EEPROM control register.
	43	* RELOAD: Write 1 to reload eeprom content.
	44	* TYPE: 0: 93c46, 1:93c66.
	45	* LOAD_STATUS: 1:loading, 0:done.
a9b3a9f7	46	*/
b54f78a8 BZ	47	#define E2PROM_CSR 0x0004
	48	#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
	49	#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
	50	#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
	51	#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
	52	#define E2PROM_CSR_TYPE FIELD32(0x00000030)
	53	#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
	54	#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
a9b3a9f7 ID	55
a9b3a9f7 ID	56	/*
b54f78a8	57	* Queue register offset macros
a9b3a9f7	58	*/
b54f78a8 BZ	59	#define TX_QUEUE_REG_OFFSET 0x10
	60	#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
	61	#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
	62	#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
	63	#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
a9b3a9f7	64
a9b3a9f7 ID	65	/*
	66	* 8051 firmware image.
	67	*/
	68	#define FIRMWARE_RT2860 "rt2860.bin"
	69	#define FIRMWARE_IMAGE_BASE 0x2000
	70
a9b3a9f7 ID	71	/*
	72	* DMA descriptor defines.
	73	*/
	74	#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
a9b3a9f7	75	#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
a9b3a9f7 ID	76
	77	/*
	78	* TX descriptor format for TX, PRIO and Beacon Ring.
	79	*/
	80
	81	/*
	82	* Word0
	83	*/
	84	#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
	85
	86	/*
	87	* Word1
	88	*/
	89	#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
	90	#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
	91	#define TXD_W1_BURST FIELD32(0x00008000)
	92	#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
	93	#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
	94	#define TXD_W1_DMA_DONE FIELD32(0x80000000)
	95
	96	/*
	97	* Word2
	98	*/
	99	#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
	100
	101	/*
	102	* Word3
	103	* WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
	104	* QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
	105	* 0:MGMT, 1:HCCA 2:EDCA
	106	*/
	107	#define TXD_W3_WIV FIELD32(0x01000000)
	108	#define TXD_W3_QSEL FIELD32(0x06000000)
	109	#define TXD_W3_TCO FIELD32(0x20000000)
	110	#define TXD_W3_UCO FIELD32(0x40000000)
	111	#define TXD_W3_ICO FIELD32(0x80000000)
	112
a9b3a9f7 ID	113	/*
	114	* RX descriptor format for RX Ring.
	115	*/
	116
	117	/*
	118	* Word0
	119	*/
	120	#define RXD_W0_SDP0 FIELD32(0xffffffff)
	121
	122	/*
	123	* Word1
	124	*/
	125	#define RXD_W1_SDL1 FIELD32(0x00003fff)
	126	#define RXD_W1_SDL0 FIELD32(0x3fff0000)
	127	#define RXD_W1_LS0 FIELD32(0x40000000)
	128	#define RXD_W1_DMA_DONE FIELD32(0x80000000)
	129
	130	/*
	131	* Word2
	132	*/
	133	#define RXD_W2_SDP1 FIELD32(0xffffffff)
	134
	135	/*
	136	* Word3
	137	* AMSDU: RX with 802.3 header, not 802.11 header.
	138	* DECRYPTED: This frame is being decrypted.
	139	*/
	140	#define RXD_W3_BA FIELD32(0x00000001)
	141	#define RXD_W3_DATA FIELD32(0x00000002)
	142	#define RXD_W3_NULLDATA FIELD32(0x00000004)
	143	#define RXD_W3_FRAG FIELD32(0x00000008)
	144	#define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
	145	#define RXD_W3_MULTICAST FIELD32(0x00000020)
	146	#define RXD_W3_BROADCAST FIELD32(0x00000040)
	147	#define RXD_W3_MY_BSS FIELD32(0x00000080)
	148	#define RXD_W3_CRC_ERROR FIELD32(0x00000100)
	149	#define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
	150	#define RXD_W3_AMSDU FIELD32(0x00000800)
	151	#define RXD_W3_HTC FIELD32(0x00001000)
	152	#define RXD_W3_RSSI FIELD32(0x00002000)
	153	#define RXD_W3_L2PAD FIELD32(0x00004000)
	154	#define RXD_W3_AMPDU FIELD32(0x00008000)
	155	#define RXD_W3_DECRYPTED FIELD32(0x00010000)
	156	#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
	157	#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
	158
a9b3a9f7	159	#endif /* RT2800PCI_H */