[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / rt2x00 / rt2x00pci.c

/*
	Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
	<http://rt2x00.serialmonkey.com>

	This program is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with this program; if not, write to the
	Free Software Foundation, Inc.,
	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

/*
	Module: rt2x00pci
	Abstract: rt2x00 generic pci device routines.
 */

#include <linux/dma-mapping.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>

#include "rt2x00.h"
#include "rt2x00pci.h"

/*
 * Beacon handlers.
 */
int rt2x00pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
			    struct ieee80211_tx_control *control)
{
	struct rt2x00_dev *rt2x00dev = hw->priv;
	struct queue_entry_priv_pci_tx *priv_tx;
	struct skb_frame_desc *skbdesc;
	struct data_queue *queue;
	struct queue_entry *entry;

	/*
	 * Just in case mac80211 doesn't set this correctly,
	 * but we need this queue set for the descriptor
	 * initialization.
	 */
	control->queue = IEEE80211_TX_QUEUE_BEACON;
	queue = rt2x00queue_get_queue(rt2x00dev, control->queue);
	entry = rt2x00queue_get_entry(queue, Q_INDEX);
	priv_tx = entry->priv_data;

	/*
	 * Fill in skb descriptor
	 */
	skbdesc = get_skb_frame_desc(skb);
	memset(skbdesc, 0, sizeof(*skbdesc));
	skbdesc->data = skb->data;
	skbdesc->data_len = queue->data_size;
	skbdesc->desc = priv_tx->desc;
	skbdesc->desc_len = queue->desc_size;
	skbdesc->entry = entry;

	memcpy(priv_tx->data, skb->data, skb->len);
	rt2x00lib_write_tx_desc(rt2x00dev, skb, control);

	/*
	 * Enable beacon generation.
	 */
	rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);

	return 0;
}
EXPORT_SYMBOL_GPL(rt2x00pci_beacon_update);

/*
 * TX data handlers.
 */
int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev,
			    struct data_queue *queue, struct sk_buff *skb,
			    struct ieee80211_tx_control *control)
{
	struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
	struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
	struct skb_frame_desc *skbdesc;
	u32 word;

	if (rt2x00queue_full(queue))
		return -EINVAL;

	rt2x00_desc_read(priv_tx->desc, 0, &word);

	if (rt2x00_get_field32(word, TXD_ENTRY_OWNER_NIC) ||
	    rt2x00_get_field32(word, TXD_ENTRY_VALID)) {
		ERROR(rt2x00dev,
		      "Arrived at non-free entry in the non-full queue %d.\n"
		      "Please file bug report to %s.\n",
		      control->queue, DRV_PROJECT);
		return -EINVAL;
	}

	/*
	 * Fill in skb descriptor
	 */
	skbdesc = get_skb_frame_desc(skb);
	memset(skbdesc, 0, sizeof(*skbdesc));
	skbdesc->data = skb->data;
	skbdesc->data_len = queue->data_size;
	skbdesc->desc = priv_tx->desc;
	skbdesc->desc_len = queue->desc_size;
	skbdesc->entry = entry;

	memcpy(priv_tx->data, skb->data, skb->len);
	rt2x00lib_write_tx_desc(rt2x00dev, skb, control);

	rt2x00queue_index_inc(queue, Q_INDEX);

	return 0;
}
EXPORT_SYMBOL_GPL(rt2x00pci_write_tx_data);

/*
 * TX/RX data handlers.
 */
void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
{
	struct data_queue *queue = rt2x00dev->rx;
	struct queue_entry *entry;
	struct queue_entry_priv_pci_rx *priv_rx;
	struct ieee80211_hdr *hdr;
	struct skb_frame_desc *skbdesc;
	struct rxdone_entry_desc rxdesc;
	int header_size;
	int align;
	u32 word;

	while (1) {
		entry = rt2x00queue_get_entry(queue, Q_INDEX);
		priv_rx = entry->priv_data;
		rt2x00_desc_read(priv_rx->desc, 0, &word);

		if (rt2x00_get_field32(word, RXD_ENTRY_OWNER_NIC))
			break;

		memset(&rxdesc, 0, sizeof(rxdesc));
		rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc);

		hdr = (struct ieee80211_hdr *)priv_rx->data;
		header_size =
		    ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_control));

		/*
		 * The data behind the ieee80211 header must be
		 * aligned on a 4 byte boundary.
		 */
		align = header_size % 4;

		/*
		 * Allocate the sk_buffer, initialize it and copy
		 * all data into it.
		 */
		entry->skb = dev_alloc_skb(rxdesc.size + align);
		if (!entry->skb)
			return;

		skb_reserve(entry->skb, align);
		memcpy(skb_put(entry->skb, rxdesc.size),
		       priv_rx->data, rxdesc.size);

		/*
		 * Fill in skb descriptor
		 */
		skbdesc = get_skb_frame_desc(entry->skb);
		memset(skbdesc, 0, sizeof(*skbdesc));
		skbdesc->data = entry->skb->data;
		skbdesc->data_len = queue->data_size;
		skbdesc->desc = priv_rx->desc;
		skbdesc->desc_len = queue->desc_size;
		skbdesc->entry = entry;

		/*
		 * Send the frame to rt2x00lib for further processing.
		 */
		rt2x00lib_rxdone(entry, &rxdesc);

		if (test_bit(DEVICE_ENABLED_RADIO, &queue->rt2x00dev->flags)) {
			rt2x00_set_field32(&word, RXD_ENTRY_OWNER_NIC, 1);
			rt2x00_desc_write(priv_rx->desc, 0, word);
		}

		rt2x00queue_index_inc(queue, Q_INDEX);
	}
}
EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);

void rt2x00pci_txdone(struct rt2x00_dev *rt2x00dev, struct queue_entry *entry,
		      struct txdone_entry_desc *txdesc)
{
	struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
	u32 word;

	txdesc->control = &priv_tx->control;
	rt2x00lib_txdone(entry, txdesc);

	/*
	 * Make this entry available for reuse.
	 */
	entry->flags = 0;

	rt2x00_desc_read(priv_tx->desc, 0, &word);
	rt2x00_set_field32(&word, TXD_ENTRY_OWNER_NIC, 0);
	rt2x00_set_field32(&word, TXD_ENTRY_VALID, 0);
	rt2x00_desc_write(priv_tx->desc, 0, word);

	rt2x00queue_index_inc(entry->queue, Q_INDEX_DONE);

	/*
	 * If the data queue was full before the txdone handler
	 * we must make sure the packet queue in the mac80211 stack
	 * is reenabled when the txdone handler has finished.
	 */
	if (!rt2x00queue_full(entry->queue))
		ieee80211_wake_queue(rt2x00dev->hw, priv_tx->control.queue);

}
EXPORT_SYMBOL_GPL(rt2x00pci_txdone);

/*
 * Device initialization handlers.
 */
#define dma_size(__queue)				\
({							\
	(__queue)->limit *				\
	    ((__queue)->desc_size + (__queue)->data_size);\
})

#define priv_offset(__queue, __base, __i)		\
({							\
	(__base) + ((__i) * (__queue)->desc_size);	\
})

#define data_addr_offset(__queue, __base, __i)		\
({							\
	(__base) +					\
	    ((__queue)->limit * (__queue)->desc_size) +	\
	    ((__i) * (__queue)->data_size);		\
})

#define data_dma_offset(__queue, __base, __i)		\
({							\
	(__base) +					\
	    ((__queue)->limit * (__queue)->desc_size) +	\
	    ((__i) * (__queue)->data_size);		\
})

static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
				     struct data_queue *queue)
{
	struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
	struct queue_entry_priv_pci_tx *priv_tx;
	void *data_addr;
	dma_addr_t data_dma;
	unsigned int i;

	/*
	 * Allocate DMA memory for descriptor and buffer.
	 */
	data_addr = pci_alloc_consistent(pci_dev, dma_size(queue), &data_dma);
	if (!data_addr)
		return -ENOMEM;

	/*
	 * Initialize all queue entries to contain valid addresses.
	 */
	for (i = 0; i < queue->limit; i++) {
		priv_tx = queue->entries[i].priv_data;
		priv_tx->desc = priv_offset(queue, data_addr, i);
		priv_tx->data = data_addr_offset(queue, data_addr, i);
		priv_tx->dma = data_dma_offset(queue, data_dma, i);
	}

	return 0;
}

static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
				     struct data_queue *queue)
{
	struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
	struct queue_entry_priv_pci_tx *priv_tx = queue->entries[0].priv_data;

	if (priv_tx->data)
		pci_free_consistent(pci_dev, dma_size(queue),
				    priv_tx->data, priv_tx->dma);
	priv_tx->data = NULL;
}

int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
{
	struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
	struct data_queue *queue;
	int status;

	/*
	 * Allocate DMA
	 */
	queue_for_each(rt2x00dev, queue) {
		status = rt2x00pci_alloc_queue_dma(rt2x00dev, queue);
		if (status)
			goto exit;
	}

	/*
	 * Register interrupt handler.
	 */
	status = request_irq(pci_dev->irq, rt2x00dev->ops->lib->irq_handler,
			     IRQF_SHARED, pci_name(pci_dev), rt2x00dev);
	if (status) {
		ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
		      pci_dev->irq, status);
		return status;
	}

	return 0;

exit:
	rt2x00pci_uninitialize(rt2x00dev);

	return status;
}
EXPORT_SYMBOL_GPL(rt2x00pci_initialize);

void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
{
	struct data_queue *queue;

	/*
	 * Free irq line.
	 */
	free_irq(rt2x00dev_pci(rt2x00dev)->irq, rt2x00dev);

	/*
	 * Free DMA
	 */
	queue_for_each(rt2x00dev, queue)
		rt2x00pci_free_queue_dma(rt2x00dev, queue);
}
EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);

/*
 * PCI driver handlers.
 */
static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
{
	kfree(rt2x00dev->rf);
	rt2x00dev->rf = NULL;

	kfree(rt2x00dev->eeprom);
	rt2x00dev->eeprom = NULL;

	if (rt2x00dev->csr_addr) {
		iounmap(rt2x00dev->csr_addr);
		rt2x00dev->csr_addr = NULL;
	}
}

static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
{
	struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);

	rt2x00dev->csr_addr = ioremap(pci_resource_start(pci_dev, 0),
				      pci_resource_len(pci_dev, 0));
	if (!rt2x00dev->csr_addr)
		goto exit;

	rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
	if (!rt2x00dev->eeprom)
		goto exit;

	rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
	if (!rt2x00dev->rf)
		goto exit;

	return 0;

exit:
	ERROR_PROBE("Failed to allocate registers.\n");

	rt2x00pci_free_reg(rt2x00dev);

	return -ENOMEM;
}

int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
{
	struct rt2x00_ops *ops = (struct rt2x00_ops *)id->driver_data;
	struct ieee80211_hw *hw;
	struct rt2x00_dev *rt2x00dev;
	int retval;

	retval = pci_request_regions(pci_dev, pci_name(pci_dev));
	if (retval) {
		ERROR_PROBE("PCI request regions failed.\n");
		return retval;
	}

	retval = pci_enable_device(pci_dev);
	if (retval) {
		ERROR_PROBE("Enable device failed.\n");
		goto exit_release_regions;
	}

	pci_set_master(pci_dev);

	if (pci_set_mwi(pci_dev))
		ERROR_PROBE("MWI not available.\n");

	if (pci_set_dma_mask(pci_dev, DMA_64BIT_MASK) &&
	    pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
		ERROR_PROBE("PCI DMA not supported.\n");
		retval = -EIO;
		goto exit_disable_device;
	}

	hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
	if (!hw) {
		ERROR_PROBE("Failed to allocate hardware.\n");
		retval = -ENOMEM;
		goto exit_disable_device;
	}

	pci_set_drvdata(pci_dev, hw);

	rt2x00dev = hw->priv;
	rt2x00dev->dev = pci_dev;
	rt2x00dev->ops = ops;
	rt2x00dev->hw = hw;

	retval = rt2x00pci_alloc_reg(rt2x00dev);
	if (retval)
		goto exit_free_device;

	retval = rt2x00lib_probe_dev(rt2x00dev);
	if (retval)
		goto exit_free_reg;

	return 0;

exit_free_reg:
	rt2x00pci_free_reg(rt2x00dev);

exit_free_device:
	ieee80211_free_hw(hw);

exit_disable_device:
	if (retval != -EBUSY)
		pci_disable_device(pci_dev);

exit_release_regions:
	pci_release_regions(pci_dev);

	pci_set_drvdata(pci_dev, NULL);

	return retval;
}
EXPORT_SYMBOL_GPL(rt2x00pci_probe);

void rt2x00pci_remove(struct pci_dev *pci_dev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
	struct rt2x00_dev *rt2x00dev = hw->priv;

	/*
	 * Free all allocated data.
	 */
	rt2x00lib_remove_dev(rt2x00dev);
	rt2x00pci_free_reg(rt2x00dev);
	ieee80211_free_hw(hw);

	/*
	 * Free the PCI device data.
	 */
	pci_set_drvdata(pci_dev, NULL);
	pci_disable_device(pci_dev);
	pci_release_regions(pci_dev);
}
EXPORT_SYMBOL_GPL(rt2x00pci_remove);

#ifdef CONFIG_PM
int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
	struct rt2x00_dev *rt2x00dev = hw->priv;
	int retval;

	retval = rt2x00lib_suspend(rt2x00dev, state);
	if (retval)
		return retval;

	rt2x00pci_free_reg(rt2x00dev);

	pci_save_state(pci_dev);
	pci_disable_device(pci_dev);
	return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
}
EXPORT_SYMBOL_GPL(rt2x00pci_suspend);

int rt2x00pci_resume(struct pci_dev *pci_dev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
	struct rt2x00_dev *rt2x00dev = hw->priv;
	int retval;

	if (pci_set_power_state(pci_dev, PCI_D0) ||
	    pci_enable_device(pci_dev) ||
	    pci_restore_state(pci_dev)) {
		ERROR(rt2x00dev, "Failed to resume device.\n");
		return -EIO;
	}

	retval = rt2x00pci_alloc_reg(rt2x00dev);
	if (retval)
		return retval;

	retval = rt2x00lib_resume(rt2x00dev);
	if (retval)
		goto exit_free_reg;

	return 0;

exit_free_reg:
	rt2x00pci_free_reg(rt2x00dev);

	return retval;
}
EXPORT_SYMBOL_GPL(rt2x00pci_resume);
#endif /* CONFIG_PM */

/*
 * rt2x00pci module information.
 */
MODULE_AUTHOR(DRV_PROJECT);
MODULE_VERSION(DRV_VERSION);
MODULE_DESCRIPTION("rt2x00 pci library");
MODULE_LICENSE("GPL");
Commit	Line	Data
95ea3627	1	/*
811aa9ca	2	Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627 ID	3	<http://rt2x00.serialmonkey.com>
	4
	5	This program is free software; you can redistribute it and/or modify
	6	it under the terms of the GNU General Public License as published by
	7	the Free Software Foundation; either version 2 of the License, or
	8	(at your option) any later version.
	9
	10	This program is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	GNU General Public License for more details.
	14
	15	You should have received a copy of the GNU General Public License
	16	along with this program; if not, write to the
	17	Free Software Foundation, Inc.,
	18	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	19	*/
	20
	21	/*
	22	Module: rt2x00pci
	23	Abstract: rt2x00 generic pci device routines.
	24	*/
	25
95ea3627 ID	26	#include <linux/dma-mapping.h>
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
	29	#include <linux/pci.h>
	30
	31	#include "rt2x00.h"
	32	#include "rt2x00pci.h"
	33
	34	/*
	35	* Beacon handlers.
	36	*/
	37	int rt2x00pci_beacon_update(struct ieee80211_hw hw, struct sk_buff skb,
	38	struct ieee80211_tx_control *control)
	39	{
	40	struct rt2x00_dev *rt2x00dev = hw->priv;
181d6902 ID	41	struct queue_entry_priv_pci_tx *priv_tx;
	42	struct skb_frame_desc *skbdesc;
	43	struct data_queue *queue;
	44	struct queue_entry *entry;
95ea3627 ID	45
	46	/*
	47	* Just in case mac80211 doesn't set this correctly,
	48	* but we need this queue set for the descriptor
	49	* initialization.
	50	*/
	51	control->queue = IEEE80211_TX_QUEUE_BEACON;
181d6902 ID	52	queue = rt2x00queue_get_queue(rt2x00dev, control->queue);
	53	entry = rt2x00queue_get_entry(queue, Q_INDEX);
	54	priv_tx = entry->priv_data;
95ea3627 ID	55
95ea3627 ID	56	/*
08992f7f	57	* Fill in skb descriptor
95ea3627	58	*/
181d6902 ID	59	skbdesc = get_skb_frame_desc(skb);
	60	memset(skbdesc, 0, sizeof(*skbdesc));
	61	skbdesc->data = skb->data;
	62	skbdesc->data_len = queue->data_size;
	63	skbdesc->desc = priv_tx->desc;
	64	skbdesc->desc_len = queue->desc_size;
	65	skbdesc->entry = entry;
	66
	67	memcpy(priv_tx->data, skb->data, skb->len);
08992f7f	68	rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
95ea3627 ID	69
	70	/*
	71	* Enable beacon generation.
	72	*/
	73	rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
	74
	75	return 0;
	76	}
	77	EXPORT_SYMBOL_GPL(rt2x00pci_beacon_update);
	78
	79	/*
	80	* TX data handlers.
	81	*/
	82	int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev,
181d6902	83	struct data_queue queue, struct sk_buff skb,
95ea3627 ID	84	struct ieee80211_tx_control *control)
95ea3627 ID	85	{
181d6902 ID	86	struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
	87	struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
	88	struct skb_frame_desc *skbdesc;
95ea3627 ID	89	u32 word;
95ea3627 ID	90
181d6902	91	if (rt2x00queue_full(queue))
95ea3627	92	return -EINVAL;
95ea3627	93
181d6902	94	rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627 ID	95
	96	if (rt2x00_get_field32(word, TXD_ENTRY_OWNER_NIC) \|\|
	97	rt2x00_get_field32(word, TXD_ENTRY_VALID)) {
	98	ERROR(rt2x00dev,
	99	"Arrived at non-free entry in the non-full queue %d.\n"
	100	"Please file bug report to %s.\n",
	101	control->queue, DRV_PROJECT);
95ea3627 ID	102	return -EINVAL;
	103	}
	104
08992f7f ID	105	/*
	106	* Fill in skb descriptor
	107	*/
181d6902 ID	108	skbdesc = get_skb_frame_desc(skb);
	109	memset(skbdesc, 0, sizeof(*skbdesc));
	110	skbdesc->data = skb->data;
	111	skbdesc->data_len = queue->data_size;
	112	skbdesc->desc = priv_tx->desc;
	113	skbdesc->desc_len = queue->desc_size;
	114	skbdesc->entry = entry;
	115
	116	memcpy(priv_tx->data, skb->data, skb->len);
08992f7f	117	rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
95ea3627	118
181d6902	119	rt2x00queue_index_inc(queue, Q_INDEX);
95ea3627	120
95ea3627 ID	121	return 0;
	122	}
	123	EXPORT_SYMBOL_GPL(rt2x00pci_write_tx_data);
	124
	125	/*
3957ccb5	126	* TX/RX data handlers.
95ea3627 ID	127	*/
	128	void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
	129	{
181d6902 ID	130	struct data_queue *queue = rt2x00dev->rx;
	131	struct queue_entry *entry;
	132	struct queue_entry_priv_pci_rx *priv_rx;
c5d0dc5f	133	struct ieee80211_hdr *hdr;
181d6902 ID	134	struct skb_frame_desc *skbdesc;
181d6902 ID	135	struct rxdone_entry_desc rxdesc;
c5d0dc5f ID	136	int header_size;
c5d0dc5f ID	137	int align;
4150c572	138	u32 word;
95ea3627 ID	139
95ea3627 ID	140	while (1) {
181d6902 ID	141	entry = rt2x00queue_get_entry(queue, Q_INDEX);
	142	priv_rx = entry->priv_data;
	143	rt2x00_desc_read(priv_rx->desc, 0, &word);
95ea3627	144
4150c572	145	if (rt2x00_get_field32(word, RXD_ENTRY_OWNER_NIC))
95ea3627 ID	146	break;
95ea3627 ID	147
181d6902 ID	148	memset(&rxdesc, 0, sizeof(rxdesc));
181d6902 ID	149	rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc);
95ea3627	150
181d6902	151	hdr = (struct ieee80211_hdr *)priv_rx->data;
c5d0dc5f ID	152	header_size =
	153	ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_control));
	154
	155	/*
	156	* The data behind the ieee80211 header must be
	157	* aligned on a 4 byte boundary.
	158	*/
d101f649	159	align = header_size % 4;
c5d0dc5f	160
95ea3627 ID	161	/*
	162	* Allocate the sk_buffer, initialize it and copy
	163	* all data into it.
	164	*/
181d6902 ID	165	entry->skb = dev_alloc_skb(rxdesc.size + align);
181d6902 ID	166	if (!entry->skb)
95ea3627 ID	167	return;
95ea3627 ID	168
181d6902 ID	169	skb_reserve(entry->skb, align);
	170	memcpy(skb_put(entry->skb, rxdesc.size),
	171	priv_rx->data, rxdesc.size);
95ea3627	172
08992f7f ID	173	/*
	174	* Fill in skb descriptor
	175	*/
181d6902 ID	176	skbdesc = get_skb_frame_desc(entry->skb);
	177	memset(skbdesc, 0, sizeof(*skbdesc));
	178	skbdesc->data = entry->skb->data;
	179	skbdesc->data_len = queue->data_size;
	180	skbdesc->desc = priv_rx->desc;
	181	skbdesc->desc_len = queue->desc_size;
08992f7f ID	182	skbdesc->entry = entry;
08992f7f ID	183
95ea3627 ID	184	/*
	185	* Send the frame to rt2x00lib for further processing.
	186	*/
181d6902	187	rt2x00lib_rxdone(entry, &rxdesc);
95ea3627	188
181d6902	189	if (test_bit(DEVICE_ENABLED_RADIO, &queue->rt2x00dev->flags)) {
4150c572	190	rt2x00_set_field32(&word, RXD_ENTRY_OWNER_NIC, 1);
181d6902	191	rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627 ID	192	}
95ea3627 ID	193
181d6902	194	rt2x00queue_index_inc(queue, Q_INDEX);
95ea3627 ID	195	}
	196	}
	197	EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);
	198
181d6902 ID	199	void rt2x00pci_txdone(struct rt2x00_dev rt2x00dev, struct queue_entry entry,
181d6902 ID	200	struct txdone_entry_desc *txdesc)
3957ccb5	201	{
181d6902	202	struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
3957ccb5 ID	203	u32 word;
3957ccb5 ID	204
181d6902 ID	205	txdesc->control = &priv_tx->control;
181d6902 ID	206	rt2x00lib_txdone(entry, txdesc);
3957ccb5 ID	207
	208	/*
	209	* Make this entry available for reuse.
	210	*/
	211	entry->flags = 0;
	212
181d6902	213	rt2x00_desc_read(priv_tx->desc, 0, &word);
3957ccb5 ID	214	rt2x00_set_field32(&word, TXD_ENTRY_OWNER_NIC, 0);
3957ccb5 ID	215	rt2x00_set_field32(&word, TXD_ENTRY_VALID, 0);
181d6902	216	rt2x00_desc_write(priv_tx->desc, 0, word);
3957ccb5	217
181d6902	218	rt2x00queue_index_inc(entry->queue, Q_INDEX_DONE);
3957ccb5 ID	219
3957ccb5 ID	220	/*
181d6902	221	* If the data queue was full before the txdone handler
3957ccb5 ID	222	* we must make sure the packet queue in the mac80211 stack
	223	* is reenabled when the txdone handler has finished.
	224	*/
181d6902 ID	225	if (!rt2x00queue_full(entry->queue))
181d6902 ID	226	ieee80211_wake_queue(rt2x00dev->hw, priv_tx->control.queue);
3957ccb5 ID	227
	228	}
	229	EXPORT_SYMBOL_GPL(rt2x00pci_txdone);
	230
95ea3627 ID	231	/*
	232	* Device initialization handlers.
	233	*/
181d6902 ID	234	#define dma_size(__queue) \
	235	({ \
	236	(__queue)->limit * \
	237	((__queue)->desc_size + (__queue)->data_size);\
95ea3627 ID	238	})
95ea3627 ID	239
181d6902 ID	240	#define priv_offset(__queue, __base, __i) \
	241	({ \
	242	(__base) + ((__i) * (__queue)->desc_size); \
95ea3627 ID	243	})
95ea3627 ID	244
181d6902 ID	245	#define data_addr_offset(__queue, __base, __i) \
	246	({ \
	247	(__base) + \
	248	((__queue)->limit * (__queue)->desc_size) + \
	249	((__i) * (__queue)->data_size); \
95ea3627 ID	250	})
95ea3627 ID	251
181d6902 ID	252	#define data_dma_offset(__queue, __base, __i) \
	253	({ \
	254	(__base) + \
	255	((__queue)->limit * (__queue)->desc_size) + \
	256	((__i) * (__queue)->data_size); \
	257	})
	258
	259	static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
	260	struct data_queue *queue)
95ea3627	261	{
181d6902 ID	262	struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
	263	struct queue_entry_priv_pci_tx *priv_tx;
	264	void *data_addr;
	265	dma_addr_t data_dma;
95ea3627 ID	266	unsigned int i;
	267
	268	/*
	269	* Allocate DMA memory for descriptor and buffer.
	270	*/
181d6902 ID	271	data_addr = pci_alloc_consistent(pci_dev, dma_size(queue), &data_dma);
181d6902 ID	272	if (!data_addr)
95ea3627 ID	273	return -ENOMEM;
	274
	275	/*
181d6902	276	* Initialize all queue entries to contain valid addresses.
95ea3627	277	*/
181d6902 ID	278	for (i = 0; i < queue->limit; i++) {
	279	priv_tx = queue->entries[i].priv_data;
	280	priv_tx->desc = priv_offset(queue, data_addr, i);
	281	priv_tx->data = data_addr_offset(queue, data_addr, i);
	282	priv_tx->dma = data_dma_offset(queue, data_dma, i);
95ea3627 ID	283	}
	284
	285	return 0;
	286	}
	287
181d6902 ID	288	static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
181d6902 ID	289	struct data_queue *queue)
95ea3627	290	{
181d6902 ID	291	struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
	292	struct queue_entry_priv_pci_tx *priv_tx = queue->entries[0].priv_data;
	293
	294	if (priv_tx->data)
	295	pci_free_consistent(pci_dev, dma_size(queue),
	296	priv_tx->data, priv_tx->dma);
	297	priv_tx->data = NULL;
95ea3627 ID	298	}
	299
	300	int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
	301	{
	302	struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
181d6902	303	struct data_queue *queue;
95ea3627 ID	304	int status;
	305
	306	/*
	307	* Allocate DMA
	308	*/
181d6902 ID	309	queue_for_each(rt2x00dev, queue) {
181d6902 ID	310	status = rt2x00pci_alloc_queue_dma(rt2x00dev, queue);
95ea3627 ID	311	if (status)
	312	goto exit;
	313	}
	314
	315	/*
	316	* Register interrupt handler.
	317	*/
	318	status = request_irq(pci_dev->irq, rt2x00dev->ops->lib->irq_handler,
	319	IRQF_SHARED, pci_name(pci_dev), rt2x00dev);
	320	if (status) {
	321	ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
	322	pci_dev->irq, status);
	323	return status;
	324	}
	325
	326	return 0;
	327
	328	exit:
	329	rt2x00pci_uninitialize(rt2x00dev);
	330
	331	return status;
	332	}
	333	EXPORT_SYMBOL_GPL(rt2x00pci_initialize);
	334
	335	void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
	336	{
181d6902	337	struct data_queue *queue;
95ea3627 ID	338
	339	/*
	340	* Free irq line.
	341	*/
	342	free_irq(rt2x00dev_pci(rt2x00dev)->irq, rt2x00dev);
	343
	344	/*
	345	* Free DMA
	346	*/
181d6902 ID	347	queue_for_each(rt2x00dev, queue)
181d6902 ID	348	rt2x00pci_free_queue_dma(rt2x00dev, queue);
95ea3627 ID	349	}
	350	EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);
	351
	352	/*
	353	* PCI driver handlers.
	354	*/
	355	static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
	356	{
	357	kfree(rt2x00dev->rf);
	358	rt2x00dev->rf = NULL;
	359
	360	kfree(rt2x00dev->eeprom);
	361	rt2x00dev->eeprom = NULL;
	362
	363	if (rt2x00dev->csr_addr) {
	364	iounmap(rt2x00dev->csr_addr);
	365	rt2x00dev->csr_addr = NULL;
	366	}
	367	}
	368
	369	static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
	370	{
	371	struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
	372
	373	rt2x00dev->csr_addr = ioremap(pci_resource_start(pci_dev, 0),
	374	pci_resource_len(pci_dev, 0));
	375	if (!rt2x00dev->csr_addr)
	376	goto exit;
	377
	378	rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
	379	if (!rt2x00dev->eeprom)
	380	goto exit;
	381
	382	rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
	383	if (!rt2x00dev->rf)
	384	goto exit;
	385
	386	return 0;
	387
	388	exit:
	389	ERROR_PROBE("Failed to allocate registers.\n");
	390
	391	rt2x00pci_free_reg(rt2x00dev);
	392
	393	return -ENOMEM;
	394	}
	395
	396	int rt2x00pci_probe(struct pci_dev pci_dev, const struct pci_device_id id)
	397	{
	398	struct rt2x00_ops ops = (struct rt2x00_ops )id->driver_data;
	399	struct ieee80211_hw *hw;
	400	struct rt2x00_dev *rt2x00dev;
	401	int retval;
	402
	403	retval = pci_request_regions(pci_dev, pci_name(pci_dev));
	404	if (retval) {
	405	ERROR_PROBE("PCI request regions failed.\n");
	406	return retval;
	407	}
	408
	409	retval = pci_enable_device(pci_dev);
	410	if (retval) {
	411	ERROR_PROBE("Enable device failed.\n");
	412	goto exit_release_regions;
413	}
414
415	pci_set_master(pci_dev);
416
417	if (pci_set_mwi(pci_dev))
418	ERROR_PROBE("MWI not available.\n");
419
420	if (pci_set_dma_mask(pci_dev, DMA_64BIT_MASK) &&
421	pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
422	ERROR_PROBE("PCI DMA not supported.\n");
423	retval = -EIO;
424	goto exit_disable_device;
425	}
426
427	hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
428	if (!hw) {
429	ERROR_PROBE("Failed to allocate hardware.\n");
430	retval = -ENOMEM;
431	goto exit_disable_device;
432	}
433
434	pci_set_drvdata(pci_dev, hw);
435
436	rt2x00dev = hw->priv;
437	rt2x00dev->dev = pci_dev;
438	rt2x00dev->ops = ops;
439	rt2x00dev->hw = hw;
440
441	retval = rt2x00pci_alloc_reg(rt2x00dev);
442	if (retval)
443	goto exit_free_device;
444
445	retval = rt2x00lib_probe_dev(rt2x00dev);
446	if (retval)
447	goto exit_free_reg;
448
449	return 0;
450
451	exit_free_reg:
452	rt2x00pci_free_reg(rt2x00dev);
453
454	exit_free_device:
455	ieee80211_free_hw(hw);
456
457	exit_disable_device:
458	if (retval != -EBUSY)
459	pci_disable_device(pci_dev);
460
461	exit_release_regions:
462	pci_release_regions(pci_dev);
463
464	pci_set_drvdata(pci_dev, NULL);
465
466	return retval;
467	}
468	EXPORT_SYMBOL_GPL(rt2x00pci_probe);
469
470	void rt2x00pci_remove(struct pci_dev *pci_dev)
471	{
472	struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
473	struct rt2x00_dev *rt2x00dev = hw->priv;
474
475	/*
476	* Free all allocated data.
477	*/
478	rt2x00lib_remove_dev(rt2x00dev);
479	rt2x00pci_free_reg(rt2x00dev);
480	ieee80211_free_hw(hw);
481
482	/*
483	* Free the PCI device data.
484	*/
485	pci_set_drvdata(pci_dev, NULL);
486	pci_disable_device(pci_dev);
487	pci_release_regions(pci_dev);
488	}
489	EXPORT_SYMBOL_GPL(rt2x00pci_remove);
490
491	#ifdef CONFIG_PM
492	int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state)
493	{
494	struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
495	struct rt2x00_dev *rt2x00dev = hw->priv;
496	int retval;
497
498	retval = rt2x00lib_suspend(rt2x00dev, state);
499	if (retval)
500	return retval;
501
502	rt2x00pci_free_reg(rt2x00dev);
503
504	pci_save_state(pci_dev);
505	pci_disable_device(pci_dev);
506	return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
507	}
508	EXPORT_SYMBOL_GPL(rt2x00pci_suspend);
509
510	int rt2x00pci_resume(struct pci_dev *pci_dev)
511	{
512	struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
513	struct rt2x00_dev *rt2x00dev = hw->priv;
514	int retval;
515
516	if (pci_set_power_state(pci_dev, PCI_D0) \|\|
517	pci_enable_device(pci_dev) \|\|
518	pci_restore_state(pci_dev)) {
519	ERROR(rt2x00dev, "Failed to resume device.\n");
520	return -EIO;
521	}
522
523	retval = rt2x00pci_alloc_reg(rt2x00dev);
524	if (retval)
525	return retval;
526
527	retval = rt2x00lib_resume(rt2x00dev);
528	if (retval)
529	goto exit_free_reg;
530
531	return 0;
532
533	exit_free_reg:
534	rt2x00pci_free_reg(rt2x00dev);
535
536	return retval;
537	}
538	EXPORT_SYMBOL_GPL(rt2x00pci_resume);
539	#endif /* CONFIG_PM */
540
541	/*
542	* rt2x00pci module information.
543	*/
544	MODULE_AUTHOR(DRV_PROJECT);
545	MODULE_VERSION(DRV_VERSION);
181d6902	546	MODULE_DESCRIPTION("rt2x00 pci library");
95ea3627	547	MODULE_LICENSE("GPL");