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rt2x00: Fix QOS sequence counting
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902
ID
1/*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2x00lib
23 Abstract: rt2x00 queue specific routines.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
c4da0048 28#include <linux/dma-mapping.h>
181d6902
ID
29
30#include "rt2x00.h"
31#include "rt2x00lib.h"
32
c4da0048
GW
33struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
34 struct queue_entry *entry)
239c249d 35{
239c249d
GW
36 unsigned int frame_size;
37 unsigned int reserved_size;
c4da0048
GW
38 struct sk_buff *skb;
39 struct skb_frame_desc *skbdesc;
239c249d
GW
40
41 /*
42 * The frame size includes descriptor size, because the
43 * hardware directly receive the frame into the skbuffer.
44 */
c4da0048 45 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
46
47 /*
ff352391
ID
48 * The payload should be aligned to a 4-byte boundary,
49 * this means we need at least 3 bytes for moving the frame
50 * into the correct offset.
239c249d 51 */
ff352391 52 reserved_size = 4;
239c249d
GW
53
54 /*
55 * Allocate skbuffer.
56 */
57 skb = dev_alloc_skb(frame_size + reserved_size);
58 if (!skb)
59 return NULL;
60
61 skb_reserve(skb, reserved_size);
62 skb_put(skb, frame_size);
63
c4da0048
GW
64 /*
65 * Populate skbdesc.
66 */
67 skbdesc = get_skb_frame_desc(skb);
68 memset(skbdesc, 0, sizeof(*skbdesc));
69 skbdesc->entry = entry;
70
71 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
72 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
73 skb->data,
74 skb->len,
75 DMA_FROM_DEVICE);
76 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
77 }
78
239c249d
GW
79 return skb;
80}
30caa6e3 81
c4da0048 82void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
30caa6e3 83{
c4da0048
GW
84 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
85
86 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev, skb->data, skb->len,
87 DMA_TO_DEVICE);
88 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
89}
90EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
91
92void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
93{
94 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
95
96 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
97 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
98 DMA_FROM_DEVICE);
99 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
100 }
101
102 if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
103 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
104 DMA_TO_DEVICE);
105 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
106 }
107}
c4da0048
GW
108
109void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
110{
9a613195
ID
111 if (!skb)
112 return;
113
61243d8e 114 rt2x00queue_unmap_skb(rt2x00dev, skb);
30caa6e3
GW
115 dev_kfree_skb_any(skb);
116}
239c249d 117
bd88a781
ID
118static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
119 struct txentry_desc *txdesc)
7050ec82 120{
2e92e6f2 121 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 122 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
5adf6d63 123 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
7050ec82 124 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
2e92e6f2 125 struct ieee80211_rate *rate =
e039fa4a 126 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
127 const struct rt2x00_rate *hwrate;
128 unsigned int data_length;
129 unsigned int duration;
130 unsigned int residual;
7050ec82
ID
131
132 memset(txdesc, 0, sizeof(*txdesc));
133
134 /*
135 * Initialize information from queue
136 */
137 txdesc->queue = entry->queue->qid;
138 txdesc->cw_min = entry->queue->cw_min;
139 txdesc->cw_max = entry->queue->cw_max;
140 txdesc->aifs = entry->queue->aifs;
141
142 /* Data length should be extended with 4 bytes for CRC */
143 data_length = entry->skb->len + 4;
144
7050ec82
ID
145 /*
146 * Check whether this frame is to be acked.
147 */
e039fa4a 148 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
149 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
150
151 /*
152 * Check if this is a RTS/CTS frame
153 */
ac104462
ID
154 if (ieee80211_is_rts(hdr->frame_control) ||
155 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 156 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 157 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 158 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 159 else
7050ec82 160 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 161 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 162 rate =
e039fa4a 163 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
164 }
165
166 /*
167 * Determine retry information.
168 */
e039fa4a
JB
169 txdesc->retry_limit = tx_info->control.retry_limit;
170 if (tx_info->flags & IEEE80211_TX_CTL_LONG_RETRY_LIMIT)
7050ec82
ID
171 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
172
173 /*
174 * Check if more fragments are pending
175 */
8b7b1e05 176 if (ieee80211_has_morefrags(hdr->frame_control)) {
7050ec82
ID
177 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
178 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
179 }
180
181 /*
182 * Beacons and probe responses require the tsf timestamp
183 * to be inserted into the frame.
184 */
ac104462
ID
185 if (ieee80211_is_beacon(hdr->frame_control) ||
186 ieee80211_is_probe_resp(hdr->frame_control))
7050ec82
ID
187 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
188
189 /*
190 * Determine with what IFS priority this frame should be send.
191 * Set ifs to IFS_SIFS when the this is not the first fragment,
192 * or this fragment came after RTS/CTS.
193 */
194 if (test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
195 txdesc->ifs = IFS_SIFS;
e039fa4a 196 } else if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) {
7050ec82
ID
197 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
198 txdesc->ifs = IFS_BACKOFF;
199 } else {
200 txdesc->ifs = IFS_SIFS;
201 }
202
5adf6d63
ID
203 /*
204 * Hardware should insert sequence counter.
205 * FIXME: We insert a software sequence counter first for
206 * hardware that doesn't support hardware sequence counting.
207 *
208 * This is wrong because beacons are not getting sequence
209 * numbers assigned properly.
210 *
211 * A secondary problem exists for drivers that cannot toggle
212 * sequence counting per-frame, since those will override the
213 * sequence counter given by mac80211.
214 */
215 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
216 spin_lock(&intf->lock);
217
218 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
219 intf->seqno += 0x10;
220 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
221 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
222
223 spin_unlock(&intf->lock);
224
225 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
226 }
227
7050ec82
ID
228 /*
229 * PLCP setup
230 * Length calculation depends on OFDM/CCK rate.
231 */
232 hwrate = rt2x00_get_rate(rate->hw_value);
233 txdesc->signal = hwrate->plcp;
234 txdesc->service = 0x04;
235
236 if (hwrate->flags & DEV_RATE_OFDM) {
237 __set_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags);
238
239 txdesc->length_high = (data_length >> 6) & 0x3f;
240 txdesc->length_low = data_length & 0x3f;
241 } else {
242 /*
243 * Convert length to microseconds.
244 */
245 residual = get_duration_res(data_length, hwrate->bitrate);
246 duration = get_duration(data_length, hwrate->bitrate);
247
248 if (residual != 0) {
249 duration++;
250
251 /*
252 * Check if we need to set the Length Extension
253 */
254 if (hwrate->bitrate == 110 && residual <= 30)
255 txdesc->service |= 0x80;
256 }
257
258 txdesc->length_high = (duration >> 8) & 0xff;
259 txdesc->length_low = duration & 0xff;
260
261 /*
262 * When preamble is enabled we should set the
263 * preamble bit for the signal.
264 */
265 if (rt2x00_get_rate_preamble(rate->hw_value))
266 txdesc->signal |= 0x08;
267 }
268}
7050ec82 269
bd88a781
ID
270static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
271 struct txentry_desc *txdesc)
7050ec82 272{
b869767b
ID
273 struct data_queue *queue = entry->queue;
274 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
275
276 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
277
278 /*
279 * All processing on the frame has been completed, this means
280 * it is now ready to be dumped to userspace through debugfs.
281 */
282 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
283
284 /*
b869767b
ID
285 * Check if we need to kick the queue, there are however a few rules
286 * 1) Don't kick beacon queue
287 * 2) Don't kick unless this is the last in frame in a burst.
288 * When the burst flag is set, this frame is always followed
289 * by another frame which in some way are related to eachother.
290 * This is true for fragments, RTS or CTS-to-self frames.
291 * 3) Rule 2 can be broken when the available entries
292 * in the queue are less then a certain threshold.
7050ec82 293 */
b869767b
ID
294 if (entry->queue->qid == QID_BEACON)
295 return;
296
297 if (rt2x00queue_threshold(queue) ||
298 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
299 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
7050ec82 300}
7050ec82 301
6db3786a
ID
302int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
303{
304 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
305 struct txentry_desc txdesc;
d74f5ba4 306 struct skb_frame_desc *skbdesc;
6db3786a
ID
307
308 if (unlikely(rt2x00queue_full(queue)))
309 return -EINVAL;
310
311 if (__test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
312 ERROR(queue->rt2x00dev,
313 "Arrived at non-free entry in the non-full queue %d.\n"
314 "Please file bug report to %s.\n",
315 queue->qid, DRV_PROJECT);
316 return -EINVAL;
317 }
318
319 /*
320 * Copy all TX descriptor information into txdesc,
321 * after that we are free to use the skb->cb array
322 * for our information.
323 */
324 entry->skb = skb;
325 rt2x00queue_create_tx_descriptor(entry, &txdesc);
326
d74f5ba4
ID
327 /*
328 * skb->cb array is now ours and we are free to use it.
329 */
330 skbdesc = get_skb_frame_desc(entry->skb);
331 memset(skbdesc, 0, sizeof(*skbdesc));
332 skbdesc->entry = entry;
333
6db3786a
ID
334 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) {
335 __clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
336 return -EIO;
337 }
338
d74f5ba4
ID
339 if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
340 rt2x00queue_map_txskb(queue->rt2x00dev, skb);
341
6db3786a
ID
342 __set_bit(ENTRY_DATA_PENDING, &entry->flags);
343
344 rt2x00queue_index_inc(queue, Q_INDEX);
345 rt2x00queue_write_tx_descriptor(entry, &txdesc);
346
347 return 0;
348}
349
bd88a781
ID
350int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
351 struct ieee80211_vif *vif)
352{
353 struct rt2x00_intf *intf = vif_to_intf(vif);
354 struct skb_frame_desc *skbdesc;
355 struct txentry_desc txdesc;
356 __le32 desc[16];
357
358 if (unlikely(!intf->beacon))
359 return -ENOBUFS;
360
361 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
362 if (!intf->beacon->skb)
363 return -ENOMEM;
364
365 /*
366 * Copy all TX descriptor information into txdesc,
367 * after that we are free to use the skb->cb array
368 * for our information.
369 */
370 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
371
372 /*
373 * For the descriptor we use a local array from where the
374 * driver can move it to the correct location required for
375 * the hardware.
376 */
377 memset(desc, 0, sizeof(desc));
378
379 /*
380 * Fill in skb descriptor
381 */
382 skbdesc = get_skb_frame_desc(intf->beacon->skb);
383 memset(skbdesc, 0, sizeof(*skbdesc));
384 skbdesc->desc = desc;
385 skbdesc->desc_len = intf->beacon->queue->desc_size;
386 skbdesc->entry = intf->beacon;
387
388 /*
389 * Write TX descriptor into reserved room in front of the beacon.
390 */
391 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
392
393 /*
394 * Send beacon to hardware.
395 * Also enable beacon generation, which might have been disabled
396 * by the driver during the config_beacon() callback function.
397 */
398 rt2x00dev->ops->lib->write_beacon(intf->beacon);
399 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
400
401 return 0;
402}
403
181d6902 404struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 405 const enum data_queue_qid queue)
181d6902
ID
406{
407 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
408
61448f88 409 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
181d6902
ID
410 return &rt2x00dev->tx[queue];
411
412 if (!rt2x00dev->bcn)
413 return NULL;
414
e58c6aca 415 if (queue == QID_BEACON)
181d6902 416 return &rt2x00dev->bcn[0];
e58c6aca 417 else if (queue == QID_ATIM && atim)
181d6902
ID
418 return &rt2x00dev->bcn[1];
419
420 return NULL;
421}
422EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
423
424struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
425 enum queue_index index)
426{
427 struct queue_entry *entry;
5f46c4d0 428 unsigned long irqflags;
181d6902
ID
429
430 if (unlikely(index >= Q_INDEX_MAX)) {
431 ERROR(queue->rt2x00dev,
432 "Entry requested from invalid index type (%d)\n", index);
433 return NULL;
434 }
435
5f46c4d0 436 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
437
438 entry = &queue->entries[queue->index[index]];
439
5f46c4d0 440 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
441
442 return entry;
443}
444EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
445
446void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
447{
5f46c4d0
ID
448 unsigned long irqflags;
449
181d6902
ID
450 if (unlikely(index >= Q_INDEX_MAX)) {
451 ERROR(queue->rt2x00dev,
452 "Index change on invalid index type (%d)\n", index);
453 return;
454 }
455
5f46c4d0 456 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
457
458 queue->index[index]++;
459 if (queue->index[index] >= queue->limit)
460 queue->index[index] = 0;
461
10b6b801
ID
462 if (index == Q_INDEX) {
463 queue->length++;
464 } else if (index == Q_INDEX_DONE) {
465 queue->length--;
466 queue->count ++;
467 }
181d6902 468
5f46c4d0 469 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902 470}
181d6902
ID
471
472static void rt2x00queue_reset(struct data_queue *queue)
473{
5f46c4d0
ID
474 unsigned long irqflags;
475
476 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
477
478 queue->count = 0;
479 queue->length = 0;
480 memset(queue->index, 0, sizeof(queue->index));
481
5f46c4d0 482 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
483}
484
485void rt2x00queue_init_rx(struct rt2x00_dev *rt2x00dev)
486{
487 struct data_queue *queue = rt2x00dev->rx;
488 unsigned int i;
489
490 rt2x00queue_reset(queue);
491
492 if (!rt2x00dev->ops->lib->init_rxentry)
493 return;
494
495 for (i = 0; i < queue->limit; i++)
496 rt2x00dev->ops->lib->init_rxentry(rt2x00dev,
497 &queue->entries[i]);
498}
499
500void rt2x00queue_init_tx(struct rt2x00_dev *rt2x00dev)
501{
502 struct data_queue *queue;
503 unsigned int i;
504
505 txall_queue_for_each(rt2x00dev, queue) {
506 rt2x00queue_reset(queue);
507
508 if (!rt2x00dev->ops->lib->init_txentry)
509 continue;
510
511 for (i = 0; i < queue->limit; i++)
512 rt2x00dev->ops->lib->init_txentry(rt2x00dev,
513 &queue->entries[i]);
514 }
515}
516
517static int rt2x00queue_alloc_entries(struct data_queue *queue,
518 const struct data_queue_desc *qdesc)
519{
520 struct queue_entry *entries;
521 unsigned int entry_size;
522 unsigned int i;
523
524 rt2x00queue_reset(queue);
525
526 queue->limit = qdesc->entry_num;
b869767b 527 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
528 queue->data_size = qdesc->data_size;
529 queue->desc_size = qdesc->desc_size;
530
531 /*
532 * Allocate all queue entries.
533 */
534 entry_size = sizeof(*entries) + qdesc->priv_size;
535 entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
536 if (!entries)
537 return -ENOMEM;
538
539#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
231be4e9
AB
540 ( ((char *)(__base)) + ((__limit) * (__esize)) + \
541 ((__index) * (__psize)) )
181d6902
ID
542
543 for (i = 0; i < queue->limit; i++) {
544 entries[i].flags = 0;
545 entries[i].queue = queue;
546 entries[i].skb = NULL;
547 entries[i].entry_idx = i;
548 entries[i].priv_data =
549 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
550 sizeof(*entries), qdesc->priv_size);
551 }
552
553#undef QUEUE_ENTRY_PRIV_OFFSET
554
555 queue->entries = entries;
556
557 return 0;
558}
559
c4da0048
GW
560static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
561 struct data_queue *queue)
30caa6e3
GW
562{
563 unsigned int i;
564
565 if (!queue->entries)
566 return;
567
568 for (i = 0; i < queue->limit; i++) {
569 if (queue->entries[i].skb)
c4da0048 570 rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
30caa6e3
GW
571 }
572}
573
c4da0048
GW
574static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
575 struct data_queue *queue)
30caa6e3
GW
576{
577 unsigned int i;
578 struct sk_buff *skb;
579
580 for (i = 0; i < queue->limit; i++) {
c4da0048 581 skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
30caa6e3 582 if (!skb)
61243d8e 583 return -ENOMEM;
30caa6e3
GW
584 queue->entries[i].skb = skb;
585 }
586
587 return 0;
30caa6e3
GW
588}
589
181d6902
ID
590int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
591{
592 struct data_queue *queue;
593 int status;
594
181d6902
ID
595 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
596 if (status)
597 goto exit;
598
599 tx_queue_for_each(rt2x00dev, queue) {
600 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
601 if (status)
602 goto exit;
603 }
604
605 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
606 if (status)
607 goto exit;
608
30caa6e3
GW
609 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
610 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
611 rt2x00dev->ops->atim);
612 if (status)
613 goto exit;
614 }
181d6902 615
c4da0048 616 status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
181d6902
ID
617 if (status)
618 goto exit;
619
620 return 0;
621
622exit:
623 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
624
625 rt2x00queue_uninitialize(rt2x00dev);
626
627 return status;
628}
629
630void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
631{
632 struct data_queue *queue;
633
c4da0048 634 rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
30caa6e3 635
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636 queue_for_each(rt2x00dev, queue) {
637 kfree(queue->entries);
638 queue->entries = NULL;
639 }
640}
641
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642static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
643 struct data_queue *queue, enum data_queue_qid qid)
644{
645 spin_lock_init(&queue->lock);
646
647 queue->rt2x00dev = rt2x00dev;
648 queue->qid = qid;
649 queue->aifs = 2;
650 queue->cw_min = 5;
651 queue->cw_max = 10;
652}
653
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654int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
655{
656 struct data_queue *queue;
657 enum data_queue_qid qid;
658 unsigned int req_atim =
659 !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
660
661 /*
662 * We need the following queues:
663 * RX: 1
61448f88 664 * TX: ops->tx_queues
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665 * Beacon: 1
666 * Atim: 1 (if required)
667 */
61448f88 668 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
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669
670 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
671 if (!queue) {
672 ERROR(rt2x00dev, "Queue allocation failed.\n");
673 return -ENOMEM;
674 }
675
676 /*
677 * Initialize pointers
678 */
679 rt2x00dev->rx = queue;
680 rt2x00dev->tx = &queue[1];
61448f88 681 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
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682
683 /*
684 * Initialize queue parameters.
685 * RX: qid = QID_RX
686 * TX: qid = QID_AC_BE + index
687 * TX: cw_min: 2^5 = 32.
688 * TX: cw_max: 2^10 = 1024.
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689 * BCN: qid = QID_BEACON
690 * ATIM: qid = QID_ATIM
181d6902 691 */
8f539276 692 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 693
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694 qid = QID_AC_BE;
695 tx_queue_for_each(rt2x00dev, queue)
696 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 697
565a019a 698 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
181d6902 699 if (req_atim)
565a019a 700 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
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701
702 return 0;
703}
704
705void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
706{
707 kfree(rt2x00dev->rx);
708 rt2x00dev->rx = NULL;
709 rt2x00dev->tx = NULL;
710 rt2x00dev->bcn = NULL;
711}