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rt2x00: Simplify Queue function arguments
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
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181d6902 1/*
7e613e16
ID
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
181d6902
ID
5 <http://rt2x00.serialmonkey.com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the
19 Free Software Foundation, Inc.,
20 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23/*
24 Module: rt2x00lib
25 Abstract: rt2x00 queue specific routines.
26 */
27
5a0e3ad6 28#include <linux/slab.h>
181d6902
ID
29#include <linux/kernel.h>
30#include <linux/module.h>
c4da0048 31#include <linux/dma-mapping.h>
181d6902
ID
32
33#include "rt2x00.h"
34#include "rt2x00lib.h"
35
fa69560f 36struct sk_buff *rt2x00queue_alloc_rxskb(struct queue_entry *entry)
239c249d 37{
fa69560f 38 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
c4da0048
GW
39 struct sk_buff *skb;
40 struct skb_frame_desc *skbdesc;
2bb057d0
ID
41 unsigned int frame_size;
42 unsigned int head_size = 0;
43 unsigned int tail_size = 0;
239c249d
GW
44
45 /*
46 * The frame size includes descriptor size, because the
47 * hardware directly receive the frame into the skbuffer.
48 */
c4da0048 49 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
50
51 /*
ff352391
ID
52 * The payload should be aligned to a 4-byte boundary,
53 * this means we need at least 3 bytes for moving the frame
54 * into the correct offset.
239c249d 55 */
2bb057d0
ID
56 head_size = 4;
57
58 /*
59 * For IV/EIV/ICV assembly we must make sure there is
60 * at least 8 bytes bytes available in headroom for IV/EIV
9c3444d3 61 * and 8 bytes for ICV data as tailroon.
2bb057d0 62 */
2bb057d0
ID
63 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
64 head_size += 8;
9c3444d3 65 tail_size += 8;
2bb057d0 66 }
239c249d
GW
67
68 /*
69 * Allocate skbuffer.
70 */
2bb057d0 71 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
72 if (!skb)
73 return NULL;
74
2bb057d0
ID
75 /*
76 * Make sure we not have a frame with the requested bytes
77 * available in the head and tail.
78 */
79 skb_reserve(skb, head_size);
239c249d
GW
80 skb_put(skb, frame_size);
81
c4da0048
GW
82 /*
83 * Populate skbdesc.
84 */
85 skbdesc = get_skb_frame_desc(skb);
86 memset(skbdesc, 0, sizeof(*skbdesc));
87 skbdesc->entry = entry;
88
89 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
90 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
91 skb->data,
92 skb->len,
93 DMA_FROM_DEVICE);
94 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
95 }
96
239c249d
GW
97 return skb;
98}
30caa6e3 99
fa69560f 100void rt2x00queue_map_txskb(struct queue_entry *entry)
30caa6e3 101{
fa69560f
ID
102 struct device *dev = entry->queue->rt2x00dev->dev;
103 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
c4da0048 104
3ee54a07 105 skbdesc->skb_dma =
fa69560f 106 dma_map_single(dev, entry->skb->data, entry->skb->len, DMA_TO_DEVICE);
c4da0048
GW
107 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
108}
109EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
110
fa69560f 111void rt2x00queue_unmap_skb(struct queue_entry *entry)
c4da0048 112{
fa69560f
ID
113 struct device *dev = entry->queue->rt2x00dev->dev;
114 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
c4da0048
GW
115
116 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
fa69560f 117 dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
c4da0048
GW
118 DMA_FROM_DEVICE);
119 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
546adf29 120 } else if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
fa69560f 121 dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
c4da0048
GW
122 DMA_TO_DEVICE);
123 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
124 }
125}
0b8004aa 126EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb);
c4da0048 127
fa69560f 128void rt2x00queue_free_skb(struct queue_entry *entry)
c4da0048 129{
fa69560f 130 if (!entry->skb)
9a613195
ID
131 return;
132
fa69560f
ID
133 rt2x00queue_unmap_skb(entry);
134 dev_kfree_skb_any(entry->skb);
135 entry->skb = NULL;
30caa6e3 136}
239c249d 137
daee6c09 138void rt2x00queue_align_frame(struct sk_buff *skb)
9f166171 139{
9f166171 140 unsigned int frame_length = skb->len;
daee6c09 141 unsigned int align = ALIGN_SIZE(skb, 0);
9f166171
ID
142
143 if (!align)
144 return;
145
daee6c09
ID
146 skb_push(skb, align);
147 memmove(skb->data, skb->data + align, frame_length);
148 skb_trim(skb, frame_length);
149}
150
95d69aa0 151void rt2x00queue_align_payload(struct sk_buff *skb, unsigned int header_length)
daee6c09
ID
152{
153 unsigned int frame_length = skb->len;
95d69aa0 154 unsigned int align = ALIGN_SIZE(skb, header_length);
daee6c09
ID
155
156 if (!align)
157 return;
158
159 skb_push(skb, align);
160 memmove(skb->data, skb->data + align, frame_length);
161 skb_trim(skb, frame_length);
162}
163
164void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
165{
2e331462 166 unsigned int payload_length = skb->len - header_length;
daee6c09
ID
167 unsigned int header_align = ALIGN_SIZE(skb, 0);
168 unsigned int payload_align = ALIGN_SIZE(skb, header_length);
e54be4e7 169 unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0;
daee6c09 170
2e331462
GW
171 /*
172 * Adjust the header alignment if the payload needs to be moved more
173 * than the header.
174 */
175 if (payload_align > header_align)
176 header_align += 4;
177
178 /* There is nothing to do if no alignment is needed */
179 if (!header_align)
180 return;
daee6c09 181
2e331462
GW
182 /* Reserve the amount of space needed in front of the frame */
183 skb_push(skb, header_align);
184
185 /*
186 * Move the header.
187 */
188 memmove(skb->data, skb->data + header_align, header_length);
189
190 /* Move the payload, if present and if required */
191 if (payload_length && payload_align)
daee6c09 192 memmove(skb->data + header_length + l2pad,
a5186e99 193 skb->data + header_length + l2pad + payload_align,
2e331462
GW
194 payload_length);
195
196 /* Trim the skb to the correct size */
197 skb_trim(skb, header_length + l2pad + payload_length);
9f166171
ID
198}
199
daee6c09
ID
200void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
201{
77e73d18 202 unsigned int l2pad = L2PAD_SIZE(header_length);
daee6c09 203
354e39db 204 if (!l2pad)
daee6c09
ID
205 return;
206
207 memmove(skb->data + l2pad, skb->data, header_length);
208 skb_pull(skb, l2pad);
209}
210
7b40982e
ID
211static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
212 struct txentry_desc *txdesc)
213{
214 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
215 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
216 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
217 unsigned long irqflags;
218
219 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) ||
220 unlikely(!tx_info->control.vif))
221 return;
222
223 /*
224 * Hardware should insert sequence counter.
225 * FIXME: We insert a software sequence counter first for
226 * hardware that doesn't support hardware sequence counting.
227 *
228 * This is wrong because beacons are not getting sequence
229 * numbers assigned properly.
230 *
231 * A secondary problem exists for drivers that cannot toggle
232 * sequence counting per-frame, since those will override the
233 * sequence counter given by mac80211.
234 */
235 spin_lock_irqsave(&intf->seqlock, irqflags);
236
237 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
238 intf->seqno += 0x10;
239 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
240 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
241
242 spin_unlock_irqrestore(&intf->seqlock, irqflags);
243
244 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
245}
246
247static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
248 struct txentry_desc *txdesc,
249 const struct rt2x00_rate *hwrate)
250{
251 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
252 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
253 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
254 unsigned int data_length;
255 unsigned int duration;
256 unsigned int residual;
257
258 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
259 data_length = entry->skb->len + 4;
260 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
261
262 /*
263 * PLCP setup
264 * Length calculation depends on OFDM/CCK rate.
265 */
266 txdesc->signal = hwrate->plcp;
267 txdesc->service = 0x04;
268
269 if (hwrate->flags & DEV_RATE_OFDM) {
270 txdesc->length_high = (data_length >> 6) & 0x3f;
271 txdesc->length_low = data_length & 0x3f;
272 } else {
273 /*
274 * Convert length to microseconds.
275 */
276 residual = GET_DURATION_RES(data_length, hwrate->bitrate);
277 duration = GET_DURATION(data_length, hwrate->bitrate);
278
279 if (residual != 0) {
280 duration++;
281
282 /*
283 * Check if we need to set the Length Extension
284 */
285 if (hwrate->bitrate == 110 && residual <= 30)
286 txdesc->service |= 0x80;
287 }
288
289 txdesc->length_high = (duration >> 8) & 0xff;
290 txdesc->length_low = duration & 0xff;
291
292 /*
293 * When preamble is enabled we should set the
294 * preamble bit for the signal.
295 */
296 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
297 txdesc->signal |= 0x08;
298 }
299}
300
bd88a781
ID
301static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
302 struct txentry_desc *txdesc)
7050ec82 303{
2e92e6f2 304 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 305 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
7050ec82 306 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
2e92e6f2 307 struct ieee80211_rate *rate =
e039fa4a 308 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
7050ec82 309 const struct rt2x00_rate *hwrate;
7050ec82
ID
310
311 memset(txdesc, 0, sizeof(*txdesc));
312
313 /*
314 * Initialize information from queue
315 */
a908a743 316 txdesc->qid = entry->queue->qid;
7050ec82
ID
317 txdesc->cw_min = entry->queue->cw_min;
318 txdesc->cw_max = entry->queue->cw_max;
319 txdesc->aifs = entry->queue->aifs;
320
9f166171 321 /*
df624ca5 322 * Header and frame information.
9f166171 323 */
df624ca5 324 txdesc->length = entry->skb->len;
9f166171 325 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
9f166171 326
7050ec82
ID
327 /*
328 * Check whether this frame is to be acked.
329 */
e039fa4a 330 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
331 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
332
333 /*
334 * Check if this is a RTS/CTS frame
335 */
ac104462
ID
336 if (ieee80211_is_rts(hdr->frame_control) ||
337 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 338 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 339 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 340 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 341 else
7050ec82 342 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 343 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 344 rate =
e039fa4a 345 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
346 }
347
348 /*
349 * Determine retry information.
350 */
e6a9854b 351 txdesc->retry_limit = tx_info->control.rates[0].count - 1;
42c82857 352 if (txdesc->retry_limit >= rt2x00dev->long_retry)
7050ec82
ID
353 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
354
355 /*
356 * Check if more fragments are pending
357 */
2606e422 358 if (ieee80211_has_morefrags(hdr->frame_control)) {
7050ec82
ID
359 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
360 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
361 }
362
2606e422
HS
363 /*
364 * Check if more frames (!= fragments) are pending
365 */
366 if (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES)
367 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
368
7050ec82
ID
369 /*
370 * Beacons and probe responses require the tsf timestamp
e81e0aef
AB
371 * to be inserted into the frame, except for a frame that has been injected
372 * through a monitor interface. This latter is needed for testing a
373 * monitor interface.
7050ec82 374 */
e81e0aef
AB
375 if ((ieee80211_is_beacon(hdr->frame_control) ||
376 ieee80211_is_probe_resp(hdr->frame_control)) &&
377 (!(tx_info->flags & IEEE80211_TX_CTL_INJECTED)))
7050ec82
ID
378 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
379
380 /*
381 * Determine with what IFS priority this frame should be send.
382 * Set ifs to IFS_SIFS when the this is not the first fragment,
383 * or this fragment came after RTS/CTS.
384 */
7b40982e
ID
385 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
386 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
7050ec82
ID
387 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
388 txdesc->ifs = IFS_BACKOFF;
7b40982e 389 } else
7050ec82 390 txdesc->ifs = IFS_SIFS;
7050ec82 391
076f9582
ID
392 /*
393 * Determine rate modulation.
394 */
7050ec82 395 hwrate = rt2x00_get_rate(rate->hw_value);
076f9582 396 txdesc->rate_mode = RATE_MODE_CCK;
7b40982e 397 if (hwrate->flags & DEV_RATE_OFDM)
076f9582 398 txdesc->rate_mode = RATE_MODE_OFDM;
7050ec82 399
7b40982e
ID
400 /*
401 * Apply TX descriptor handling by components
402 */
403 rt2x00crypto_create_tx_descriptor(entry, txdesc);
35f00cfc 404 rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
7b40982e
ID
405 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
406 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
7050ec82 407}
7050ec82 408
78eea11b
GW
409static int rt2x00queue_write_tx_data(struct queue_entry *entry,
410 struct txentry_desc *txdesc)
411{
412 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
413
414 /*
415 * This should not happen, we already checked the entry
416 * was ours. When the hardware disagrees there has been
417 * a queue corruption!
418 */
419 if (unlikely(rt2x00dev->ops->lib->get_entry_state &&
420 rt2x00dev->ops->lib->get_entry_state(entry))) {
421 ERROR(rt2x00dev,
422 "Corrupt queue %d, accessing entry which is not ours.\n"
423 "Please file bug report to %s.\n",
424 entry->queue->qid, DRV_PROJECT);
425 return -EINVAL;
426 }
427
428 /*
429 * Add the requested extra tx headroom in front of the skb.
430 */
431 skb_push(entry->skb, rt2x00dev->ops->extra_tx_headroom);
432 memset(entry->skb->data, 0, rt2x00dev->ops->extra_tx_headroom);
433
434 /*
76dd5ddf 435 * Call the driver's write_tx_data function, if it exists.
78eea11b 436 */
76dd5ddf
GW
437 if (rt2x00dev->ops->lib->write_tx_data)
438 rt2x00dev->ops->lib->write_tx_data(entry, txdesc);
78eea11b
GW
439
440 /*
441 * Map the skb to DMA.
442 */
443 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags))
fa69560f 444 rt2x00queue_map_txskb(entry);
78eea11b
GW
445
446 return 0;
447}
448
bd88a781
ID
449static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
450 struct txentry_desc *txdesc)
7050ec82 451{
b869767b 452 struct data_queue *queue = entry->queue;
7050ec82 453
93331458 454 queue->rt2x00dev->ops->lib->write_tx_desc(entry, txdesc);
7050ec82
ID
455
456 /*
457 * All processing on the frame has been completed, this means
458 * it is now ready to be dumped to userspace through debugfs.
459 */
93331458 460 rt2x00debug_dump_frame(queue->rt2x00dev, DUMP_FRAME_TX, entry->skb);
6295d815
GW
461}
462
463static void rt2x00queue_kick_tx_queue(struct queue_entry *entry,
464 struct txentry_desc *txdesc)
465{
466 struct data_queue *queue = entry->queue;
467 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
468
469 /*
b869767b 470 * Check if we need to kick the queue, there are however a few rules
6295d815 471 * 1) Don't kick unless this is the last in frame in a burst.
b869767b
ID
472 * When the burst flag is set, this frame is always followed
473 * by another frame which in some way are related to eachother.
474 * This is true for fragments, RTS or CTS-to-self frames.
6295d815 475 * 2) Rule 1 can be broken when the available entries
b869767b 476 * in the queue are less then a certain threshold.
7050ec82 477 */
b869767b
ID
478 if (rt2x00queue_threshold(queue) ||
479 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
93331458 480 rt2x00dev->ops->lib->kick_tx_queue(queue);
7050ec82 481}
7050ec82 482
7351c6bd
JB
483int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
484 bool local)
6db3786a 485{
e6a9854b 486 struct ieee80211_tx_info *tx_info;
6db3786a
ID
487 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
488 struct txentry_desc txdesc;
d74f5ba4 489 struct skb_frame_desc *skbdesc;
e6a9854b 490 u8 rate_idx, rate_flags;
6db3786a
ID
491
492 if (unlikely(rt2x00queue_full(queue)))
0e3de998 493 return -ENOBUFS;
6db3786a 494
c6084d5f
HS
495 if (unlikely(test_and_set_bit(ENTRY_OWNER_DEVICE_DATA,
496 &entry->flags))) {
6db3786a
ID
497 ERROR(queue->rt2x00dev,
498 "Arrived at non-free entry in the non-full queue %d.\n"
499 "Please file bug report to %s.\n",
500 queue->qid, DRV_PROJECT);
501 return -EINVAL;
502 }
503
504 /*
505 * Copy all TX descriptor information into txdesc,
506 * after that we are free to use the skb->cb array
507 * for our information.
508 */
509 entry->skb = skb;
510 rt2x00queue_create_tx_descriptor(entry, &txdesc);
511
d74f5ba4 512 /*
e6a9854b 513 * All information is retrieved from the skb->cb array,
2bb057d0 514 * now we should claim ownership of the driver part of that
e6a9854b 515 * array, preserving the bitrate index and flags.
d74f5ba4 516 */
e6a9854b
JB
517 tx_info = IEEE80211_SKB_CB(skb);
518 rate_idx = tx_info->control.rates[0].idx;
519 rate_flags = tx_info->control.rates[0].flags;
0e3de998 520 skbdesc = get_skb_frame_desc(skb);
d74f5ba4
ID
521 memset(skbdesc, 0, sizeof(*skbdesc));
522 skbdesc->entry = entry;
e6a9854b
JB
523 skbdesc->tx_rate_idx = rate_idx;
524 skbdesc->tx_rate_flags = rate_flags;
d74f5ba4 525
7351c6bd
JB
526 if (local)
527 skbdesc->flags |= SKBDESC_NOT_MAC80211;
528
2bb057d0
ID
529 /*
530 * When hardware encryption is supported, and this frame
531 * is to be encrypted, we should strip the IV/EIV data from
3ad2f3fb 532 * the frame so we can provide it to the driver separately.
2bb057d0
ID
533 */
534 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
dddfb478 535 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
3f787bd6 536 if (test_bit(DRIVER_REQUIRE_COPY_IV, &queue->rt2x00dev->flags))
9eb4e21e 537 rt2x00crypto_tx_copy_iv(skb, &txdesc);
dddfb478 538 else
9eb4e21e 539 rt2x00crypto_tx_remove_iv(skb, &txdesc);
dddfb478 540 }
2bb057d0 541
93354cbb
ID
542 /*
543 * When DMA allocation is required we should guarentee to the
544 * driver that the DMA is aligned to a 4-byte boundary.
93354cbb
ID
545 * However some drivers require L2 padding to pad the payload
546 * rather then the header. This could be a requirement for
547 * PCI and USB devices, while header alignment only is valid
548 * for PCI devices.
549 */
9f166171 550 if (test_bit(DRIVER_REQUIRE_L2PAD, &queue->rt2x00dev->flags))
daee6c09 551 rt2x00queue_insert_l2pad(entry->skb, txdesc.header_length);
93354cbb 552 else if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
daee6c09 553 rt2x00queue_align_frame(entry->skb);
9f166171 554
2bb057d0
ID
555 /*
556 * It could be possible that the queue was corrupted and this
0e3de998
ID
557 * call failed. Since we always return NETDEV_TX_OK to mac80211,
558 * this frame will simply be dropped.
2bb057d0 559 */
78eea11b 560 if (unlikely(rt2x00queue_write_tx_data(entry, &txdesc))) {
0262ab0d 561 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0 562 entry->skb = NULL;
0e3de998 563 return -EIO;
6db3786a
ID
564 }
565
0262ab0d 566 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a
ID
567
568 rt2x00queue_index_inc(queue, Q_INDEX);
569 rt2x00queue_write_tx_descriptor(entry, &txdesc);
6295d815 570 rt2x00queue_kick_tx_queue(entry, &txdesc);
6db3786a
ID
571
572 return 0;
573}
574
bd88a781 575int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
a2c9b652
ID
576 struct ieee80211_vif *vif,
577 const bool enable_beacon)
bd88a781
ID
578{
579 struct rt2x00_intf *intf = vif_to_intf(vif);
580 struct skb_frame_desc *skbdesc;
581 struct txentry_desc txdesc;
bd88a781
ID
582
583 if (unlikely(!intf->beacon))
584 return -ENOBUFS;
585
17512dc3
IP
586 mutex_lock(&intf->beacon_skb_mutex);
587
588 /*
589 * Clean up the beacon skb.
590 */
fa69560f 591 rt2x00queue_free_skb(intf->beacon);
17512dc3 592
a2c9b652 593 if (!enable_beacon) {
93331458 594 rt2x00dev->ops->lib->kill_tx_queue(intf->beacon->queue);
17512dc3 595 mutex_unlock(&intf->beacon_skb_mutex);
a2c9b652
ID
596 return 0;
597 }
598
bd88a781 599 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
17512dc3
IP
600 if (!intf->beacon->skb) {
601 mutex_unlock(&intf->beacon_skb_mutex);
bd88a781 602 return -ENOMEM;
17512dc3 603 }
bd88a781
ID
604
605 /*
606 * Copy all TX descriptor information into txdesc,
607 * after that we are free to use the skb->cb array
608 * for our information.
609 */
610 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
611
bd88a781
ID
612 /*
613 * Fill in skb descriptor
614 */
615 skbdesc = get_skb_frame_desc(intf->beacon->skb);
616 memset(skbdesc, 0, sizeof(*skbdesc));
bd88a781
ID
617 skbdesc->entry = intf->beacon;
618
bd88a781 619 /*
d61cb266 620 * Send beacon to hardware and enable beacon genaration..
bd88a781 621 */
f224f4ef 622 rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc);
bd88a781 623
17512dc3
IP
624 mutex_unlock(&intf->beacon_skb_mutex);
625
bd88a781
ID
626 return 0;
627}
628
5eb7efe8
ID
629void rt2x00queue_for_each_entry(struct data_queue *queue,
630 enum queue_index start,
631 enum queue_index end,
632 void (*fn)(struct queue_entry *entry))
633{
634 unsigned long irqflags;
635 unsigned int index_start;
636 unsigned int index_end;
637 unsigned int i;
638
639 if (unlikely(start >= Q_INDEX_MAX || end >= Q_INDEX_MAX)) {
640 ERROR(queue->rt2x00dev,
641 "Entry requested from invalid index range (%d - %d)\n",
642 start, end);
643 return;
644 }
645
646 /*
647 * Only protect the range we are going to loop over,
648 * if during our loop a extra entry is set to pending
649 * it should not be kicked during this run, since it
650 * is part of another TX operation.
651 */
652 spin_lock_irqsave(&queue->lock, irqflags);
653 index_start = queue->index[start];
654 index_end = queue->index[end];
655 spin_unlock_irqrestore(&queue->lock, irqflags);
656
657 /*
658 * Start from the TX done pointer, this guarentees that we will
659 * send out all frames in the correct order.
660 */
661 if (index_start < index_end) {
662 for (i = index_start; i < index_end; i++)
663 fn(&queue->entries[i]);
664 } else {
665 for (i = index_start; i < queue->limit; i++)
666 fn(&queue->entries[i]);
667
668 for (i = 0; i < index_end; i++)
669 fn(&queue->entries[i]);
670 }
671}
672EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry);
673
181d6902 674struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 675 const enum data_queue_qid queue)
181d6902
ID
676{
677 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
678
a2c9b652
ID
679 if (queue == QID_RX)
680 return rt2x00dev->rx;
681
61448f88 682 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
181d6902
ID
683 return &rt2x00dev->tx[queue];
684
685 if (!rt2x00dev->bcn)
686 return NULL;
687
e58c6aca 688 if (queue == QID_BEACON)
181d6902 689 return &rt2x00dev->bcn[0];
e58c6aca 690 else if (queue == QID_ATIM && atim)
181d6902
ID
691 return &rt2x00dev->bcn[1];
692
693 return NULL;
694}
695EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
696
697struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
698 enum queue_index index)
699{
700 struct queue_entry *entry;
5f46c4d0 701 unsigned long irqflags;
181d6902
ID
702
703 if (unlikely(index >= Q_INDEX_MAX)) {
704 ERROR(queue->rt2x00dev,
705 "Entry requested from invalid index type (%d)\n", index);
706 return NULL;
707 }
708
5f46c4d0 709 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
710
711 entry = &queue->entries[queue->index[index]];
712
5f46c4d0 713 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
714
715 return entry;
716}
717EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
718
719void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
720{
5f46c4d0
ID
721 unsigned long irqflags;
722
181d6902
ID
723 if (unlikely(index >= Q_INDEX_MAX)) {
724 ERROR(queue->rt2x00dev,
725 "Index change on invalid index type (%d)\n", index);
726 return;
727 }
728
5f46c4d0 729 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
730
731 queue->index[index]++;
732 if (queue->index[index] >= queue->limit)
733 queue->index[index] = 0;
734
652a9dd2
ID
735 queue->last_action[index] = jiffies;
736
10b6b801
ID
737 if (index == Q_INDEX) {
738 queue->length++;
739 } else if (index == Q_INDEX_DONE) {
740 queue->length--;
55887511 741 queue->count++;
10b6b801 742 }
181d6902 743
5f46c4d0 744 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902 745}
181d6902
ID
746
747static void rt2x00queue_reset(struct data_queue *queue)
748{
5f46c4d0 749 unsigned long irqflags;
652a9dd2 750 unsigned int i;
5f46c4d0
ID
751
752 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
753
754 queue->count = 0;
755 queue->length = 0;
652a9dd2
ID
756
757 for (i = 0; i < Q_INDEX_MAX; i++) {
758 queue->index[i] = 0;
759 queue->last_action[i] = jiffies;
760 }
181d6902 761
5f46c4d0 762 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
763}
764
a2c9b652
ID
765void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
766{
767 struct data_queue *queue;
768
769 txall_queue_for_each(rt2x00dev, queue)
93331458 770 rt2x00dev->ops->lib->kill_tx_queue(queue);
a2c9b652
ID
771}
772
798b7adb 773void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
181d6902
ID
774{
775 struct data_queue *queue;
776 unsigned int i;
777
798b7adb 778 queue_for_each(rt2x00dev, queue) {
181d6902
ID
779 rt2x00queue_reset(queue);
780
9c0ab712 781 for (i = 0; i < queue->limit; i++) {
798b7adb 782 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
7e613e16
ID
783 if (queue->qid == QID_RX)
784 rt2x00queue_index_inc(queue, Q_INDEX);
9c0ab712 785 }
181d6902
ID
786 }
787}
788
789static int rt2x00queue_alloc_entries(struct data_queue *queue,
790 const struct data_queue_desc *qdesc)
791{
792 struct queue_entry *entries;
793 unsigned int entry_size;
794 unsigned int i;
795
796 rt2x00queue_reset(queue);
797
798 queue->limit = qdesc->entry_num;
b869767b 799 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
800 queue->data_size = qdesc->data_size;
801 queue->desc_size = qdesc->desc_size;
802
803 /*
804 * Allocate all queue entries.
805 */
806 entry_size = sizeof(*entries) + qdesc->priv_size;
807 entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
808 if (!entries)
809 return -ENOMEM;
810
811#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
231be4e9
AB
812 ( ((char *)(__base)) + ((__limit) * (__esize)) + \
813 ((__index) * (__psize)) )
181d6902
ID
814
815 for (i = 0; i < queue->limit; i++) {
816 entries[i].flags = 0;
817 entries[i].queue = queue;
818 entries[i].skb = NULL;
819 entries[i].entry_idx = i;
820 entries[i].priv_data =
821 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
822 sizeof(*entries), qdesc->priv_size);
823 }
824
825#undef QUEUE_ENTRY_PRIV_OFFSET
826
827 queue->entries = entries;
828
829 return 0;
830}
831
fa69560f 832static void rt2x00queue_free_skbs(struct data_queue *queue)
30caa6e3
GW
833{
834 unsigned int i;
835
836 if (!queue->entries)
837 return;
838
839 for (i = 0; i < queue->limit; i++) {
fa69560f 840 rt2x00queue_free_skb(&queue->entries[i]);
30caa6e3
GW
841 }
842}
843
fa69560f 844static int rt2x00queue_alloc_rxskbs(struct data_queue *queue)
30caa6e3
GW
845{
846 unsigned int i;
847 struct sk_buff *skb;
848
849 for (i = 0; i < queue->limit; i++) {
fa69560f 850 skb = rt2x00queue_alloc_rxskb(&queue->entries[i]);
30caa6e3 851 if (!skb)
61243d8e 852 return -ENOMEM;
30caa6e3
GW
853 queue->entries[i].skb = skb;
854 }
855
856 return 0;
30caa6e3
GW
857}
858
181d6902
ID
859int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
860{
861 struct data_queue *queue;
862 int status;
863
181d6902
ID
864 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
865 if (status)
866 goto exit;
867
868 tx_queue_for_each(rt2x00dev, queue) {
869 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
870 if (status)
871 goto exit;
872 }
873
874 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
875 if (status)
876 goto exit;
877
30caa6e3
GW
878 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
879 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
880 rt2x00dev->ops->atim);
881 if (status)
882 goto exit;
883 }
181d6902 884
fa69560f 885 status = rt2x00queue_alloc_rxskbs(rt2x00dev->rx);
181d6902
ID
886 if (status)
887 goto exit;
888
889 return 0;
890
891exit:
892 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
893
894 rt2x00queue_uninitialize(rt2x00dev);
895
896 return status;
897}
898
899void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
900{
901 struct data_queue *queue;
902
fa69560f 903 rt2x00queue_free_skbs(rt2x00dev->rx);
30caa6e3 904
181d6902
ID
905 queue_for_each(rt2x00dev, queue) {
906 kfree(queue->entries);
907 queue->entries = NULL;
908 }
909}
910
8f539276
ID
911static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
912 struct data_queue *queue, enum data_queue_qid qid)
913{
914 spin_lock_init(&queue->lock);
915
916 queue->rt2x00dev = rt2x00dev;
917 queue->qid = qid;
2af0a570 918 queue->txop = 0;
8f539276
ID
919 queue->aifs = 2;
920 queue->cw_min = 5;
921 queue->cw_max = 10;
922}
923
181d6902
ID
924int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
925{
926 struct data_queue *queue;
927 enum data_queue_qid qid;
928 unsigned int req_atim =
929 !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
930
931 /*
932 * We need the following queues:
933 * RX: 1
61448f88 934 * TX: ops->tx_queues
181d6902
ID
935 * Beacon: 1
936 * Atim: 1 (if required)
937 */
61448f88 938 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
181d6902
ID
939
940 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
941 if (!queue) {
942 ERROR(rt2x00dev, "Queue allocation failed.\n");
943 return -ENOMEM;
944 }
945
946 /*
947 * Initialize pointers
948 */
949 rt2x00dev->rx = queue;
950 rt2x00dev->tx = &queue[1];
61448f88 951 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
181d6902
ID
952
953 /*
954 * Initialize queue parameters.
955 * RX: qid = QID_RX
956 * TX: qid = QID_AC_BE + index
957 * TX: cw_min: 2^5 = 32.
958 * TX: cw_max: 2^10 = 1024.
565a019a
ID
959 * BCN: qid = QID_BEACON
960 * ATIM: qid = QID_ATIM
181d6902 961 */
8f539276 962 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 963
8f539276
ID
964 qid = QID_AC_BE;
965 tx_queue_for_each(rt2x00dev, queue)
966 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 967
565a019a 968 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
181d6902 969 if (req_atim)
565a019a 970 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
181d6902
ID
971
972 return 0;
973}
974
975void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
976{
977 kfree(rt2x00dev->rx);
978 rt2x00dev->rx = NULL;
979 rt2x00dev->tx = NULL;
980 rt2x00dev->bcn = NULL;
981}