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181d6902 | 1 | /* |
9c9a0d14 | 2 | Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> |
181d6902 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt2x00 | |
23 | Abstract: rt2x00 queue datastructures and routines | |
24 | */ | |
25 | ||
26 | #ifndef RT2X00QUEUE_H | |
27 | #define RT2X00QUEUE_H | |
28 | ||
29 | #include <linux/prefetch.h> | |
30 | ||
31 | /** | |
49513481 | 32 | * DOC: Entry frame size |
181d6902 ID |
33 | * |
34 | * Ralink PCI devices demand the Frame size to be a multiple of 128 bytes, | |
35 | * for USB devices this restriction does not apply, but the value of | |
36 | * 2432 makes sense since it is big enough to contain the maximum fragment | |
37 | * size according to the ieee802.11 specs. | |
35f00cfc ID |
38 | * The aggregation size depends on support from the driver, but should |
39 | * be something around 3840 bytes. | |
181d6902 | 40 | */ |
35f00cfc ID |
41 | #define DATA_FRAME_SIZE 2432 |
42 | #define MGMT_FRAME_SIZE 256 | |
43 | #define AGGREGATION_SIZE 3840 | |
181d6902 ID |
44 | |
45 | /** | |
46 | * DOC: Number of entries per queue | |
47 | * | |
49513481 | 48 | * Under normal load without fragmentation, 12 entries are sufficient |
f529932c | 49 | * without the queue being filled up to the maximum. When using fragmentation |
49513481 | 50 | * and the queue threshold code, we need to add some additional margins to |
f529932c ID |
51 | * make sure the queue will never (or only under extreme load) fill up |
52 | * completely. | |
49513481 LC |
53 | * Since we don't use preallocated DMA, having a large number of queue entries |
54 | * will have minimal impact on the memory requirements for the queue. | |
181d6902 | 55 | */ |
f529932c ID |
56 | #define RX_ENTRIES 24 |
57 | #define TX_ENTRIES 24 | |
181d6902 | 58 | #define BEACON_ENTRIES 1 |
f529932c | 59 | #define ATIM_ENTRIES 8 |
181d6902 ID |
60 | |
61 | /** | |
62 | * enum data_queue_qid: Queue identification | |
e58c6aca ID |
63 | * |
64 | * @QID_AC_BE: AC BE queue | |
65 | * @QID_AC_BK: AC BK queue | |
66 | * @QID_AC_VI: AC VI queue | |
67 | * @QID_AC_VO: AC VO queue | |
68 | * @QID_HCCA: HCCA queue | |
69 | * @QID_MGMT: MGMT queue (prio queue) | |
70 | * @QID_RX: RX queue | |
71 | * @QID_OTHER: None of the above (don't use, only present for completeness) | |
72 | * @QID_BEACON: Beacon queue (value unspecified, don't send it to device) | |
73 | * @QID_ATIM: Atim queue (value unspeficied, don't send it to device) | |
181d6902 ID |
74 | */ |
75 | enum data_queue_qid { | |
76 | QID_AC_BE = 0, | |
77 | QID_AC_BK = 1, | |
78 | QID_AC_VI = 2, | |
79 | QID_AC_VO = 3, | |
80 | QID_HCCA = 4, | |
81 | QID_MGMT = 13, | |
82 | QID_RX = 14, | |
83 | QID_OTHER = 15, | |
e58c6aca ID |
84 | QID_BEACON, |
85 | QID_ATIM, | |
181d6902 ID |
86 | }; |
87 | ||
baf26a7e ID |
88 | /** |
89 | * enum skb_frame_desc_flags: Flags for &struct skb_frame_desc | |
90 | * | |
d74f5ba4 ID |
91 | * @SKBDESC_DMA_MAPPED_RX: &skb_dma field has been mapped for RX |
92 | * @SKBDESC_DMA_MAPPED_TX: &skb_dma field has been mapped for TX | |
9f166171 | 93 | * @SKBDESC_IV_STRIPPED: Frame contained a IV/EIV provided by |
2bb057d0 | 94 | * mac80211 but was stripped for processing by the driver. |
9f166171 ID |
95 | * @SKBDESC_L2_PADDED: Payload has been padded for 4-byte alignment, |
96 | * the padded bytes are located between header and payload. | |
7351c6bd JB |
97 | * @SKBDESC_NOT_MAC80211: Frame didn't originate from mac80211, |
98 | * don't try to pass it back. | |
baf26a7e | 99 | */ |
c4da0048 | 100 | enum skb_frame_desc_flags { |
2bb057d0 ID |
101 | SKBDESC_DMA_MAPPED_RX = 1 << 0, |
102 | SKBDESC_DMA_MAPPED_TX = 1 << 1, | |
9f166171 | 103 | SKBDESC_IV_STRIPPED = 1 << 2, |
7351c6bd JB |
104 | SKBDESC_L2_PADDED = 1 << 3, |
105 | SKBDESC_NOT_MAC80211 = 1 << 4, | |
c4da0048 | 106 | }; |
baf26a7e | 107 | |
181d6902 ID |
108 | /** |
109 | * struct skb_frame_desc: Descriptor information for the skb buffer | |
110 | * | |
e039fa4a JB |
111 | * This structure is placed over the driver_data array, this means that |
112 | * this structure should not exceed the size of that array (40 bytes). | |
181d6902 | 113 | * |
baf26a7e | 114 | * @flags: Frame flags, see &enum skb_frame_desc_flags. |
c4da0048 | 115 | * @desc_len: Length of the frame descriptor. |
e6a9854b JB |
116 | * @tx_rate_idx: the index of the TX rate, used for TX status reporting |
117 | * @tx_rate_flags: the TX rate flags, used for TX status reporting | |
181d6902 ID |
118 | * @desc: Pointer to descriptor part of the frame. |
119 | * Note that this pointer could point to something outside | |
120 | * of the scope of the skb->data pointer. | |
1ce9cdac | 121 | * @iv: IV/EIV data used during encryption/decryption. |
c4da0048 | 122 | * @skb_dma: (PCI-only) the DMA address associated with the sk buffer. |
181d6902 ID |
123 | * @entry: The entry to which this sk buffer belongs. |
124 | */ | |
125 | struct skb_frame_desc { | |
e6a9854b JB |
126 | u8 flags; |
127 | ||
128 | u8 desc_len; | |
129 | u8 tx_rate_idx; | |
130 | u8 tx_rate_flags; | |
181d6902 | 131 | |
c4da0048 GW |
132 | void *desc; |
133 | ||
1ce9cdac | 134 | __le32 iv[2]; |
2bb057d0 | 135 | |
c4da0048 | 136 | dma_addr_t skb_dma; |
181d6902 | 137 | |
181d6902 ID |
138 | struct queue_entry *entry; |
139 | }; | |
140 | ||
e039fa4a JB |
141 | /** |
142 | * get_skb_frame_desc - Obtain the rt2x00 frame descriptor from a sk_buff. | |
143 | * @skb: &struct sk_buff from where we obtain the &struct skb_frame_desc | |
144 | */ | |
181d6902 ID |
145 | static inline struct skb_frame_desc* get_skb_frame_desc(struct sk_buff *skb) |
146 | { | |
e039fa4a JB |
147 | BUILD_BUG_ON(sizeof(struct skb_frame_desc) > |
148 | IEEE80211_TX_INFO_DRIVER_DATA_SIZE); | |
149 | return (struct skb_frame_desc *)&IEEE80211_SKB_CB(skb)->driver_data; | |
181d6902 ID |
150 | } |
151 | ||
19d30e02 ID |
152 | /** |
153 | * enum rxdone_entry_desc_flags: Flags for &struct rxdone_entry_desc | |
154 | * | |
6c6aa3c0 ID |
155 | * @RXDONE_SIGNAL_PLCP: Signal field contains the plcp value. |
156 | * @RXDONE_SIGNAL_BITRATE: Signal field contains the bitrate value. | |
35f00cfc | 157 | * @RXDONE_SIGNAL_MCS: Signal field contains the mcs value. |
19d30e02 | 158 | * @RXDONE_MY_BSS: Does this frame originate from device's BSS. |
74415edb ID |
159 | * @RXDONE_CRYPTO_IV: Driver provided IV/EIV data. |
160 | * @RXDONE_CRYPTO_ICV: Driver provided ICV data. | |
9f166171 | 161 | * @RXDONE_L2PAD: 802.11 payload has been padded to 4-byte boundary. |
19d30e02 ID |
162 | */ |
163 | enum rxdone_entry_desc_flags { | |
35f00cfc ID |
164 | RXDONE_SIGNAL_PLCP = BIT(0), |
165 | RXDONE_SIGNAL_BITRATE = BIT(1), | |
166 | RXDONE_SIGNAL_MCS = BIT(2), | |
167 | RXDONE_MY_BSS = BIT(3), | |
168 | RXDONE_CRYPTO_IV = BIT(4), | |
169 | RXDONE_CRYPTO_ICV = BIT(5), | |
170 | RXDONE_L2PAD = BIT(6), | |
19d30e02 ID |
171 | }; |
172 | ||
b30dd5c0 ID |
173 | /** |
174 | * RXDONE_SIGNAL_MASK - Define to mask off all &rxdone_entry_desc_flags flags | |
175 | * except for the RXDONE_SIGNAL_* flags. This is useful to convert the dev_flags | |
176 | * from &rxdone_entry_desc to a signal value type. | |
177 | */ | |
178 | #define RXDONE_SIGNAL_MASK \ | |
35f00cfc | 179 | ( RXDONE_SIGNAL_PLCP | RXDONE_SIGNAL_BITRATE | RXDONE_SIGNAL_MCS ) |
b30dd5c0 | 180 | |
181d6902 ID |
181 | /** |
182 | * struct rxdone_entry_desc: RX Entry descriptor | |
183 | * | |
184 | * Summary of information that has been read from the RX frame descriptor. | |
185 | * | |
ae73e58e | 186 | * @timestamp: RX Timestamp |
181d6902 ID |
187 | * @signal: Signal of the received frame. |
188 | * @rssi: RSSI of the received frame. | |
2bdb35c7 | 189 | * @noise: Measured noise during frame reception. |
181d6902 ID |
190 | * @size: Data size of the received frame. |
191 | * @flags: MAC80211 receive flags (See &enum mac80211_rx_flags). | |
19d30e02 | 192 | * @dev_flags: Ralink receive flags (See &enum rxdone_entry_desc_flags). |
35f00cfc | 193 | * @rate_mode: Rate mode (See @enum rate_modulation). |
2bb057d0 ID |
194 | * @cipher: Cipher type used during decryption. |
195 | * @cipher_status: Decryption status. | |
1ce9cdac | 196 | * @iv: IV/EIV data used during decryption. |
2bb057d0 | 197 | * @icv: ICV data used during decryption. |
181d6902 ID |
198 | */ |
199 | struct rxdone_entry_desc { | |
ae73e58e | 200 | u64 timestamp; |
181d6902 ID |
201 | int signal; |
202 | int rssi; | |
2bdb35c7 | 203 | int noise; |
181d6902 ID |
204 | int size; |
205 | int flags; | |
19d30e02 | 206 | int dev_flags; |
35f00cfc | 207 | u16 rate_mode; |
2bb057d0 ID |
208 | u8 cipher; |
209 | u8 cipher_status; | |
210 | ||
1ce9cdac | 211 | __le32 iv[2]; |
2bb057d0 | 212 | __le32 icv; |
181d6902 ID |
213 | }; |
214 | ||
fb55f4d1 ID |
215 | /** |
216 | * enum txdone_entry_desc_flags: Flags for &struct txdone_entry_desc | |
217 | * | |
218 | * @TXDONE_UNKNOWN: Hardware could not determine success of transmission. | |
219 | * @TXDONE_SUCCESS: Frame was successfully send | |
92ed48e5 | 220 | * @TXDONE_FALLBACK: Frame was successfully send using a fallback rate. |
fb55f4d1 ID |
221 | * @TXDONE_FAILURE: Frame was not successfully send |
222 | * @TXDONE_EXCESSIVE_RETRY: In addition to &TXDONE_FAILURE, the | |
223 | * frame transmission failed due to excessive retries. | |
224 | */ | |
225 | enum txdone_entry_desc_flags { | |
f126cba4 JF |
226 | TXDONE_UNKNOWN, |
227 | TXDONE_SUCCESS, | |
92ed48e5 | 228 | TXDONE_FALLBACK, |
f126cba4 JF |
229 | TXDONE_FAILURE, |
230 | TXDONE_EXCESSIVE_RETRY, | |
fb55f4d1 ID |
231 | }; |
232 | ||
181d6902 ID |
233 | /** |
234 | * struct txdone_entry_desc: TX done entry descriptor | |
235 | * | |
236 | * Summary of information that has been read from the TX frame descriptor | |
237 | * after the device is done with transmission. | |
238 | * | |
fb55f4d1 | 239 | * @flags: TX done flags (See &enum txdone_entry_desc_flags). |
181d6902 ID |
240 | * @retry: Retry count. |
241 | */ | |
242 | struct txdone_entry_desc { | |
fb55f4d1 | 243 | unsigned long flags; |
181d6902 ID |
244 | int retry; |
245 | }; | |
246 | ||
247 | /** | |
248 | * enum txentry_desc_flags: Status flags for TX entry descriptor | |
249 | * | |
250 | * @ENTRY_TXD_RTS_FRAME: This frame is a RTS frame. | |
7050ec82 | 251 | * @ENTRY_TXD_CTS_FRAME: This frame is a CTS-to-self frame. |
5adf6d63 | 252 | * @ENTRY_TXD_GENERATE_SEQ: This frame requires sequence counter. |
61486e0f | 253 | * @ENTRY_TXD_FIRST_FRAGMENT: This is the first frame. |
181d6902 ID |
254 | * @ENTRY_TXD_MORE_FRAG: This frame is followed by another fragment. |
255 | * @ENTRY_TXD_REQ_TIMESTAMP: Require timestamp to be inserted. | |
256 | * @ENTRY_TXD_BURST: This frame belongs to the same burst event. | |
257 | * @ENTRY_TXD_ACK: An ACK is required for this frame. | |
61486e0f | 258 | * @ENTRY_TXD_RETRY_MODE: When set, the long retry count is used. |
2bb057d0 ID |
259 | * @ENTRY_TXD_ENCRYPT: This frame should be encrypted. |
260 | * @ENTRY_TXD_ENCRYPT_PAIRWISE: Use pairwise key table (instead of shared). | |
261 | * @ENTRY_TXD_ENCRYPT_IV: Generate IV/EIV in hardware. | |
262 | * @ENTRY_TXD_ENCRYPT_MMIC: Generate MIC in hardware. | |
35f00cfc ID |
263 | * @ENTRY_TXD_HT_AMPDU: This frame is part of an AMPDU. |
264 | * @ENTRY_TXD_HT_BW_40: Use 40MHz Bandwidth. | |
265 | * @ENTRY_TXD_HT_SHORT_GI: Use short GI. | |
181d6902 ID |
266 | */ |
267 | enum txentry_desc_flags { | |
268 | ENTRY_TXD_RTS_FRAME, | |
7050ec82 | 269 | ENTRY_TXD_CTS_FRAME, |
5adf6d63 | 270 | ENTRY_TXD_GENERATE_SEQ, |
61486e0f | 271 | ENTRY_TXD_FIRST_FRAGMENT, |
181d6902 ID |
272 | ENTRY_TXD_MORE_FRAG, |
273 | ENTRY_TXD_REQ_TIMESTAMP, | |
274 | ENTRY_TXD_BURST, | |
275 | ENTRY_TXD_ACK, | |
61486e0f | 276 | ENTRY_TXD_RETRY_MODE, |
2bb057d0 ID |
277 | ENTRY_TXD_ENCRYPT, |
278 | ENTRY_TXD_ENCRYPT_PAIRWISE, | |
279 | ENTRY_TXD_ENCRYPT_IV, | |
280 | ENTRY_TXD_ENCRYPT_MMIC, | |
35f00cfc ID |
281 | ENTRY_TXD_HT_AMPDU, |
282 | ENTRY_TXD_HT_BW_40, | |
283 | ENTRY_TXD_HT_SHORT_GI, | |
181d6902 ID |
284 | }; |
285 | ||
286 | /** | |
287 | * struct txentry_desc: TX Entry descriptor | |
288 | * | |
289 | * Summary of information for the frame descriptor before sending a TX frame. | |
290 | * | |
291 | * @flags: Descriptor flags (See &enum queue_entry_flags). | |
292 | * @queue: Queue identification (See &enum data_queue_qid). | |
9f166171 ID |
293 | * @header_length: Length of 802.11 header. |
294 | * @l2pad: Amount of padding to align 802.11 payload to 4-byte boundrary. | |
181d6902 ID |
295 | * @length_high: PLCP length high word. |
296 | * @length_low: PLCP length low word. | |
297 | * @signal: PLCP signal. | |
298 | * @service: PLCP service. | |
35f00cfc ID |
299 | * @msc: MCS. |
300 | * @stbc: STBC. | |
301 | * @ba_size: BA size. | |
076f9582 | 302 | * @rate_mode: Rate mode (See @enum rate_modulation). |
35f00cfc | 303 | * @mpdu_density: MDPU density. |
61486e0f | 304 | * @retry_limit: Max number of retries. |
181d6902 ID |
305 | * @aifs: AIFS value. |
306 | * @ifs: IFS value. | |
307 | * @cw_min: cwmin value. | |
308 | * @cw_max: cwmax value. | |
2bb057d0 ID |
309 | * @cipher: Cipher type used for encryption. |
310 | * @key_idx: Key index used for encryption. | |
311 | * @iv_offset: Position where IV should be inserted by hardware. | |
9eb4e21e | 312 | * @iv_len: Length of IV data. |
181d6902 ID |
313 | */ |
314 | struct txentry_desc { | |
315 | unsigned long flags; | |
316 | ||
317 | enum data_queue_qid queue; | |
318 | ||
9f166171 ID |
319 | u16 header_length; |
320 | u16 l2pad; | |
321 | ||
181d6902 ID |
322 | u16 length_high; |
323 | u16 length_low; | |
324 | u16 signal; | |
325 | u16 service; | |
326 | ||
35f00cfc ID |
327 | u16 mcs; |
328 | u16 stbc; | |
329 | u16 ba_size; | |
076f9582 | 330 | u16 rate_mode; |
35f00cfc | 331 | u16 mpdu_density; |
076f9582 | 332 | |
61486e0f ID |
333 | short retry_limit; |
334 | short aifs; | |
335 | short ifs; | |
336 | short cw_min; | |
337 | short cw_max; | |
2bb057d0 ID |
338 | |
339 | enum cipher cipher; | |
340 | u16 key_idx; | |
341 | u16 iv_offset; | |
9eb4e21e | 342 | u16 iv_len; |
181d6902 ID |
343 | }; |
344 | ||
345 | /** | |
346 | * enum queue_entry_flags: Status flags for queue entry | |
347 | * | |
348 | * @ENTRY_BCN_ASSIGNED: This entry has been assigned to an interface. | |
349 | * As long as this bit is set, this entry may only be touched | |
350 | * through the interface structure. | |
351 | * @ENTRY_OWNER_DEVICE_DATA: This entry is owned by the device for data | |
352 | * transfer (either TX or RX depending on the queue). The entry should | |
353 | * only be touched after the device has signaled it is done with it. | |
354 | * @ENTRY_OWNER_DEVICE_CRYPTO: This entry is owned by the device for data | |
355 | * encryption or decryption. The entry should only be touched after | |
356 | * the device has signaled it is done with it. | |
f019d514 ID |
357 | * @ENTRY_DATA_PENDING: This entry contains a valid frame and is waiting |
358 | * for the signal to start sending. | |
181d6902 | 359 | */ |
181d6902 ID |
360 | enum queue_entry_flags { |
361 | ENTRY_BCN_ASSIGNED, | |
362 | ENTRY_OWNER_DEVICE_DATA, | |
363 | ENTRY_OWNER_DEVICE_CRYPTO, | |
f019d514 | 364 | ENTRY_DATA_PENDING, |
181d6902 ID |
365 | }; |
366 | ||
367 | /** | |
368 | * struct queue_entry: Entry inside the &struct data_queue | |
369 | * | |
370 | * @flags: Entry flags, see &enum queue_entry_flags. | |
371 | * @queue: The data queue (&struct data_queue) to which this entry belongs. | |
372 | * @skb: The buffer which is currently being transmitted (for TX queue), | |
373 | * or used to directly recieve data in (for RX queue). | |
374 | * @entry_idx: The entry index number. | |
375 | * @priv_data: Private data belonging to this queue entry. The pointer | |
376 | * points to data specific to a particular driver and queue type. | |
377 | */ | |
378 | struct queue_entry { | |
379 | unsigned long flags; | |
380 | ||
381 | struct data_queue *queue; | |
382 | ||
383 | struct sk_buff *skb; | |
384 | ||
385 | unsigned int entry_idx; | |
386 | ||
387 | void *priv_data; | |
388 | }; | |
389 | ||
390 | /** | |
391 | * enum queue_index: Queue index type | |
392 | * | |
393 | * @Q_INDEX: Index pointer to the current entry in the queue, if this entry is | |
394 | * owned by the hardware then the queue is considered to be full. | |
395 | * @Q_INDEX_DONE: Index pointer to the next entry which will be completed by | |
396 | * the hardware and for which we need to run the txdone handler. If this | |
397 | * entry is not owned by the hardware the queue is considered to be empty. | |
398 | * @Q_INDEX_CRYPTO: Index pointer to the next entry which encryption/decription | |
399 | * will be completed by the hardware next. | |
400 | * @Q_INDEX_MAX: Keep last, used in &struct data_queue to determine the size | |
401 | * of the index array. | |
402 | */ | |
403 | enum queue_index { | |
404 | Q_INDEX, | |
405 | Q_INDEX_DONE, | |
406 | Q_INDEX_CRYPTO, | |
407 | Q_INDEX_MAX, | |
408 | }; | |
409 | ||
410 | /** | |
411 | * struct data_queue: Data queue | |
412 | * | |
413 | * @rt2x00dev: Pointer to main &struct rt2x00dev where this queue belongs to. | |
414 | * @entries: Base address of the &struct queue_entry which are | |
415 | * part of this queue. | |
416 | * @qid: The queue identification, see &enum data_queue_qid. | |
417 | * @lock: Spinlock to protect index handling. Whenever @index, @index_done or | |
418 | * @index_crypt needs to be changed this lock should be grabbed to prevent | |
419 | * index corruption due to concurrency. | |
420 | * @count: Number of frames handled in the queue. | |
421 | * @limit: Maximum number of entries in the queue. | |
b869767b | 422 | * @threshold: Minimum number of free entries before queue is kicked by force. |
181d6902 ID |
423 | * @length: Number of frames in queue. |
424 | * @index: Index pointers to entry positions in the queue, | |
425 | * use &enum queue_index to get a specific index field. | |
2af0a570 | 426 | * @txop: maximum burst time. |
181d6902 ID |
427 | * @aifs: The aifs value for outgoing frames (field ignored in RX queue). |
428 | * @cw_min: The cw min value for outgoing frames (field ignored in RX queue). | |
429 | * @cw_max: The cw max value for outgoing frames (field ignored in RX queue). | |
430 | * @data_size: Maximum data size for the frames in this queue. | |
431 | * @desc_size: Hardware descriptor size for the data in this queue. | |
f1ca2167 ID |
432 | * @usb_endpoint: Device endpoint used for communication (USB only) |
433 | * @usb_maxpacket: Max packet size for given endpoint (USB only) | |
181d6902 ID |
434 | */ |
435 | struct data_queue { | |
436 | struct rt2x00_dev *rt2x00dev; | |
437 | struct queue_entry *entries; | |
438 | ||
439 | enum data_queue_qid qid; | |
440 | ||
441 | spinlock_t lock; | |
442 | unsigned int count; | |
443 | unsigned short limit; | |
b869767b | 444 | unsigned short threshold; |
181d6902 ID |
445 | unsigned short length; |
446 | unsigned short index[Q_INDEX_MAX]; | |
447 | ||
2af0a570 | 448 | unsigned short txop; |
181d6902 ID |
449 | unsigned short aifs; |
450 | unsigned short cw_min; | |
451 | unsigned short cw_max; | |
452 | ||
453 | unsigned short data_size; | |
454 | unsigned short desc_size; | |
f1ca2167 ID |
455 | |
456 | unsigned short usb_endpoint; | |
457 | unsigned short usb_maxpacket; | |
181d6902 ID |
458 | }; |
459 | ||
460 | /** | |
461 | * struct data_queue_desc: Data queue description | |
462 | * | |
463 | * The information in this structure is used by drivers | |
464 | * to inform rt2x00lib about the creation of the data queue. | |
465 | * | |
466 | * @entry_num: Maximum number of entries for a queue. | |
467 | * @data_size: Maximum data size for the frames in this queue. | |
468 | * @desc_size: Hardware descriptor size for the data in this queue. | |
469 | * @priv_size: Size of per-queue_entry private data. | |
470 | */ | |
471 | struct data_queue_desc { | |
472 | unsigned short entry_num; | |
473 | unsigned short data_size; | |
474 | unsigned short desc_size; | |
475 | unsigned short priv_size; | |
476 | }; | |
477 | ||
478 | /** | |
479 | * queue_end - Return pointer to the last queue (HELPER MACRO). | |
480 | * @__dev: Pointer to &struct rt2x00_dev | |
481 | * | |
482 | * Using the base rx pointer and the maximum number of available queues, | |
483 | * this macro will return the address of 1 position beyond the end of the | |
484 | * queues array. | |
485 | */ | |
486 | #define queue_end(__dev) \ | |
487 | &(__dev)->rx[(__dev)->data_queues] | |
488 | ||
489 | /** | |
490 | * tx_queue_end - Return pointer to the last TX queue (HELPER MACRO). | |
491 | * @__dev: Pointer to &struct rt2x00_dev | |
492 | * | |
493 | * Using the base tx pointer and the maximum number of available TX | |
494 | * queues, this macro will return the address of 1 position beyond | |
495 | * the end of the TX queue array. | |
496 | */ | |
497 | #define tx_queue_end(__dev) \ | |
61448f88 | 498 | &(__dev)->tx[(__dev)->ops->tx_queues] |
181d6902 | 499 | |
f1ca2167 ID |
500 | /** |
501 | * queue_next - Return pointer to next queue in list (HELPER MACRO). | |
502 | * @__queue: Current queue for which we need the next queue | |
503 | * | |
504 | * Using the current queue address we take the address directly | |
505 | * after the queue to take the next queue. Note that this macro | |
506 | * should be used carefully since it does not protect against | |
507 | * moving past the end of the list. (See macros &queue_end and | |
508 | * &tx_queue_end for determining the end of the queue). | |
509 | */ | |
510 | #define queue_next(__queue) \ | |
511 | &(__queue)[1] | |
512 | ||
181d6902 ID |
513 | /** |
514 | * queue_loop - Loop through the queues within a specific range (HELPER MACRO). | |
515 | * @__entry: Pointer where the current queue entry will be stored in. | |
516 | * @__start: Start queue pointer. | |
517 | * @__end: End queue pointer. | |
518 | * | |
519 | * This macro will loop through all queues between &__start and &__end. | |
520 | */ | |
521 | #define queue_loop(__entry, __start, __end) \ | |
522 | for ((__entry) = (__start); \ | |
f1ca2167 ID |
523 | prefetch(queue_next(__entry)), (__entry) != (__end);\ |
524 | (__entry) = queue_next(__entry)) | |
181d6902 ID |
525 | |
526 | /** | |
527 | * queue_for_each - Loop through all queues | |
528 | * @__dev: Pointer to &struct rt2x00_dev | |
529 | * @__entry: Pointer where the current queue entry will be stored in. | |
530 | * | |
531 | * This macro will loop through all available queues. | |
532 | */ | |
533 | #define queue_for_each(__dev, __entry) \ | |
534 | queue_loop(__entry, (__dev)->rx, queue_end(__dev)) | |
535 | ||
536 | /** | |
537 | * tx_queue_for_each - Loop through the TX queues | |
538 | * @__dev: Pointer to &struct rt2x00_dev | |
539 | * @__entry: Pointer where the current queue entry will be stored in. | |
540 | * | |
541 | * This macro will loop through all TX related queues excluding | |
542 | * the Beacon and Atim queues. | |
543 | */ | |
544 | #define tx_queue_for_each(__dev, __entry) \ | |
545 | queue_loop(__entry, (__dev)->tx, tx_queue_end(__dev)) | |
546 | ||
547 | /** | |
548 | * txall_queue_for_each - Loop through all TX related queues | |
549 | * @__dev: Pointer to &struct rt2x00_dev | |
550 | * @__entry: Pointer where the current queue entry will be stored in. | |
551 | * | |
552 | * This macro will loop through all TX related queues including | |
553 | * the Beacon and Atim queues. | |
554 | */ | |
555 | #define txall_queue_for_each(__dev, __entry) \ | |
556 | queue_loop(__entry, (__dev)->tx, queue_end(__dev)) | |
557 | ||
558 | /** | |
559 | * rt2x00queue_empty - Check if the queue is empty. | |
560 | * @queue: Queue to check if empty. | |
561 | */ | |
562 | static inline int rt2x00queue_empty(struct data_queue *queue) | |
563 | { | |
564 | return queue->length == 0; | |
565 | } | |
566 | ||
567 | /** | |
568 | * rt2x00queue_full - Check if the queue is full. | |
569 | * @queue: Queue to check if full. | |
570 | */ | |
571 | static inline int rt2x00queue_full(struct data_queue *queue) | |
572 | { | |
573 | return queue->length == queue->limit; | |
574 | } | |
575 | ||
576 | /** | |
577 | * rt2x00queue_free - Check the number of available entries in queue. | |
578 | * @queue: Queue to check. | |
579 | */ | |
580 | static inline int rt2x00queue_available(struct data_queue *queue) | |
581 | { | |
582 | return queue->limit - queue->length; | |
583 | } | |
584 | ||
b869767b ID |
585 | /** |
586 | * rt2x00queue_threshold - Check if the queue is below threshold | |
587 | * @queue: Queue to check. | |
588 | */ | |
589 | static inline int rt2x00queue_threshold(struct data_queue *queue) | |
590 | { | |
591 | return rt2x00queue_available(queue) < queue->threshold; | |
592 | } | |
593 | ||
181d6902 | 594 | /** |
2bb057d0 ID |
595 | * _rt2x00_desc_read - Read a word from the hardware descriptor. |
596 | * @desc: Base descriptor address | |
597 | * @word: Word index from where the descriptor should be read. | |
598 | * @value: Address where the descriptor value should be written into. | |
599 | */ | |
600 | static inline void _rt2x00_desc_read(__le32 *desc, const u8 word, __le32 *value) | |
601 | { | |
602 | *value = desc[word]; | |
603 | } | |
604 | ||
605 | /** | |
606 | * rt2x00_desc_read - Read a word from the hardware descriptor, this | |
607 | * function will take care of the byte ordering. | |
181d6902 ID |
608 | * @desc: Base descriptor address |
609 | * @word: Word index from where the descriptor should be read. | |
610 | * @value: Address where the descriptor value should be written into. | |
611 | */ | |
612 | static inline void rt2x00_desc_read(__le32 *desc, const u8 word, u32 *value) | |
613 | { | |
2bb057d0 ID |
614 | __le32 tmp; |
615 | _rt2x00_desc_read(desc, word, &tmp); | |
616 | *value = le32_to_cpu(tmp); | |
617 | } | |
618 | ||
619 | /** | |
620 | * rt2x00_desc_write - write a word to the hardware descriptor, this | |
621 | * function will take care of the byte ordering. | |
622 | * @desc: Base descriptor address | |
623 | * @word: Word index from where the descriptor should be written. | |
624 | * @value: Value that should be written into the descriptor. | |
625 | */ | |
626 | static inline void _rt2x00_desc_write(__le32 *desc, const u8 word, __le32 value) | |
627 | { | |
628 | desc[word] = value; | |
181d6902 ID |
629 | } |
630 | ||
631 | /** | |
2bb057d0 | 632 | * rt2x00_desc_write - write a word to the hardware descriptor. |
181d6902 ID |
633 | * @desc: Base descriptor address |
634 | * @word: Word index from where the descriptor should be written. | |
635 | * @value: Value that should be written into the descriptor. | |
636 | */ | |
637 | static inline void rt2x00_desc_write(__le32 *desc, const u8 word, u32 value) | |
638 | { | |
2bb057d0 | 639 | _rt2x00_desc_write(desc, word, cpu_to_le32(value)); |
181d6902 ID |
640 | } |
641 | ||
642 | #endif /* RT2X00QUEUE_H */ |