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181d6902 ID |
1 | /* |
2 | Copyright (C) 2004 - 2008 rt2x00 SourceForge Project | |
3 | <http://rt2x00.serialmonkey.com> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt2x00 | |
23 | Abstract: rt2x00 queue datastructures and routines | |
24 | */ | |
25 | ||
26 | #ifndef RT2X00QUEUE_H | |
27 | #define RT2X00QUEUE_H | |
28 | ||
29 | #include <linux/prefetch.h> | |
30 | ||
31 | /** | |
32 | * DOC: Entrie frame size | |
33 | * | |
34 | * Ralink PCI devices demand the Frame size to be a multiple of 128 bytes, | |
35 | * for USB devices this restriction does not apply, but the value of | |
36 | * 2432 makes sense since it is big enough to contain the maximum fragment | |
37 | * size according to the ieee802.11 specs. | |
38 | */ | |
39 | #define DATA_FRAME_SIZE 2432 | |
40 | #define MGMT_FRAME_SIZE 256 | |
41 | ||
42 | /** | |
43 | * DOC: Number of entries per queue | |
44 | * | |
f529932c ID |
45 | * Under normal load without fragmentation 12 entries are sufficient |
46 | * without the queue being filled up to the maximum. When using fragmentation | |
47 | * and the queue threshold code we need to add some additional margins to | |
48 | * make sure the queue will never (or only under extreme load) fill up | |
49 | * completely. | |
50 | * Since we don't use preallocated DMA having a large number of queue entries | |
51 | * will have only minimal impact on the memory requirements for the queue. | |
181d6902 | 52 | */ |
f529932c ID |
53 | #define RX_ENTRIES 24 |
54 | #define TX_ENTRIES 24 | |
181d6902 | 55 | #define BEACON_ENTRIES 1 |
f529932c | 56 | #define ATIM_ENTRIES 8 |
181d6902 ID |
57 | |
58 | /** | |
59 | * enum data_queue_qid: Queue identification | |
e58c6aca ID |
60 | * |
61 | * @QID_AC_BE: AC BE queue | |
62 | * @QID_AC_BK: AC BK queue | |
63 | * @QID_AC_VI: AC VI queue | |
64 | * @QID_AC_VO: AC VO queue | |
65 | * @QID_HCCA: HCCA queue | |
66 | * @QID_MGMT: MGMT queue (prio queue) | |
67 | * @QID_RX: RX queue | |
68 | * @QID_OTHER: None of the above (don't use, only present for completeness) | |
69 | * @QID_BEACON: Beacon queue (value unspecified, don't send it to device) | |
70 | * @QID_ATIM: Atim queue (value unspeficied, don't send it to device) | |
181d6902 ID |
71 | */ |
72 | enum data_queue_qid { | |
73 | QID_AC_BE = 0, | |
74 | QID_AC_BK = 1, | |
75 | QID_AC_VI = 2, | |
76 | QID_AC_VO = 3, | |
77 | QID_HCCA = 4, | |
78 | QID_MGMT = 13, | |
79 | QID_RX = 14, | |
80 | QID_OTHER = 15, | |
e58c6aca ID |
81 | QID_BEACON, |
82 | QID_ATIM, | |
181d6902 ID |
83 | }; |
84 | ||
baf26a7e ID |
85 | /** |
86 | * enum skb_frame_desc_flags: Flags for &struct skb_frame_desc | |
87 | * | |
d74f5ba4 ID |
88 | * @SKBDESC_DMA_MAPPED_RX: &skb_dma field has been mapped for RX |
89 | * @SKBDESC_DMA_MAPPED_TX: &skb_dma field has been mapped for TX | |
2bb057d0 ID |
90 | * @FRAME_DESC_IV_STRIPPED: Frame contained a IV/EIV provided by |
91 | * mac80211 but was stripped for processing by the driver. | |
baf26a7e | 92 | */ |
c4da0048 | 93 | enum skb_frame_desc_flags { |
2bb057d0 ID |
94 | SKBDESC_DMA_MAPPED_RX = 1 << 0, |
95 | SKBDESC_DMA_MAPPED_TX = 1 << 1, | |
96 | FRAME_DESC_IV_STRIPPED = 1 << 2, | |
c4da0048 | 97 | }; |
baf26a7e | 98 | |
181d6902 ID |
99 | /** |
100 | * struct skb_frame_desc: Descriptor information for the skb buffer | |
101 | * | |
e039fa4a JB |
102 | * This structure is placed over the driver_data array, this means that |
103 | * this structure should not exceed the size of that array (40 bytes). | |
181d6902 | 104 | * |
baf26a7e | 105 | * @flags: Frame flags, see &enum skb_frame_desc_flags. |
c4da0048 | 106 | * @desc_len: Length of the frame descriptor. |
181d6902 ID |
107 | * @desc: Pointer to descriptor part of the frame. |
108 | * Note that this pointer could point to something outside | |
109 | * of the scope of the skb->data pointer. | |
2bb057d0 ID |
110 | * @iv: IV data used during encryption/decryption. |
111 | * @eiv: EIV data used during encryption/decryption. | |
c4da0048 | 112 | * @skb_dma: (PCI-only) the DMA address associated with the sk buffer. |
181d6902 ID |
113 | * @entry: The entry to which this sk buffer belongs. |
114 | */ | |
115 | struct skb_frame_desc { | |
116 | unsigned int flags; | |
117 | ||
d56d453a | 118 | unsigned int desc_len; |
c4da0048 GW |
119 | void *desc; |
120 | ||
2bb057d0 ID |
121 | __le32 iv; |
122 | __le32 eiv; | |
123 | ||
c4da0048 | 124 | dma_addr_t skb_dma; |
181d6902 | 125 | |
181d6902 ID |
126 | struct queue_entry *entry; |
127 | }; | |
128 | ||
e039fa4a JB |
129 | /** |
130 | * get_skb_frame_desc - Obtain the rt2x00 frame descriptor from a sk_buff. | |
131 | * @skb: &struct sk_buff from where we obtain the &struct skb_frame_desc | |
132 | */ | |
181d6902 ID |
133 | static inline struct skb_frame_desc* get_skb_frame_desc(struct sk_buff *skb) |
134 | { | |
e039fa4a JB |
135 | BUILD_BUG_ON(sizeof(struct skb_frame_desc) > |
136 | IEEE80211_TX_INFO_DRIVER_DATA_SIZE); | |
137 | return (struct skb_frame_desc *)&IEEE80211_SKB_CB(skb)->driver_data; | |
181d6902 ID |
138 | } |
139 | ||
19d30e02 ID |
140 | /** |
141 | * enum rxdone_entry_desc_flags: Flags for &struct rxdone_entry_desc | |
142 | * | |
143 | * @RXDONE_SIGNAL_PLCP: Does the signal field contain the plcp value, | |
144 | * or does it contain the bitrate itself. | |
145 | * @RXDONE_MY_BSS: Does this frame originate from device's BSS. | |
146 | */ | |
147 | enum rxdone_entry_desc_flags { | |
148 | RXDONE_SIGNAL_PLCP = 1 << 0, | |
149 | RXDONE_MY_BSS = 1 << 1, | |
150 | }; | |
151 | ||
181d6902 ID |
152 | /** |
153 | * struct rxdone_entry_desc: RX Entry descriptor | |
154 | * | |
155 | * Summary of information that has been read from the RX frame descriptor. | |
156 | * | |
ae73e58e | 157 | * @timestamp: RX Timestamp |
181d6902 ID |
158 | * @signal: Signal of the received frame. |
159 | * @rssi: RSSI of the received frame. | |
181d6902 ID |
160 | * @size: Data size of the received frame. |
161 | * @flags: MAC80211 receive flags (See &enum mac80211_rx_flags). | |
19d30e02 | 162 | * @dev_flags: Ralink receive flags (See &enum rxdone_entry_desc_flags). |
2bb057d0 ID |
163 | * @cipher: Cipher type used during decryption. |
164 | * @cipher_status: Decryption status. | |
165 | * @iv: IV data used during decryption. | |
166 | * @eiv: EIV data used during decryption. | |
167 | * @icv: ICV data used during decryption. | |
181d6902 ID |
168 | */ |
169 | struct rxdone_entry_desc { | |
ae73e58e | 170 | u64 timestamp; |
181d6902 ID |
171 | int signal; |
172 | int rssi; | |
181d6902 ID |
173 | int size; |
174 | int flags; | |
19d30e02 | 175 | int dev_flags; |
2bb057d0 ID |
176 | u8 cipher; |
177 | u8 cipher_status; | |
178 | ||
179 | __le32 iv; | |
180 | __le32 eiv; | |
181 | __le32 icv; | |
181d6902 ID |
182 | }; |
183 | ||
fb55f4d1 ID |
184 | /** |
185 | * enum txdone_entry_desc_flags: Flags for &struct txdone_entry_desc | |
186 | * | |
187 | * @TXDONE_UNKNOWN: Hardware could not determine success of transmission. | |
188 | * @TXDONE_SUCCESS: Frame was successfully send | |
189 | * @TXDONE_FAILURE: Frame was not successfully send | |
190 | * @TXDONE_EXCESSIVE_RETRY: In addition to &TXDONE_FAILURE, the | |
191 | * frame transmission failed due to excessive retries. | |
192 | */ | |
193 | enum txdone_entry_desc_flags { | |
f126cba4 JF |
194 | TXDONE_UNKNOWN, |
195 | TXDONE_SUCCESS, | |
196 | TXDONE_FAILURE, | |
197 | TXDONE_EXCESSIVE_RETRY, | |
fb55f4d1 ID |
198 | }; |
199 | ||
181d6902 ID |
200 | /** |
201 | * struct txdone_entry_desc: TX done entry descriptor | |
202 | * | |
203 | * Summary of information that has been read from the TX frame descriptor | |
204 | * after the device is done with transmission. | |
205 | * | |
fb55f4d1 | 206 | * @flags: TX done flags (See &enum txdone_entry_desc_flags). |
181d6902 ID |
207 | * @retry: Retry count. |
208 | */ | |
209 | struct txdone_entry_desc { | |
fb55f4d1 | 210 | unsigned long flags; |
181d6902 ID |
211 | int retry; |
212 | }; | |
213 | ||
214 | /** | |
215 | * enum txentry_desc_flags: Status flags for TX entry descriptor | |
216 | * | |
217 | * @ENTRY_TXD_RTS_FRAME: This frame is a RTS frame. | |
7050ec82 | 218 | * @ENTRY_TXD_CTS_FRAME: This frame is a CTS-to-self frame. |
181d6902 | 219 | * @ENTRY_TXD_OFDM_RATE: This frame is send out with an OFDM rate. |
5adf6d63 | 220 | * @ENTRY_TXD_GENERATE_SEQ: This frame requires sequence counter. |
61486e0f | 221 | * @ENTRY_TXD_FIRST_FRAGMENT: This is the first frame. |
181d6902 ID |
222 | * @ENTRY_TXD_MORE_FRAG: This frame is followed by another fragment. |
223 | * @ENTRY_TXD_REQ_TIMESTAMP: Require timestamp to be inserted. | |
224 | * @ENTRY_TXD_BURST: This frame belongs to the same burst event. | |
225 | * @ENTRY_TXD_ACK: An ACK is required for this frame. | |
61486e0f | 226 | * @ENTRY_TXD_RETRY_MODE: When set, the long retry count is used. |
2bb057d0 ID |
227 | * @ENTRY_TXD_ENCRYPT: This frame should be encrypted. |
228 | * @ENTRY_TXD_ENCRYPT_PAIRWISE: Use pairwise key table (instead of shared). | |
229 | * @ENTRY_TXD_ENCRYPT_IV: Generate IV/EIV in hardware. | |
230 | * @ENTRY_TXD_ENCRYPT_MMIC: Generate MIC in hardware. | |
181d6902 ID |
231 | */ |
232 | enum txentry_desc_flags { | |
233 | ENTRY_TXD_RTS_FRAME, | |
7050ec82 | 234 | ENTRY_TXD_CTS_FRAME, |
181d6902 | 235 | ENTRY_TXD_OFDM_RATE, |
5adf6d63 | 236 | ENTRY_TXD_GENERATE_SEQ, |
61486e0f | 237 | ENTRY_TXD_FIRST_FRAGMENT, |
181d6902 ID |
238 | ENTRY_TXD_MORE_FRAG, |
239 | ENTRY_TXD_REQ_TIMESTAMP, | |
240 | ENTRY_TXD_BURST, | |
241 | ENTRY_TXD_ACK, | |
61486e0f | 242 | ENTRY_TXD_RETRY_MODE, |
2bb057d0 ID |
243 | ENTRY_TXD_ENCRYPT, |
244 | ENTRY_TXD_ENCRYPT_PAIRWISE, | |
245 | ENTRY_TXD_ENCRYPT_IV, | |
246 | ENTRY_TXD_ENCRYPT_MMIC, | |
181d6902 ID |
247 | }; |
248 | ||
249 | /** | |
250 | * struct txentry_desc: TX Entry descriptor | |
251 | * | |
252 | * Summary of information for the frame descriptor before sending a TX frame. | |
253 | * | |
254 | * @flags: Descriptor flags (See &enum queue_entry_flags). | |
255 | * @queue: Queue identification (See &enum data_queue_qid). | |
256 | * @length_high: PLCP length high word. | |
257 | * @length_low: PLCP length low word. | |
258 | * @signal: PLCP signal. | |
259 | * @service: PLCP service. | |
61486e0f | 260 | * @retry_limit: Max number of retries. |
181d6902 ID |
261 | * @aifs: AIFS value. |
262 | * @ifs: IFS value. | |
263 | * @cw_min: cwmin value. | |
264 | * @cw_max: cwmax value. | |
2bb057d0 ID |
265 | * @cipher: Cipher type used for encryption. |
266 | * @key_idx: Key index used for encryption. | |
267 | * @iv_offset: Position where IV should be inserted by hardware. | |
181d6902 ID |
268 | */ |
269 | struct txentry_desc { | |
270 | unsigned long flags; | |
271 | ||
272 | enum data_queue_qid queue; | |
273 | ||
274 | u16 length_high; | |
275 | u16 length_low; | |
276 | u16 signal; | |
277 | u16 service; | |
278 | ||
61486e0f ID |
279 | short retry_limit; |
280 | short aifs; | |
281 | short ifs; | |
282 | short cw_min; | |
283 | short cw_max; | |
2bb057d0 ID |
284 | |
285 | enum cipher cipher; | |
286 | u16 key_idx; | |
287 | u16 iv_offset; | |
181d6902 ID |
288 | }; |
289 | ||
290 | /** | |
291 | * enum queue_entry_flags: Status flags for queue entry | |
292 | * | |
293 | * @ENTRY_BCN_ASSIGNED: This entry has been assigned to an interface. | |
294 | * As long as this bit is set, this entry may only be touched | |
295 | * through the interface structure. | |
296 | * @ENTRY_OWNER_DEVICE_DATA: This entry is owned by the device for data | |
297 | * transfer (either TX or RX depending on the queue). The entry should | |
298 | * only be touched after the device has signaled it is done with it. | |
299 | * @ENTRY_OWNER_DEVICE_CRYPTO: This entry is owned by the device for data | |
300 | * encryption or decryption. The entry should only be touched after | |
301 | * the device has signaled it is done with it. | |
f019d514 ID |
302 | * @ENTRY_DATA_PENDING: This entry contains a valid frame and is waiting |
303 | * for the signal to start sending. | |
181d6902 | 304 | */ |
181d6902 ID |
305 | enum queue_entry_flags { |
306 | ENTRY_BCN_ASSIGNED, | |
307 | ENTRY_OWNER_DEVICE_DATA, | |
308 | ENTRY_OWNER_DEVICE_CRYPTO, | |
f019d514 | 309 | ENTRY_DATA_PENDING, |
181d6902 ID |
310 | }; |
311 | ||
312 | /** | |
313 | * struct queue_entry: Entry inside the &struct data_queue | |
314 | * | |
315 | * @flags: Entry flags, see &enum queue_entry_flags. | |
316 | * @queue: The data queue (&struct data_queue) to which this entry belongs. | |
317 | * @skb: The buffer which is currently being transmitted (for TX queue), | |
318 | * or used to directly recieve data in (for RX queue). | |
319 | * @entry_idx: The entry index number. | |
320 | * @priv_data: Private data belonging to this queue entry. The pointer | |
321 | * points to data specific to a particular driver and queue type. | |
322 | */ | |
323 | struct queue_entry { | |
324 | unsigned long flags; | |
325 | ||
326 | struct data_queue *queue; | |
327 | ||
328 | struct sk_buff *skb; | |
329 | ||
330 | unsigned int entry_idx; | |
331 | ||
332 | void *priv_data; | |
333 | }; | |
334 | ||
335 | /** | |
336 | * enum queue_index: Queue index type | |
337 | * | |
338 | * @Q_INDEX: Index pointer to the current entry in the queue, if this entry is | |
339 | * owned by the hardware then the queue is considered to be full. | |
340 | * @Q_INDEX_DONE: Index pointer to the next entry which will be completed by | |
341 | * the hardware and for which we need to run the txdone handler. If this | |
342 | * entry is not owned by the hardware the queue is considered to be empty. | |
343 | * @Q_INDEX_CRYPTO: Index pointer to the next entry which encryption/decription | |
344 | * will be completed by the hardware next. | |
345 | * @Q_INDEX_MAX: Keep last, used in &struct data_queue to determine the size | |
346 | * of the index array. | |
347 | */ | |
348 | enum queue_index { | |
349 | Q_INDEX, | |
350 | Q_INDEX_DONE, | |
351 | Q_INDEX_CRYPTO, | |
352 | Q_INDEX_MAX, | |
353 | }; | |
354 | ||
355 | /** | |
356 | * struct data_queue: Data queue | |
357 | * | |
358 | * @rt2x00dev: Pointer to main &struct rt2x00dev where this queue belongs to. | |
359 | * @entries: Base address of the &struct queue_entry which are | |
360 | * part of this queue. | |
361 | * @qid: The queue identification, see &enum data_queue_qid. | |
362 | * @lock: Spinlock to protect index handling. Whenever @index, @index_done or | |
363 | * @index_crypt needs to be changed this lock should be grabbed to prevent | |
364 | * index corruption due to concurrency. | |
365 | * @count: Number of frames handled in the queue. | |
366 | * @limit: Maximum number of entries in the queue. | |
b869767b | 367 | * @threshold: Minimum number of free entries before queue is kicked by force. |
181d6902 ID |
368 | * @length: Number of frames in queue. |
369 | * @index: Index pointers to entry positions in the queue, | |
370 | * use &enum queue_index to get a specific index field. | |
2af0a570 | 371 | * @txop: maximum burst time. |
181d6902 ID |
372 | * @aifs: The aifs value for outgoing frames (field ignored in RX queue). |
373 | * @cw_min: The cw min value for outgoing frames (field ignored in RX queue). | |
374 | * @cw_max: The cw max value for outgoing frames (field ignored in RX queue). | |
375 | * @data_size: Maximum data size for the frames in this queue. | |
376 | * @desc_size: Hardware descriptor size for the data in this queue. | |
377 | */ | |
378 | struct data_queue { | |
379 | struct rt2x00_dev *rt2x00dev; | |
380 | struct queue_entry *entries; | |
381 | ||
382 | enum data_queue_qid qid; | |
383 | ||
384 | spinlock_t lock; | |
385 | unsigned int count; | |
386 | unsigned short limit; | |
b869767b | 387 | unsigned short threshold; |
181d6902 ID |
388 | unsigned short length; |
389 | unsigned short index[Q_INDEX_MAX]; | |
390 | ||
2af0a570 | 391 | unsigned short txop; |
181d6902 ID |
392 | unsigned short aifs; |
393 | unsigned short cw_min; | |
394 | unsigned short cw_max; | |
395 | ||
396 | unsigned short data_size; | |
397 | unsigned short desc_size; | |
398 | }; | |
399 | ||
400 | /** | |
401 | * struct data_queue_desc: Data queue description | |
402 | * | |
403 | * The information in this structure is used by drivers | |
404 | * to inform rt2x00lib about the creation of the data queue. | |
405 | * | |
406 | * @entry_num: Maximum number of entries for a queue. | |
407 | * @data_size: Maximum data size for the frames in this queue. | |
408 | * @desc_size: Hardware descriptor size for the data in this queue. | |
409 | * @priv_size: Size of per-queue_entry private data. | |
410 | */ | |
411 | struct data_queue_desc { | |
412 | unsigned short entry_num; | |
413 | unsigned short data_size; | |
414 | unsigned short desc_size; | |
415 | unsigned short priv_size; | |
416 | }; | |
417 | ||
418 | /** | |
419 | * queue_end - Return pointer to the last queue (HELPER MACRO). | |
420 | * @__dev: Pointer to &struct rt2x00_dev | |
421 | * | |
422 | * Using the base rx pointer and the maximum number of available queues, | |
423 | * this macro will return the address of 1 position beyond the end of the | |
424 | * queues array. | |
425 | */ | |
426 | #define queue_end(__dev) \ | |
427 | &(__dev)->rx[(__dev)->data_queues] | |
428 | ||
429 | /** | |
430 | * tx_queue_end - Return pointer to the last TX queue (HELPER MACRO). | |
431 | * @__dev: Pointer to &struct rt2x00_dev | |
432 | * | |
433 | * Using the base tx pointer and the maximum number of available TX | |
434 | * queues, this macro will return the address of 1 position beyond | |
435 | * the end of the TX queue array. | |
436 | */ | |
437 | #define tx_queue_end(__dev) \ | |
61448f88 | 438 | &(__dev)->tx[(__dev)->ops->tx_queues] |
181d6902 ID |
439 | |
440 | /** | |
441 | * queue_loop - Loop through the queues within a specific range (HELPER MACRO). | |
442 | * @__entry: Pointer where the current queue entry will be stored in. | |
443 | * @__start: Start queue pointer. | |
444 | * @__end: End queue pointer. | |
445 | * | |
446 | * This macro will loop through all queues between &__start and &__end. | |
447 | */ | |
448 | #define queue_loop(__entry, __start, __end) \ | |
449 | for ((__entry) = (__start); \ | |
450 | prefetch(&(__entry)[1]), (__entry) != (__end); \ | |
451 | (__entry) = &(__entry)[1]) | |
452 | ||
453 | /** | |
454 | * queue_for_each - Loop through all queues | |
455 | * @__dev: Pointer to &struct rt2x00_dev | |
456 | * @__entry: Pointer where the current queue entry will be stored in. | |
457 | * | |
458 | * This macro will loop through all available queues. | |
459 | */ | |
460 | #define queue_for_each(__dev, __entry) \ | |
461 | queue_loop(__entry, (__dev)->rx, queue_end(__dev)) | |
462 | ||
463 | /** | |
464 | * tx_queue_for_each - Loop through the TX queues | |
465 | * @__dev: Pointer to &struct rt2x00_dev | |
466 | * @__entry: Pointer where the current queue entry will be stored in. | |
467 | * | |
468 | * This macro will loop through all TX related queues excluding | |
469 | * the Beacon and Atim queues. | |
470 | */ | |
471 | #define tx_queue_for_each(__dev, __entry) \ | |
472 | queue_loop(__entry, (__dev)->tx, tx_queue_end(__dev)) | |
473 | ||
474 | /** | |
475 | * txall_queue_for_each - Loop through all TX related queues | |
476 | * @__dev: Pointer to &struct rt2x00_dev | |
477 | * @__entry: Pointer where the current queue entry will be stored in. | |
478 | * | |
479 | * This macro will loop through all TX related queues including | |
480 | * the Beacon and Atim queues. | |
481 | */ | |
482 | #define txall_queue_for_each(__dev, __entry) \ | |
483 | queue_loop(__entry, (__dev)->tx, queue_end(__dev)) | |
484 | ||
485 | /** | |
486 | * rt2x00queue_empty - Check if the queue is empty. | |
487 | * @queue: Queue to check if empty. | |
488 | */ | |
489 | static inline int rt2x00queue_empty(struct data_queue *queue) | |
490 | { | |
491 | return queue->length == 0; | |
492 | } | |
493 | ||
494 | /** | |
495 | * rt2x00queue_full - Check if the queue is full. | |
496 | * @queue: Queue to check if full. | |
497 | */ | |
498 | static inline int rt2x00queue_full(struct data_queue *queue) | |
499 | { | |
500 | return queue->length == queue->limit; | |
501 | } | |
502 | ||
503 | /** | |
504 | * rt2x00queue_free - Check the number of available entries in queue. | |
505 | * @queue: Queue to check. | |
506 | */ | |
507 | static inline int rt2x00queue_available(struct data_queue *queue) | |
508 | { | |
509 | return queue->limit - queue->length; | |
510 | } | |
511 | ||
b869767b ID |
512 | /** |
513 | * rt2x00queue_threshold - Check if the queue is below threshold | |
514 | * @queue: Queue to check. | |
515 | */ | |
516 | static inline int rt2x00queue_threshold(struct data_queue *queue) | |
517 | { | |
518 | return rt2x00queue_available(queue) < queue->threshold; | |
519 | } | |
520 | ||
181d6902 | 521 | /** |
2bb057d0 ID |
522 | * _rt2x00_desc_read - Read a word from the hardware descriptor. |
523 | * @desc: Base descriptor address | |
524 | * @word: Word index from where the descriptor should be read. | |
525 | * @value: Address where the descriptor value should be written into. | |
526 | */ | |
527 | static inline void _rt2x00_desc_read(__le32 *desc, const u8 word, __le32 *value) | |
528 | { | |
529 | *value = desc[word]; | |
530 | } | |
531 | ||
532 | /** | |
533 | * rt2x00_desc_read - Read a word from the hardware descriptor, this | |
534 | * function will take care of the byte ordering. | |
181d6902 ID |
535 | * @desc: Base descriptor address |
536 | * @word: Word index from where the descriptor should be read. | |
537 | * @value: Address where the descriptor value should be written into. | |
538 | */ | |
539 | static inline void rt2x00_desc_read(__le32 *desc, const u8 word, u32 *value) | |
540 | { | |
2bb057d0 ID |
541 | __le32 tmp; |
542 | _rt2x00_desc_read(desc, word, &tmp); | |
543 | *value = le32_to_cpu(tmp); | |
544 | } | |
545 | ||
546 | /** | |
547 | * rt2x00_desc_write - write a word to the hardware descriptor, this | |
548 | * function will take care of the byte ordering. | |
549 | * @desc: Base descriptor address | |
550 | * @word: Word index from where the descriptor should be written. | |
551 | * @value: Value that should be written into the descriptor. | |
552 | */ | |
553 | static inline void _rt2x00_desc_write(__le32 *desc, const u8 word, __le32 value) | |
554 | { | |
555 | desc[word] = value; | |
181d6902 ID |
556 | } |
557 | ||
558 | /** | |
2bb057d0 | 559 | * rt2x00_desc_write - write a word to the hardware descriptor. |
181d6902 ID |
560 | * @desc: Base descriptor address |
561 | * @word: Word index from where the descriptor should be written. | |
562 | * @value: Value that should be written into the descriptor. | |
563 | */ | |
564 | static inline void rt2x00_desc_write(__le32 *desc, const u8 word, u32 value) | |
565 | { | |
2bb057d0 | 566 | _rt2x00_desc_write(desc, word, cpu_to_le32(value)); |
181d6902 ID |
567 | } |
568 | ||
569 | #endif /* RT2X00QUEUE_H */ |