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rt2x00: Add dev_flags to rx descriptor
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/eeprom_93cx6.h>
35
36#include "rt2x00.h"
37#include "rt2x00pci.h"
38#include "rt61pci.h"
39
40/*
41 * Register access.
42 * BBP and RF register require indirect register access,
43 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attampt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
50 */
0e14f6d3 51static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 52{
53 u32 reg;
54 unsigned int i;
55
56 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
57 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
58 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
59 break;
60 udelay(REGISTER_BUSY_DELAY);
61 }
62
63 return reg;
64}
65
0e14f6d3 66static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 67 const unsigned int word, const u8 value)
68{
69 u32 reg;
70
71 /*
72 * Wait until the BBP becomes ready.
73 */
74 reg = rt61pci_bbp_check(rt2x00dev);
75 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
76 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
77 return;
78 }
79
80 /*
81 * Write the data into the BBP.
82 */
83 reg = 0;
84 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
85 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
86 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
87 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
88
89 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
90}
91
0e14f6d3 92static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 93 const unsigned int word, u8 *value)
94{
95 u32 reg;
96
97 /*
98 * Wait until the BBP becomes ready.
99 */
100 reg = rt61pci_bbp_check(rt2x00dev);
101 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
102 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
103 return;
104 }
105
106 /*
107 * Write the request into the BBP.
108 */
109 reg = 0;
110 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
111 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
112 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
113
114 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
115
116 /*
117 * Wait until the BBP becomes ready.
118 */
119 reg = rt61pci_bbp_check(rt2x00dev);
120 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
121 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
122 *value = 0xff;
123 return;
124 }
125
126 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
127}
128
0e14f6d3 129static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 130 const unsigned int word, const u32 value)
131{
132 u32 reg;
133 unsigned int i;
134
135 if (!word)
136 return;
137
138 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
139 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
140 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
141 goto rf_write;
142 udelay(REGISTER_BUSY_DELAY);
143 }
144
145 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
146 return;
147
148rf_write:
149 reg = 0;
150 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
151 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
152 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
153 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
154
155 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
156 rt2x00_rf_write(rt2x00dev, word, value);
157}
158
a9450b70
ID		 159#ifdef CONFIG_RT61PCI_LEDS
160/*
161 * This function is only called from rt61pci_led_brightness()
162 * make gcc happy by placing this function inside the
163 * same ifdef statement as the caller.
164 */
0e14f6d3 165static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 166 const u8 command, const u8 token,
167 const u8 arg0, const u8 arg1)
168{
169 u32 reg;
170
171 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
172
173 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
174 ERROR(rt2x00dev, "mcu request error. "
175 "Request 0x%02x failed for token 0x%02x.\n",
176 command, token);
177 return;
178 }
179
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
181 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
182 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
183 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
184 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
185
186 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
187 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
188 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
189 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
190}
a9450b70 191#endif /* CONFIG_RT61PCI_LEDS */
95ea3627
ID		 192
193static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
194{
195 struct rt2x00_dev *rt2x00dev = eeprom->data;
196 u32 reg;
197
198 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
199
200 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
201 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
202 eeprom->reg_data_clock =
203 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
204 eeprom->reg_chip_select =
205 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
206}
207
208static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
209{
210 struct rt2x00_dev *rt2x00dev = eeprom->data;
211 u32 reg = 0;
212
213 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
214 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
215 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
216 !!eeprom->reg_data_clock);
217 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
218 !!eeprom->reg_chip_select);
219
220 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
221}
222
223#ifdef CONFIG_RT2X00_LIB_DEBUGFS
224#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
225
0e14f6d3 226static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 227 const unsigned int word, u32 *data)
228{
229 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
230}
231
0e14f6d3 232static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 233 const unsigned int word, u32 data)
234{
235 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
236}
237
238static const struct rt2x00debug rt61pci_rt2x00debug = {
239 .owner = THIS_MODULE,
240 .csr = {
241 .read = rt61pci_read_csr,
242 .write = rt61pci_write_csr,
243 .word_size = sizeof(u32),
244 .word_count = CSR_REG_SIZE / sizeof(u32),
245 },
246 .eeprom = {
247 .read = rt2x00_eeprom_read,
248 .write = rt2x00_eeprom_write,
249 .word_size = sizeof(u16),
250 .word_count = EEPROM_SIZE / sizeof(u16),
251 },
252 .bbp = {
253 .read = rt61pci_bbp_read,
254 .write = rt61pci_bbp_write,
255 .word_size = sizeof(u8),
256 .word_count = BBP_SIZE / sizeof(u8),
257 },
258 .rf = {
259 .read = rt2x00_rf_read,
260 .write = rt61pci_rf_write,
261 .word_size = sizeof(u32),
262 .word_count = RF_SIZE / sizeof(u32),
263 },
264};
265#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
266
267#ifdef CONFIG_RT61PCI_RFKILL
268static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
269{
270 u32 reg;
271
272 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 273 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 274}
81873e9c
ID		 275#else
276#define rt61pci_rfkill_poll NULL
dcf5475b 277#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627 278
a9450b70
ID		 279#ifdef CONFIG_RT61PCI_LEDS
280static void rt61pci_led_brightness(struct led_classdev *led_cdev,
281 enum led_brightness brightness)
282{
283 struct rt2x00_led *led =
284 container_of(led_cdev, struct rt2x00_led, led_dev);
285 unsigned int enabled = brightness != LED_OFF;
286 unsigned int a_mode =
287 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
288 unsigned int bg_mode =
289 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
290
291 if (led->type == LED_TYPE_RADIO) {
292 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
293 MCU_LEDCS_RADIO_STATUS, enabled);
294
295 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
296 (led->rt2x00dev->led_mcu_reg & 0xff),
297 ((led->rt2x00dev->led_mcu_reg >> 8)));
298 } else if (led->type == LED_TYPE_ASSOC) {
299 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
300 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
301 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
302 MCU_LEDCS_LINK_A_STATUS, a_mode);
303
304 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
305 (led->rt2x00dev->led_mcu_reg & 0xff),
306 ((led->rt2x00dev->led_mcu_reg >> 8)));
307 } else if (led->type == LED_TYPE_QUALITY) {
308 /*
309 * The brightness is divided into 6 levels (0 - 5),
310 * this means we need to convert the brightness
311 * argument into the matching level within that range.
312 */
313 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
314 brightness / (LED_FULL / 6), 0);
315 }
316}
317#else
318#define rt61pci_led_brightness NULL
319#endif /* CONFIG_RT61PCI_LEDS */
320
95ea3627
ID		 321/*
322 * Configuration handlers.
323 */
6bb40dd1
ID		 324static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
325 struct rt2x00_intf *intf,
326 struct rt2x00intf_conf *conf,
327 const unsigned int flags)
95ea3627 328{
6bb40dd1
ID		 329 unsigned int beacon_base;
330 u32 reg;
95ea3627 331
6bb40dd1
ID		 332 if (flags & CONFIG_UPDATE_TYPE) {
333 /*
334 * Clear current synchronisation setup.
335 * For the Beacon base registers we only need to clear
336 * the first byte since that byte contains the VALID and OWNER
337 * bits which (when set to 0) will invalidate the entire beacon.
338 */
339 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 340 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
95ea3627 341
6bb40dd1
ID		 342 /*
343 * Enable synchronisation.
344 */
345 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 346 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 347 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 348 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 349 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
350 }
95ea3627 351
6bb40dd1
ID		 352 if (flags & CONFIG_UPDATE_MAC) {
353 reg = le32_to_cpu(conf->mac[1]);
354 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
355 conf->mac[1] = cpu_to_le32(reg);
95ea3627 356
6bb40dd1
ID		 357 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
358 conf->mac, sizeof(conf->mac));
359 }
95ea3627 360
6bb40dd1
ID		 361 if (flags & CONFIG_UPDATE_BSSID) {
362 reg = le32_to_cpu(conf->bssid[1]);
363 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
364 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 365
6bb40dd1
ID		 366 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
367 conf->bssid, sizeof(conf->bssid));
368 }
95ea3627
ID		 369}
370
72810379
ID		 371static int rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
372 struct rt2x00lib_erp *erp)
95ea3627 373{
95ea3627 374 u32 reg;
95ea3627
ID		 375
376 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 377 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
95ea3627
ID		 378 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
379
380 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 381 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 382 !!erp->short_preamble);
95ea3627 383 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
6bb40dd1
ID		 384
385 return 0;
95ea3627
ID		 386}
387
388static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 389 const int basic_rate_mask)
95ea3627 390{
5c58ee51 391 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 392}
393
5c58ee51
ID		 394static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
395 struct rf_channel *rf, const int txpower)
95ea3627
ID		 396{
397 u8 r3;
398 u8 r94;
399 u8 smart;
400
401 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
402 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
403
404 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
405 rt2x00_rf(&rt2x00dev->chip, RF2527));
406
407 rt61pci_bbp_read(rt2x00dev, 3, &r3);
408 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
409 rt61pci_bbp_write(rt2x00dev, 3, r3);
410
411 r94 = 6;
412 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
413 r94 += txpower - MAX_TXPOWER;
414 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
415 r94 += txpower;
416 rt61pci_bbp_write(rt2x00dev, 94, r94);
417
418 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
419 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
420 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
421 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
422
423 udelay(200);
424
425 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
426 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
427 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
428 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
429
430 udelay(200);
431
432 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
433 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
434 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
435 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
436
437 msleep(1);
438}
439
95ea3627
ID		 440static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
441 const int txpower)
442{
443 struct rf_channel rf;
444
445 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
446 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
447 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
448 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
449
5c58ee51 450 rt61pci_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 451}
452
453static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 454 struct antenna_setup *ant)
95ea3627
ID		 455{
456 u8 r3;
457 u8 r4;
458 u8 r77;
459
460 rt61pci_bbp_read(rt2x00dev, 3, &r3);
461 rt61pci_bbp_read(rt2x00dev, 4, &r4);
462 rt61pci_bbp_read(rt2x00dev, 77, &r77);
463
464 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 465 rt2x00_rf(&rt2x00dev->chip, RF5325));
e4cd2ff8
ID		 466
467 /*
468 * Configure the RX antenna.
469 */
addc81bd 470 switch (ant->rx) {
95ea3627 471 case ANTENNA_HW_DIVERSITY:
acaa410d 472 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 473 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 474 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 475 break;
476 case ANTENNA_A:
acaa410d 477 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 478 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 479 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 480 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
481 else
482 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 483 break;
484 case ANTENNA_B:
a4fe07d9 485 default:
acaa410d 486 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 487 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 488 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 489 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
490 else
491 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 492 break;
493 }
494
495 rt61pci_bbp_write(rt2x00dev, 77, r77);
496 rt61pci_bbp_write(rt2x00dev, 3, r3);
497 rt61pci_bbp_write(rt2x00dev, 4, r4);
498}
499
500static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 501 struct antenna_setup *ant)
95ea3627
ID		 502{
503 u8 r3;
504 u8 r4;
505 u8 r77;
506
507 rt61pci_bbp_read(rt2x00dev, 3, &r3);
508 rt61pci_bbp_read(rt2x00dev, 4, &r4);
509 rt61pci_bbp_read(rt2x00dev, 77, &r77);
510
511 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 512 rt2x00_rf(&rt2x00dev->chip, RF2529));
95ea3627
ID		 513 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
514 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
515
e4cd2ff8
ID		 516 /*
517 * Configure the RX antenna.
518 */
addc81bd 519 switch (ant->rx) {
95ea3627 520 case ANTENNA_HW_DIVERSITY:
acaa410d 521 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 522 break;
523 case ANTENNA_A:
acaa410d
MN		 524 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
525 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 526 break;
527 case ANTENNA_B:
a4fe07d9 528 default:
acaa410d
MN		 529 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
530 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 531 break;
532 }
533
534 rt61pci_bbp_write(rt2x00dev, 77, r77);
535 rt61pci_bbp_write(rt2x00dev, 3, r3);
536 rt61pci_bbp_write(rt2x00dev, 4, r4);
537}
538
539static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
540 const int p1, const int p2)
541{
542 u32 reg;
543
544 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
545
acaa410d
MN		 546 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
547 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
548
549 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
550 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
551
552 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 553}
554
555static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 556 struct antenna_setup *ant)
95ea3627 557{
95ea3627
ID		 558 u8 r3;
559 u8 r4;
560 u8 r77;
561
562 rt61pci_bbp_read(rt2x00dev, 3, &r3);
563 rt61pci_bbp_read(rt2x00dev, 4, &r4);
564 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 565
e4cd2ff8
ID		 566 /*
567 * Configure the RX antenna.
568 */
569 switch (ant->rx) {
570 case ANTENNA_A:
acaa410d
MN		 571 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
572 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
573 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8 574 break;
e4cd2ff8
ID		 575 case ANTENNA_HW_DIVERSITY:
576 /*
a4fe07d9
ID		 577 * FIXME: Antenna selection for the rf 2529 is very confusing
578 * in the legacy driver. Just default to antenna B until the
579 * legacy code can be properly translated into rt2x00 code.
e4cd2ff8
ID		 580 */
581 case ANTENNA_B:
a4fe07d9 582 default:
acaa410d
MN		 583 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
584 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
585 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 586 break;
587 }
588
e4cd2ff8 589 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 590 rt61pci_bbp_write(rt2x00dev, 3, r3);
591 rt61pci_bbp_write(rt2x00dev, 4, r4);
592}
593
594struct antenna_sel {
595 u8 word;
596 /*
597 * value[0] -> non-LNA
598 * value[1] -> LNA
599 */
600 u8 value[2];
601};
602
603static const struct antenna_sel antenna_sel_a[] = {
604 { 96, { 0x58, 0x78 } },
605 { 104, { 0x38, 0x48 } },
606 { 75, { 0xfe, 0x80 } },
607 { 86, { 0xfe, 0x80 } },
608 { 88, { 0xfe, 0x80 } },
609 { 35, { 0x60, 0x60 } },
610 { 97, { 0x58, 0x58 } },
611 { 98, { 0x58, 0x58 } },
612};
613
614static const struct antenna_sel antenna_sel_bg[] = {
615 { 96, { 0x48, 0x68 } },
616 { 104, { 0x2c, 0x3c } },
617 { 75, { 0xfe, 0x80 } },
618 { 86, { 0xfe, 0x80 } },
619 { 88, { 0xfe, 0x80 } },
620 { 35, { 0x50, 0x50 } },
621 { 97, { 0x48, 0x48 } },
622 { 98, { 0x48, 0x48 } },
623};
624
625static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 626 struct antenna_setup *ant)
95ea3627
ID		 627{
628 const struct antenna_sel *sel;
629 unsigned int lna;
630 unsigned int i;
631 u32 reg;
632
a4fe07d9
ID		 633 /*
634 * We should never come here because rt2x00lib is supposed
635 * to catch this and send us the correct antenna explicitely.
636 */
637 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
638 ant->tx == ANTENNA_SW_DIVERSITY);
639
8318d78a 640 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 641 sel = antenna_sel_a;
642 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 643 } else {
644 sel = antenna_sel_bg;
645 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 646 }
647
acaa410d
MN		 648 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
649 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
650
651 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
652
ddc827f9 653 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 654 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 655 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 656 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 657
95ea3627
ID		 658 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
659
660 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
661 rt2x00_rf(&rt2x00dev->chip, RF5325))
addc81bd 662 rt61pci_config_antenna_5x(rt2x00dev, ant);
95ea3627 663 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 664 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 665 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
666 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 667 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 668 else
addc81bd 669 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 670 }
671}
672
673static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 674 struct rt2x00lib_conf *libconf)
95ea3627
ID		 675{
676 u32 reg;
677
678 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 679 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 680 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
681
682 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 683 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 684 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 685 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 686 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
687
688 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
689 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
690 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
691
692 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
693 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
694 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
695
696 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 697 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
698 libconf->conf->beacon_int * 16);
95ea3627
ID		 699 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
700}
701
702static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 703 struct rt2x00lib_conf *libconf,
704 const unsigned int flags)
95ea3627 705{
95ea3627 706 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 707 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 708 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 709 rt61pci_config_channel(rt2x00dev, &libconf->rf,
710 libconf->conf->power_level);
95ea3627 711 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 712 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 713 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 714 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 715 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 716 rt61pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 717}
718
95ea3627
ID		 719/*
720 * Link tuning
721 */
ebcf26da
ID		 722static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
723 struct link_qual *qual)
95ea3627
ID		 724{
725 u32 reg;
726
727 /*
728 * Update FCS error count from register.
729 */
730 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 731 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 732
733 /*
734 * Update False CCA count from register.
735 */
736 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 737 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 738}
739
740static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
741{
742 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
743 rt2x00dev->link.vgc_level = 0x20;
744}
745
746static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
747{
748 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
749 u8 r17;
750 u8 up_bound;
751 u8 low_bound;
752
95ea3627
ID		 753 rt61pci_bbp_read(rt2x00dev, 17, &r17);
754
755 /*
756 * Determine r17 bounds.
757 */
1497074a 758 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 759 low_bound = 0x28;
760 up_bound = 0x48;
761 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
762 low_bound += 0x10;
763 up_bound += 0x10;
764 }
765 } else {
766 low_bound = 0x20;
767 up_bound = 0x40;
768 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
769 low_bound += 0x10;
770 up_bound += 0x10;
771 }
772 }
773
6bb40dd1
ID		 774 /*
775 * If we are not associated, we should go straight to the
776 * dynamic CCA tuning.
777 */
778 if (!rt2x00dev->intf_associated)
779 goto dynamic_cca_tune;
780
95ea3627
ID		 781 /*
782 * Special big-R17 for very short distance
783 */
784 if (rssi >= -35) {
785 if (r17 != 0x60)
786 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
787 return;
788 }
789
790 /*
791 * Special big-R17 for short distance
792 */
793 if (rssi >= -58) {
794 if (r17 != up_bound)
795 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
796 return;
797 }
798
799 /*
800 * Special big-R17 for middle-short distance
801 */
802 if (rssi >= -66) {
803 low_bound += 0x10;
804 if (r17 != low_bound)
805 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
806 return;
807 }
808
809 /*
810 * Special mid-R17 for middle distance
811 */
812 if (rssi >= -74) {
813 low_bound += 0x08;
814 if (r17 != low_bound)
815 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
816 return;
817 }
818
819 /*
820 * Special case: Change up_bound based on the rssi.
821 * Lower up_bound when rssi is weaker then -74 dBm.
822 */
823 up_bound -= 2 * (-74 - rssi);
824 if (low_bound > up_bound)
825 up_bound = low_bound;
826
827 if (r17 > up_bound) {
828 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
829 return;
830 }
831
6bb40dd1
ID		 832dynamic_cca_tune:
833
95ea3627
ID		 834 /*
835 * r17 does not yet exceed upper limit, continue and base
836 * the r17 tuning on the false CCA count.
837 */
ebcf26da 838 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 839 if (++r17 > up_bound)
840 r17 = up_bound;
841 rt61pci_bbp_write(rt2x00dev, 17, r17);
ebcf26da 842 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 843 if (--r17 < low_bound)
844 r17 = low_bound;
845 rt61pci_bbp_write(rt2x00dev, 17, r17);
846 }
847}
848
849/*
a7f3a06c 850 * Firmware functions
95ea3627
ID		 851 */
852static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
853{
854 char *fw_name;
855
856 switch (rt2x00dev->chip.rt) {
857 case RT2561:
858 fw_name = FIRMWARE_RT2561;
859 break;
860 case RT2561s:
861 fw_name = FIRMWARE_RT2561s;
862 break;
863 case RT2661:
864 fw_name = FIRMWARE_RT2661;
865 break;
866 default:
867 fw_name = NULL;
868 break;
869 }
870
871 return fw_name;
872}
873
a7f3a06c
ID		 874static u16 rt61pci_get_firmware_crc(void *data, const size_t len)
875{
876 u16 crc;
877
878 /*
879 * Use the crc itu-t algorithm.
880 * The last 2 bytes in the firmware array are the crc checksum itself,
881 * this means that we should never pass those 2 bytes to the crc
882 * algorithm.
883 */
884 crc = crc_itu_t(0, data, len - 2);
885 crc = crc_itu_t_byte(crc, 0);
886 crc = crc_itu_t_byte(crc, 0);
887
888 return crc;
889}
890
95ea3627
ID		 891static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
892 const size_t len)
893{
894 int i;
895 u32 reg;
896
897 /*
898 * Wait for stable hardware.
899 */
900 for (i = 0; i < 100; i++) {
901 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
902 if (reg)
903 break;
904 msleep(1);
905 }
906
907 if (!reg) {
908 ERROR(rt2x00dev, "Unstable hardware.\n");
909 return -EBUSY;
910 }
911
912 /*
913 * Prepare MCU and mailbox for firmware loading.
914 */
915 reg = 0;
916 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
917 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
918 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
919 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
920 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
921
922 /*
923 * Write firmware to device.
924 */
925 reg = 0;
926 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
927 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
928 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
929
930 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
931 data, len);
932
933 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
934 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
935
936 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
937 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
938
939 for (i = 0; i < 100; i++) {
940 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
941 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
942 break;
943 msleep(1);
944 }
945
946 if (i == 100) {
947 ERROR(rt2x00dev, "MCU Control register not ready.\n");
948 return -EBUSY;
949 }
950
951 /*
952 * Reset MAC and BBP registers.
953 */
954 reg = 0;
955 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
956 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
957 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
958
959 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
960 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
961 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
962 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
963
964 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
965 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
966 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
967
968 return 0;
969}
970
a7f3a06c
ID		 971/*
972 * Initialization functions.
973 */
837e7f24 974static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 975 struct queue_entry *entry)
95ea3627 976{
181d6902 977 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 978 u32 word;
979
181d6902 980 rt2x00_desc_read(priv_rx->desc, 5, &word);
30b3a23c
ID		 981 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
982 priv_rx->data_dma);
181d6902 983 rt2x00_desc_write(priv_rx->desc, 5, word);
95ea3627 984
181d6902 985 rt2x00_desc_read(priv_rx->desc, 0, &word);
837e7f24 986 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
181d6902 987 rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627
ID		 988}
989
837e7f24 990static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 991 struct queue_entry *entry)
95ea3627 992{
181d6902 993 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
95ea3627
ID		 994 u32 word;
995
181d6902 996 rt2x00_desc_read(priv_tx->desc, 1, &word);
837e7f24 997 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
181d6902 998 rt2x00_desc_write(priv_tx->desc, 1, word);
95ea3627 999
181d6902
ID		 1000 rt2x00_desc_read(priv_tx->desc, 5, &word);
1001 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
837e7f24 1002 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
181d6902 1003 rt2x00_desc_write(priv_tx->desc, 5, word);
95ea3627 1004
181d6902 1005 rt2x00_desc_read(priv_tx->desc, 6, &word);
30b3a23c
ID		 1006 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1007 priv_tx->data_dma);
181d6902 1008 rt2x00_desc_write(priv_tx->desc, 6, word);
95ea3627 1009
181d6902 1010 rt2x00_desc_read(priv_tx->desc, 0, &word);
837e7f24
ID		 1011 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1012 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
181d6902 1013 rt2x00_desc_write(priv_tx->desc, 0, word);
95ea3627
ID		 1014}
1015
181d6902 1016static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1017{
181d6902
ID		 1018 struct queue_entry_priv_pci_rx *priv_rx;
1019 struct queue_entry_priv_pci_tx *priv_tx;
95ea3627
ID		 1020 u32 reg;
1021
95ea3627
ID		 1022 /*
1023 * Initialize registers.
1024 */
1025 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1026 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1027 rt2x00dev->tx[0].limit);
95ea3627 1028 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1029 rt2x00dev->tx[1].limit);
95ea3627 1030 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1031 rt2x00dev->tx[2].limit);
95ea3627 1032 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1033 rt2x00dev->tx[3].limit);
95ea3627
ID		 1034 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1035
1036 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1037 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1038 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1039 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1040
181d6902 1041 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1042 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
30b3a23c
ID		 1043 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1044 priv_tx->desc_dma);
95ea3627
ID		 1045 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1046
181d6902 1047 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1048 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
30b3a23c
ID		 1049 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1050 priv_tx->desc_dma);
95ea3627
ID		 1051 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1052
181d6902 1053 priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1054 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
30b3a23c
ID		 1055 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1056 priv_tx->desc_dma);
95ea3627
ID		 1057 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1058
181d6902 1059 priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1060 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
30b3a23c
ID		 1061 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1062 priv_tx->desc_dma);
95ea3627
ID		 1063 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1064
95ea3627 1065 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1066 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1067 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1068 rt2x00dev->rx->desc_size / 4);
1069 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1070 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1071
181d6902 1072 priv_rx = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1073 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
30b3a23c
ID		 1074 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1075 priv_rx->desc_dma);
95ea3627
ID		 1076 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1077
1078 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1079 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1080 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1081 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1082 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
95ea3627
ID		 1083 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1084
1085 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1086 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1087 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1088 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1089 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
95ea3627
ID		 1090 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1091
1092 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1093 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1094 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1095
1096 return 0;
1097}
1098
1099static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1100{
1101 u32 reg;
1102
1103 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1104 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1105 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1106 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1107 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1108
1109 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1110 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1111 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1112 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1113 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1114 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1115 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1116 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1117 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1118 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1119
1120 /*
1121 * CCK TXD BBP registers
1122 */
1123 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1124 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1125 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1126 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1127 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1128 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1129 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1130 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1131 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1132 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1133
1134 /*
1135 * OFDM TXD BBP registers
1136 */
1137 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1138 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1139 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1140 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1141 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1142 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1143 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1144 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1145
1146 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1147 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1148 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1149 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1150 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1151 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1152
1153 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1154 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1155 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1156 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1157 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1158 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1159
1160 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1161
1162 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1163
1164 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1165 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1166 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1167
1168 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1169
1170 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1171 return -EBUSY;
1172
1173 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1174
a9450b70
ID		 1175 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
1176 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
1177 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
1178 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
1179
95ea3627
ID		 1180 /*
1181 * Invalidate all Shared Keys (SEC_CSR0),
1182 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1183 */
1184 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1185 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1186 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1187
1188 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1189 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1190 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1191 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1192
1193 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1194
1195 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1196
1197 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1198
1199 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1200 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1201 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1202 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1203
1204 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1205 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1206 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1207 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1208
6bb40dd1
ID		 1209 /*
1210 * Clear all beacons
1211 * For the Beacon base registers we only need to clear
1212 * the first byte since that byte contains the VALID and OWNER
1213 * bits which (when set to 0) will invalidate the entire beacon.
1214 */
1215 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1216 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1217 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1218 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1219
95ea3627
ID		 1220 /*
1221 * We must clear the error counters.
1222 * These registers are cleared on read,
1223 * so we may pass a useless variable to store the value.
1224 */
1225 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1226 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1227 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1228
1229 /*
1230 * Reset MAC and BBP registers.
1231 */
1232 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1233 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1234 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1235 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1236
1237 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1238 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1239 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1240 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1241
1242 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1243 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1244 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1245
1246 return 0;
1247}
1248
1249static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1250{
1251 unsigned int i;
1252 u16 eeprom;
1253 u8 reg_id;
1254 u8 value;
1255
1256 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1257 rt61pci_bbp_read(rt2x00dev, 0, &value);
1258 if ((value != 0xff) && (value != 0x00))
1259 goto continue_csr_init;
1260 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1261 udelay(REGISTER_BUSY_DELAY);
1262 }
1263
1264 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1265 return -EACCES;
1266
1267continue_csr_init:
1268 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1269 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1270 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1271 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1272 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1273 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1274 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1275 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1276 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1277 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1278 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1279 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1280 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1281 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1282 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1283 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1284 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1285 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1286 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1287 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1288 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1289 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1290 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1291 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1292
95ea3627
ID		 1293 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1294 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1295
1296 if (eeprom != 0xffff && eeprom != 0x0000) {
1297 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1298 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1299 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1300 }
1301 }
95ea3627
ID		 1302
1303 return 0;
1304}
1305
1306/*
1307 * Device state switch handlers.
1308 */
1309static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1310 enum dev_state state)
1311{
1312 u32 reg;
1313
1314 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1315 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1316 state == STATE_RADIO_RX_OFF);
1317 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1318}
1319
1320static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1321 enum dev_state state)
1322{
1323 int mask = (state == STATE_RADIO_IRQ_OFF);
1324 u32 reg;
1325
1326 /*
1327 * When interrupts are being enabled, the interrupt registers
1328 * should clear the register to assure a clean state.
1329 */
1330 if (state == STATE_RADIO_IRQ_ON) {
1331 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1332 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1333
1334 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1335 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1336 }
1337
1338 /*
1339 * Only toggle the interrupts bits we are going to use.
1340 * Non-checked interrupt bits are disabled by default.
1341 */
1342 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1343 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1344 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1345 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1346 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1347 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1348
1349 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1350 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1351 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1352 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1353 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1354 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1355 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1356 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1357 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1358 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1359}
1360
1361static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1362{
1363 u32 reg;
1364
1365 /*
1366 * Initialize all registers.
1367 */
181d6902 1368 if (rt61pci_init_queues(rt2x00dev) ||
95ea3627
ID		 1369 rt61pci_init_registers(rt2x00dev) ||
1370 rt61pci_init_bbp(rt2x00dev)) {
1371 ERROR(rt2x00dev, "Register initialization failed.\n");
1372 return -EIO;
1373 }
1374
1375 /*
1376 * Enable interrupts.
1377 */
1378 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1379
1380 /*
1381 * Enable RX.
1382 */
1383 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1384 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1385 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1386
95ea3627
ID		 1387 return 0;
1388}
1389
1390static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1391{
1392 u32 reg;
1393
95ea3627
ID		 1394 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1395
1396 /*
1397 * Disable synchronisation.
1398 */
1399 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1400
1401 /*
1402 * Cancel RX and TX.
1403 */
1404 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1405 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1406 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1407 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1408 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
95ea3627
ID		 1409 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1410
1411 /*
1412 * Disable interrupts.
1413 */
1414 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1415}
1416
1417static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1418{
1419 u32 reg;
1420 unsigned int i;
1421 char put_to_sleep;
1422 char current_state;
1423
1424 put_to_sleep = (state != STATE_AWAKE);
1425
1426 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1427 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1428 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1429 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1430
1431 /*
1432 * Device is not guaranteed to be in the requested state yet.
1433 * We must wait until the register indicates that the
1434 * device has entered the correct state.
1435 */
1436 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1437 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1438 current_state =
1439 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1440 if (current_state == !put_to_sleep)
1441 return 0;
1442 msleep(10);
1443 }
1444
1445 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1446 "current device state %d.\n", !put_to_sleep, current_state);
1447
1448 return -EBUSY;
1449}
1450
1451static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1452 enum dev_state state)
1453{
1454 int retval = 0;
1455
1456 switch (state) {
1457 case STATE_RADIO_ON:
1458 retval = rt61pci_enable_radio(rt2x00dev);
1459 break;
1460 case STATE_RADIO_OFF:
1461 rt61pci_disable_radio(rt2x00dev);
1462 break;
1463 case STATE_RADIO_RX_ON:
61667d8d
ID		 1464 case STATE_RADIO_RX_ON_LINK:
1465 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1466 break;
95ea3627 1467 case STATE_RADIO_RX_OFF:
61667d8d
ID		 1468 case STATE_RADIO_RX_OFF_LINK:
1469 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 1470 break;
1471 case STATE_DEEP_SLEEP:
1472 case STATE_SLEEP:
1473 case STATE_STANDBY:
1474 case STATE_AWAKE:
1475 retval = rt61pci_set_state(rt2x00dev, state);
1476 break;
1477 default:
1478 retval = -ENOTSUPP;
1479 break;
1480 }
1481
1482 return retval;
1483}
1484
1485/*
1486 * TX descriptor initialization
1487 */
1488static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1489 struct sk_buff *skb,
181d6902 1490 struct txentry_desc *txdesc,
dd3193e1 1491 struct ieee80211_tx_control *control)
95ea3627 1492{
181d6902 1493 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1494 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1495 u32 word;
1496
1497 /*
1498 * Start writing the descriptor words.
1499 */
1500 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1501 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1502 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1503 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1504 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1505 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1506 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1507 rt2x00_desc_write(txd, 1, word);
1508
1509 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1510 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1511 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1512 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1513 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1514 rt2x00_desc_write(txd, 2, word);
1515
1516 rt2x00_desc_read(txd, 5, &word);
1517 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1518 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1519 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1520 rt2x00_desc_write(txd, 5, word);
1521
d7bafff3
AB		 1522 if (skbdesc->desc_len > TXINFO_SIZE) {
1523 rt2x00_desc_read(txd, 11, &word);
1524 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1525 rt2x00_desc_write(txd, 11, word);
1526 }
95ea3627
ID		 1527
1528 rt2x00_desc_read(txd, 0, &word);
1529 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1530 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1531 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1532 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1533 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1534 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1535 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1536 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1537 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1538 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1539 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1540 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1541 !!(control->flags &
1542 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1543 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
dd3193e1 1544 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627 1545 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1546 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1547 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1548 rt2x00_desc_write(txd, 0, word);
1549}
1550
1551/*
1552 * TX data initialization
1553 */
1554static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1555 const unsigned int queue)
95ea3627
ID		 1556{
1557 u32 reg;
1558
5957da4c 1559 if (queue == RT2X00_BCN_QUEUE_BEACON) {
95ea3627
ID		 1560 /*
1561 * For Wi-Fi faily generated beacons between participating
1562 * stations. Set TBTT phase adaptive adjustment step to 8us.
1563 */
1564 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1565
1566 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1567 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1568 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1569 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1570 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1571 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1572 }
1573 return;
1574 }
1575
1576 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
ddc827f9
ID		 1577 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0,
1578 (queue == IEEE80211_TX_QUEUE_DATA0));
1579 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1,
1580 (queue == IEEE80211_TX_QUEUE_DATA1));
1581 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
1582 (queue == IEEE80211_TX_QUEUE_DATA2));
1583 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1584 (queue == IEEE80211_TX_QUEUE_DATA3));
95ea3627
ID		 1585 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1586}
1587
1588/*
1589 * RX control handlers
1590 */
1591static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1592{
1593 u16 eeprom;
1594 u8 offset;
1595 u8 lna;
1596
1597 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1598 switch (lna) {
1599 case 3:
1600 offset = 90;
1601 break;
1602 case 2:
1603 offset = 74;
1604 break;
1605 case 1:
1606 offset = 64;
1607 break;
1608 default:
1609 return 0;
1610 }
1611
8318d78a 1612 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1613 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1614 offset += 14;
1615
1616 if (lna == 3 || lna == 2)
1617 offset += 10;
1618
1619 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1620 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1621 } else {
1622 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1623 offset += 14;
1624
1625 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1626 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1627 }
1628
1629 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1630}
1631
181d6902
ID		 1632static void rt61pci_fill_rxdone(struct queue_entry *entry,
1633 struct rxdone_entry_desc *rxdesc)
95ea3627 1634{
181d6902 1635 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 1636 u32 word0;
1637 u32 word1;
1638
181d6902
ID		 1639 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1640 rt2x00_desc_read(priv_rx->desc, 1, &word1);
95ea3627 1641
181d6902 1642 rxdesc->flags = 0;
4150c572 1643 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1644 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1645
1646 /*
1647 * Obtain the status about this packet.
89993890
ID		 1648 * When frame was received with an OFDM bitrate,
1649 * the signal is the PLCP value. If it was received with
1650 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1651 */
181d6902
ID		 1652 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1653 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
181d6902 1654 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02
ID		 1655
1656 rxdesc->dev_flags = 0;
1657 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1658 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1659 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1660 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1661}
1662
1663/*
1664 * Interrupt functions.
1665 */
1666static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1667{
181d6902
ID		 1668 struct data_queue *queue;
1669 struct queue_entry *entry;
1670 struct queue_entry *entry_done;
1671 struct queue_entry_priv_pci_tx *priv_tx;
1672 struct txdone_entry_desc txdesc;
95ea3627
ID		 1673 u32 word;
1674 u32 reg;
1675 u32 old_reg;
1676 int type;
1677 int index;
95ea3627
ID		 1678
1679 /*
1680 * During each loop we will compare the freshly read
1681 * STA_CSR4 register value with the value read from
1682 * the previous loop. If the 2 values are equal then
1683 * we should stop processing because the chance it
1684 * quite big that the device has been unplugged and
1685 * we risk going into an endless loop.
1686 */
1687 old_reg = 0;
1688
1689 while (1) {
1690 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1691 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1692 break;
1693
1694 if (old_reg == reg)
1695 break;
1696 old_reg = reg;
1697
1698 /*
1699 * Skip this entry when it contains an invalid
181d6902 1700 * queue identication number.
95ea3627
ID		 1701 */
1702 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 1703 queue = rt2x00queue_get_queue(rt2x00dev, type);
1704 if (unlikely(!queue))
95ea3627
ID		 1705 continue;
1706
1707 /*
1708 * Skip this entry when it contains an invalid
1709 * index number.
1710 */
1711 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 1712 if (unlikely(index >= queue->limit))
95ea3627
ID		 1713 continue;
1714
181d6902
ID		 1715 entry = &queue->entries[index];
1716 priv_tx = entry->priv_data;
1717 rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627
ID		 1718
1719 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1720 !rt2x00_get_field32(word, TXD_W0_VALID))
1721 return;
1722
181d6902 1723 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 1724 while (entry != entry_done) {
181d6902
ID		 1725 /* Catch up.
1726 * Just report any entries we missed as failed.
1727 */
62bc060b 1728 WARNING(rt2x00dev,
181d6902
ID		 1729 "TX status report missed for entry %d\n",
1730 entry_done->entry_idx);
1731
1732 txdesc.status = TX_FAIL_OTHER;
1733 txdesc.retry = 0;
1734
1735 rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1736 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 1737 }
1738
95ea3627
ID		 1739 /*
1740 * Obtain the status about this packet.
1741 */
181d6902
ID		 1742 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1743 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 1744
181d6902 1745 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627
ID		 1746 }
1747}
1748
1749static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1750{
1751 struct rt2x00_dev *rt2x00dev = dev_instance;
1752 u32 reg_mcu;
1753 u32 reg;
1754
1755 /*
1756 * Get the interrupt sources & saved to local variable.
1757 * Write register value back to clear pending interrupts.
1758 */
1759 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1760 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1761
1762 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1763 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1764
1765 if (!reg && !reg_mcu)
1766 return IRQ_NONE;
1767
1768 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1769 return IRQ_HANDLED;
1770
1771 /*
1772 * Handle interrupts, walk through all bits
1773 * and run the tasks, the bits are checked in order of
1774 * priority.
1775 */
1776
1777 /*
1778 * 1 - Rx ring done interrupt.
1779 */
1780 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1781 rt2x00pci_rxdone(rt2x00dev);
1782
1783 /*
1784 * 2 - Tx ring done interrupt.
1785 */
1786 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1787 rt61pci_txdone(rt2x00dev);
1788
1789 /*
1790 * 3 - Handle MCU command done.
1791 */
1792 if (reg_mcu)
1793 rt2x00pci_register_write(rt2x00dev,
1794 M2H_CMD_DONE_CSR, 0xffffffff);
1795
1796 return IRQ_HANDLED;
1797}
1798
1799/*
1800 * Device probe functions.
1801 */
1802static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1803{
1804 struct eeprom_93cx6 eeprom;
1805 u32 reg;
1806 u16 word;
1807 u8 *mac;
1808 s8 value;
1809
1810 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1811
1812 eeprom.data = rt2x00dev;
1813 eeprom.register_read = rt61pci_eepromregister_read;
1814 eeprom.register_write = rt61pci_eepromregister_write;
1815 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1816 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1817 eeprom.reg_data_in = 0;
1818 eeprom.reg_data_out = 0;
1819 eeprom.reg_data_clock = 0;
1820 eeprom.reg_chip_select = 0;
1821
1822 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1823 EEPROM_SIZE / sizeof(u16));
1824
1825 /*
1826 * Start validation of the data that has been read.
1827 */
1828 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1829 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1830 DECLARE_MAC_BUF(macbuf);
1831
95ea3627 1832 random_ether_addr(mac);
0795af57 1833 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1834 }
1835
1836 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1837 if (word == 0xffff) {
1838 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1839 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1840 ANTENNA_B);
1841 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1842 ANTENNA_B);
95ea3627
ID		 1843 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1844 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1845 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1846 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1847 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1848 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1849 }
1850
1851 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1852 if (word == 0xffff) {
1853 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1854 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1855 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1856 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1857 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1858 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1859 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1860 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1861 }
1862
1863 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1864 if (word == 0xffff) {
1865 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1866 LED_MODE_DEFAULT);
1867 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1868 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1869 }
1870
1871 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1872 if (word == 0xffff) {
1873 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1874 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1875 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1876 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1877 }
1878
1879 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1880 if (word == 0xffff) {
1881 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1882 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1883 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1884 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1885 } else {
1886 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1887 if (value < -10 || value > 10)
1888 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1889 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1890 if (value < -10 || value > 10)
1891 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1892 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1893 }
1894
1895 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1896 if (word == 0xffff) {
1897 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1898 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1899 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1900 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1901 } else {
1902 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1903 if (value < -10 || value > 10)
1904 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1905 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1906 if (value < -10 || value > 10)
1907 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1908 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1909 }
1910
1911 return 0;
1912}
1913
1914static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1915{
1916 u32 reg;
1917 u16 value;
1918 u16 eeprom;
1919 u16 device;
1920
1921 /*
1922 * Read EEPROM word for configuration.
1923 */
1924 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1925
1926 /*
1927 * Identify RF chipset.
1928 * To determine the RT chip we have to read the
1929 * PCI header of the device.
1930 */
1931 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1932 PCI_CONFIG_HEADER_DEVICE, &device);
1933 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1934 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1935 rt2x00_set_chip(rt2x00dev, device, value, reg);
1936
1937 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1938 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1939 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1940 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1941 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1942 return -ENODEV;
1943 }
1944
e4cd2ff8
ID		 1945 /*
1946 * Determine number of antenna's.
1947 */
1948 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1949 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1950
95ea3627
ID		 1951 /*
1952 * Identify default antenna configuration.
1953 */
addc81bd 1954 rt2x00dev->default_ant.tx =
95ea3627 1955 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1956 rt2x00dev->default_ant.rx =
95ea3627
ID		 1957 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1958
1959 /*
1960 * Read the Frame type.
1961 */
1962 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1963 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1964
95ea3627
ID		 1965 /*
1966 * Detect if this device has an hardware controlled radio.
1967 */
81873e9c 1968#ifdef CONFIG_RT61PCI_RFKILL
95ea3627 1969 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1970 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1971#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627
ID		 1972
1973 /*
1974 * Read frequency offset and RF programming sequence.
1975 */
1976 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1977 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
1978 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
1979
1980 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1981
1982 /*
1983 * Read external LNA informations.
1984 */
1985 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1986
1987 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1988 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1989 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1990 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1991
e4cd2ff8
ID		 1992 /*
1993 * When working with a RF2529 chip without double antenna
1994 * the antenna settings should be gathered from the NIC
1995 * eeprom word.
1996 */
1997 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
1998 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
1999 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2000 case 0:
2001 rt2x00dev->default_ant.tx = ANTENNA_B;
2002 rt2x00dev->default_ant.rx = ANTENNA_A;
2003 break;
2004 case 1:
2005 rt2x00dev->default_ant.tx = ANTENNA_B;
2006 rt2x00dev->default_ant.rx = ANTENNA_B;
2007 break;
2008 case 2:
2009 rt2x00dev->default_ant.tx = ANTENNA_A;
2010 rt2x00dev->default_ant.rx = ANTENNA_A;
2011 break;
2012 case 3:
2013 rt2x00dev->default_ant.tx = ANTENNA_A;
2014 rt2x00dev->default_ant.rx = ANTENNA_B;
2015 break;
2016 }
2017
2018 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2019 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2020 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2021 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2022 }
2023
95ea3627
ID		 2024 /*
2025 * Store led settings, for correct led behaviour.
2026 * If the eeprom value is invalid,
2027 * switch to default led mode.
2028 */
a9450b70 2029#ifdef CONFIG_RT61PCI_LEDS
95ea3627
ID		 2030 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2031
a9450b70
ID		 2032 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2033
2034 switch (value) {
2035 case LED_MODE_TXRX_ACTIVITY:
2036 case LED_MODE_ASUS:
2037 case LED_MODE_ALPHA:
2038 case LED_MODE_DEFAULT:
2039 rt2x00dev->led_flags =
2040 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
2041 break;
2042 case LED_MODE_SIGNAL_STRENGTH:
2043 rt2x00dev->led_flags =
2044 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
2045 LED_SUPPORT_QUALITY;
2046 break;
2047 }
95ea3627 2048
a9450b70
ID		 2049 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2050 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2051 rt2x00_get_field16(eeprom,
2052 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2053 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2054 rt2x00_get_field16(eeprom,
2055 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2056 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2057 rt2x00_get_field16(eeprom,
2058 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2059 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2060 rt2x00_get_field16(eeprom,
2061 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2062 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2063 rt2x00_get_field16(eeprom,
2064 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2065 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2066 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2067 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2068 rt2x00_get_field16(eeprom,
2069 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2070 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2071 rt2x00_get_field16(eeprom,
2072 EEPROM_LED_POLARITY_RDY_A));
a9450b70 2073#endif /* CONFIG_RT61PCI_LEDS */
95ea3627
ID		 2074
2075 return 0;
2076}
2077
2078/*
2079 * RF value list for RF5225 & RF5325
2080 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2081 */
2082static const struct rf_channel rf_vals_noseq[] = {
2083 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2084 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2085 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2086 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2087 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2088 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2089 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2090 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2091 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2092 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2093 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2094 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2095 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2096 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2097
2098 /* 802.11 UNI / HyperLan 2 */
2099 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2100 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2101 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2102 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2103 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2104 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2105 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2106 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2107
2108 /* 802.11 HyperLan 2 */
2109 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2110 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2111 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2112 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2113 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2114 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2115 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2116 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2117 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2118 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2119
2120 /* 802.11 UNII */
2121 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2122 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2123 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2124 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2125 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2126 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2127
2128 /* MMAC(Japan)J52 ch 34,38,42,46 */
2129 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2130 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2131 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2132 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2133};
2134
2135/*
2136 * RF value list for RF5225 & RF5325
2137 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2138 */
2139static const struct rf_channel rf_vals_seq[] = {
2140 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2141 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2142 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2143 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2144 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2145 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2146 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2147 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2148 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2149 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2150 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2151 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2152 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2153 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2154
2155 /* 802.11 UNI / HyperLan 2 */
2156 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2157 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2158 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2159 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2160 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2161 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2162 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2163 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2164
2165 /* 802.11 HyperLan 2 */
2166 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2167 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2168 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2169 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2170 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2171 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2172 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2173 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2174 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2175 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2176
2177 /* 802.11 UNII */
2178 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2179 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2180 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2181 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2182 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2183 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2184
2185 /* MMAC(Japan)J52 ch 34,38,42,46 */
2186 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2187 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2188 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2189 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2190};
2191
2192static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2193{
2194 struct hw_mode_spec *spec = &rt2x00dev->spec;
2195 u8 *txpower;
2196 unsigned int i;
2197
2198 /*
2199 * Initialize all hw fields.
2200 */
2201 rt2x00dev->hw->flags =
2202 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 2203 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 2204 rt2x00dev->hw->extra_tx_headroom = 0;
2205 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2206 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
871ff6ed 2207 rt2x00dev->hw->queues = 4;
95ea3627
ID		 2208
2209 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2210 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2211 rt2x00_eeprom_addr(rt2x00dev,
2212 EEPROM_MAC_ADDR_0));
2213
2214 /*
2215 * Convert tx_power array in eeprom.
2216 */
2217 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2218 for (i = 0; i < 14; i++)
2219 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2220
2221 /*
2222 * Initialize hw_mode information.
2223 */
31562e80
ID		 2224 spec->supported_bands = SUPPORT_BAND_2GHZ;
2225 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2226 spec->tx_power_a = NULL;
2227 spec->tx_power_bg = txpower;
2228 spec->tx_power_default = DEFAULT_TXPOWER;
2229
2230 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2231 spec->num_channels = 14;
2232 spec->channels = rf_vals_noseq;
2233 } else {
2234 spec->num_channels = 14;
2235 spec->channels = rf_vals_seq;
2236 }
2237
2238 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2239 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
31562e80 2240 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2241 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2242
2243 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2244 for (i = 0; i < 14; i++)
2245 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2246
2247 spec->tx_power_a = txpower;
2248 }
2249}
2250
2251static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2252{
2253 int retval;
2254
2255 /*
2256 * Allocate eeprom data.
2257 */
2258 retval = rt61pci_validate_eeprom(rt2x00dev);
2259 if (retval)
2260 return retval;
2261
2262 retval = rt61pci_init_eeprom(rt2x00dev);
2263 if (retval)
2264 return retval;
2265
2266 /*
2267 * Initialize hw specifications.
2268 */
2269 rt61pci_probe_hw_mode(rt2x00dev);
2270
2271 /*
9404ef34 2272 * This device requires firmware.
95ea3627 2273 */
066cb637 2274 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
95ea3627
ID		 2275
2276 /*
2277 * Set the rssi offset.
2278 */
2279 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2280
2281 return 0;
2282}
2283
2284/*
2285 * IEEE80211 stack callback functions.
2286 */
4150c572
JB		 2287static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2288 unsigned int changed_flags,
2289 unsigned int *total_flags,
2290 int mc_count,
2291 struct dev_addr_list *mc_list)
2292{
2293 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 2294 u32 reg;
2295
2296 /*
2297 * Mask off any flags we are going to ignore from
2298 * the total_flags field.
2299 */
2300 *total_flags &=
2301 FIF_ALLMULTI |
2302 FIF_FCSFAIL |
2303 FIF_PLCPFAIL |
2304 FIF_CONTROL |
2305 FIF_OTHER_BSS |
2306 FIF_PROMISC_IN_BSS;
2307
2308 /*
2309 * Apply some rules to the filters:
2310 * - Some filters imply different filters to be set.
2311 * - Some things we can't filter out at all.
fbb0a27a 2312 * - Multicast filter seems to kill broadcast traffic so never use it.
4150c572 2313 */
fbb0a27a 2314 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 2315 if (*total_flags & FIF_OTHER_BSS ||
2316 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 2317 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 2318
2319 /*
2320 * Check if there is any work left for us.
2321 */
3c4f2085 2322 if (rt2x00dev->packet_filter == *total_flags)
4150c572 2323 return;
3c4f2085 2324 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 2325
2326 /*
2327 * Start configuration steps.
2328 * Note that the version error will always be dropped
2329 * and broadcast frames will always be accepted since
2330 * there is no filter for it at this time.
2331 */
2332 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2333 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2334 !(*total_flags & FIF_FCSFAIL));
2335 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2336 !(*total_flags & FIF_PLCPFAIL));
2337 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2338 !(*total_flags & FIF_CONTROL));
2339 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2340 !(*total_flags & FIF_PROMISC_IN_BSS));
2341 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2342 !(*total_flags & FIF_PROMISC_IN_BSS));
2343 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2344 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2345 !(*total_flags & FIF_ALLMULTI));
e542239f
ID		 2346 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
2347 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
2348 !(*total_flags & FIF_CONTROL));
4150c572
JB		 2349 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2350}
2351
95ea3627
ID		 2352static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2353 u32 short_retry, u32 long_retry)
2354{
2355 struct rt2x00_dev *rt2x00dev = hw->priv;
2356 u32 reg;
2357
2358 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2359 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2360 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2361 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2362
2363 return 0;
2364}
2365
2366static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2367{
2368 struct rt2x00_dev *rt2x00dev = hw->priv;
2369 u64 tsf;
2370 u32 reg;
2371
2372 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2373 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2374 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2375 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2376
2377 return tsf;
2378}
2379
24845910 2380static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
95ea3627
ID		 2381 struct ieee80211_tx_control *control)
2382{
2383 struct rt2x00_dev *rt2x00dev = hw->priv;
6bb40dd1 2384 struct rt2x00_intf *intf = vif_to_intf(control->vif);
181d6902 2385 struct skb_frame_desc *skbdesc;
6bb40dd1 2386 unsigned int beacon_base;
8af244cc 2387 u32 reg;
95ea3627 2388
6bb40dd1
ID		 2389 if (unlikely(!intf->beacon))
2390 return -ENOBUFS;
95ea3627
ID		 2391
2392 /*
2393 * We need to append the descriptor in front of the
2394 * beacon frame.
2395 */
6bb40dd1
ID		 2396 if (skb_headroom(skb) < intf->beacon->queue->desc_size) {
2397 if (pskb_expand_head(skb, intf->beacon->queue->desc_size,
2398 0, GFP_ATOMIC)) {
95ea3627
ID		 2399 dev_kfree_skb(skb);
2400 return -ENOMEM;
2401 }
2402 }
2403
2404 /*
08992f7f
ID		 2405 * Add the descriptor in front of the skb.
2406 */
6bb40dd1
ID		 2407 skb_push(skb, intf->beacon->queue->desc_size);
2408 memset(skb->data, 0, intf->beacon->queue->desc_size);
08992f7f
ID		 2409
2410 /*
2411 * Fill in skb descriptor
95ea3627 2412 */
181d6902
ID		 2413 skbdesc = get_skb_frame_desc(skb);
2414 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 2415 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
6bb40dd1
ID		 2416 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2417 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
181d6902 2418 skbdesc->desc = skb->data;
6bb40dd1
ID		 2419 skbdesc->desc_len = intf->beacon->queue->desc_size;
2420 skbdesc->entry = intf->beacon;
c22eb87b 2421
8af244cc
ID		 2422 /*
2423 * Disable beaconing while we are reloading the beacon data,
2424 * otherwise we might be sending out invalid data.
2425 */
2426 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2427 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2428 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2429 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2430 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2431
6bb40dd1 2432 /*
5957da4c
ID		 2433 * mac80211 doesn't provide the control->queue variable
2434 * for beacons. Set our own queue identification so
2435 * it can be used during descriptor initialization.
6bb40dd1 2436 */
5957da4c 2437 control->queue = RT2X00_BCN_QUEUE_BEACON;
08992f7f 2438 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
95ea3627
ID		 2439
2440 /*
2441 * Write entire beacon with descriptor to register,
2442 * and kick the beacon generator.
2443 */
6bb40dd1
ID		 2444 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2445 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
9ee8f57e 2446 skb->data, skb->len);
6bb40dd1 2447 rt61pci_kick_tx_queue(rt2x00dev, control->queue);
95ea3627
ID		 2448
2449 return 0;
2450}
2451
2452static const struct ieee80211_ops rt61pci_mac80211_ops = {
2453 .tx = rt2x00mac_tx,
4150c572
JB		 2454 .start = rt2x00mac_start,
2455 .stop = rt2x00mac_stop,
95ea3627
ID		 2456 .add_interface = rt2x00mac_add_interface,
2457 .remove_interface = rt2x00mac_remove_interface,
2458 .config = rt2x00mac_config,
2459 .config_interface = rt2x00mac_config_interface,
4150c572 2460 .configure_filter = rt61pci_configure_filter,
95ea3627
ID		 2461 .get_stats = rt2x00mac_get_stats,
2462 .set_retry_limit = rt61pci_set_retry_limit,
471b3efd 2463 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2464 .conf_tx = rt2x00mac_conf_tx,
2465 .get_tx_stats = rt2x00mac_get_tx_stats,
2466 .get_tsf = rt61pci_get_tsf,
95ea3627
ID		 2467 .beacon_update = rt61pci_beacon_update,
2468};
2469
2470static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2471 .irq_handler = rt61pci_interrupt,
2472 .probe_hw = rt61pci_probe_hw,
2473 .get_firmware_name = rt61pci_get_firmware_name,
a7f3a06c 2474 .get_firmware_crc = rt61pci_get_firmware_crc,
95ea3627
ID		 2475 .load_firmware = rt61pci_load_firmware,
2476 .initialize = rt2x00pci_initialize,
2477 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 2478 .init_rxentry = rt61pci_init_rxentry,
2479 .init_txentry = rt61pci_init_txentry,
95ea3627 2480 .set_device_state = rt61pci_set_device_state,
95ea3627 2481 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2482 .link_stats = rt61pci_link_stats,
2483 .reset_tuner = rt61pci_reset_tuner,
2484 .link_tuner = rt61pci_link_tuner,
a9450b70 2485 .led_brightness = rt61pci_led_brightness,
95ea3627
ID		 2486 .write_tx_desc = rt61pci_write_tx_desc,
2487 .write_tx_data = rt2x00pci_write_tx_data,
2488 .kick_tx_queue = rt61pci_kick_tx_queue,
2489 .fill_rxdone = rt61pci_fill_rxdone,
6bb40dd1 2490 .config_intf = rt61pci_config_intf,
72810379 2491 .config_erp = rt61pci_config_erp,
95ea3627
ID		 2492 .config = rt61pci_config,
2493};
2494
181d6902
ID		 2495static const struct data_queue_desc rt61pci_queue_rx = {
2496 .entry_num = RX_ENTRIES,
2497 .data_size = DATA_FRAME_SIZE,
2498 .desc_size = RXD_DESC_SIZE,
2499 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
2500};
2501
2502static const struct data_queue_desc rt61pci_queue_tx = {
2503 .entry_num = TX_ENTRIES,
2504 .data_size = DATA_FRAME_SIZE,
2505 .desc_size = TXD_DESC_SIZE,
2506 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2507};
2508
2509static const struct data_queue_desc rt61pci_queue_bcn = {
6bb40dd1 2510 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2511 .data_size = MGMT_FRAME_SIZE,
2512 .desc_size = TXINFO_SIZE,
2513 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2514};
2515
95ea3627 2516static const struct rt2x00_ops rt61pci_ops = {
2360157c 2517 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2518 .max_sta_intf = 1,
2519 .max_ap_intf = 4,
95ea3627
ID		 2520 .eeprom_size = EEPROM_SIZE,
2521 .rf_size = RF_SIZE,
181d6902
ID		 2522 .rx = &rt61pci_queue_rx,
2523 .tx = &rt61pci_queue_tx,
2524 .bcn = &rt61pci_queue_bcn,
95ea3627
ID		 2525 .lib = &rt61pci_rt2x00_ops,
2526 .hw = &rt61pci_mac80211_ops,
2527#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2528 .debugfs = &rt61pci_rt2x00debug,
2529#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2530};
2531
2532/*
2533 * RT61pci module information.
2534 */
2535static struct pci_device_id rt61pci_device_table[] = {
2536 /* RT2561s */
2537 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2538 /* RT2561 v2 */
2539 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2540 /* RT2661 */
2541 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2542 { 0, }
2543};
2544
2545MODULE_AUTHOR(DRV_PROJECT);
2546MODULE_VERSION(DRV_VERSION);
2547MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2548MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2549 "PCI & PCMCIA chipset based cards");
2550MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2551MODULE_FIRMWARE(FIRMWARE_RT2561);
2552MODULE_FIRMWARE(FIRMWARE_RT2561s);
2553MODULE_FIRMWARE(FIRMWARE_RT2661);
2554MODULE_LICENSE("GPL");
2555
2556static struct pci_driver rt61pci_driver = {
2360157c 2557 .name = KBUILD_MODNAME,
95ea3627
ID		 2558 .id_table = rt61pci_device_table,
2559 .probe = rt2x00pci_probe,
2560 .remove = __devexit_p(rt2x00pci_remove),
2561 .suspend = rt2x00pci_suspend,
2562 .resume = rt2x00pci_resume,
2563};
2564
2565static int __init rt61pci_init(void)
2566{
2567 return pci_register_driver(&rt61pci_driver);
2568}
2569
2570static void __exit rt61pci_exit(void)
2571{
2572 pci_unregister_driver(&rt61pci_driver);
2573}
2574
2575module_init(rt61pci_init);
2576module_exit(rt61pci_exit);
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