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[PATCH] rt2x00: Don't use changed_flags inside configure_packet_filter
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627
ID		 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27/*
28 * Set enviroment defines for rt2x00.h
29 */
30#define DRV_NAME "rt61pci"
31
32#include <linux/delay.h>
33#include <linux/etherdevice.h>
34#include <linux/init.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/eeprom_93cx6.h>
39
40#include "rt2x00.h"
41#include "rt2x00pci.h"
42#include "rt61pci.h"
43
44/*
45 * Register access.
46 * BBP and RF register require indirect register access,
47 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
48 * These indirect registers work with busy bits,
49 * and we will try maximal REGISTER_BUSY_COUNT times to access
50 * the register while taking a REGISTER_BUSY_DELAY us delay
51 * between each attampt. When the busy bit is still set at that time,
52 * the access attempt is considered to have failed,
53 * and we will print an error.
54 */
55static u32 rt61pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
56{
57 u32 reg;
58 unsigned int i;
59
60 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
61 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
62 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
63 break;
64 udelay(REGISTER_BUSY_DELAY);
65 }
66
67 return reg;
68}
69
70static void rt61pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
72{
73 u32 reg;
74
75 /*
76 * Wait until the BBP becomes ready.
77 */
78 reg = rt61pci_bbp_check(rt2x00dev);
79 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
80 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
81 return;
82 }
83
84 /*
85 * Write the data into the BBP.
86 */
87 reg = 0;
88 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
89 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
90 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
91 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
92
93 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
94}
95
96static void rt61pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
97 const unsigned int word, u8 *value)
98{
99 u32 reg;
100
101 /*
102 * Wait until the BBP becomes ready.
103 */
104 reg = rt61pci_bbp_check(rt2x00dev);
105 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
106 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
107 return;
108 }
109
110 /*
111 * Write the request into the BBP.
112 */
113 reg = 0;
114 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
115 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
116 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
117
118 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
119
120 /*
121 * Wait until the BBP becomes ready.
122 */
123 reg = rt61pci_bbp_check(rt2x00dev);
124 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
125 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
126 *value = 0xff;
127 return;
128 }
129
130 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
131}
132
133static void rt61pci_rf_write(const struct rt2x00_dev *rt2x00dev,
134 const unsigned int word, const u32 value)
135{
136 u32 reg;
137 unsigned int i;
138
139 if (!word)
140 return;
141
142 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
143 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
144 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
145 goto rf_write;
146 udelay(REGISTER_BUSY_DELAY);
147 }
148
149 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
150 return;
151
152rf_write:
153 reg = 0;
154 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
155 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
156 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
157 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
158
159 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
160 rt2x00_rf_write(rt2x00dev, word, value);
161}
162
163static void rt61pci_mcu_request(const struct rt2x00_dev *rt2x00dev,
164 const u8 command, const u8 token,
165 const u8 arg0, const u8 arg1)
166{
167 u32 reg;
168
169 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
170
171 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
172 ERROR(rt2x00dev, "mcu request error. "
173 "Request 0x%02x failed for token 0x%02x.\n",
174 command, token);
175 return;
176 }
177
178 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
179 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
181 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
182 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
183
184 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
185 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
186 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
187 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
188}
189
190static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
191{
192 struct rt2x00_dev *rt2x00dev = eeprom->data;
193 u32 reg;
194
195 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
196
197 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
198 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
199 eeprom->reg_data_clock =
200 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
201 eeprom->reg_chip_select =
202 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
203}
204
205static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
206{
207 struct rt2x00_dev *rt2x00dev = eeprom->data;
208 u32 reg = 0;
209
210 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
211 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
212 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
213 !!eeprom->reg_data_clock);
214 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
215 !!eeprom->reg_chip_select);
216
217 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
218}
219
220#ifdef CONFIG_RT2X00_LIB_DEBUGFS
221#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
222
223static void rt61pci_read_csr(const struct rt2x00_dev *rt2x00dev,
224 const unsigned int word, u32 *data)
225{
226 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
227}
228
229static void rt61pci_write_csr(const struct rt2x00_dev *rt2x00dev,
230 const unsigned int word, u32 data)
231{
232 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
233}
234
235static const struct rt2x00debug rt61pci_rt2x00debug = {
236 .owner = THIS_MODULE,
237 .csr = {
238 .read = rt61pci_read_csr,
239 .write = rt61pci_write_csr,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
242 },
243 .eeprom = {
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_size = sizeof(u16),
247 .word_count = EEPROM_SIZE / sizeof(u16),
248 },
249 .bbp = {
250 .read = rt61pci_bbp_read,
251 .write = rt61pci_bbp_write,
252 .word_size = sizeof(u8),
253 .word_count = BBP_SIZE / sizeof(u8),
254 },
255 .rf = {
256 .read = rt2x00_rf_read,
257 .write = rt61pci_rf_write,
258 .word_size = sizeof(u32),
259 .word_count = RF_SIZE / sizeof(u32),
260 },
261};
262#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
263
264#ifdef CONFIG_RT61PCI_RFKILL
265static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
266{
267 u32 reg;
268
269 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
270 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
271}
dcf5475b 272#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627
ID		 273
274/*
275 * Configuration handlers.
276 */
4abee4bb 277static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
95ea3627 278{
95ea3627
ID		 279 u32 tmp;
280
4abee4bb 281 tmp = le32_to_cpu(mac[1]);
95ea3627 282 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
4abee4bb 283 mac[1] = cpu_to_le32(tmp);
95ea3627 284
4abee4bb
ID		 285 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
286 (2 * sizeof(__le32)));
95ea3627
ID		 287}
288
4abee4bb 289static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
95ea3627 290{
95ea3627
ID		 291 u32 tmp;
292
4abee4bb 293 tmp = le32_to_cpu(bssid[1]);
95ea3627 294 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
4abee4bb 295 bssid[1] = cpu_to_le32(tmp);
95ea3627 296
4abee4bb
ID		 297 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
298 (2 * sizeof(__le32)));
95ea3627
ID		 299}
300
95ea3627
ID		 301static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type)
302{
4150c572 303 struct interface *intf = &rt2x00dev->interface;
95ea3627
ID		 304 u32 reg;
305
306 /*
307 * Clear current synchronisation setup.
308 * For the Beacon base registers we only need to clear
309 * the first byte since that byte contains the VALID and OWNER
310 * bits which (when set to 0) will invalidate the entire beacon.
311 */
312 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
313 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
314 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
315 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
316 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
317
95ea3627
ID		 318 /*
319 * Enable synchronisation.
320 */
321 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
4150c572
JB		 322 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
323 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627 324 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
4150c572
JB		 325 if (is_interface_type(intf, IEEE80211_IF_TYPE_IBSS) ||
326 is_interface_type(intf, IEEE80211_IF_TYPE_AP))
95ea3627 327 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 2);
4150c572 328 else if (is_interface_type(intf, IEEE80211_IF_TYPE_STA))
95ea3627 329 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 1);
4150c572 330 else
95ea3627 331 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
95ea3627
ID		 332 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
333}
334
335static void rt61pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
336{
337 struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
338 u32 reg;
339 u32 value;
340 u32 preamble;
341
342 if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
343 preamble = SHORT_PREAMBLE;
344 else
345 preamble = PREAMBLE;
346
347 /*
348 * Extract the allowed ratemask from the device specific rate value,
349 * We need to set TXRX_CSR5 to the basic rate mask so we need to mask
350 * off the non-basic rates.
351 */
352 reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
353
354 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, reg);
355
356 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
357 value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
358 SHORT_DIFS : DIFS) +
359 PLCP + preamble + get_duration(ACK_SIZE, 10);
360 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, value);
361 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
362
363 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
364 if (preamble == SHORT_PREAMBLE)
365 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 1);
366 else
367 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 0);
368 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
369}
370
371static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
372 const int phymode)
373{
374 struct ieee80211_hw_mode *mode;
375 struct ieee80211_rate *rate;
376
377 if (phymode == MODE_IEEE80211A)
378 rt2x00dev->curr_hwmode = HWMODE_A;
379 else if (phymode == MODE_IEEE80211B)
380 rt2x00dev->curr_hwmode = HWMODE_B;
381 else
382 rt2x00dev->curr_hwmode = HWMODE_G;
383
384 mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
385 rate = &mode->rates[mode->num_rates - 1];
386
387 rt61pci_config_rate(rt2x00dev, rate->val2);
388}
389
390static void rt61pci_config_lock_channel(struct rt2x00_dev *rt2x00dev,
391 struct rf_channel *rf,
392 const int txpower)
393{
394 u8 r3;
395 u8 r94;
396 u8 smart;
397
398 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
399 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
400
401 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
402 rt2x00_rf(&rt2x00dev->chip, RF2527));
403
404 rt61pci_bbp_read(rt2x00dev, 3, &r3);
405 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
406 rt61pci_bbp_write(rt2x00dev, 3, r3);
407
408 r94 = 6;
409 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
410 r94 += txpower - MAX_TXPOWER;
411 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
412 r94 += txpower;
413 rt61pci_bbp_write(rt2x00dev, 94, r94);
414
415 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
416 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
417 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
418 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
419
420 udelay(200);
421
422 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
423 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
424 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
425 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
426
427 udelay(200);
428
429 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
430 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
431 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
432 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
433
434 msleep(1);
435}
436
437static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
438 const int index, const int channel,
439 const int txpower)
440{
441 struct rf_channel rf;
442
443 /*
444 * Fill rf_reg structure.
445 */
446 memcpy(&rf, &rt2x00dev->spec.channels[index], sizeof(rf));
447
448 rt61pci_config_lock_channel(rt2x00dev, &rf, txpower);
449}
450
451static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
452 const int txpower)
453{
454 struct rf_channel rf;
455
456 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
457 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
458 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
459 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
460
461 rt61pci_config_lock_channel(rt2x00dev, &rf, txpower);
462}
463
464static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
465 const int antenna_tx,
466 const int antenna_rx)
467{
468 u8 r3;
469 u8 r4;
470 u8 r77;
471
472 rt61pci_bbp_read(rt2x00dev, 3, &r3);
473 rt61pci_bbp_read(rt2x00dev, 4, &r4);
474 rt61pci_bbp_read(rt2x00dev, 77, &r77);
475
476 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
477 !rt2x00_rf(&rt2x00dev->chip, RF5225));
478
479 switch (antenna_rx) {
480 case ANTENNA_SW_DIVERSITY:
481 case ANTENNA_HW_DIVERSITY:
482 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
483 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
484 !!(rt2x00dev->curr_hwmode != HWMODE_A));
485 break;
486 case ANTENNA_A:
487 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
488 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
489
490 if (rt2x00dev->curr_hwmode == HWMODE_A)
491 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
492 else
493 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
494 break;
495 case ANTENNA_B:
496 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
497 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
498
499 if (rt2x00dev->curr_hwmode == HWMODE_A)
500 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
501 else
502 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
503 break;
504 }
505
506 rt61pci_bbp_write(rt2x00dev, 77, r77);
507 rt61pci_bbp_write(rt2x00dev, 3, r3);
508 rt61pci_bbp_write(rt2x00dev, 4, r4);
509}
510
511static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
512 const int antenna_tx,
513 const int antenna_rx)
514{
515 u8 r3;
516 u8 r4;
517 u8 r77;
518
519 rt61pci_bbp_read(rt2x00dev, 3, &r3);
520 rt61pci_bbp_read(rt2x00dev, 4, &r4);
521 rt61pci_bbp_read(rt2x00dev, 77, &r77);
522
523 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
524 !rt2x00_rf(&rt2x00dev->chip, RF2527));
525 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
526 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
527
528 switch (antenna_rx) {
529 case ANTENNA_SW_DIVERSITY:
530 case ANTENNA_HW_DIVERSITY:
531 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
532 break;
533 case ANTENNA_A:
534 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
535 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
536 break;
537 case ANTENNA_B:
538 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
539 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
540 break;
541 }
542
543 rt61pci_bbp_write(rt2x00dev, 77, r77);
544 rt61pci_bbp_write(rt2x00dev, 3, r3);
545 rt61pci_bbp_write(rt2x00dev, 4, r4);
546}
547
548static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
549 const int p1, const int p2)
550{
551 u32 reg;
552
553 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
554
555 if (p1 != 0xff) {
556 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, !!p1);
557 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
558 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
559 }
560 if (p2 != 0xff) {
561 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
562 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
563 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
564 }
565}
566
567static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
568 const int antenna_tx,
569 const int antenna_rx)
570{
571 u16 eeprom;
572 u8 r3;
573 u8 r4;
574 u8 r77;
575
576 rt61pci_bbp_read(rt2x00dev, 3, &r3);
577 rt61pci_bbp_read(rt2x00dev, 4, &r4);
578 rt61pci_bbp_read(rt2x00dev, 77, &r77);
579 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
580
581 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
582
583 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
584 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
585 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
586 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 1);
587 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
588 } else if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) {
589 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED) >= 2) {
590 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
591 rt61pci_bbp_write(rt2x00dev, 77, r77);
592 }
593 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
594 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
595 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
596 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
597 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
598 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
599
600 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
601 case 0:
602 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
603 break;
604 case 1:
605 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
606 break;
607 case 2:
608 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
609 break;
610 case 3:
611 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
612 break;
613 }
614 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
615 !rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
616 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
617 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
618
619 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
620 case 0:
621 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
622 rt61pci_bbp_write(rt2x00dev, 77, r77);
623 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
624 break;
625 case 1:
626 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
627 rt61pci_bbp_write(rt2x00dev, 77, r77);
628 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
629 break;
630 case 2:
631 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
632 rt61pci_bbp_write(rt2x00dev, 77, r77);
633 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
634 break;
635 case 3:
636 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
637 rt61pci_bbp_write(rt2x00dev, 77, r77);
638 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
639 break;
640 }
641 }
642
643 rt61pci_bbp_write(rt2x00dev, 3, r3);
644 rt61pci_bbp_write(rt2x00dev, 4, r4);
645}
646
647struct antenna_sel {
648 u8 word;
649 /*
650 * value[0] -> non-LNA
651 * value[1] -> LNA
652 */
653 u8 value[2];
654};
655
656static const struct antenna_sel antenna_sel_a[] = {
657 { 96, { 0x58, 0x78 } },
658 { 104, { 0x38, 0x48 } },
659 { 75, { 0xfe, 0x80 } },
660 { 86, { 0xfe, 0x80 } },
661 { 88, { 0xfe, 0x80 } },
662 { 35, { 0x60, 0x60 } },
663 { 97, { 0x58, 0x58 } },
664 { 98, { 0x58, 0x58 } },
665};
666
667static const struct antenna_sel antenna_sel_bg[] = {
668 { 96, { 0x48, 0x68 } },
669 { 104, { 0x2c, 0x3c } },
670 { 75, { 0xfe, 0x80 } },
671 { 86, { 0xfe, 0x80 } },
672 { 88, { 0xfe, 0x80 } },
673 { 35, { 0x50, 0x50 } },
674 { 97, { 0x48, 0x48 } },
675 { 98, { 0x48, 0x48 } },
676};
677
678static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
679 const int antenna_tx, const int antenna_rx)
680{
681 const struct antenna_sel *sel;
682 unsigned int lna;
683 unsigned int i;
684 u32 reg;
685
686 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
687
688 if (rt2x00dev->curr_hwmode == HWMODE_A) {
689 sel = antenna_sel_a;
690 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
691
692 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 0);
693 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 1);
694 } else {
695 sel = antenna_sel_bg;
696 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
697
698 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 1);
699 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 0);
700 }
701
702 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
703 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
704
705 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
706
707 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
708 rt2x00_rf(&rt2x00dev->chip, RF5325))
709 rt61pci_config_antenna_5x(rt2x00dev, antenna_tx, antenna_rx);
710 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
711 rt61pci_config_antenna_2x(rt2x00dev, antenna_tx, antenna_rx);
712 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
713 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
714 rt61pci_config_antenna_2x(rt2x00dev, antenna_tx,
715 antenna_rx);
716 else
717 rt61pci_config_antenna_2529(rt2x00dev, antenna_tx,
718 antenna_rx);
719 }
720}
721
722static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
723 const int short_slot_time,
724 const int beacon_int)
725{
726 u32 reg;
727
728 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
729 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME,
730 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
731 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
732
733 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
734 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, SIFS);
735 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
736 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, EIFS);
737 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
738
739 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
740 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
741 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
742
743 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
744 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
745 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
746
747 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
748 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, beacon_int * 16);
749 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
750}
751
752static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
753 const unsigned int flags,
754 struct ieee80211_conf *conf)
755{
756 int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
757
758 if (flags & CONFIG_UPDATE_PHYMODE)
759 rt61pci_config_phymode(rt2x00dev, conf->phymode);
760 if (flags & CONFIG_UPDATE_CHANNEL)
761 rt61pci_config_channel(rt2x00dev, conf->channel_val,
762 conf->channel, conf->power_level);
763 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
764 rt61pci_config_txpower(rt2x00dev, conf->power_level);
765 if (flags & CONFIG_UPDATE_ANTENNA)
766 rt61pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
767 conf->antenna_sel_rx);
768 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
769 rt61pci_config_duration(rt2x00dev, short_slot_time,
770 conf->beacon_int);
771}
772
773/*
774 * LED functions.
775 */
776static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
777{
778 u32 reg;
779 u16 led_reg;
780 u8 arg0;
781 u8 arg1;
782
783 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
784 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
785 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
786 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
787
788 led_reg = rt2x00dev->led_reg;
789 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 1);
790 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
791 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 1);
792 else
793 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 1);
794
795 arg0 = led_reg & 0xff;
796 arg1 = (led_reg >> 8) & 0xff;
797
798 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
799}
800
801static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
802{
803 u16 led_reg;
804 u8 arg0;
805 u8 arg1;
806
807 led_reg = rt2x00dev->led_reg;
808 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
809 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
810 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
811
812 arg0 = led_reg & 0xff;
813 arg1 = (led_reg >> 8) & 0xff;
814
815 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
816}
817
818static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
819{
820 u8 led;
821
822 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
823 return;
824
825 /*
826 * Led handling requires a positive value for the rssi,
827 * to do that correctly we need to add the correction.
828 */
829 rssi += rt2x00dev->rssi_offset;
830
831 if (rssi <= 30)
832 led = 0;
833 else if (rssi <= 39)
834 led = 1;
835 else if (rssi <= 49)
836 led = 2;
837 else if (rssi <= 53)
838 led = 3;
839 else if (rssi <= 63)
840 led = 4;
841 else
842 led = 5;
843
844 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
845}
846
847/*
848 * Link tuning
849 */
850static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev)
851{
852 u32 reg;
853
854 /*
855 * Update FCS error count from register.
856 */
857 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
858 rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
859
860 /*
861 * Update False CCA count from register.
862 */
863 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
864 rt2x00dev->link.false_cca =
865 rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
866}
867
868static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
869{
870 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
871 rt2x00dev->link.vgc_level = 0x20;
872}
873
874static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
875{
876 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
877 u8 r17;
878 u8 up_bound;
879 u8 low_bound;
880
881 /*
882 * Update Led strength
883 */
884 rt61pci_activity_led(rt2x00dev, rssi);
885
886 rt61pci_bbp_read(rt2x00dev, 17, &r17);
887
888 /*
889 * Determine r17 bounds.
890 */
891 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
892 low_bound = 0x28;
893 up_bound = 0x48;
894 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
895 low_bound += 0x10;
896 up_bound += 0x10;
897 }
898 } else {
899 low_bound = 0x20;
900 up_bound = 0x40;
901 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
902 low_bound += 0x10;
903 up_bound += 0x10;
904 }
905 }
906
907 /*
908 * Special big-R17 for very short distance
909 */
910 if (rssi >= -35) {
911 if (r17 != 0x60)
912 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
913 return;
914 }
915
916 /*
917 * Special big-R17 for short distance
918 */
919 if (rssi >= -58) {
920 if (r17 != up_bound)
921 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
922 return;
923 }
924
925 /*
926 * Special big-R17 for middle-short distance
927 */
928 if (rssi >= -66) {
929 low_bound += 0x10;
930 if (r17 != low_bound)
931 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
932 return;
933 }
934
935 /*
936 * Special mid-R17 for middle distance
937 */
938 if (rssi >= -74) {
939 low_bound += 0x08;
940 if (r17 != low_bound)
941 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
942 return;
943 }
944
945 /*
946 * Special case: Change up_bound based on the rssi.
947 * Lower up_bound when rssi is weaker then -74 dBm.
948 */
949 up_bound -= 2 * (-74 - rssi);
950 if (low_bound > up_bound)
951 up_bound = low_bound;
952
953 if (r17 > up_bound) {
954 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
955 return;
956 }
957
958 /*
959 * r17 does not yet exceed upper limit, continue and base
960 * the r17 tuning on the false CCA count.
961 */
962 if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
963 if (++r17 > up_bound)
964 r17 = up_bound;
965 rt61pci_bbp_write(rt2x00dev, 17, r17);
966 } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
967 if (--r17 < low_bound)
968 r17 = low_bound;
969 rt61pci_bbp_write(rt2x00dev, 17, r17);
970 }
971}
972
973/*
974 * Firmware name function.
975 */
976static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
977{
978 char *fw_name;
979
980 switch (rt2x00dev->chip.rt) {
981 case RT2561:
982 fw_name = FIRMWARE_RT2561;
983 break;
984 case RT2561s:
985 fw_name = FIRMWARE_RT2561s;
986 break;
987 case RT2661:
988 fw_name = FIRMWARE_RT2661;
989 break;
990 default:
991 fw_name = NULL;
992 break;
993 }
994
995 return fw_name;
996}
997
998/*
999 * Initialization functions.
1000 */
1001static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
1002 const size_t len)
1003{
1004 int i;
1005 u32 reg;
1006
1007 /*
1008 * Wait for stable hardware.
1009 */
1010 for (i = 0; i < 100; i++) {
1011 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1012 if (reg)
1013 break;
1014 msleep(1);
1015 }
1016
1017 if (!reg) {
1018 ERROR(rt2x00dev, "Unstable hardware.\n");
1019 return -EBUSY;
1020 }
1021
1022 /*
1023 * Prepare MCU and mailbox for firmware loading.
1024 */
1025 reg = 0;
1026 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1027 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1028 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1029 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1030 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1031
1032 /*
1033 * Write firmware to device.
1034 */
1035 reg = 0;
1036 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1037 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1038 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1039
1040 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1041 data, len);
1042
1043 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1044 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1045
1046 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1047 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1048
1049 for (i = 0; i < 100; i++) {
1050 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1051 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1052 break;
1053 msleep(1);
1054 }
1055
1056 if (i == 100) {
1057 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1058 return -EBUSY;
1059 }
1060
1061 /*
1062 * Reset MAC and BBP registers.
1063 */
1064 reg = 0;
1065 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1066 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1067 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1068
1069 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1070 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1071 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1072 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1073
1074 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1075 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1076 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1077
1078 return 0;
1079}
1080
1081static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
1082{
1083 struct data_ring *ring = rt2x00dev->rx;
1084 struct data_desc *rxd;
1085 unsigned int i;
1086 u32 word;
1087
1088 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1089
1090 for (i = 0; i < ring->stats.limit; i++) {
1091 rxd = ring->entry[i].priv;
1092
1093 rt2x00_desc_read(rxd, 5, &word);
1094 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1095 ring->entry[i].data_dma);
1096 rt2x00_desc_write(rxd, 5, word);
1097
1098 rt2x00_desc_read(rxd, 0, &word);
1099 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1100 rt2x00_desc_write(rxd, 0, word);
1101 }
1102
1103 rt2x00_ring_index_clear(rt2x00dev->rx);
1104}
1105
1106static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
1107{
1108 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1109 struct data_desc *txd;
1110 unsigned int i;
1111 u32 word;
1112
1113 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1114
1115 for (i = 0; i < ring->stats.limit; i++) {
1116 txd = ring->entry[i].priv;
1117
1118 rt2x00_desc_read(txd, 1, &word);
1119 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1120 rt2x00_desc_write(txd, 1, word);
1121
1122 rt2x00_desc_read(txd, 5, &word);
1123 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
1124 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
1125 rt2x00_desc_write(txd, 5, word);
1126
1127 rt2x00_desc_read(txd, 6, &word);
1128 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1129 ring->entry[i].data_dma);
1130 rt2x00_desc_write(txd, 6, word);
1131
1132 rt2x00_desc_read(txd, 0, &word);
1133 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1134 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1135 rt2x00_desc_write(txd, 0, word);
1136 }
1137
1138 rt2x00_ring_index_clear(ring);
1139}
1140
1141static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1142{
1143 u32 reg;
1144
1145 /*
1146 * Initialize rings.
1147 */
1148 rt61pci_init_rxring(rt2x00dev);
1149 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1150 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1151 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
1152 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
1153 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
1154
1155 /*
1156 * Initialize registers.
1157 */
1158 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1159 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1160 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
1161 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1162 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
1163 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1164 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
1165 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1166 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
1167 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1168
1169 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1170 rt2x00_set_field32(&reg, TX_RING_CSR1_MGMT_RING_SIZE,
1171 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1172 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1173 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
1174 4);
1175 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1176
1177 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1178 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1179 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1180 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1181
1182 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1183 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1184 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1185 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1186
1187 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1188 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1189 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1190 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1191
1192 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1193 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1194 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1195 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1196
1197 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, &reg);
1198 rt2x00_set_field32(&reg, MGMT_BASE_CSR_RING_REGISTER,
1199 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1200 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1201
1202 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1203 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE,
1204 rt2x00dev->rx->stats.limit);
1205 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1206 rt2x00dev->rx->desc_size / 4);
1207 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1208 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1209
1210 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1211 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1212 rt2x00dev->rx->data_dma);
1213 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1214
1215 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1216 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1217 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1218 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1219 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1220 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_MGMT, 0);
1221 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1222
1223 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1224 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1225 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1226 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1227 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1228 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
1229 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1230
1231 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1232 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1233 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1234
1235 return 0;
1236}
1237
1238static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1239{
1240 u32 reg;
1241
1242 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1243 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1244 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1245 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1246 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1247
1248 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1249 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1250 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1251 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1252 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1253 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1254 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1255 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1256 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1257 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1258
1259 /*
1260 * CCK TXD BBP registers
1261 */
1262 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1263 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1264 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1265 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1266 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1267 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1268 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1269 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1270 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1271 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1272
1273 /*
1274 * OFDM TXD BBP registers
1275 */
1276 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1277 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1278 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1279 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1280 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1281 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1282 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1283 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1284
1285 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1286 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1287 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1288 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1289 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1290 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1291
1292 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1293 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1294 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1295 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1296 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1297 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1298
1299 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1300
1301 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1302
1303 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1304 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1305 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1306
1307 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1308
1309 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1310 return -EBUSY;
1311
1312 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1313
1314 /*
1315 * Invalidate all Shared Keys (SEC_CSR0),
1316 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1317 */
1318 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1319 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1320 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1321
1322 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1323 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1324 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1325 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1326
1327 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1328
1329 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1330
1331 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1332
1333 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1334 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1335 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1336 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1337
1338 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1339 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1340 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1341 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1342
1343 /*
1344 * We must clear the error counters.
1345 * These registers are cleared on read,
1346 * so we may pass a useless variable to store the value.
1347 */
1348 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1349 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1350 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1351
1352 /*
1353 * Reset MAC and BBP registers.
1354 */
1355 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1356 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1357 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1358 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1359
1360 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1361 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1362 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1363 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1364
1365 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1366 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1367 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1368
1369 return 0;
1370}
1371
1372static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1373{
1374 unsigned int i;
1375 u16 eeprom;
1376 u8 reg_id;
1377 u8 value;
1378
1379 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1380 rt61pci_bbp_read(rt2x00dev, 0, &value);
1381 if ((value != 0xff) && (value != 0x00))
1382 goto continue_csr_init;
1383 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1384 udelay(REGISTER_BUSY_DELAY);
1385 }
1386
1387 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1388 return -EACCES;
1389
1390continue_csr_init:
1391 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1392 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1393 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1394 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1395 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1396 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1397 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1398 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1399 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1400 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1401 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1402 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1403 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1404 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1405 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1406 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1407 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1408 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1409 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1410 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1411 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1412 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1413 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1414 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1415
1416 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1417 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1418 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1419
1420 if (eeprom != 0xffff && eeprom != 0x0000) {
1421 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1422 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1423 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1424 reg_id, value);
1425 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1426 }
1427 }
1428 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1429
1430 return 0;
1431}
1432
1433/*
1434 * Device state switch handlers.
1435 */
1436static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1437 enum dev_state state)
1438{
1439 u32 reg;
1440
1441 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1442 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1443 state == STATE_RADIO_RX_OFF);
1444 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1445}
1446
1447static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1448 enum dev_state state)
1449{
1450 int mask = (state == STATE_RADIO_IRQ_OFF);
1451 u32 reg;
1452
1453 /*
1454 * When interrupts are being enabled, the interrupt registers
1455 * should clear the register to assure a clean state.
1456 */
1457 if (state == STATE_RADIO_IRQ_ON) {
1458 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1459 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1460
1461 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1462 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1463 }
1464
1465 /*
1466 * Only toggle the interrupts bits we are going to use.
1467 * Non-checked interrupt bits are disabled by default.
1468 */
1469 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1470 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1471 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1472 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1473 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1474 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1475
1476 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1477 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1478 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1479 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1480 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1481 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1482 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1483 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1484 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1485 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1486}
1487
1488static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1489{
1490 u32 reg;
1491
1492 /*
1493 * Initialize all registers.
1494 */
1495 if (rt61pci_init_rings(rt2x00dev) ||
1496 rt61pci_init_registers(rt2x00dev) ||
1497 rt61pci_init_bbp(rt2x00dev)) {
1498 ERROR(rt2x00dev, "Register initialization failed.\n");
1499 return -EIO;
1500 }
1501
1502 /*
1503 * Enable interrupts.
1504 */
1505 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1506
1507 /*
1508 * Enable RX.
1509 */
1510 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1511 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1512 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1513
1514 /*
1515 * Enable LED
1516 */
1517 rt61pci_enable_led(rt2x00dev);
1518
1519 return 0;
1520}
1521
1522static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1523{
1524 u32 reg;
1525
1526 /*
1527 * Disable LED
1528 */
1529 rt61pci_disable_led(rt2x00dev);
1530
1531 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1532
1533 /*
1534 * Disable synchronisation.
1535 */
1536 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1537
1538 /*
1539 * Cancel RX and TX.
1540 */
1541 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1542 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1543 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1544 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1545 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1546 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1547 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1548
1549 /*
1550 * Disable interrupts.
1551 */
1552 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1553}
1554
1555static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1556{
1557 u32 reg;
1558 unsigned int i;
1559 char put_to_sleep;
1560 char current_state;
1561
1562 put_to_sleep = (state != STATE_AWAKE);
1563
1564 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1565 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1566 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1567 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1568
1569 /*
1570 * Device is not guaranteed to be in the requested state yet.
1571 * We must wait until the register indicates that the
1572 * device has entered the correct state.
1573 */
1574 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1575 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1576 current_state =
1577 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1578 if (current_state == !put_to_sleep)
1579 return 0;
1580 msleep(10);
1581 }
1582
1583 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1584 "current device state %d.\n", !put_to_sleep, current_state);
1585
1586 return -EBUSY;
1587}
1588
1589static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1590 enum dev_state state)
1591{
1592 int retval = 0;
1593
1594 switch (state) {
1595 case STATE_RADIO_ON:
1596 retval = rt61pci_enable_radio(rt2x00dev);
1597 break;
1598 case STATE_RADIO_OFF:
1599 rt61pci_disable_radio(rt2x00dev);
1600 break;
1601 case STATE_RADIO_RX_ON:
1602 case STATE_RADIO_RX_OFF:
1603 rt61pci_toggle_rx(rt2x00dev, state);
1604 break;
1605 case STATE_DEEP_SLEEP:
1606 case STATE_SLEEP:
1607 case STATE_STANDBY:
1608 case STATE_AWAKE:
1609 retval = rt61pci_set_state(rt2x00dev, state);
1610 break;
1611 default:
1612 retval = -ENOTSUPP;
1613 break;
1614 }
1615
1616 return retval;
1617}
1618
1619/*
1620 * TX descriptor initialization
1621 */
1622static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1623 struct data_desc *txd,
4150c572 1624 struct txdata_entry_desc *desc,
95ea3627
ID		 1625 struct ieee80211_hdr *ieee80211hdr,
1626 unsigned int length,
1627 struct ieee80211_tx_control *control)
1628{
1629 u32 word;
1630
1631 /*
1632 * Start writing the descriptor words.
1633 */
1634 rt2x00_desc_read(txd, 1, &word);
1635 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1636 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1637 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1638 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1639 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1640 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1641 rt2x00_desc_write(txd, 1, word);
1642
1643 rt2x00_desc_read(txd, 2, &word);
1644 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1645 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1646 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1647 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1648 rt2x00_desc_write(txd, 2, word);
1649
1650 rt2x00_desc_read(txd, 5, &word);
1651 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1652 TXPOWER_TO_DEV(control->power_level));
1653 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1654 rt2x00_desc_write(txd, 5, word);
1655
1656 rt2x00_desc_read(txd, 11, &word);
1657 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
1658 rt2x00_desc_write(txd, 11, word);
1659
1660 rt2x00_desc_read(txd, 0, &word);
1661 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1662 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1663 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1664 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1665 rt2x00_set_field32(&word, TXD_W0_ACK,
1666 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1667 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1668 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1669 rt2x00_set_field32(&word, TXD_W0_OFDM,
1670 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1671 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1672 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1673 !!(control->flags &
1674 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1675 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1676 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1677 rt2x00_set_field32(&word, TXD_W0_BURST,
1678 test_bit(ENTRY_TXD_BURST, &desc->flags));
1679 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1680 rt2x00_desc_write(txd, 0, word);
1681}
1682
1683/*
1684 * TX data initialization
1685 */
1686static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1687 unsigned int queue)
1688{
1689 u32 reg;
1690
1691 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1692 /*
1693 * For Wi-Fi faily generated beacons between participating
1694 * stations. Set TBTT phase adaptive adjustment step to 8us.
1695 */
1696 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1697
1698 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1699 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1700 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1701 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1702 }
1703 return;
1704 }
1705
1706 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1707 if (queue == IEEE80211_TX_QUEUE_DATA0)
1708 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1709 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1710 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1711 else if (queue == IEEE80211_TX_QUEUE_DATA2)
1712 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1713 else if (queue == IEEE80211_TX_QUEUE_DATA3)
1714 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1715 else if (queue == IEEE80211_TX_QUEUE_DATA4)
1716 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_MGMT, 1);
1717 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1718}
1719
1720/*
1721 * RX control handlers
1722 */
1723static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1724{
1725 u16 eeprom;
1726 u8 offset;
1727 u8 lna;
1728
1729 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1730 switch (lna) {
1731 case 3:
1732 offset = 90;
1733 break;
1734 case 2:
1735 offset = 74;
1736 break;
1737 case 1:
1738 offset = 64;
1739 break;
1740 default:
1741 return 0;
1742 }
1743
1744 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1745 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1746 offset += 14;
1747
1748 if (lna == 3 || lna == 2)
1749 offset += 10;
1750
1751 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1752 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1753 } else {
1754 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1755 offset += 14;
1756
1757 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1758 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1759 }
1760
1761 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1762}
1763
4150c572
JB		 1764static void rt61pci_fill_rxdone(struct data_entry *entry,
1765 struct rxdata_entry_desc *desc)
95ea3627
ID		 1766{
1767 struct data_desc *rxd = entry->priv;
1768 u32 word0;
1769 u32 word1;
1770
1771 rt2x00_desc_read(rxd, 0, &word0);
1772 rt2x00_desc_read(rxd, 1, &word1);
1773
4150c572
JB		 1774 desc->flags = 0;
1775 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1776 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1777
1778 /*
1779 * Obtain the status about this packet.
1780 */
4150c572
JB		 1781 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1782 desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
1783 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1784 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
95ea3627 1785
4150c572 1786 return;
95ea3627
ID		 1787}
1788
1789/*
1790 * Interrupt functions.
1791 */
1792static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1793{
1794 struct data_ring *ring;
1795 struct data_entry *entry;
1796 struct data_desc *txd;
1797 u32 word;
1798 u32 reg;
1799 u32 old_reg;
1800 int type;
1801 int index;
1802 int tx_status;
1803 int retry;
1804
1805 /*
1806 * During each loop we will compare the freshly read
1807 * STA_CSR4 register value with the value read from
1808 * the previous loop. If the 2 values are equal then
1809 * we should stop processing because the chance it
1810 * quite big that the device has been unplugged and
1811 * we risk going into an endless loop.
1812 */
1813 old_reg = 0;
1814
1815 while (1) {
1816 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1817 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1818 break;
1819
1820 if (old_reg == reg)
1821 break;
1822 old_reg = reg;
1823
1824 /*
1825 * Skip this entry when it contains an invalid
1826 * ring identication number.
1827 */
1828 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1829 ring = rt2x00lib_get_ring(rt2x00dev, type);
1830 if (unlikely(!ring))
1831 continue;
1832
1833 /*
1834 * Skip this entry when it contains an invalid
1835 * index number.
1836 */
1837 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1838 if (unlikely(index >= ring->stats.limit))
1839 continue;
1840
1841 entry = &ring->entry[index];
1842 txd = entry->priv;
1843 rt2x00_desc_read(txd, 0, &word);
1844
1845 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1846 !rt2x00_get_field32(word, TXD_W0_VALID))
1847 return;
1848
1849 /*
1850 * Obtain the status about this packet.
1851 */
1852 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1853 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1854
1855 rt2x00lib_txdone(entry, tx_status, retry);
1856
1857 /*
1858 * Make this entry available for reuse.
1859 */
1860 entry->flags = 0;
1861 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1862 rt2x00_desc_write(txd, 0, word);
1863 rt2x00_ring_index_done_inc(entry->ring);
1864
1865 /*
1866 * If the data ring was full before the txdone handler
1867 * we must make sure the packet queue in the mac80211 stack
1868 * is reenabled when the txdone handler has finished.
1869 */
1870 if (!rt2x00_ring_full(ring))
1871 ieee80211_wake_queue(rt2x00dev->hw,
1872 entry->tx_status.control.queue);
1873 }
1874}
1875
1876static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1877{
1878 struct rt2x00_dev *rt2x00dev = dev_instance;
1879 u32 reg_mcu;
1880 u32 reg;
1881
1882 /*
1883 * Get the interrupt sources & saved to local variable.
1884 * Write register value back to clear pending interrupts.
1885 */
1886 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1887 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1888
1889 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1890 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1891
1892 if (!reg && !reg_mcu)
1893 return IRQ_NONE;
1894
1895 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1896 return IRQ_HANDLED;
1897
1898 /*
1899 * Handle interrupts, walk through all bits
1900 * and run the tasks, the bits are checked in order of
1901 * priority.
1902 */
1903
1904 /*
1905 * 1 - Rx ring done interrupt.
1906 */
1907 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1908 rt2x00pci_rxdone(rt2x00dev);
1909
1910 /*
1911 * 2 - Tx ring done interrupt.
1912 */
1913 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1914 rt61pci_txdone(rt2x00dev);
1915
1916 /*
1917 * 3 - Handle MCU command done.
1918 */
1919 if (reg_mcu)
1920 rt2x00pci_register_write(rt2x00dev,
1921 M2H_CMD_DONE_CSR, 0xffffffff);
1922
1923 return IRQ_HANDLED;
1924}
1925
1926/*
1927 * Device probe functions.
1928 */
1929static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1930{
1931 struct eeprom_93cx6 eeprom;
1932 u32 reg;
1933 u16 word;
1934 u8 *mac;
1935 s8 value;
1936
1937 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1938
1939 eeprom.data = rt2x00dev;
1940 eeprom.register_read = rt61pci_eepromregister_read;
1941 eeprom.register_write = rt61pci_eepromregister_write;
1942 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1943 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1944 eeprom.reg_data_in = 0;
1945 eeprom.reg_data_out = 0;
1946 eeprom.reg_data_clock = 0;
1947 eeprom.reg_chip_select = 0;
1948
1949 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1950 EEPROM_SIZE / sizeof(u16));
1951
1952 /*
1953 * Start validation of the data that has been read.
1954 */
1955 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1956 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1957 DECLARE_MAC_BUF(macbuf);
1958
95ea3627 1959 random_ether_addr(mac);
0795af57 1960 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1961 }
1962
1963 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1964 if (word == 0xffff) {
1965 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1966 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2);
1967 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2);
1968 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1969 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1970 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1971 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1972 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1973 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1974 }
1975
1976 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1977 if (word == 0xffff) {
1978 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1979 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1980 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1981 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1982 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1983 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1984 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1985 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1986 }
1987
1988 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1989 if (word == 0xffff) {
1990 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1991 LED_MODE_DEFAULT);
1992 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1993 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1994 }
1995
1996 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1997 if (word == 0xffff) {
1998 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1999 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2000 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2001 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2002 }
2003
2004 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2005 if (word == 0xffff) {
2006 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2007 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2008 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2009 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2010 } else {
2011 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2012 if (value < -10 || value > 10)
2013 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2014 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2015 if (value < -10 || value > 10)
2016 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2017 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2018 }
2019
2020 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2021 if (word == 0xffff) {
2022 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2023 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2024 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2025 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2026 } else {
2027 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2028 if (value < -10 || value > 10)
2029 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2030 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2031 if (value < -10 || value > 10)
2032 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2033 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2034 }
2035
2036 return 0;
2037}
2038
2039static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2040{
2041 u32 reg;
2042 u16 value;
2043 u16 eeprom;
2044 u16 device;
2045
2046 /*
2047 * Read EEPROM word for configuration.
2048 */
2049 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2050
2051 /*
2052 * Identify RF chipset.
2053 * To determine the RT chip we have to read the
2054 * PCI header of the device.
2055 */
2056 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
2057 PCI_CONFIG_HEADER_DEVICE, &device);
2058 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2059 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2060 rt2x00_set_chip(rt2x00dev, device, value, reg);
2061
2062 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2063 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2064 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2065 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2066 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2067 return -ENODEV;
2068 }
2069
2070 /*
2071 * Identify default antenna configuration.
2072 */
2073 rt2x00dev->hw->conf.antenna_sel_tx =
2074 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2075 rt2x00dev->hw->conf.antenna_sel_rx =
2076 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2077
2078 /*
2079 * Read the Frame type.
2080 */
2081 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2082 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2083
2084 /*
2085 * Determine number of antenna's.
2086 */
2087 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2088 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2089
2090 /*
2091 * Detect if this device has an hardware controlled radio.
2092 */
2093 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 2094 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 2095
2096 /*
2097 * Read frequency offset and RF programming sequence.
2098 */
2099 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2100 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2101 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2102
2103 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2104
2105 /*
2106 * Read external LNA informations.
2107 */
2108 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2109
2110 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2111 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2112 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2113 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2114
2115 /*
2116 * Store led settings, for correct led behaviour.
2117 * If the eeprom value is invalid,
2118 * switch to default led mode.
2119 */
2120 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2121
2122 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2123
2124 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2125 rt2x00dev->led_mode);
2126 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2127 rt2x00_get_field16(eeprom,
2128 EEPROM_LED_POLARITY_GPIO_0));
2129 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2130 rt2x00_get_field16(eeprom,
2131 EEPROM_LED_POLARITY_GPIO_1));
2132 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2133 rt2x00_get_field16(eeprom,
2134 EEPROM_LED_POLARITY_GPIO_2));
2135 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2136 rt2x00_get_field16(eeprom,
2137 EEPROM_LED_POLARITY_GPIO_3));
2138 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2139 rt2x00_get_field16(eeprom,
2140 EEPROM_LED_POLARITY_GPIO_4));
2141 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2142 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2143 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2144 rt2x00_get_field16(eeprom,
2145 EEPROM_LED_POLARITY_RDY_G));
2146 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2147 rt2x00_get_field16(eeprom,
2148 EEPROM_LED_POLARITY_RDY_A));
2149
2150 return 0;
2151}
2152
2153/*
2154 * RF value list for RF5225 & RF5325
2155 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2156 */
2157static const struct rf_channel rf_vals_noseq[] = {
2158 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2159 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2160 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2161 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2162 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2163 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2164 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2165 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2166 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2167 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2168 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2169 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2170 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2171 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2172
2173 /* 802.11 UNI / HyperLan 2 */
2174 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2175 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2176 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2177 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2178 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2179 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2180 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2181 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2182
2183 /* 802.11 HyperLan 2 */
2184 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2185 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2186 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2187 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2188 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2189 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2190 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2191 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2192 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2193 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2194
2195 /* 802.11 UNII */
2196 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2197 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2198 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2199 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2200 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2201 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2202
2203 /* MMAC(Japan)J52 ch 34,38,42,46 */
2204 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2205 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2206 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2207 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2208};
2209
2210/*
2211 * RF value list for RF5225 & RF5325
2212 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2213 */
2214static const struct rf_channel rf_vals_seq[] = {
2215 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2216 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2217 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2218 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2219 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2220 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2221 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2222 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2223 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2224 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2225 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2226 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2227 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2228 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2229
2230 /* 802.11 UNI / HyperLan 2 */
2231 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2232 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2233 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2234 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2235 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2236 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2237 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2238 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2239
2240 /* 802.11 HyperLan 2 */
2241 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2242 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2243 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2244 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2245 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2246 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2247 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2248 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2249 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2250 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2251
2252 /* 802.11 UNII */
2253 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2254 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2255 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2256 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2257 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2258 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2259
2260 /* MMAC(Japan)J52 ch 34,38,42,46 */
2261 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2262 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2263 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2264 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2265};
2266
2267static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2268{
2269 struct hw_mode_spec *spec = &rt2x00dev->spec;
2270 u8 *txpower;
2271 unsigned int i;
2272
2273 /*
2274 * Initialize all hw fields.
2275 */
2276 rt2x00dev->hw->flags =
2277 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 2278 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 2279 rt2x00dev->hw->extra_tx_headroom = 0;
2280 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2281 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2282 rt2x00dev->hw->queues = 5;
2283
2284 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2285 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2286 rt2x00_eeprom_addr(rt2x00dev,
2287 EEPROM_MAC_ADDR_0));
2288
2289 /*
2290 * Convert tx_power array in eeprom.
2291 */
2292 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2293 for (i = 0; i < 14; i++)
2294 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2295
2296 /*
2297 * Initialize hw_mode information.
2298 */
2299 spec->num_modes = 2;
2300 spec->num_rates = 12;
2301 spec->tx_power_a = NULL;
2302 spec->tx_power_bg = txpower;
2303 spec->tx_power_default = DEFAULT_TXPOWER;
2304
2305 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2306 spec->num_channels = 14;
2307 spec->channels = rf_vals_noseq;
2308 } else {
2309 spec->num_channels = 14;
2310 spec->channels = rf_vals_seq;
2311 }
2312
2313 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2314 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2315 spec->num_modes = 3;
2316 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2317
2318 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2319 for (i = 0; i < 14; i++)
2320 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2321
2322 spec->tx_power_a = txpower;
2323 }
2324}
2325
2326static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2327{
2328 int retval;
2329
2330 /*
2331 * Allocate eeprom data.
2332 */
2333 retval = rt61pci_validate_eeprom(rt2x00dev);
2334 if (retval)
2335 return retval;
2336
2337 retval = rt61pci_init_eeprom(rt2x00dev);
2338 if (retval)
2339 return retval;
2340
2341 /*
2342 * Initialize hw specifications.
2343 */
2344 rt61pci_probe_hw_mode(rt2x00dev);
2345
2346 /*
2347 * This device requires firmware
2348 */
066cb637 2349 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
95ea3627
ID		 2350
2351 /*
2352 * Set the rssi offset.
2353 */
2354 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2355
2356 return 0;
2357}
2358
2359/*
2360 * IEEE80211 stack callback functions.
2361 */
4150c572
JB		 2362static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2363 unsigned int changed_flags,
2364 unsigned int *total_flags,
2365 int mc_count,
2366 struct dev_addr_list *mc_list)
2367{
2368 struct rt2x00_dev *rt2x00dev = hw->priv;
2369 struct interface *intf = &rt2x00dev->interface;
2370 u32 reg;
2371
2372 /*
2373 * Mask off any flags we are going to ignore from
2374 * the total_flags field.
2375 */
2376 *total_flags &=
2377 FIF_ALLMULTI |
2378 FIF_FCSFAIL |
2379 FIF_PLCPFAIL |
2380 FIF_CONTROL |
2381 FIF_OTHER_BSS |
2382 FIF_PROMISC_IN_BSS;
2383
2384 /*
2385 * Apply some rules to the filters:
2386 * - Some filters imply different filters to be set.
2387 * - Some things we can't filter out at all.
2388 * - Some filters are set based on interface type.
2389 */
2390 if (mc_count)
2391 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 2392 if (*total_flags & FIF_OTHER_BSS ||
2393 *total_flags & FIF_PROMISC_IN_BSS)
4150c572
JB		 2394 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2395 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
2396 *total_flags |= FIF_PROMISC_IN_BSS;
2397
2398 /*
2399 * Check if there is any work left for us.
2400 */
2401 if (intf->filter == *total_flags)
2402 return;
2403 intf->filter = *total_flags;
2404
2405 /*
2406 * Start configuration steps.
2407 * Note that the version error will always be dropped
2408 * and broadcast frames will always be accepted since
2409 * there is no filter for it at this time.
2410 */
2411 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2412 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2413 !(*total_flags & FIF_FCSFAIL));
2414 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2415 !(*total_flags & FIF_PLCPFAIL));
2416 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2417 !(*total_flags & FIF_CONTROL));
2418 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2419 !(*total_flags & FIF_PROMISC_IN_BSS));
2420 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2421 !(*total_flags & FIF_PROMISC_IN_BSS));
2422 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2423 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2424 !(*total_flags & FIF_ALLMULTI));
2425 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
2426 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
2427 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2428}
2429
95ea3627
ID		 2430static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2431 u32 short_retry, u32 long_retry)
2432{
2433 struct rt2x00_dev *rt2x00dev = hw->priv;
2434 u32 reg;
2435
2436 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2437 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2438 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2439 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2440
2441 return 0;
2442}
2443
2444static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2445{
2446 struct rt2x00_dev *rt2x00dev = hw->priv;
2447 u64 tsf;
2448 u32 reg;
2449
2450 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2451 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2452 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2453 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2454
2455 return tsf;
2456}
2457
2458static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2459{
2460 struct rt2x00_dev *rt2x00dev = hw->priv;
2461
2462 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2463 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2464}
2465
24845910 2466static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
95ea3627
ID		 2467 struct ieee80211_tx_control *control)
2468{
2469 struct rt2x00_dev *rt2x00dev = hw->priv;
2470
2471 /*
2472 * Just in case the ieee80211 doesn't set this,
2473 * but we need this queue set for the descriptor
2474 * initialization.
2475 */
2476 control->queue = IEEE80211_TX_QUEUE_BEACON;
2477
2478 /*
2479 * We need to append the descriptor in front of the
2480 * beacon frame.
2481 */
2482 if (skb_headroom(skb) < TXD_DESC_SIZE) {
2483 if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
2484 dev_kfree_skb(skb);
2485 return -ENOMEM;
2486 }
2487 }
2488
2489 /*
2490 * First we create the beacon.
2491 */
2492 skb_push(skb, TXD_DESC_SIZE);
2493 rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
2494 (struct ieee80211_hdr *)(skb->data +
2495 TXD_DESC_SIZE),
2496 skb->len - TXD_DESC_SIZE, control);
2497
2498 /*
2499 * Write entire beacon with descriptor to register,
2500 * and kick the beacon generator.
2501 */
2502 rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0, skb->data, skb->len);
2503 rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2504
2505 return 0;
2506}
2507
2508static const struct ieee80211_ops rt61pci_mac80211_ops = {
2509 .tx = rt2x00mac_tx,
4150c572
JB		 2510 .start = rt2x00mac_start,
2511 .stop = rt2x00mac_stop,
95ea3627
ID		 2512 .add_interface = rt2x00mac_add_interface,
2513 .remove_interface = rt2x00mac_remove_interface,
2514 .config = rt2x00mac_config,
2515 .config_interface = rt2x00mac_config_interface,
4150c572 2516 .configure_filter = rt61pci_configure_filter,
95ea3627
ID		 2517 .get_stats = rt2x00mac_get_stats,
2518 .set_retry_limit = rt61pci_set_retry_limit,
2519 .conf_tx = rt2x00mac_conf_tx,
2520 .get_tx_stats = rt2x00mac_get_tx_stats,
2521 .get_tsf = rt61pci_get_tsf,
2522 .reset_tsf = rt61pci_reset_tsf,
2523 .beacon_update = rt61pci_beacon_update,
2524};
2525
2526static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2527 .irq_handler = rt61pci_interrupt,
2528 .probe_hw = rt61pci_probe_hw,
2529 .get_firmware_name = rt61pci_get_firmware_name,
2530 .load_firmware = rt61pci_load_firmware,
2531 .initialize = rt2x00pci_initialize,
2532 .uninitialize = rt2x00pci_uninitialize,
2533 .set_device_state = rt61pci_set_device_state,
2534#ifdef CONFIG_RT61PCI_RFKILL
2535 .rfkill_poll = rt61pci_rfkill_poll,
2536#endif /* CONFIG_RT61PCI_RFKILL */
2537 .link_stats = rt61pci_link_stats,
2538 .reset_tuner = rt61pci_reset_tuner,
2539 .link_tuner = rt61pci_link_tuner,
2540 .write_tx_desc = rt61pci_write_tx_desc,
2541 .write_tx_data = rt2x00pci_write_tx_data,
2542 .kick_tx_queue = rt61pci_kick_tx_queue,
2543 .fill_rxdone = rt61pci_fill_rxdone,
2544 .config_mac_addr = rt61pci_config_mac_addr,
2545 .config_bssid = rt61pci_config_bssid,
95ea3627
ID		 2546 .config_type = rt61pci_config_type,
2547 .config = rt61pci_config,
2548};
2549
2550static const struct rt2x00_ops rt61pci_ops = {
2551 .name = DRV_NAME,
2552 .rxd_size = RXD_DESC_SIZE,
2553 .txd_size = TXD_DESC_SIZE,
2554 .eeprom_size = EEPROM_SIZE,
2555 .rf_size = RF_SIZE,
2556 .lib = &rt61pci_rt2x00_ops,
2557 .hw = &rt61pci_mac80211_ops,
2558#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2559 .debugfs = &rt61pci_rt2x00debug,
2560#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2561};
2562
2563/*
2564 * RT61pci module information.
2565 */
2566static struct pci_device_id rt61pci_device_table[] = {
2567 /* RT2561s */
2568 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2569 /* RT2561 v2 */
2570 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2571 /* RT2661 */
2572 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2573 { 0, }
2574};
2575
2576MODULE_AUTHOR(DRV_PROJECT);
2577MODULE_VERSION(DRV_VERSION);
2578MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2579MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2580 "PCI & PCMCIA chipset based cards");
2581MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2582MODULE_FIRMWARE(FIRMWARE_RT2561);
2583MODULE_FIRMWARE(FIRMWARE_RT2561s);
2584MODULE_FIRMWARE(FIRMWARE_RT2661);
2585MODULE_LICENSE("GPL");
2586
2587static struct pci_driver rt61pci_driver = {
2588 .name = DRV_NAME,
2589 .id_table = rt61pci_device_table,
2590 .probe = rt2x00pci_probe,
2591 .remove = __devexit_p(rt2x00pci_remove),
2592 .suspend = rt2x00pci_suspend,
2593 .resume = rt2x00pci_resume,
2594};
2595
2596static int __init rt61pci_init(void)
2597{
2598 return pci_register_driver(&rt61pci_driver);
2599}
2600
2601static void __exit rt61pci_exit(void)
2602{
2603 pci_unregister_driver(&rt61pci_driver);
2604}
2605
2606module_init(rt61pci_init);
2607module_exit(rt61pci_exit);
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