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[PATCH] rt2x00: Pass dev_state to rt2x00lib_toggle_rx
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627
ID		 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27/*
28 * Set enviroment defines for rt2x00.h
29 */
30#define DRV_NAME "rt61pci"
31
32#include <linux/delay.h>
33#include <linux/etherdevice.h>
34#include <linux/init.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/eeprom_93cx6.h>
39
40#include "rt2x00.h"
41#include "rt2x00pci.h"
42#include "rt61pci.h"
43
44/*
45 * Register access.
46 * BBP and RF register require indirect register access,
47 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
48 * These indirect registers work with busy bits,
49 * and we will try maximal REGISTER_BUSY_COUNT times to access
50 * the register while taking a REGISTER_BUSY_DELAY us delay
51 * between each attampt. When the busy bit is still set at that time,
52 * the access attempt is considered to have failed,
53 * and we will print an error.
54 */
55static u32 rt61pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
56{
57 u32 reg;
58 unsigned int i;
59
60 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
61 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
62 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
63 break;
64 udelay(REGISTER_BUSY_DELAY);
65 }
66
67 return reg;
68}
69
70static void rt61pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
72{
73 u32 reg;
74
75 /*
76 * Wait until the BBP becomes ready.
77 */
78 reg = rt61pci_bbp_check(rt2x00dev);
79 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
80 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
81 return;
82 }
83
84 /*
85 * Write the data into the BBP.
86 */
87 reg = 0;
88 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
89 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
90 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
91 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
92
93 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
94}
95
96static void rt61pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
97 const unsigned int word, u8 *value)
98{
99 u32 reg;
100
101 /*
102 * Wait until the BBP becomes ready.
103 */
104 reg = rt61pci_bbp_check(rt2x00dev);
105 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
106 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
107 return;
108 }
109
110 /*
111 * Write the request into the BBP.
112 */
113 reg = 0;
114 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
115 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
116 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
117
118 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
119
120 /*
121 * Wait until the BBP becomes ready.
122 */
123 reg = rt61pci_bbp_check(rt2x00dev);
124 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
125 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
126 *value = 0xff;
127 return;
128 }
129
130 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
131}
132
133static void rt61pci_rf_write(const struct rt2x00_dev *rt2x00dev,
134 const unsigned int word, const u32 value)
135{
136 u32 reg;
137 unsigned int i;
138
139 if (!word)
140 return;
141
142 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
143 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
144 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
145 goto rf_write;
146 udelay(REGISTER_BUSY_DELAY);
147 }
148
149 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
150 return;
151
152rf_write:
153 reg = 0;
154 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
155 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
156 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
157 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
158
159 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
160 rt2x00_rf_write(rt2x00dev, word, value);
161}
162
163static void rt61pci_mcu_request(const struct rt2x00_dev *rt2x00dev,
164 const u8 command, const u8 token,
165 const u8 arg0, const u8 arg1)
166{
167 u32 reg;
168
169 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
170
171 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
172 ERROR(rt2x00dev, "mcu request error. "
173 "Request 0x%02x failed for token 0x%02x.\n",
174 command, token);
175 return;
176 }
177
178 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
179 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
181 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
182 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
183
184 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
185 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
186 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
187 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
188}
189
190static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
191{
192 struct rt2x00_dev *rt2x00dev = eeprom->data;
193 u32 reg;
194
195 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
196
197 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
198 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
199 eeprom->reg_data_clock =
200 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
201 eeprom->reg_chip_select =
202 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
203}
204
205static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
206{
207 struct rt2x00_dev *rt2x00dev = eeprom->data;
208 u32 reg = 0;
209
210 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
211 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
212 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
213 !!eeprom->reg_data_clock);
214 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
215 !!eeprom->reg_chip_select);
216
217 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
218}
219
220#ifdef CONFIG_RT2X00_LIB_DEBUGFS
221#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
222
223static void rt61pci_read_csr(const struct rt2x00_dev *rt2x00dev,
224 const unsigned int word, u32 *data)
225{
226 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
227}
228
229static void rt61pci_write_csr(const struct rt2x00_dev *rt2x00dev,
230 const unsigned int word, u32 data)
231{
232 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
233}
234
235static const struct rt2x00debug rt61pci_rt2x00debug = {
236 .owner = THIS_MODULE,
237 .csr = {
238 .read = rt61pci_read_csr,
239 .write = rt61pci_write_csr,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
242 },
243 .eeprom = {
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_size = sizeof(u16),
247 .word_count = EEPROM_SIZE / sizeof(u16),
248 },
249 .bbp = {
250 .read = rt61pci_bbp_read,
251 .write = rt61pci_bbp_write,
252 .word_size = sizeof(u8),
253 .word_count = BBP_SIZE / sizeof(u8),
254 },
255 .rf = {
256 .read = rt2x00_rf_read,
257 .write = rt61pci_rf_write,
258 .word_size = sizeof(u32),
259 .word_count = RF_SIZE / sizeof(u32),
260 },
261};
262#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
263
264#ifdef CONFIG_RT61PCI_RFKILL
265static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
266{
267 u32 reg;
268
269 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
270 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
271}
81873e9c
ID		 272#else
273#define rt61pci_rfkill_poll NULL
dcf5475b 274#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627
ID		 275
276/*
277 * Configuration handlers.
278 */
4abee4bb 279static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
95ea3627 280{
95ea3627
ID		 281 u32 tmp;
282
4abee4bb 283 tmp = le32_to_cpu(mac[1]);
95ea3627 284 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
4abee4bb 285 mac[1] = cpu_to_le32(tmp);
95ea3627 286
4abee4bb
ID		 287 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
288 (2 * sizeof(__le32)));
95ea3627
ID		 289}
290
4abee4bb 291static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
95ea3627 292{
95ea3627
ID		 293 u32 tmp;
294
4abee4bb 295 tmp = le32_to_cpu(bssid[1]);
95ea3627 296 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
4abee4bb 297 bssid[1] = cpu_to_le32(tmp);
95ea3627 298
4abee4bb
ID		 299 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
300 (2 * sizeof(__le32)));
95ea3627
ID		 301}
302
feb24691
ID		 303static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
304 const int tsf_sync)
95ea3627
ID		 305{
306 u32 reg;
307
308 /*
309 * Clear current synchronisation setup.
310 * For the Beacon base registers we only need to clear
311 * the first byte since that byte contains the VALID and OWNER
312 * bits which (when set to 0) will invalidate the entire beacon.
313 */
314 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
315 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
316 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
317 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
318 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
319
95ea3627
ID		 320 /*
321 * Enable synchronisation.
322 */
323 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
4150c572
JB		 324 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
325 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627 326 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
feb24691 327 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
95ea3627
ID		 328 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
329}
330
331static void rt61pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
332{
333 struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
334 u32 reg;
335 u32 value;
336 u32 preamble;
337
338 if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
339 preamble = SHORT_PREAMBLE;
340 else
341 preamble = PREAMBLE;
342
343 /*
344 * Extract the allowed ratemask from the device specific rate value,
345 * We need to set TXRX_CSR5 to the basic rate mask so we need to mask
346 * off the non-basic rates.
347 */
348 reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
349
350 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, reg);
351
352 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
353 value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
354 SHORT_DIFS : DIFS) +
355 PLCP + preamble + get_duration(ACK_SIZE, 10);
356 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, value);
357 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
358
359 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
360 if (preamble == SHORT_PREAMBLE)
361 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 1);
362 else
363 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 0);
364 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
365}
366
367static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
368 const int phymode)
369{
370 struct ieee80211_hw_mode *mode;
371 struct ieee80211_rate *rate;
372
373 if (phymode == MODE_IEEE80211A)
374 rt2x00dev->curr_hwmode = HWMODE_A;
375 else if (phymode == MODE_IEEE80211B)
376 rt2x00dev->curr_hwmode = HWMODE_B;
377 else
378 rt2x00dev->curr_hwmode = HWMODE_G;
379
380 mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
381 rate = &mode->rates[mode->num_rates - 1];
382
383 rt61pci_config_rate(rt2x00dev, rate->val2);
384}
385
386static void rt61pci_config_lock_channel(struct rt2x00_dev *rt2x00dev,
387 struct rf_channel *rf,
388 const int txpower)
389{
390 u8 r3;
391 u8 r94;
392 u8 smart;
393
394 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
395 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
396
397 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
398 rt2x00_rf(&rt2x00dev->chip, RF2527));
399
400 rt61pci_bbp_read(rt2x00dev, 3, &r3);
401 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
402 rt61pci_bbp_write(rt2x00dev, 3, r3);
403
404 r94 = 6;
405 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
406 r94 += txpower - MAX_TXPOWER;
407 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
408 r94 += txpower;
409 rt61pci_bbp_write(rt2x00dev, 94, r94);
410
411 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
412 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
413 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
414 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
415
416 udelay(200);
417
418 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
419 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
420 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
421 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
422
423 udelay(200);
424
425 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
426 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
427 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
428 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
429
430 msleep(1);
431}
432
433static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
434 const int index, const int channel,
435 const int txpower)
436{
437 struct rf_channel rf;
438
439 /*
440 * Fill rf_reg structure.
441 */
442 memcpy(&rf, &rt2x00dev->spec.channels[index], sizeof(rf));
443
444 rt61pci_config_lock_channel(rt2x00dev, &rf, txpower);
445}
446
447static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
448 const int txpower)
449{
450 struct rf_channel rf;
451
452 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
453 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
454 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
455 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
456
457 rt61pci_config_lock_channel(rt2x00dev, &rf, txpower);
458}
459
460static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
461 const int antenna_tx,
462 const int antenna_rx)
463{
464 u8 r3;
465 u8 r4;
466 u8 r77;
467
468 rt61pci_bbp_read(rt2x00dev, 3, &r3);
469 rt61pci_bbp_read(rt2x00dev, 4, &r4);
470 rt61pci_bbp_read(rt2x00dev, 77, &r77);
471
472 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
473 !rt2x00_rf(&rt2x00dev->chip, RF5225));
474
475 switch (antenna_rx) {
476 case ANTENNA_SW_DIVERSITY:
477 case ANTENNA_HW_DIVERSITY:
478 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
479 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
480 !!(rt2x00dev->curr_hwmode != HWMODE_A));
481 break;
482 case ANTENNA_A:
483 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
484 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
485
486 if (rt2x00dev->curr_hwmode == HWMODE_A)
487 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
488 else
489 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
490 break;
491 case ANTENNA_B:
492 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
493 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
494
495 if (rt2x00dev->curr_hwmode == HWMODE_A)
496 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
497 else
498 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
499 break;
500 }
501
502 rt61pci_bbp_write(rt2x00dev, 77, r77);
503 rt61pci_bbp_write(rt2x00dev, 3, r3);
504 rt61pci_bbp_write(rt2x00dev, 4, r4);
505}
506
507static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
508 const int antenna_tx,
509 const int antenna_rx)
510{
511 u8 r3;
512 u8 r4;
513 u8 r77;
514
515 rt61pci_bbp_read(rt2x00dev, 3, &r3);
516 rt61pci_bbp_read(rt2x00dev, 4, &r4);
517 rt61pci_bbp_read(rt2x00dev, 77, &r77);
518
519 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
520 !rt2x00_rf(&rt2x00dev->chip, RF2527));
521 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
522 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
523
524 switch (antenna_rx) {
525 case ANTENNA_SW_DIVERSITY:
526 case ANTENNA_HW_DIVERSITY:
527 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
528 break;
529 case ANTENNA_A:
530 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
531 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
532 break;
533 case ANTENNA_B:
534 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
535 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
536 break;
537 }
538
539 rt61pci_bbp_write(rt2x00dev, 77, r77);
540 rt61pci_bbp_write(rt2x00dev, 3, r3);
541 rt61pci_bbp_write(rt2x00dev, 4, r4);
542}
543
544static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
545 const int p1, const int p2)
546{
547 u32 reg;
548
549 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
550
551 if (p1 != 0xff) {
552 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, !!p1);
553 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
554 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
555 }
556 if (p2 != 0xff) {
557 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
558 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
559 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
560 }
561}
562
563static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
564 const int antenna_tx,
565 const int antenna_rx)
566{
567 u16 eeprom;
568 u8 r3;
569 u8 r4;
570 u8 r77;
571
572 rt61pci_bbp_read(rt2x00dev, 3, &r3);
573 rt61pci_bbp_read(rt2x00dev, 4, &r4);
574 rt61pci_bbp_read(rt2x00dev, 77, &r77);
575 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
576
577 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
578
579 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
580 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
581 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
582 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 1);
583 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
584 } else if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) {
585 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED) >= 2) {
586 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
587 rt61pci_bbp_write(rt2x00dev, 77, r77);
588 }
589 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
590 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
591 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
592 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
593 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
594 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
595
596 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
597 case 0:
598 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
599 break;
600 case 1:
601 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
602 break;
603 case 2:
604 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
605 break;
606 case 3:
607 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
608 break;
609 }
610 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
611 !rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
612 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
613 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
614
615 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
616 case 0:
617 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
618 rt61pci_bbp_write(rt2x00dev, 77, r77);
619 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
620 break;
621 case 1:
622 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
623 rt61pci_bbp_write(rt2x00dev, 77, r77);
624 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
625 break;
626 case 2:
627 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
628 rt61pci_bbp_write(rt2x00dev, 77, r77);
629 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
630 break;
631 case 3:
632 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
633 rt61pci_bbp_write(rt2x00dev, 77, r77);
634 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
635 break;
636 }
637 }
638
639 rt61pci_bbp_write(rt2x00dev, 3, r3);
640 rt61pci_bbp_write(rt2x00dev, 4, r4);
641}
642
643struct antenna_sel {
644 u8 word;
645 /*
646 * value[0] -> non-LNA
647 * value[1] -> LNA
648 */
649 u8 value[2];
650};
651
652static const struct antenna_sel antenna_sel_a[] = {
653 { 96, { 0x58, 0x78 } },
654 { 104, { 0x38, 0x48 } },
655 { 75, { 0xfe, 0x80 } },
656 { 86, { 0xfe, 0x80 } },
657 { 88, { 0xfe, 0x80 } },
658 { 35, { 0x60, 0x60 } },
659 { 97, { 0x58, 0x58 } },
660 { 98, { 0x58, 0x58 } },
661};
662
663static const struct antenna_sel antenna_sel_bg[] = {
664 { 96, { 0x48, 0x68 } },
665 { 104, { 0x2c, 0x3c } },
666 { 75, { 0xfe, 0x80 } },
667 { 86, { 0xfe, 0x80 } },
668 { 88, { 0xfe, 0x80 } },
669 { 35, { 0x50, 0x50 } },
670 { 97, { 0x48, 0x48 } },
671 { 98, { 0x48, 0x48 } },
672};
673
674static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
675 const int antenna_tx, const int antenna_rx)
676{
677 const struct antenna_sel *sel;
678 unsigned int lna;
679 unsigned int i;
680 u32 reg;
681
682 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
683
684 if (rt2x00dev->curr_hwmode == HWMODE_A) {
685 sel = antenna_sel_a;
686 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
687
688 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 0);
689 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 1);
690 } else {
691 sel = antenna_sel_bg;
692 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
693
694 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 1);
695 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 0);
696 }
697
698 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
699 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
700
701 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
702
703 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
704 rt2x00_rf(&rt2x00dev->chip, RF5325))
705 rt61pci_config_antenna_5x(rt2x00dev, antenna_tx, antenna_rx);
706 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
707 rt61pci_config_antenna_2x(rt2x00dev, antenna_tx, antenna_rx);
708 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
709 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
710 rt61pci_config_antenna_2x(rt2x00dev, antenna_tx,
711 antenna_rx);
712 else
713 rt61pci_config_antenna_2529(rt2x00dev, antenna_tx,
714 antenna_rx);
715 }
716}
717
718static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
719 const int short_slot_time,
720 const int beacon_int)
721{
722 u32 reg;
723
724 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
725 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME,
726 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
727 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
728
729 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
730 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, SIFS);
731 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
732 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, EIFS);
733 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
734
735 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
736 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
737 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
738
739 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
740 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
741 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
742
743 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
744 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, beacon_int * 16);
745 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
746}
747
748static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
749 const unsigned int flags,
750 struct ieee80211_conf *conf)
751{
752 int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
753
754 if (flags & CONFIG_UPDATE_PHYMODE)
755 rt61pci_config_phymode(rt2x00dev, conf->phymode);
756 if (flags & CONFIG_UPDATE_CHANNEL)
757 rt61pci_config_channel(rt2x00dev, conf->channel_val,
758 conf->channel, conf->power_level);
759 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
760 rt61pci_config_txpower(rt2x00dev, conf->power_level);
761 if (flags & CONFIG_UPDATE_ANTENNA)
762 rt61pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
763 conf->antenna_sel_rx);
764 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
765 rt61pci_config_duration(rt2x00dev, short_slot_time,
766 conf->beacon_int);
767}
768
769/*
770 * LED functions.
771 */
772static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
773{
774 u32 reg;
775 u16 led_reg;
776 u8 arg0;
777 u8 arg1;
778
779 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
780 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
781 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
782 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
783
784 led_reg = rt2x00dev->led_reg;
785 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 1);
786 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
787 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 1);
788 else
789 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 1);
790
791 arg0 = led_reg & 0xff;
792 arg1 = (led_reg >> 8) & 0xff;
793
794 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
795}
796
797static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
798{
799 u16 led_reg;
800 u8 arg0;
801 u8 arg1;
802
803 led_reg = rt2x00dev->led_reg;
804 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
805 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
806 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
807
808 arg0 = led_reg & 0xff;
809 arg1 = (led_reg >> 8) & 0xff;
810
811 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
812}
813
814static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
815{
816 u8 led;
817
818 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
819 return;
820
821 /*
822 * Led handling requires a positive value for the rssi,
823 * to do that correctly we need to add the correction.
824 */
825 rssi += rt2x00dev->rssi_offset;
826
827 if (rssi <= 30)
828 led = 0;
829 else if (rssi <= 39)
830 led = 1;
831 else if (rssi <= 49)
832 led = 2;
833 else if (rssi <= 53)
834 led = 3;
835 else if (rssi <= 63)
836 led = 4;
837 else
838 led = 5;
839
840 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
841}
842
843/*
844 * Link tuning
845 */
846static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev)
847{
848 u32 reg;
849
850 /*
851 * Update FCS error count from register.
852 */
853 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
854 rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
855
856 /*
857 * Update False CCA count from register.
858 */
859 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
860 rt2x00dev->link.false_cca =
861 rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
862}
863
864static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
865{
866 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
867 rt2x00dev->link.vgc_level = 0x20;
868}
869
870static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
871{
872 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
873 u8 r17;
874 u8 up_bound;
875 u8 low_bound;
876
877 /*
878 * Update Led strength
879 */
880 rt61pci_activity_led(rt2x00dev, rssi);
881
882 rt61pci_bbp_read(rt2x00dev, 17, &r17);
883
884 /*
885 * Determine r17 bounds.
886 */
887 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
888 low_bound = 0x28;
889 up_bound = 0x48;
890 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
891 low_bound += 0x10;
892 up_bound += 0x10;
893 }
894 } else {
895 low_bound = 0x20;
896 up_bound = 0x40;
897 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
898 low_bound += 0x10;
899 up_bound += 0x10;
900 }
901 }
902
903 /*
904 * Special big-R17 for very short distance
905 */
906 if (rssi >= -35) {
907 if (r17 != 0x60)
908 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
909 return;
910 }
911
912 /*
913 * Special big-R17 for short distance
914 */
915 if (rssi >= -58) {
916 if (r17 != up_bound)
917 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
918 return;
919 }
920
921 /*
922 * Special big-R17 for middle-short distance
923 */
924 if (rssi >= -66) {
925 low_bound += 0x10;
926 if (r17 != low_bound)
927 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
928 return;
929 }
930
931 /*
932 * Special mid-R17 for middle distance
933 */
934 if (rssi >= -74) {
935 low_bound += 0x08;
936 if (r17 != low_bound)
937 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
938 return;
939 }
940
941 /*
942 * Special case: Change up_bound based on the rssi.
943 * Lower up_bound when rssi is weaker then -74 dBm.
944 */
945 up_bound -= 2 * (-74 - rssi);
946 if (low_bound > up_bound)
947 up_bound = low_bound;
948
949 if (r17 > up_bound) {
950 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
951 return;
952 }
953
954 /*
955 * r17 does not yet exceed upper limit, continue and base
956 * the r17 tuning on the false CCA count.
957 */
958 if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
959 if (++r17 > up_bound)
960 r17 = up_bound;
961 rt61pci_bbp_write(rt2x00dev, 17, r17);
962 } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
963 if (--r17 < low_bound)
964 r17 = low_bound;
965 rt61pci_bbp_write(rt2x00dev, 17, r17);
966 }
967}
968
969/*
970 * Firmware name function.
971 */
972static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
973{
974 char *fw_name;
975
976 switch (rt2x00dev->chip.rt) {
977 case RT2561:
978 fw_name = FIRMWARE_RT2561;
979 break;
980 case RT2561s:
981 fw_name = FIRMWARE_RT2561s;
982 break;
983 case RT2661:
984 fw_name = FIRMWARE_RT2661;
985 break;
986 default:
987 fw_name = NULL;
988 break;
989 }
990
991 return fw_name;
992}
993
994/*
995 * Initialization functions.
996 */
997static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
998 const size_t len)
999{
1000 int i;
1001 u32 reg;
1002
1003 /*
1004 * Wait for stable hardware.
1005 */
1006 for (i = 0; i < 100; i++) {
1007 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1008 if (reg)
1009 break;
1010 msleep(1);
1011 }
1012
1013 if (!reg) {
1014 ERROR(rt2x00dev, "Unstable hardware.\n");
1015 return -EBUSY;
1016 }
1017
1018 /*
1019 * Prepare MCU and mailbox for firmware loading.
1020 */
1021 reg = 0;
1022 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1023 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1024 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1025 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1026 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1027
1028 /*
1029 * Write firmware to device.
1030 */
1031 reg = 0;
1032 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1033 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1034 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1035
1036 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1037 data, len);
1038
1039 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1040 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1041
1042 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1043 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1044
1045 for (i = 0; i < 100; i++) {
1046 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1047 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1048 break;
1049 msleep(1);
1050 }
1051
1052 if (i == 100) {
1053 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1054 return -EBUSY;
1055 }
1056
1057 /*
1058 * Reset MAC and BBP registers.
1059 */
1060 reg = 0;
1061 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1062 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1063 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1064
1065 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1066 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1067 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1068 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1069
1070 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1071 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1072 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1073
1074 return 0;
1075}
1076
1077static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
1078{
1079 struct data_ring *ring = rt2x00dev->rx;
1080 struct data_desc *rxd;
1081 unsigned int i;
1082 u32 word;
1083
1084 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1085
1086 for (i = 0; i < ring->stats.limit; i++) {
1087 rxd = ring->entry[i].priv;
1088
1089 rt2x00_desc_read(rxd, 5, &word);
1090 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1091 ring->entry[i].data_dma);
1092 rt2x00_desc_write(rxd, 5, word);
1093
1094 rt2x00_desc_read(rxd, 0, &word);
1095 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1096 rt2x00_desc_write(rxd, 0, word);
1097 }
1098
1099 rt2x00_ring_index_clear(rt2x00dev->rx);
1100}
1101
1102static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
1103{
1104 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1105 struct data_desc *txd;
1106 unsigned int i;
1107 u32 word;
1108
1109 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1110
1111 for (i = 0; i < ring->stats.limit; i++) {
1112 txd = ring->entry[i].priv;
1113
1114 rt2x00_desc_read(txd, 1, &word);
1115 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1116 rt2x00_desc_write(txd, 1, word);
1117
1118 rt2x00_desc_read(txd, 5, &word);
1119 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
1120 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
1121 rt2x00_desc_write(txd, 5, word);
1122
1123 rt2x00_desc_read(txd, 6, &word);
1124 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1125 ring->entry[i].data_dma);
1126 rt2x00_desc_write(txd, 6, word);
1127
1128 rt2x00_desc_read(txd, 0, &word);
1129 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1130 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1131 rt2x00_desc_write(txd, 0, word);
1132 }
1133
1134 rt2x00_ring_index_clear(ring);
1135}
1136
1137static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1138{
1139 u32 reg;
1140
1141 /*
1142 * Initialize rings.
1143 */
1144 rt61pci_init_rxring(rt2x00dev);
1145 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1146 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1147 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
1148 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
1149 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
1150
1151 /*
1152 * Initialize registers.
1153 */
1154 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1155 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1156 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
1157 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1158 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
1159 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1160 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
1161 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1162 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
1163 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1164
1165 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1166 rt2x00_set_field32(&reg, TX_RING_CSR1_MGMT_RING_SIZE,
1167 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1168 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1169 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
1170 4);
1171 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1172
1173 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1174 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1175 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1176 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1177
1178 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1179 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1180 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1181 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1182
1183 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1184 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1185 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1186 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1187
1188 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1189 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1190 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1191 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1192
1193 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, &reg);
1194 rt2x00_set_field32(&reg, MGMT_BASE_CSR_RING_REGISTER,
1195 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1196 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1197
1198 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1199 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE,
1200 rt2x00dev->rx->stats.limit);
1201 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1202 rt2x00dev->rx->desc_size / 4);
1203 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1204 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1205
1206 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1207 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1208 rt2x00dev->rx->data_dma);
1209 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1210
1211 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1212 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1213 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1214 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1215 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1216 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_MGMT, 0);
1217 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1218
1219 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1220 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1221 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1222 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1223 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1224 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
1225 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1226
1227 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1228 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1229 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1230
1231 return 0;
1232}
1233
1234static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1235{
1236 u32 reg;
1237
1238 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1239 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1240 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1241 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1242 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1243
1244 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1245 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1246 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1247 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1248 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1249 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1250 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1251 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1252 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1253 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1254
1255 /*
1256 * CCK TXD BBP registers
1257 */
1258 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1259 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1260 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1261 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1262 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1263 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1264 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1265 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1266 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1267 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1268
1269 /*
1270 * OFDM TXD BBP registers
1271 */
1272 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1273 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1274 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1275 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1276 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1277 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1278 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1279 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1280
1281 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1282 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1283 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1284 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1285 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1286 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1287
1288 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1289 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1290 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1291 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1292 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1293 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1294
1295 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1296
1297 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1298
1299 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1300 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1301 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1302
1303 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1304
1305 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1306 return -EBUSY;
1307
1308 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1309
1310 /*
1311 * Invalidate all Shared Keys (SEC_CSR0),
1312 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1313 */
1314 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1315 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1316 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1317
1318 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1319 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1320 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1321 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1322
1323 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1324
1325 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1326
1327 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1328
1329 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1330 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1331 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1332 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1333
1334 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1335 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1336 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1337 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1338
1339 /*
1340 * We must clear the error counters.
1341 * These registers are cleared on read,
1342 * so we may pass a useless variable to store the value.
1343 */
1344 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1345 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1346 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1347
1348 /*
1349 * Reset MAC and BBP registers.
1350 */
1351 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1352 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1353 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1354 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1355
1356 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1357 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1358 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1359 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1360
1361 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1362 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1363 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1364
1365 return 0;
1366}
1367
1368static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1369{
1370 unsigned int i;
1371 u16 eeprom;
1372 u8 reg_id;
1373 u8 value;
1374
1375 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1376 rt61pci_bbp_read(rt2x00dev, 0, &value);
1377 if ((value != 0xff) && (value != 0x00))
1378 goto continue_csr_init;
1379 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1380 udelay(REGISTER_BUSY_DELAY);
1381 }
1382
1383 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1384 return -EACCES;
1385
1386continue_csr_init:
1387 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1388 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1389 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1390 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1391 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1392 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1393 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1394 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1395 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1396 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1397 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1398 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1399 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1400 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1401 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1402 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1403 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1404 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1405 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1406 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1407 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1408 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1409 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1410 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1411
1412 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1413 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1414 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1415
1416 if (eeprom != 0xffff && eeprom != 0x0000) {
1417 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1418 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1419 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1420 reg_id, value);
1421 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1422 }
1423 }
1424 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1425
1426 return 0;
1427}
1428
1429/*
1430 * Device state switch handlers.
1431 */
1432static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1433 enum dev_state state)
1434{
1435 u32 reg;
1436
1437 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1438 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1439 state == STATE_RADIO_RX_OFF);
1440 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1441}
1442
1443static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1444 enum dev_state state)
1445{
1446 int mask = (state == STATE_RADIO_IRQ_OFF);
1447 u32 reg;
1448
1449 /*
1450 * When interrupts are being enabled, the interrupt registers
1451 * should clear the register to assure a clean state.
1452 */
1453 if (state == STATE_RADIO_IRQ_ON) {
1454 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1455 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1456
1457 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1458 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1459 }
1460
1461 /*
1462 * Only toggle the interrupts bits we are going to use.
1463 * Non-checked interrupt bits are disabled by default.
1464 */
1465 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1466 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1467 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1468 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1469 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1470 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1471
1472 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1473 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1474 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1475 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1476 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1477 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1478 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1479 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1480 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1481 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1482}
1483
1484static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1485{
1486 u32 reg;
1487
1488 /*
1489 * Initialize all registers.
1490 */
1491 if (rt61pci_init_rings(rt2x00dev) ||
1492 rt61pci_init_registers(rt2x00dev) ||
1493 rt61pci_init_bbp(rt2x00dev)) {
1494 ERROR(rt2x00dev, "Register initialization failed.\n");
1495 return -EIO;
1496 }
1497
1498 /*
1499 * Enable interrupts.
1500 */
1501 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1502
1503 /*
1504 * Enable RX.
1505 */
1506 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1507 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1508 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1509
1510 /*
1511 * Enable LED
1512 */
1513 rt61pci_enable_led(rt2x00dev);
1514
1515 return 0;
1516}
1517
1518static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1519{
1520 u32 reg;
1521
1522 /*
1523 * Disable LED
1524 */
1525 rt61pci_disable_led(rt2x00dev);
1526
1527 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1528
1529 /*
1530 * Disable synchronisation.
1531 */
1532 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1533
1534 /*
1535 * Cancel RX and TX.
1536 */
1537 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1538 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1539 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1540 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1541 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1542 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1543 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1544
1545 /*
1546 * Disable interrupts.
1547 */
1548 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1549}
1550
1551static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1552{
1553 u32 reg;
1554 unsigned int i;
1555 char put_to_sleep;
1556 char current_state;
1557
1558 put_to_sleep = (state != STATE_AWAKE);
1559
1560 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1561 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1562 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1563 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1564
1565 /*
1566 * Device is not guaranteed to be in the requested state yet.
1567 * We must wait until the register indicates that the
1568 * device has entered the correct state.
1569 */
1570 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1571 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1572 current_state =
1573 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1574 if (current_state == !put_to_sleep)
1575 return 0;
1576 msleep(10);
1577 }
1578
1579 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1580 "current device state %d.\n", !put_to_sleep, current_state);
1581
1582 return -EBUSY;
1583}
1584
1585static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1586 enum dev_state state)
1587{
1588 int retval = 0;
1589
1590 switch (state) {
1591 case STATE_RADIO_ON:
1592 retval = rt61pci_enable_radio(rt2x00dev);
1593 break;
1594 case STATE_RADIO_OFF:
1595 rt61pci_disable_radio(rt2x00dev);
1596 break;
1597 case STATE_RADIO_RX_ON:
1598 case STATE_RADIO_RX_OFF:
1599 rt61pci_toggle_rx(rt2x00dev, state);
1600 break;
1601 case STATE_DEEP_SLEEP:
1602 case STATE_SLEEP:
1603 case STATE_STANDBY:
1604 case STATE_AWAKE:
1605 retval = rt61pci_set_state(rt2x00dev, state);
1606 break;
1607 default:
1608 retval = -ENOTSUPP;
1609 break;
1610 }
1611
1612 return retval;
1613}
1614
1615/*
1616 * TX descriptor initialization
1617 */
1618static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1619 struct data_desc *txd,
4150c572 1620 struct txdata_entry_desc *desc,
95ea3627
ID		 1621 struct ieee80211_hdr *ieee80211hdr,
1622 unsigned int length,
1623 struct ieee80211_tx_control *control)
1624{
1625 u32 word;
1626
1627 /*
1628 * Start writing the descriptor words.
1629 */
1630 rt2x00_desc_read(txd, 1, &word);
1631 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1632 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1633 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1634 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1635 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1636 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1637 rt2x00_desc_write(txd, 1, word);
1638
1639 rt2x00_desc_read(txd, 2, &word);
1640 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1641 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1642 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1643 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1644 rt2x00_desc_write(txd, 2, word);
1645
1646 rt2x00_desc_read(txd, 5, &word);
1647 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1648 TXPOWER_TO_DEV(control->power_level));
1649 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1650 rt2x00_desc_write(txd, 5, word);
1651
1652 rt2x00_desc_read(txd, 11, &word);
1653 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
1654 rt2x00_desc_write(txd, 11, word);
1655
1656 rt2x00_desc_read(txd, 0, &word);
1657 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1658 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1659 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1660 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1661 rt2x00_set_field32(&word, TXD_W0_ACK,
1662 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1663 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1664 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1665 rt2x00_set_field32(&word, TXD_W0_OFDM,
1666 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1667 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1668 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1669 !!(control->flags &
1670 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1671 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1672 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1673 rt2x00_set_field32(&word, TXD_W0_BURST,
1674 test_bit(ENTRY_TXD_BURST, &desc->flags));
1675 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1676 rt2x00_desc_write(txd, 0, word);
1677}
1678
1679/*
1680 * TX data initialization
1681 */
1682static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1683 unsigned int queue)
1684{
1685 u32 reg;
1686
1687 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1688 /*
1689 * For Wi-Fi faily generated beacons between participating
1690 * stations. Set TBTT phase adaptive adjustment step to 8us.
1691 */
1692 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1693
1694 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1695 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1696 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1697 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1698 }
1699 return;
1700 }
1701
1702 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1703 if (queue == IEEE80211_TX_QUEUE_DATA0)
1704 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1705 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1706 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1707 else if (queue == IEEE80211_TX_QUEUE_DATA2)
1708 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1709 else if (queue == IEEE80211_TX_QUEUE_DATA3)
1710 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1711 else if (queue == IEEE80211_TX_QUEUE_DATA4)
1712 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_MGMT, 1);
1713 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1714}
1715
1716/*
1717 * RX control handlers
1718 */
1719static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1720{
1721 u16 eeprom;
1722 u8 offset;
1723 u8 lna;
1724
1725 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1726 switch (lna) {
1727 case 3:
1728 offset = 90;
1729 break;
1730 case 2:
1731 offset = 74;
1732 break;
1733 case 1:
1734 offset = 64;
1735 break;
1736 default:
1737 return 0;
1738 }
1739
1740 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1741 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1742 offset += 14;
1743
1744 if (lna == 3 || lna == 2)
1745 offset += 10;
1746
1747 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1748 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1749 } else {
1750 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1751 offset += 14;
1752
1753 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1754 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1755 }
1756
1757 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1758}
1759
4150c572
JB		 1760static void rt61pci_fill_rxdone(struct data_entry *entry,
1761 struct rxdata_entry_desc *desc)
95ea3627
ID		 1762{
1763 struct data_desc *rxd = entry->priv;
1764 u32 word0;
1765 u32 word1;
1766
1767 rt2x00_desc_read(rxd, 0, &word0);
1768 rt2x00_desc_read(rxd, 1, &word1);
1769
4150c572
JB		 1770 desc->flags = 0;
1771 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1772 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1773
1774 /*
1775 * Obtain the status about this packet.
1776 */
4150c572
JB		 1777 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1778 desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
1779 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1780 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
95ea3627 1781
4150c572 1782 return;
95ea3627
ID		 1783}
1784
1785/*
1786 * Interrupt functions.
1787 */
1788static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1789{
1790 struct data_ring *ring;
1791 struct data_entry *entry;
1792 struct data_desc *txd;
1793 u32 word;
1794 u32 reg;
1795 u32 old_reg;
1796 int type;
1797 int index;
1798 int tx_status;
1799 int retry;
1800
1801 /*
1802 * During each loop we will compare the freshly read
1803 * STA_CSR4 register value with the value read from
1804 * the previous loop. If the 2 values are equal then
1805 * we should stop processing because the chance it
1806 * quite big that the device has been unplugged and
1807 * we risk going into an endless loop.
1808 */
1809 old_reg = 0;
1810
1811 while (1) {
1812 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1813 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1814 break;
1815
1816 if (old_reg == reg)
1817 break;
1818 old_reg = reg;
1819
1820 /*
1821 * Skip this entry when it contains an invalid
1822 * ring identication number.
1823 */
1824 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1825 ring = rt2x00lib_get_ring(rt2x00dev, type);
1826 if (unlikely(!ring))
1827 continue;
1828
1829 /*
1830 * Skip this entry when it contains an invalid
1831 * index number.
1832 */
1833 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1834 if (unlikely(index >= ring->stats.limit))
1835 continue;
1836
1837 entry = &ring->entry[index];
1838 txd = entry->priv;
1839 rt2x00_desc_read(txd, 0, &word);
1840
1841 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1842 !rt2x00_get_field32(word, TXD_W0_VALID))
1843 return;
1844
1845 /*
1846 * Obtain the status about this packet.
1847 */
1848 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1849 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1850
1851 rt2x00lib_txdone(entry, tx_status, retry);
1852
1853 /*
1854 * Make this entry available for reuse.
1855 */
1856 entry->flags = 0;
1857 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1858 rt2x00_desc_write(txd, 0, word);
1859 rt2x00_ring_index_done_inc(entry->ring);
1860
1861 /*
1862 * If the data ring was full before the txdone handler
1863 * we must make sure the packet queue in the mac80211 stack
1864 * is reenabled when the txdone handler has finished.
1865 */
1866 if (!rt2x00_ring_full(ring))
1867 ieee80211_wake_queue(rt2x00dev->hw,
1868 entry->tx_status.control.queue);
1869 }
1870}
1871
1872static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1873{
1874 struct rt2x00_dev *rt2x00dev = dev_instance;
1875 u32 reg_mcu;
1876 u32 reg;
1877
1878 /*
1879 * Get the interrupt sources & saved to local variable.
1880 * Write register value back to clear pending interrupts.
1881 */
1882 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1883 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1884
1885 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1886 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1887
1888 if (!reg && !reg_mcu)
1889 return IRQ_NONE;
1890
1891 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1892 return IRQ_HANDLED;
1893
1894 /*
1895 * Handle interrupts, walk through all bits
1896 * and run the tasks, the bits are checked in order of
1897 * priority.
1898 */
1899
1900 /*
1901 * 1 - Rx ring done interrupt.
1902 */
1903 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1904 rt2x00pci_rxdone(rt2x00dev);
1905
1906 /*
1907 * 2 - Tx ring done interrupt.
1908 */
1909 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1910 rt61pci_txdone(rt2x00dev);
1911
1912 /*
1913 * 3 - Handle MCU command done.
1914 */
1915 if (reg_mcu)
1916 rt2x00pci_register_write(rt2x00dev,
1917 M2H_CMD_DONE_CSR, 0xffffffff);
1918
1919 return IRQ_HANDLED;
1920}
1921
1922/*
1923 * Device probe functions.
1924 */
1925static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1926{
1927 struct eeprom_93cx6 eeprom;
1928 u32 reg;
1929 u16 word;
1930 u8 *mac;
1931 s8 value;
1932
1933 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1934
1935 eeprom.data = rt2x00dev;
1936 eeprom.register_read = rt61pci_eepromregister_read;
1937 eeprom.register_write = rt61pci_eepromregister_write;
1938 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1939 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1940 eeprom.reg_data_in = 0;
1941 eeprom.reg_data_out = 0;
1942 eeprom.reg_data_clock = 0;
1943 eeprom.reg_chip_select = 0;
1944
1945 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1946 EEPROM_SIZE / sizeof(u16));
1947
1948 /*
1949 * Start validation of the data that has been read.
1950 */
1951 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1952 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1953 DECLARE_MAC_BUF(macbuf);
1954
95ea3627 1955 random_ether_addr(mac);
0795af57 1956 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1957 }
1958
1959 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1960 if (word == 0xffff) {
1961 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1962 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2);
1963 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2);
1964 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1965 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1966 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1967 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1968 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1969 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1970 }
1971
1972 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1973 if (word == 0xffff) {
1974 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1975 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1976 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1977 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1978 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1979 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1980 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1981 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1982 }
1983
1984 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1985 if (word == 0xffff) {
1986 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1987 LED_MODE_DEFAULT);
1988 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1989 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1990 }
1991
1992 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1993 if (word == 0xffff) {
1994 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1995 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1996 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1997 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1998 }
1999
2000 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2001 if (word == 0xffff) {
2002 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2003 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2004 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2005 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2006 } else {
2007 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2008 if (value < -10 || value > 10)
2009 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2010 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2011 if (value < -10 || value > 10)
2012 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2013 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2014 }
2015
2016 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2017 if (word == 0xffff) {
2018 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2019 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2020 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2021 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2022 } else {
2023 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2024 if (value < -10 || value > 10)
2025 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2026 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2027 if (value < -10 || value > 10)
2028 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2029 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2030 }
2031
2032 return 0;
2033}
2034
2035static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2036{
2037 u32 reg;
2038 u16 value;
2039 u16 eeprom;
2040 u16 device;
2041
2042 /*
2043 * Read EEPROM word for configuration.
2044 */
2045 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2046
2047 /*
2048 * Identify RF chipset.
2049 * To determine the RT chip we have to read the
2050 * PCI header of the device.
2051 */
2052 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
2053 PCI_CONFIG_HEADER_DEVICE, &device);
2054 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2055 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2056 rt2x00_set_chip(rt2x00dev, device, value, reg);
2057
2058 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2059 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2060 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2061 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2062 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2063 return -ENODEV;
2064 }
2065
2066 /*
2067 * Identify default antenna configuration.
2068 */
2069 rt2x00dev->hw->conf.antenna_sel_tx =
2070 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2071 rt2x00dev->hw->conf.antenna_sel_rx =
2072 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2073
2074 /*
2075 * Read the Frame type.
2076 */
2077 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2078 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2079
2080 /*
2081 * Determine number of antenna's.
2082 */
2083 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2084 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2085
2086 /*
2087 * Detect if this device has an hardware controlled radio.
2088 */
81873e9c 2089#ifdef CONFIG_RT61PCI_RFKILL
95ea3627 2090 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 2091 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 2092#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627
ID		 2093
2094 /*
2095 * Read frequency offset and RF programming sequence.
2096 */
2097 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2098 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2099 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2100
2101 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2102
2103 /*
2104 * Read external LNA informations.
2105 */
2106 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2107
2108 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2109 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2110 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2111 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2112
2113 /*
2114 * Store led settings, for correct led behaviour.
2115 * If the eeprom value is invalid,
2116 * switch to default led mode.
2117 */
2118 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2119
2120 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2121
2122 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2123 rt2x00dev->led_mode);
2124 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2125 rt2x00_get_field16(eeprom,
2126 EEPROM_LED_POLARITY_GPIO_0));
2127 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2128 rt2x00_get_field16(eeprom,
2129 EEPROM_LED_POLARITY_GPIO_1));
2130 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2131 rt2x00_get_field16(eeprom,
2132 EEPROM_LED_POLARITY_GPIO_2));
2133 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2134 rt2x00_get_field16(eeprom,
2135 EEPROM_LED_POLARITY_GPIO_3));
2136 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2137 rt2x00_get_field16(eeprom,
2138 EEPROM_LED_POLARITY_GPIO_4));
2139 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2140 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2141 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2142 rt2x00_get_field16(eeprom,
2143 EEPROM_LED_POLARITY_RDY_G));
2144 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2145 rt2x00_get_field16(eeprom,
2146 EEPROM_LED_POLARITY_RDY_A));
2147
2148 return 0;
2149}
2150
2151/*
2152 * RF value list for RF5225 & RF5325
2153 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2154 */
2155static const struct rf_channel rf_vals_noseq[] = {
2156 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2157 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2158 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2159 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2160 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2161 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2162 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2163 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2164 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2165 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2166 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2167 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2168 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2169 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2170
2171 /* 802.11 UNI / HyperLan 2 */
2172 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2173 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2174 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2175 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2176 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2177 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2178 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2179 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2180
2181 /* 802.11 HyperLan 2 */
2182 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2183 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2184 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2185 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2186 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2187 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2188 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2189 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2190 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2191 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2192
2193 /* 802.11 UNII */
2194 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2195 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2196 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2197 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2198 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2199 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2200
2201 /* MMAC(Japan)J52 ch 34,38,42,46 */
2202 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2203 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2204 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2205 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2206};
2207
2208/*
2209 * RF value list for RF5225 & RF5325
2210 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2211 */
2212static const struct rf_channel rf_vals_seq[] = {
2213 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2214 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2215 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2216 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2217 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2218 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2219 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2220 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2221 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2222 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2223 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2224 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2225 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2226 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2227
2228 /* 802.11 UNI / HyperLan 2 */
2229 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2230 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2231 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2232 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2233 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2234 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2235 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2236 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2237
2238 /* 802.11 HyperLan 2 */
2239 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2240 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2241 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2242 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2243 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2244 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2245 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2246 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2247 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2248 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2249
2250 /* 802.11 UNII */
2251 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2252 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2253 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2254 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2255 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2256 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2257
2258 /* MMAC(Japan)J52 ch 34,38,42,46 */
2259 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2260 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2261 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2262 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2263};
2264
2265static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2266{
2267 struct hw_mode_spec *spec = &rt2x00dev->spec;
2268 u8 *txpower;
2269 unsigned int i;
2270
2271 /*
2272 * Initialize all hw fields.
2273 */
2274 rt2x00dev->hw->flags =
2275 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 2276 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 2277 rt2x00dev->hw->extra_tx_headroom = 0;
2278 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2279 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2280 rt2x00dev->hw->queues = 5;
2281
2282 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2283 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2284 rt2x00_eeprom_addr(rt2x00dev,
2285 EEPROM_MAC_ADDR_0));
2286
2287 /*
2288 * Convert tx_power array in eeprom.
2289 */
2290 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2291 for (i = 0; i < 14; i++)
2292 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2293
2294 /*
2295 * Initialize hw_mode information.
2296 */
2297 spec->num_modes = 2;
2298 spec->num_rates = 12;
2299 spec->tx_power_a = NULL;
2300 spec->tx_power_bg = txpower;
2301 spec->tx_power_default = DEFAULT_TXPOWER;
2302
2303 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2304 spec->num_channels = 14;
2305 spec->channels = rf_vals_noseq;
2306 } else {
2307 spec->num_channels = 14;
2308 spec->channels = rf_vals_seq;
2309 }
2310
2311 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2312 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2313 spec->num_modes = 3;
2314 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2315
2316 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2317 for (i = 0; i < 14; i++)
2318 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2319
2320 spec->tx_power_a = txpower;
2321 }
2322}
2323
2324static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2325{
2326 int retval;
2327
2328 /*
2329 * Allocate eeprom data.
2330 */
2331 retval = rt61pci_validate_eeprom(rt2x00dev);
2332 if (retval)
2333 return retval;
2334
2335 retval = rt61pci_init_eeprom(rt2x00dev);
2336 if (retval)
2337 return retval;
2338
2339 /*
2340 * Initialize hw specifications.
2341 */
2342 rt61pci_probe_hw_mode(rt2x00dev);
2343
2344 /*
2345 * This device requires firmware
2346 */
066cb637 2347 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
95ea3627
ID		 2348
2349 /*
2350 * Set the rssi offset.
2351 */
2352 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2353
2354 return 0;
2355}
2356
2357/*
2358 * IEEE80211 stack callback functions.
2359 */
4150c572
JB		 2360static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2361 unsigned int changed_flags,
2362 unsigned int *total_flags,
2363 int mc_count,
2364 struct dev_addr_list *mc_list)
2365{
2366 struct rt2x00_dev *rt2x00dev = hw->priv;
2367 struct interface *intf = &rt2x00dev->interface;
2368 u32 reg;
2369
2370 /*
2371 * Mask off any flags we are going to ignore from
2372 * the total_flags field.
2373 */
2374 *total_flags &=
2375 FIF_ALLMULTI |
2376 FIF_FCSFAIL |
2377 FIF_PLCPFAIL |
2378 FIF_CONTROL |
2379 FIF_OTHER_BSS |
2380 FIF_PROMISC_IN_BSS;
2381
2382 /*
2383 * Apply some rules to the filters:
2384 * - Some filters imply different filters to be set.
2385 * - Some things we can't filter out at all.
2386 * - Some filters are set based on interface type.
2387 */
2388 if (mc_count)
2389 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 2390 if (*total_flags & FIF_OTHER_BSS ||
2391 *total_flags & FIF_PROMISC_IN_BSS)
4150c572
JB		 2392 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2393 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
2394 *total_flags |= FIF_PROMISC_IN_BSS;
2395
2396 /*
2397 * Check if there is any work left for us.
2398 */
2399 if (intf->filter == *total_flags)
2400 return;
2401 intf->filter = *total_flags;
2402
2403 /*
2404 * Start configuration steps.
2405 * Note that the version error will always be dropped
2406 * and broadcast frames will always be accepted since
2407 * there is no filter for it at this time.
2408 */
2409 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2410 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2411 !(*total_flags & FIF_FCSFAIL));
2412 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2413 !(*total_flags & FIF_PLCPFAIL));
2414 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2415 !(*total_flags & FIF_CONTROL));
2416 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2417 !(*total_flags & FIF_PROMISC_IN_BSS));
2418 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2419 !(*total_flags & FIF_PROMISC_IN_BSS));
2420 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2421 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2422 !(*total_flags & FIF_ALLMULTI));
2423 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
2424 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
2425 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2426}
2427
95ea3627
ID		 2428static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2429 u32 short_retry, u32 long_retry)
2430{
2431 struct rt2x00_dev *rt2x00dev = hw->priv;
2432 u32 reg;
2433
2434 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2435 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2436 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2437 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2438
2439 return 0;
2440}
2441
2442static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2443{
2444 struct rt2x00_dev *rt2x00dev = hw->priv;
2445 u64 tsf;
2446 u32 reg;
2447
2448 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2449 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2450 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2451 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2452
2453 return tsf;
2454}
2455
2456static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2457{
2458 struct rt2x00_dev *rt2x00dev = hw->priv;
2459
2460 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2461 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2462}
2463
24845910 2464static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
95ea3627
ID		 2465 struct ieee80211_tx_control *control)
2466{
2467 struct rt2x00_dev *rt2x00dev = hw->priv;
2468
2469 /*
2470 * Just in case the ieee80211 doesn't set this,
2471 * but we need this queue set for the descriptor
2472 * initialization.
2473 */
2474 control->queue = IEEE80211_TX_QUEUE_BEACON;
2475
2476 /*
2477 * We need to append the descriptor in front of the
2478 * beacon frame.
2479 */
2480 if (skb_headroom(skb) < TXD_DESC_SIZE) {
2481 if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
2482 dev_kfree_skb(skb);
2483 return -ENOMEM;
2484 }
2485 }
2486
2487 /*
2488 * First we create the beacon.
2489 */
2490 skb_push(skb, TXD_DESC_SIZE);
2491 rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
2492 (struct ieee80211_hdr *)(skb->data +
2493 TXD_DESC_SIZE),
2494 skb->len - TXD_DESC_SIZE, control);
2495
2496 /*
2497 * Write entire beacon with descriptor to register,
2498 * and kick the beacon generator.
2499 */
9ee8f57e
ID		 2500 rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0,
2501 skb->data, skb->len);
95ea3627
ID		 2502 rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2503
2504 return 0;
2505}
2506
2507static const struct ieee80211_ops rt61pci_mac80211_ops = {
2508 .tx = rt2x00mac_tx,
4150c572
JB		 2509 .start = rt2x00mac_start,
2510 .stop = rt2x00mac_stop,
95ea3627
ID		 2511 .add_interface = rt2x00mac_add_interface,
2512 .remove_interface = rt2x00mac_remove_interface,
2513 .config = rt2x00mac_config,
2514 .config_interface = rt2x00mac_config_interface,
4150c572 2515 .configure_filter = rt61pci_configure_filter,
95ea3627
ID		 2516 .get_stats = rt2x00mac_get_stats,
2517 .set_retry_limit = rt61pci_set_retry_limit,
2518 .conf_tx = rt2x00mac_conf_tx,
2519 .get_tx_stats = rt2x00mac_get_tx_stats,
2520 .get_tsf = rt61pci_get_tsf,
2521 .reset_tsf = rt61pci_reset_tsf,
2522 .beacon_update = rt61pci_beacon_update,
2523};
2524
2525static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2526 .irq_handler = rt61pci_interrupt,
2527 .probe_hw = rt61pci_probe_hw,
2528 .get_firmware_name = rt61pci_get_firmware_name,
2529 .load_firmware = rt61pci_load_firmware,
2530 .initialize = rt2x00pci_initialize,
2531 .uninitialize = rt2x00pci_uninitialize,
2532 .set_device_state = rt61pci_set_device_state,
95ea3627 2533 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2534 .link_stats = rt61pci_link_stats,
2535 .reset_tuner = rt61pci_reset_tuner,
2536 .link_tuner = rt61pci_link_tuner,
2537 .write_tx_desc = rt61pci_write_tx_desc,
2538 .write_tx_data = rt2x00pci_write_tx_data,
2539 .kick_tx_queue = rt61pci_kick_tx_queue,
2540 .fill_rxdone = rt61pci_fill_rxdone,
2541 .config_mac_addr = rt61pci_config_mac_addr,
2542 .config_bssid = rt61pci_config_bssid,
95ea3627
ID		 2543 .config_type = rt61pci_config_type,
2544 .config = rt61pci_config,
2545};
2546
2547static const struct rt2x00_ops rt61pci_ops = {
2548 .name = DRV_NAME,
2549 .rxd_size = RXD_DESC_SIZE,
2550 .txd_size = TXD_DESC_SIZE,
2551 .eeprom_size = EEPROM_SIZE,
2552 .rf_size = RF_SIZE,
2553 .lib = &rt61pci_rt2x00_ops,
2554 .hw = &rt61pci_mac80211_ops,
2555#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2556 .debugfs = &rt61pci_rt2x00debug,
2557#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2558};
2559
2560/*
2561 * RT61pci module information.
2562 */
2563static struct pci_device_id rt61pci_device_table[] = {
2564 /* RT2561s */
2565 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2566 /* RT2561 v2 */
2567 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2568 /* RT2661 */
2569 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2570 { 0, }
2571};
2572
2573MODULE_AUTHOR(DRV_PROJECT);
2574MODULE_VERSION(DRV_VERSION);
2575MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2576MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2577 "PCI & PCMCIA chipset based cards");
2578MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2579MODULE_FIRMWARE(FIRMWARE_RT2561);
2580MODULE_FIRMWARE(FIRMWARE_RT2561s);
2581MODULE_FIRMWARE(FIRMWARE_RT2661);
2582MODULE_LICENSE("GPL");
2583
2584static struct pci_driver rt61pci_driver = {
2585 .name = DRV_NAME,
2586 .id_table = rt61pci_device_table,
2587 .probe = rt2x00pci_probe,
2588 .remove = __devexit_p(rt2x00pci_remove),
2589 .suspend = rt2x00pci_suspend,
2590 .resume = rt2x00pci_resume,
2591};
2592
2593static int __init rt61pci_init(void)
2594{
2595 return pci_register_driver(&rt61pci_driver);
2596}
2597
2598static void __exit rt61pci_exit(void)
2599{
2600 pci_unregister_driver(&rt61pci_driver);
2601}
2602
2603module_init(rt61pci_init);
2604module_exit(rt61pci_exit);
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