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rt2x00: Upgrade queue->lock to use irqsave
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt61pci.h"
38
39/*
40 * Register access.
41 * BBP and RF register require indirect register access,
42 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
43 * These indirect registers work with busy bits,
44 * and we will try maximal REGISTER_BUSY_COUNT times to access
45 * the register while taking a REGISTER_BUSY_DELAY us delay
46 * between each attampt. When the busy bit is still set at that time,
47 * the access attempt is considered to have failed,
48 * and we will print an error.
49 */
0e14f6d3 50static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 51{
52 u32 reg;
53 unsigned int i;
54
55 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
56 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
57 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
58 break;
59 udelay(REGISTER_BUSY_DELAY);
60 }
61
62 return reg;
63}
64
0e14f6d3 65static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 66 const unsigned int word, const u8 value)
67{
68 u32 reg;
69
70 /*
71 * Wait until the BBP becomes ready.
72 */
73 reg = rt61pci_bbp_check(rt2x00dev);
74 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
75 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
76 return;
77 }
78
79 /*
80 * Write the data into the BBP.
81 */
82 reg = 0;
83 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
84 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
85 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
86 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
87
88 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
89}
90
0e14f6d3 91static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 92 const unsigned int word, u8 *value)
93{
94 u32 reg;
95
96 /*
97 * Wait until the BBP becomes ready.
98 */
99 reg = rt61pci_bbp_check(rt2x00dev);
100 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
101 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
102 return;
103 }
104
105 /*
106 * Write the request into the BBP.
107 */
108 reg = 0;
109 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
110 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
111 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
112
113 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
114
115 /*
116 * Wait until the BBP becomes ready.
117 */
118 reg = rt61pci_bbp_check(rt2x00dev);
119 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
120 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
121 *value = 0xff;
122 return;
123 }
124
125 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
126}
127
0e14f6d3 128static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 129 const unsigned int word, const u32 value)
130{
131 u32 reg;
132 unsigned int i;
133
134 if (!word)
135 return;
136
137 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
138 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
139 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
140 goto rf_write;
141 udelay(REGISTER_BUSY_DELAY);
142 }
143
144 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
145 return;
146
147rf_write:
148 reg = 0;
149 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
150 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
151 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
152 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
153
154 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
155 rt2x00_rf_write(rt2x00dev, word, value);
156}
157
a9450b70
ID		 158#ifdef CONFIG_RT61PCI_LEDS
159/*
160 * This function is only called from rt61pci_led_brightness()
161 * make gcc happy by placing this function inside the
162 * same ifdef statement as the caller.
163 */
0e14f6d3 164static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 165 const u8 command, const u8 token,
166 const u8 arg0, const u8 arg1)
167{
168 u32 reg;
169
170 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
171
172 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
173 ERROR(rt2x00dev, "mcu request error. "
174 "Request 0x%02x failed for token 0x%02x.\n",
175 command, token);
176 return;
177 }
178
179 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
181 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
182 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
183 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
184
185 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
186 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
187 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
188 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
189}
a9450b70 190#endif /* CONFIG_RT61PCI_LEDS */
95ea3627
ID		 191
192static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
193{
194 struct rt2x00_dev *rt2x00dev = eeprom->data;
195 u32 reg;
196
197 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
198
199 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
200 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
201 eeprom->reg_data_clock =
202 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
203 eeprom->reg_chip_select =
204 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
205}
206
207static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
208{
209 struct rt2x00_dev *rt2x00dev = eeprom->data;
210 u32 reg = 0;
211
212 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
213 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
214 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
215 !!eeprom->reg_data_clock);
216 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
217 !!eeprom->reg_chip_select);
218
219 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
220}
221
222#ifdef CONFIG_RT2X00_LIB_DEBUGFS
223#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
224
0e14f6d3 225static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 226 const unsigned int word, u32 *data)
227{
228 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
229}
230
0e14f6d3 231static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 232 const unsigned int word, u32 data)
233{
234 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
235}
236
237static const struct rt2x00debug rt61pci_rt2x00debug = {
238 .owner = THIS_MODULE,
239 .csr = {
240 .read = rt61pci_read_csr,
241 .write = rt61pci_write_csr,
242 .word_size = sizeof(u32),
243 .word_count = CSR_REG_SIZE / sizeof(u32),
244 },
245 .eeprom = {
246 .read = rt2x00_eeprom_read,
247 .write = rt2x00_eeprom_write,
248 .word_size = sizeof(u16),
249 .word_count = EEPROM_SIZE / sizeof(u16),
250 },
251 .bbp = {
252 .read = rt61pci_bbp_read,
253 .write = rt61pci_bbp_write,
254 .word_size = sizeof(u8),
255 .word_count = BBP_SIZE / sizeof(u8),
256 },
257 .rf = {
258 .read = rt2x00_rf_read,
259 .write = rt61pci_rf_write,
260 .word_size = sizeof(u32),
261 .word_count = RF_SIZE / sizeof(u32),
262 },
263};
264#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
265
266#ifdef CONFIG_RT61PCI_RFKILL
267static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
268{
269 u32 reg;
270
271 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 272 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 273}
81873e9c
ID		 274#else
275#define rt61pci_rfkill_poll NULL
dcf5475b 276#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627 277
a9450b70
ID		 278#ifdef CONFIG_RT61PCI_LEDS
279static void rt61pci_led_brightness(struct led_classdev *led_cdev,
280 enum led_brightness brightness)
281{
282 struct rt2x00_led *led =
283 container_of(led_cdev, struct rt2x00_led, led_dev);
284 unsigned int enabled = brightness != LED_OFF;
285 unsigned int a_mode =
286 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
287 unsigned int bg_mode =
288 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
289
290 if (led->type == LED_TYPE_RADIO) {
291 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
292 MCU_LEDCS_RADIO_STATUS, enabled);
293
294 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
295 (led->rt2x00dev->led_mcu_reg & 0xff),
296 ((led->rt2x00dev->led_mcu_reg >> 8)));
297 } else if (led->type == LED_TYPE_ASSOC) {
298 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
299 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
300 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
301 MCU_LEDCS_LINK_A_STATUS, a_mode);
302
303 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
304 (led->rt2x00dev->led_mcu_reg & 0xff),
305 ((led->rt2x00dev->led_mcu_reg >> 8)));
306 } else if (led->type == LED_TYPE_QUALITY) {
307 /*
308 * The brightness is divided into 6 levels (0 - 5),
309 * this means we need to convert the brightness
310 * argument into the matching level within that range.
311 */
312 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
313 brightness / (LED_FULL / 6), 0);
314 }
315}
316#else
317#define rt61pci_led_brightness NULL
318#endif /* CONFIG_RT61PCI_LEDS */
319
95ea3627
ID		 320/*
321 * Configuration handlers.
322 */
6bb40dd1
ID		 323static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
324 struct rt2x00_intf *intf,
325 struct rt2x00intf_conf *conf,
326 const unsigned int flags)
95ea3627 327{
6bb40dd1
ID		 328 unsigned int beacon_base;
329 u32 reg;
95ea3627 330
6bb40dd1
ID		 331 if (flags & CONFIG_UPDATE_TYPE) {
332 /*
333 * Clear current synchronisation setup.
334 * For the Beacon base registers we only need to clear
335 * the first byte since that byte contains the VALID and OWNER
336 * bits which (when set to 0) will invalidate the entire beacon.
337 */
338 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 339 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
95ea3627 340
6bb40dd1
ID		 341 /*
342 * Enable synchronisation.
343 */
344 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
6bb40dd1
ID		 345 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
346 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
347 }
95ea3627 348
6bb40dd1
ID		 349 if (flags & CONFIG_UPDATE_MAC) {
350 reg = le32_to_cpu(conf->mac[1]);
351 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
352 conf->mac[1] = cpu_to_le32(reg);
95ea3627 353
6bb40dd1
ID		 354 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
355 conf->mac, sizeof(conf->mac));
356 }
95ea3627 357
6bb40dd1
ID		 358 if (flags & CONFIG_UPDATE_BSSID) {
359 reg = le32_to_cpu(conf->bssid[1]);
360 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
361 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 362
6bb40dd1
ID		 363 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
364 conf->bssid, sizeof(conf->bssid));
365 }
95ea3627
ID		 366}
367
6bb40dd1
ID		 368static int rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
369 const int short_preamble,
370 const int ack_timeout,
371 const int ack_consume_time)
95ea3627 372{
95ea3627 373 u32 reg;
95ea3627
ID		 374
375 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
5c58ee51 376 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
95ea3627
ID		 377 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
378
379 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 380 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
5c58ee51 381 !!short_preamble);
95ea3627 382 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
6bb40dd1
ID		 383
384 return 0;
95ea3627
ID		 385}
386
387static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 388 const int basic_rate_mask)
95ea3627 389{
5c58ee51 390 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 391}
392
5c58ee51
ID		 393static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
394 struct rf_channel *rf, const int txpower)
95ea3627
ID		 395{
396 u8 r3;
397 u8 r94;
398 u8 smart;
399
400 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
401 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
402
403 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
404 rt2x00_rf(&rt2x00dev->chip, RF2527));
405
406 rt61pci_bbp_read(rt2x00dev, 3, &r3);
407 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
408 rt61pci_bbp_write(rt2x00dev, 3, r3);
409
410 r94 = 6;
411 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
412 r94 += txpower - MAX_TXPOWER;
413 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
414 r94 += txpower;
415 rt61pci_bbp_write(rt2x00dev, 94, r94);
416
417 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
418 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
419 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
420 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
421
422 udelay(200);
423
424 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
425 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
426 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
427 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
428
429 udelay(200);
430
431 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
432 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
433 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
434 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
435
436 msleep(1);
437}
438
95ea3627
ID		 439static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
440 const int txpower)
441{
442 struct rf_channel rf;
443
444 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
445 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
446 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
447 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
448
5c58ee51 449 rt61pci_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 450}
451
452static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 453 struct antenna_setup *ant)
95ea3627
ID		 454{
455 u8 r3;
456 u8 r4;
457 u8 r77;
458
459 rt61pci_bbp_read(rt2x00dev, 3, &r3);
460 rt61pci_bbp_read(rt2x00dev, 4, &r4);
461 rt61pci_bbp_read(rt2x00dev, 77, &r77);
462
463 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 464 rt2x00_rf(&rt2x00dev->chip, RF5325));
e4cd2ff8
ID		 465
466 /*
467 * Configure the RX antenna.
468 */
addc81bd 469 switch (ant->rx) {
95ea3627 470 case ANTENNA_HW_DIVERSITY:
acaa410d 471 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 472 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 473 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 474 break;
475 case ANTENNA_A:
acaa410d 476 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 477 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 478 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 479 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
480 else
481 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627 482 break;
39e75857
ID		 483 case ANTENNA_SW_DIVERSITY:
484 /*
485 * NOTE: We should never come here because rt2x00lib is
486 * supposed to catch this and send us the correct antenna
487 * explicitely. However we are nog going to bug about this.
488 * Instead, just default to antenna B.
489 */
95ea3627 490 case ANTENNA_B:
acaa410d 491 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 492 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 493 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 494 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
495 else
496 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 497 break;
498 }
499
500 rt61pci_bbp_write(rt2x00dev, 77, r77);
501 rt61pci_bbp_write(rt2x00dev, 3, r3);
502 rt61pci_bbp_write(rt2x00dev, 4, r4);
503}
504
505static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 506 struct antenna_setup *ant)
95ea3627
ID		 507{
508 u8 r3;
509 u8 r4;
510 u8 r77;
511
512 rt61pci_bbp_read(rt2x00dev, 3, &r3);
513 rt61pci_bbp_read(rt2x00dev, 4, &r4);
514 rt61pci_bbp_read(rt2x00dev, 77, &r77);
515
516 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 517 rt2x00_rf(&rt2x00dev->chip, RF2529));
95ea3627
ID		 518 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
519 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
520
e4cd2ff8
ID		 521 /*
522 * Configure the RX antenna.
523 */
addc81bd 524 switch (ant->rx) {
95ea3627 525 case ANTENNA_HW_DIVERSITY:
acaa410d 526 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 527 break;
528 case ANTENNA_A:
acaa410d
MN		 529 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
530 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627 531 break;
39e75857
ID		 532 case ANTENNA_SW_DIVERSITY:
533 /*
534 * NOTE: We should never come here because rt2x00lib is
535 * supposed to catch this and send us the correct antenna
536 * explicitely. However we are nog going to bug about this.
537 * Instead, just default to antenna B.
538 */
95ea3627 539 case ANTENNA_B:
acaa410d
MN		 540 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
541 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 542 break;
543 }
544
545 rt61pci_bbp_write(rt2x00dev, 77, r77);
546 rt61pci_bbp_write(rt2x00dev, 3, r3);
547 rt61pci_bbp_write(rt2x00dev, 4, r4);
548}
549
550static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
551 const int p1, const int p2)
552{
553 u32 reg;
554
555 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
556
acaa410d
MN		 557 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
558 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
559
560 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
561 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
562
563 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 564}
565
566static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 567 struct antenna_setup *ant)
95ea3627 568{
95ea3627
ID		 569 u8 r3;
570 u8 r4;
571 u8 r77;
572
573 rt61pci_bbp_read(rt2x00dev, 3, &r3);
574 rt61pci_bbp_read(rt2x00dev, 4, &r4);
575 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 576
acaa410d
MN		 577 /* FIXME: Antenna selection for the rf 2529 is very confusing in the
578 * legacy driver. The code below should be ok for non-diversity setups.
e4cd2ff8 579 */
95ea3627 580
e4cd2ff8
ID		 581 /*
582 * Configure the RX antenna.
583 */
584 switch (ant->rx) {
585 case ANTENNA_A:
acaa410d
MN		 586 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
587 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
588 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8
ID		 589 break;
590 case ANTENNA_SW_DIVERSITY:
591 case ANTENNA_HW_DIVERSITY:
592 /*
593 * NOTE: We should never come here because rt2x00lib is
594 * supposed to catch this and send us the correct antenna
595 * explicitely. However we are nog going to bug about this.
596 * Instead, just default to antenna B.
597 */
598 case ANTENNA_B:
acaa410d
MN		 599 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
600 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
601 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 602 break;
603 }
604
e4cd2ff8 605 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 606 rt61pci_bbp_write(rt2x00dev, 3, r3);
607 rt61pci_bbp_write(rt2x00dev, 4, r4);
608}
609
610struct antenna_sel {
611 u8 word;
612 /*
613 * value[0] -> non-LNA
614 * value[1] -> LNA
615 */
616 u8 value[2];
617};
618
619static const struct antenna_sel antenna_sel_a[] = {
620 { 96, { 0x58, 0x78 } },
621 { 104, { 0x38, 0x48 } },
622 { 75, { 0xfe, 0x80 } },
623 { 86, { 0xfe, 0x80 } },
624 { 88, { 0xfe, 0x80 } },
625 { 35, { 0x60, 0x60 } },
626 { 97, { 0x58, 0x58 } },
627 { 98, { 0x58, 0x58 } },
628};
629
630static const struct antenna_sel antenna_sel_bg[] = {
631 { 96, { 0x48, 0x68 } },
632 { 104, { 0x2c, 0x3c } },
633 { 75, { 0xfe, 0x80 } },
634 { 86, { 0xfe, 0x80 } },
635 { 88, { 0xfe, 0x80 } },
636 { 35, { 0x50, 0x50 } },
637 { 97, { 0x48, 0x48 } },
638 { 98, { 0x48, 0x48 } },
639};
640
641static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 642 struct antenna_setup *ant)
95ea3627
ID		 643{
644 const struct antenna_sel *sel;
645 unsigned int lna;
646 unsigned int i;
647 u32 reg;
648
8318d78a 649 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 650 sel = antenna_sel_a;
651 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 652 } else {
653 sel = antenna_sel_bg;
654 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 655 }
656
acaa410d
MN		 657 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
658 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
659
660 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
661
ddc827f9 662 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 663 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 664 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 665 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 666
95ea3627
ID		 667 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
668
669 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
670 rt2x00_rf(&rt2x00dev->chip, RF5325))
addc81bd 671 rt61pci_config_antenna_5x(rt2x00dev, ant);
95ea3627 672 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 673 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 674 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
675 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 676 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 677 else
addc81bd 678 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 679 }
680}
681
682static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 683 struct rt2x00lib_conf *libconf)
95ea3627
ID		 684{
685 u32 reg;
686
687 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 688 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 689 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
690
691 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 692 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 693 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 694 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 695 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
696
697 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
698 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
699 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
700
701 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
702 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
703 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
704
705 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 706 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
707 libconf->conf->beacon_int * 16);
95ea3627
ID		 708 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
709}
710
711static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 712 struct rt2x00lib_conf *libconf,
713 const unsigned int flags)
95ea3627 714{
95ea3627 715 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 716 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 717 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 718 rt61pci_config_channel(rt2x00dev, &libconf->rf,
719 libconf->conf->power_level);
95ea3627 720 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 721 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 722 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 723 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 724 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 725 rt61pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 726}
727
95ea3627
ID		 728/*
729 * Link tuning
730 */
ebcf26da
ID		 731static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
732 struct link_qual *qual)
95ea3627
ID		 733{
734 u32 reg;
735
736 /*
737 * Update FCS error count from register.
738 */
739 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 740 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 741
742 /*
743 * Update False CCA count from register.
744 */
745 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 746 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 747}
748
749static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
750{
751 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
752 rt2x00dev->link.vgc_level = 0x20;
753}
754
755static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
756{
757 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
758 u8 r17;
759 u8 up_bound;
760 u8 low_bound;
761
95ea3627
ID		 762 rt61pci_bbp_read(rt2x00dev, 17, &r17);
763
764 /*
765 * Determine r17 bounds.
766 */
1497074a 767 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 768 low_bound = 0x28;
769 up_bound = 0x48;
770 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
771 low_bound += 0x10;
772 up_bound += 0x10;
773 }
774 } else {
775 low_bound = 0x20;
776 up_bound = 0x40;
777 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
778 low_bound += 0x10;
779 up_bound += 0x10;
780 }
781 }
782
6bb40dd1
ID		 783 /*
784 * If we are not associated, we should go straight to the
785 * dynamic CCA tuning.
786 */
787 if (!rt2x00dev->intf_associated)
788 goto dynamic_cca_tune;
789
95ea3627
ID		 790 /*
791 * Special big-R17 for very short distance
792 */
793 if (rssi >= -35) {
794 if (r17 != 0x60)
795 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
796 return;
797 }
798
799 /*
800 * Special big-R17 for short distance
801 */
802 if (rssi >= -58) {
803 if (r17 != up_bound)
804 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
805 return;
806 }
807
808 /*
809 * Special big-R17 for middle-short distance
810 */
811 if (rssi >= -66) {
812 low_bound += 0x10;
813 if (r17 != low_bound)
814 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
815 return;
816 }
817
818 /*
819 * Special mid-R17 for middle distance
820 */
821 if (rssi >= -74) {
822 low_bound += 0x08;
823 if (r17 != low_bound)
824 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
825 return;
826 }
827
828 /*
829 * Special case: Change up_bound based on the rssi.
830 * Lower up_bound when rssi is weaker then -74 dBm.
831 */
832 up_bound -= 2 * (-74 - rssi);
833 if (low_bound > up_bound)
834 up_bound = low_bound;
835
836 if (r17 > up_bound) {
837 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
838 return;
839 }
840
6bb40dd1
ID		 841dynamic_cca_tune:
842
95ea3627
ID		 843 /*
844 * r17 does not yet exceed upper limit, continue and base
845 * the r17 tuning on the false CCA count.
846 */
ebcf26da 847 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 848 if (++r17 > up_bound)
849 r17 = up_bound;
850 rt61pci_bbp_write(rt2x00dev, 17, r17);
ebcf26da 851 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 852 if (--r17 < low_bound)
853 r17 = low_bound;
854 rt61pci_bbp_write(rt2x00dev, 17, r17);
855 }
856}
857
858/*
859 * Firmware name function.
860 */
861static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
862{
863 char *fw_name;
864
865 switch (rt2x00dev->chip.rt) {
866 case RT2561:
867 fw_name = FIRMWARE_RT2561;
868 break;
869 case RT2561s:
870 fw_name = FIRMWARE_RT2561s;
871 break;
872 case RT2661:
873 fw_name = FIRMWARE_RT2661;
874 break;
875 default:
876 fw_name = NULL;
877 break;
878 }
879
880 return fw_name;
881}
882
883/*
884 * Initialization functions.
885 */
886static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
887 const size_t len)
888{
889 int i;
890 u32 reg;
891
892 /*
893 * Wait for stable hardware.
894 */
895 for (i = 0; i < 100; i++) {
896 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
897 if (reg)
898 break;
899 msleep(1);
900 }
901
902 if (!reg) {
903 ERROR(rt2x00dev, "Unstable hardware.\n");
904 return -EBUSY;
905 }
906
907 /*
908 * Prepare MCU and mailbox for firmware loading.
909 */
910 reg = 0;
911 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
912 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
913 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
914 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
915 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
916
917 /*
918 * Write firmware to device.
919 */
920 reg = 0;
921 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
922 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
923 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
924
925 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
926 data, len);
927
928 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
929 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
930
931 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
932 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
933
934 for (i = 0; i < 100; i++) {
935 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
936 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
937 break;
938 msleep(1);
939 }
940
941 if (i == 100) {
942 ERROR(rt2x00dev, "MCU Control register not ready.\n");
943 return -EBUSY;
944 }
945
946 /*
947 * Reset MAC and BBP registers.
948 */
949 reg = 0;
950 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
951 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
952 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
953
954 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
955 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
956 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
957 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
958
959 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
960 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
961 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
962
963 return 0;
964}
965
837e7f24 966static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 967 struct queue_entry *entry)
95ea3627 968{
181d6902 969 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 970 u32 word;
971
181d6902 972 rt2x00_desc_read(priv_rx->desc, 5, &word);
30b3a23c
ID		 973 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
974 priv_rx->data_dma);
181d6902 975 rt2x00_desc_write(priv_rx->desc, 5, word);
95ea3627 976
181d6902 977 rt2x00_desc_read(priv_rx->desc, 0, &word);
837e7f24 978 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
181d6902 979 rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627
ID		 980}
981
837e7f24 982static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 983 struct queue_entry *entry)
95ea3627 984{
181d6902 985 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
95ea3627
ID		 986 u32 word;
987
181d6902 988 rt2x00_desc_read(priv_tx->desc, 1, &word);
837e7f24 989 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
181d6902 990 rt2x00_desc_write(priv_tx->desc, 1, word);
95ea3627 991
181d6902
ID		 992 rt2x00_desc_read(priv_tx->desc, 5, &word);
993 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
837e7f24 994 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
181d6902 995 rt2x00_desc_write(priv_tx->desc, 5, word);
95ea3627 996
181d6902 997 rt2x00_desc_read(priv_tx->desc, 6, &word);
30b3a23c
ID		 998 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
999 priv_tx->data_dma);
181d6902 1000 rt2x00_desc_write(priv_tx->desc, 6, word);
95ea3627 1001
181d6902 1002 rt2x00_desc_read(priv_tx->desc, 0, &word);
837e7f24
ID		 1003 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1004 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
181d6902 1005 rt2x00_desc_write(priv_tx->desc, 0, word);
95ea3627
ID		 1006}
1007
181d6902 1008static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1009{
181d6902
ID		 1010 struct queue_entry_priv_pci_rx *priv_rx;
1011 struct queue_entry_priv_pci_tx *priv_tx;
95ea3627
ID		 1012 u32 reg;
1013
95ea3627
ID		 1014 /*
1015 * Initialize registers.
1016 */
1017 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1018 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1019 rt2x00dev->tx[0].limit);
95ea3627 1020 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1021 rt2x00dev->tx[1].limit);
95ea3627 1022 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1023 rt2x00dev->tx[2].limit);
95ea3627 1024 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1025 rt2x00dev->tx[3].limit);
95ea3627
ID		 1026 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1027
1028 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1029 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1030 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1031 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1032
181d6902 1033 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1034 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
30b3a23c
ID		 1035 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1036 priv_tx->desc_dma);
95ea3627
ID		 1037 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1038
181d6902 1039 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1040 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
30b3a23c
ID		 1041 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1042 priv_tx->desc_dma);
95ea3627
ID		 1043 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1044
181d6902 1045 priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1046 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
30b3a23c
ID		 1047 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1048 priv_tx->desc_dma);
95ea3627
ID		 1049 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1050
181d6902 1051 priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1052 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
30b3a23c
ID		 1053 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1054 priv_tx->desc_dma);
95ea3627
ID		 1055 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1056
95ea3627 1057 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1058 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1059 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1060 rt2x00dev->rx->desc_size / 4);
1061 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1062 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1063
181d6902 1064 priv_rx = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1065 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
30b3a23c
ID		 1066 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1067 priv_rx->desc_dma);
95ea3627
ID		 1068 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1069
1070 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1071 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1072 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1073 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1074 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
95ea3627
ID		 1075 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1076
1077 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1078 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1079 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1080 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1081 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
95ea3627
ID		 1082 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1083
1084 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1085 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1086 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1087
1088 return 0;
1089}
1090
1091static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1092{
1093 u32 reg;
1094
1095 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1096 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1097 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1098 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1099 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1100
1101 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1102 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1103 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1104 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1105 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1106 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1107 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1108 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1109 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1110 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1111
1112 /*
1113 * CCK TXD BBP registers
1114 */
1115 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1116 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1117 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1118 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1119 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1120 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1121 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1122 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1123 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1124 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1125
1126 /*
1127 * OFDM TXD BBP registers
1128 */
1129 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1130 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1131 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1132 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1133 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1134 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1135 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1136 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1137
1138 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1139 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1140 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1141 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1142 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1143 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1144
1145 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1146 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1147 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1148 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1149 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1150 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1151
1152 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1153
1154 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1155
1156 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1157 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1158 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1159
1160 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1161
1162 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1163 return -EBUSY;
1164
1165 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1166
a9450b70
ID		 1167 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
1168 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
1169 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
1170 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
1171
95ea3627
ID		 1172 /*
1173 * Invalidate all Shared Keys (SEC_CSR0),
1174 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1175 */
1176 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1177 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1178 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1179
1180 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1181 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1182 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1183 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1184
1185 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1186
1187 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1188
1189 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1190
1191 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1192 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1193 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1194 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1195
1196 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1197 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1198 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1199 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1200
6bb40dd1
ID		 1201 /*
1202 * Clear all beacons
1203 * For the Beacon base registers we only need to clear
1204 * the first byte since that byte contains the VALID and OWNER
1205 * bits which (when set to 0) will invalidate the entire beacon.
1206 */
1207 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1208 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1209 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1210 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1211
95ea3627
ID		 1212 /*
1213 * We must clear the error counters.
1214 * These registers are cleared on read,
1215 * so we may pass a useless variable to store the value.
1216 */
1217 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1218 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1219 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1220
1221 /*
1222 * Reset MAC and BBP registers.
1223 */
1224 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1225 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1226 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1227 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1228
1229 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1230 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1231 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1232 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1233
1234 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1235 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1236 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1237
1238 return 0;
1239}
1240
1241static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1242{
1243 unsigned int i;
1244 u16 eeprom;
1245 u8 reg_id;
1246 u8 value;
1247
1248 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1249 rt61pci_bbp_read(rt2x00dev, 0, &value);
1250 if ((value != 0xff) && (value != 0x00))
1251 goto continue_csr_init;
1252 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1253 udelay(REGISTER_BUSY_DELAY);
1254 }
1255
1256 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1257 return -EACCES;
1258
1259continue_csr_init:
1260 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1261 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1262 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1263 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1264 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1265 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1266 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1267 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1268 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1269 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1270 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1271 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1272 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1273 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1274 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1275 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1276 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1277 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1278 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1279 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1280 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1281 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1282 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1283 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1284
95ea3627
ID		 1285 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1286 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1287
1288 if (eeprom != 0xffff && eeprom != 0x0000) {
1289 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1290 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1291 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1292 }
1293 }
95ea3627
ID		 1294
1295 return 0;
1296}
1297
1298/*
1299 * Device state switch handlers.
1300 */
1301static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1302 enum dev_state state)
1303{
1304 u32 reg;
1305
1306 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1307 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1308 state == STATE_RADIO_RX_OFF);
1309 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1310}
1311
1312static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1313 enum dev_state state)
1314{
1315 int mask = (state == STATE_RADIO_IRQ_OFF);
1316 u32 reg;
1317
1318 /*
1319 * When interrupts are being enabled, the interrupt registers
1320 * should clear the register to assure a clean state.
1321 */
1322 if (state == STATE_RADIO_IRQ_ON) {
1323 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1324 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1325
1326 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1327 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1328 }
1329
1330 /*
1331 * Only toggle the interrupts bits we are going to use.
1332 * Non-checked interrupt bits are disabled by default.
1333 */
1334 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1335 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1336 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1337 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1338 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1339 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1340
1341 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1342 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1343 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1344 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1345 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1346 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1347 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1348 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1349 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1350 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1351}
1352
1353static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1354{
1355 u32 reg;
1356
1357 /*
1358 * Initialize all registers.
1359 */
181d6902 1360 if (rt61pci_init_queues(rt2x00dev) ||
95ea3627
ID		 1361 rt61pci_init_registers(rt2x00dev) ||
1362 rt61pci_init_bbp(rt2x00dev)) {
1363 ERROR(rt2x00dev, "Register initialization failed.\n");
1364 return -EIO;
1365 }
1366
1367 /*
1368 * Enable interrupts.
1369 */
1370 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1371
1372 /*
1373 * Enable RX.
1374 */
1375 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1376 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1377 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1378
95ea3627
ID		 1379 return 0;
1380}
1381
1382static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1383{
1384 u32 reg;
1385
95ea3627
ID		 1386 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1387
1388 /*
1389 * Disable synchronisation.
1390 */
1391 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1392
1393 /*
1394 * Cancel RX and TX.
1395 */
1396 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1397 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1398 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1399 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1400 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
95ea3627
ID		 1401 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1402
1403 /*
1404 * Disable interrupts.
1405 */
1406 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1407}
1408
1409static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1410{
1411 u32 reg;
1412 unsigned int i;
1413 char put_to_sleep;
1414 char current_state;
1415
1416 put_to_sleep = (state != STATE_AWAKE);
1417
1418 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1419 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1420 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1421 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1422
1423 /*
1424 * Device is not guaranteed to be in the requested state yet.
1425 * We must wait until the register indicates that the
1426 * device has entered the correct state.
1427 */
1428 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1429 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1430 current_state =
1431 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1432 if (current_state == !put_to_sleep)
1433 return 0;
1434 msleep(10);
1435 }
1436
1437 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1438 "current device state %d.\n", !put_to_sleep, current_state);
1439
1440 return -EBUSY;
1441}
1442
1443static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1444 enum dev_state state)
1445{
1446 int retval = 0;
1447
1448 switch (state) {
1449 case STATE_RADIO_ON:
1450 retval = rt61pci_enable_radio(rt2x00dev);
1451 break;
1452 case STATE_RADIO_OFF:
1453 rt61pci_disable_radio(rt2x00dev);
1454 break;
1455 case STATE_RADIO_RX_ON:
61667d8d
ID		 1456 case STATE_RADIO_RX_ON_LINK:
1457 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1458 break;
95ea3627 1459 case STATE_RADIO_RX_OFF:
61667d8d
ID		 1460 case STATE_RADIO_RX_OFF_LINK:
1461 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 1462 break;
1463 case STATE_DEEP_SLEEP:
1464 case STATE_SLEEP:
1465 case STATE_STANDBY:
1466 case STATE_AWAKE:
1467 retval = rt61pci_set_state(rt2x00dev, state);
1468 break;
1469 default:
1470 retval = -ENOTSUPP;
1471 break;
1472 }
1473
1474 return retval;
1475}
1476
1477/*
1478 * TX descriptor initialization
1479 */
1480static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1481 struct sk_buff *skb,
181d6902 1482 struct txentry_desc *txdesc,
dd3193e1 1483 struct ieee80211_tx_control *control)
95ea3627 1484{
181d6902 1485 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1486 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1487 u32 word;
1488
1489 /*
1490 * Start writing the descriptor words.
1491 */
1492 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1493 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1494 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1495 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1496 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1497 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1498 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1499 rt2x00_desc_write(txd, 1, word);
1500
1501 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1502 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1503 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1504 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1505 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1506 rt2x00_desc_write(txd, 2, word);
1507
1508 rt2x00_desc_read(txd, 5, &word);
1509 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1510 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1511 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1512 rt2x00_desc_write(txd, 5, word);
1513
d7bafff3
AB		 1514 if (skbdesc->desc_len > TXINFO_SIZE) {
1515 rt2x00_desc_read(txd, 11, &word);
1516 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1517 rt2x00_desc_write(txd, 11, word);
1518 }
95ea3627
ID		 1519
1520 rt2x00_desc_read(txd, 0, &word);
1521 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1522 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1523 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1524 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1525 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1526 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1527 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1528 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1529 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1530 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1531 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1532 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1533 !!(control->flags &
1534 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1535 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
dd3193e1 1536 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627 1537 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1538 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1539 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1540 rt2x00_desc_write(txd, 0, word);
1541}
1542
1543/*
1544 * TX data initialization
1545 */
1546static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1547 const unsigned int queue)
95ea3627
ID		 1548{
1549 u32 reg;
1550
5957da4c 1551 if (queue == RT2X00_BCN_QUEUE_BEACON) {
95ea3627
ID		 1552 /*
1553 * For Wi-Fi faily generated beacons between participating
1554 * stations. Set TBTT phase adaptive adjustment step to 8us.
1555 */
1556 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1557
1558 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1559 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1560 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1561 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1562 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1563 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1564 }
1565 return;
1566 }
1567
1568 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
ddc827f9
ID		 1569 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0,
1570 (queue == IEEE80211_TX_QUEUE_DATA0));
1571 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1,
1572 (queue == IEEE80211_TX_QUEUE_DATA1));
1573 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
1574 (queue == IEEE80211_TX_QUEUE_DATA2));
1575 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1576 (queue == IEEE80211_TX_QUEUE_DATA3));
95ea3627
ID		 1577 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1578}
1579
1580/*
1581 * RX control handlers
1582 */
1583static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1584{
1585 u16 eeprom;
1586 u8 offset;
1587 u8 lna;
1588
1589 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1590 switch (lna) {
1591 case 3:
1592 offset = 90;
1593 break;
1594 case 2:
1595 offset = 74;
1596 break;
1597 case 1:
1598 offset = 64;
1599 break;
1600 default:
1601 return 0;
1602 }
1603
8318d78a 1604 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1605 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1606 offset += 14;
1607
1608 if (lna == 3 || lna == 2)
1609 offset += 10;
1610
1611 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1612 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1613 } else {
1614 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1615 offset += 14;
1616
1617 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1618 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1619 }
1620
1621 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1622}
1623
181d6902
ID		 1624static void rt61pci_fill_rxdone(struct queue_entry *entry,
1625 struct rxdone_entry_desc *rxdesc)
95ea3627 1626{
181d6902 1627 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 1628 u32 word0;
1629 u32 word1;
1630
181d6902
ID		 1631 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1632 rt2x00_desc_read(priv_rx->desc, 1, &word1);
95ea3627 1633
181d6902 1634 rxdesc->flags = 0;
4150c572 1635 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1636 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1637
1638 /*
1639 * Obtain the status about this packet.
1640 */
181d6902
ID		 1641 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1642 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1643 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1644 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1645 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
95ea3627
ID		 1646}
1647
1648/*
1649 * Interrupt functions.
1650 */
1651static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1652{
181d6902
ID		 1653 struct data_queue *queue;
1654 struct queue_entry *entry;
1655 struct queue_entry *entry_done;
1656 struct queue_entry_priv_pci_tx *priv_tx;
1657 struct txdone_entry_desc txdesc;
95ea3627
ID		 1658 u32 word;
1659 u32 reg;
1660 u32 old_reg;
1661 int type;
1662 int index;
95ea3627
ID		 1663
1664 /*
1665 * During each loop we will compare the freshly read
1666 * STA_CSR4 register value with the value read from
1667 * the previous loop. If the 2 values are equal then
1668 * we should stop processing because the chance it
1669 * quite big that the device has been unplugged and
1670 * we risk going into an endless loop.
1671 */
1672 old_reg = 0;
1673
1674 while (1) {
1675 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1676 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1677 break;
1678
1679 if (old_reg == reg)
1680 break;
1681 old_reg = reg;
1682
1683 /*
1684 * Skip this entry when it contains an invalid
181d6902 1685 * queue identication number.
95ea3627
ID		 1686 */
1687 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 1688 queue = rt2x00queue_get_queue(rt2x00dev, type);
1689 if (unlikely(!queue))
95ea3627
ID		 1690 continue;
1691
1692 /*
1693 * Skip this entry when it contains an invalid
1694 * index number.
1695 */
1696 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 1697 if (unlikely(index >= queue->limit))
95ea3627
ID		 1698 continue;
1699
181d6902
ID		 1700 entry = &queue->entries[index];
1701 priv_tx = entry->priv_data;
1702 rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627
ID		 1703
1704 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1705 !rt2x00_get_field32(word, TXD_W0_VALID))
1706 return;
1707
181d6902 1708 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 1709 while (entry != entry_done) {
181d6902
ID		 1710 /* Catch up.
1711 * Just report any entries we missed as failed.
1712 */
62bc060b 1713 WARNING(rt2x00dev,
181d6902
ID		 1714 "TX status report missed for entry %d\n",
1715 entry_done->entry_idx);
1716
1717 txdesc.status = TX_FAIL_OTHER;
1718 txdesc.retry = 0;
1719
1720 rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1721 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 1722 }
1723
95ea3627
ID		 1724 /*
1725 * Obtain the status about this packet.
1726 */
181d6902
ID		 1727 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1728 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 1729
181d6902 1730 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627
ID		 1731 }
1732}
1733
1734static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1735{
1736 struct rt2x00_dev *rt2x00dev = dev_instance;
1737 u32 reg_mcu;
1738 u32 reg;
1739
1740 /*
1741 * Get the interrupt sources & saved to local variable.
1742 * Write register value back to clear pending interrupts.
1743 */
1744 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1745 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1746
1747 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1748 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1749
1750 if (!reg && !reg_mcu)
1751 return IRQ_NONE;
1752
1753 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1754 return IRQ_HANDLED;
1755
1756 /*
1757 * Handle interrupts, walk through all bits
1758 * and run the tasks, the bits are checked in order of
1759 * priority.
1760 */
1761
1762 /*
1763 * 1 - Rx ring done interrupt.
1764 */
1765 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1766 rt2x00pci_rxdone(rt2x00dev);
1767
1768 /*
1769 * 2 - Tx ring done interrupt.
1770 */
1771 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1772 rt61pci_txdone(rt2x00dev);
1773
1774 /*
1775 * 3 - Handle MCU command done.
1776 */
1777 if (reg_mcu)
1778 rt2x00pci_register_write(rt2x00dev,
1779 M2H_CMD_DONE_CSR, 0xffffffff);
1780
1781 return IRQ_HANDLED;
1782}
1783
1784/*
1785 * Device probe functions.
1786 */
1787static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1788{
1789 struct eeprom_93cx6 eeprom;
1790 u32 reg;
1791 u16 word;
1792 u8 *mac;
1793 s8 value;
1794
1795 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1796
1797 eeprom.data = rt2x00dev;
1798 eeprom.register_read = rt61pci_eepromregister_read;
1799 eeprom.register_write = rt61pci_eepromregister_write;
1800 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1801 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1802 eeprom.reg_data_in = 0;
1803 eeprom.reg_data_out = 0;
1804 eeprom.reg_data_clock = 0;
1805 eeprom.reg_chip_select = 0;
1806
1807 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1808 EEPROM_SIZE / sizeof(u16));
1809
1810 /*
1811 * Start validation of the data that has been read.
1812 */
1813 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1814 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1815 DECLARE_MAC_BUF(macbuf);
1816
95ea3627 1817 random_ether_addr(mac);
0795af57 1818 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1819 }
1820
1821 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1822 if (word == 0xffff) {
1823 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1824 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1825 ANTENNA_B);
1826 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1827 ANTENNA_B);
95ea3627
ID		 1828 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1829 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1830 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1831 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1832 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1833 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1834 }
1835
1836 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1837 if (word == 0xffff) {
1838 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1839 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1840 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1841 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1842 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1843 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1844 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1845 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1846 }
1847
1848 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1849 if (word == 0xffff) {
1850 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1851 LED_MODE_DEFAULT);
1852 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1853 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1854 }
1855
1856 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1857 if (word == 0xffff) {
1858 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1859 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1860 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1861 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1862 }
1863
1864 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1865 if (word == 0xffff) {
1866 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1867 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1868 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1869 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1870 } else {
1871 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1872 if (value < -10 || value > 10)
1873 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1874 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1875 if (value < -10 || value > 10)
1876 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1877 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1878 }
1879
1880 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1881 if (word == 0xffff) {
1882 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1883 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1884 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1885 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1886 } else {
1887 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1888 if (value < -10 || value > 10)
1889 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1890 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1891 if (value < -10 || value > 10)
1892 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1893 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1894 }
1895
1896 return 0;
1897}
1898
1899static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1900{
1901 u32 reg;
1902 u16 value;
1903 u16 eeprom;
1904 u16 device;
1905
1906 /*
1907 * Read EEPROM word for configuration.
1908 */
1909 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1910
1911 /*
1912 * Identify RF chipset.
1913 * To determine the RT chip we have to read the
1914 * PCI header of the device.
1915 */
1916 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1917 PCI_CONFIG_HEADER_DEVICE, &device);
1918 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1919 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1920 rt2x00_set_chip(rt2x00dev, device, value, reg);
1921
1922 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1923 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1924 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1925 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1926 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1927 return -ENODEV;
1928 }
1929
e4cd2ff8
ID		 1930 /*
1931 * Determine number of antenna's.
1932 */
1933 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1934 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1935
95ea3627
ID		 1936 /*
1937 * Identify default antenna configuration.
1938 */
addc81bd 1939 rt2x00dev->default_ant.tx =
95ea3627 1940 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1941 rt2x00dev->default_ant.rx =
95ea3627
ID		 1942 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1943
1944 /*
1945 * Read the Frame type.
1946 */
1947 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1948 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1949
95ea3627
ID		 1950 /*
1951 * Detect if this device has an hardware controlled radio.
1952 */
81873e9c 1953#ifdef CONFIG_RT61PCI_RFKILL
95ea3627 1954 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1955 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1956#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627
ID		 1957
1958 /*
1959 * Read frequency offset and RF programming sequence.
1960 */
1961 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1962 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
1963 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
1964
1965 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1966
1967 /*
1968 * Read external LNA informations.
1969 */
1970 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1971
1972 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1973 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1974 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1975 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1976
e4cd2ff8
ID		 1977 /*
1978 * When working with a RF2529 chip without double antenna
1979 * the antenna settings should be gathered from the NIC
1980 * eeprom word.
1981 */
1982 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
1983 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
1984 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
1985 case 0:
1986 rt2x00dev->default_ant.tx = ANTENNA_B;
1987 rt2x00dev->default_ant.rx = ANTENNA_A;
1988 break;
1989 case 1:
1990 rt2x00dev->default_ant.tx = ANTENNA_B;
1991 rt2x00dev->default_ant.rx = ANTENNA_B;
1992 break;
1993 case 2:
1994 rt2x00dev->default_ant.tx = ANTENNA_A;
1995 rt2x00dev->default_ant.rx = ANTENNA_A;
1996 break;
1997 case 3:
1998 rt2x00dev->default_ant.tx = ANTENNA_A;
1999 rt2x00dev->default_ant.rx = ANTENNA_B;
2000 break;
2001 }
2002
2003 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2004 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2005 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2006 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2007 }
2008
95ea3627
ID		 2009 /*
2010 * Store led settings, for correct led behaviour.
2011 * If the eeprom value is invalid,
2012 * switch to default led mode.
2013 */
a9450b70 2014#ifdef CONFIG_RT61PCI_LEDS
95ea3627
ID		 2015 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2016
a9450b70
ID		 2017 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2018
2019 switch (value) {
2020 case LED_MODE_TXRX_ACTIVITY:
2021 case LED_MODE_ASUS:
2022 case LED_MODE_ALPHA:
2023 case LED_MODE_DEFAULT:
2024 rt2x00dev->led_flags =
2025 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
2026 break;
2027 case LED_MODE_SIGNAL_STRENGTH:
2028 rt2x00dev->led_flags =
2029 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
2030 LED_SUPPORT_QUALITY;
2031 break;
2032 }
95ea3627 2033
a9450b70
ID		 2034 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2035 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2036 rt2x00_get_field16(eeprom,
2037 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2038 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2039 rt2x00_get_field16(eeprom,
2040 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2041 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2042 rt2x00_get_field16(eeprom,
2043 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2044 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2045 rt2x00_get_field16(eeprom,
2046 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2047 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2048 rt2x00_get_field16(eeprom,
2049 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2050 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2051 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2052 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2053 rt2x00_get_field16(eeprom,
2054 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2055 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2056 rt2x00_get_field16(eeprom,
2057 EEPROM_LED_POLARITY_RDY_A));
a9450b70 2058#endif /* CONFIG_RT61PCI_LEDS */
95ea3627
ID		 2059
2060 return 0;
2061}
2062
2063/*
2064 * RF value list for RF5225 & RF5325
2065 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2066 */
2067static const struct rf_channel rf_vals_noseq[] = {
2068 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2069 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2070 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2071 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2072 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2073 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2074 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2075 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2076 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2077 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2078 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2079 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2080 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2081 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2082
2083 /* 802.11 UNI / HyperLan 2 */
2084 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2085 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2086 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2087 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2088 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2089 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2090 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2091 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2092
2093 /* 802.11 HyperLan 2 */
2094 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2095 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2096 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2097 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2098 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2099 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2100 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2101 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2102 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2103 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2104
2105 /* 802.11 UNII */
2106 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2107 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2108 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2109 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2110 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2111 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2112
2113 /* MMAC(Japan)J52 ch 34,38,42,46 */
2114 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2115 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2116 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2117 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2118};
2119
2120/*
2121 * RF value list for RF5225 & RF5325
2122 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2123 */
2124static const struct rf_channel rf_vals_seq[] = {
2125 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2126 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2127 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2128 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2129 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2130 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2131 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2132 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2133 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2134 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2135 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2136 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2137 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2138 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2139
2140 /* 802.11 UNI / HyperLan 2 */
2141 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2142 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2143 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2144 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2145 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2146 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2147 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2148 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2149
2150 /* 802.11 HyperLan 2 */
2151 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2152 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2153 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2154 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2155 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2156 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2157 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2158 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2159 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2160 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2161
2162 /* 802.11 UNII */
2163 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2164 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2165 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2166 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2167 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2168 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2169
2170 /* MMAC(Japan)J52 ch 34,38,42,46 */
2171 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2172 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2173 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2174 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2175};
2176
2177static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2178{
2179 struct hw_mode_spec *spec = &rt2x00dev->spec;
2180 u8 *txpower;
2181 unsigned int i;
2182
2183 /*
2184 * Initialize all hw fields.
2185 */
2186 rt2x00dev->hw->flags =
2187 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 2188 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 2189 rt2x00dev->hw->extra_tx_headroom = 0;
2190 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2191 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
871ff6ed 2192 rt2x00dev->hw->queues = 4;
95ea3627
ID		 2193
2194 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2195 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2196 rt2x00_eeprom_addr(rt2x00dev,
2197 EEPROM_MAC_ADDR_0));
2198
2199 /*
2200 * Convert tx_power array in eeprom.
2201 */
2202 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2203 for (i = 0; i < 14; i++)
2204 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2205
2206 /*
2207 * Initialize hw_mode information.
2208 */
31562e80
ID		 2209 spec->supported_bands = SUPPORT_BAND_2GHZ;
2210 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2211 spec->tx_power_a = NULL;
2212 spec->tx_power_bg = txpower;
2213 spec->tx_power_default = DEFAULT_TXPOWER;
2214
2215 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2216 spec->num_channels = 14;
2217 spec->channels = rf_vals_noseq;
2218 } else {
2219 spec->num_channels = 14;
2220 spec->channels = rf_vals_seq;
2221 }
2222
2223 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2224 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
31562e80 2225 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2226 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2227
2228 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2229 for (i = 0; i < 14; i++)
2230 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2231
2232 spec->tx_power_a = txpower;
2233 }
2234}
2235
2236static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2237{
2238 int retval;
2239
2240 /*
2241 * Allocate eeprom data.
2242 */
2243 retval = rt61pci_validate_eeprom(rt2x00dev);
2244 if (retval)
2245 return retval;
2246
2247 retval = rt61pci_init_eeprom(rt2x00dev);
2248 if (retval)
2249 return retval;
2250
2251 /*
2252 * Initialize hw specifications.
2253 */
2254 rt61pci_probe_hw_mode(rt2x00dev);
2255
2256 /*
9404ef34 2257 * This device requires firmware.
95ea3627 2258 */
066cb637 2259 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
9404ef34 2260 __set_bit(DRIVER_REQUIRE_FIRMWARE_CRC_ITU_T, &rt2x00dev->flags);
95ea3627
ID		 2261
2262 /*
2263 * Set the rssi offset.
2264 */
2265 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2266
2267 return 0;
2268}
2269
2270/*
2271 * IEEE80211 stack callback functions.
2272 */
4150c572
JB		 2273static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2274 unsigned int changed_flags,
2275 unsigned int *total_flags,
2276 int mc_count,
2277 struct dev_addr_list *mc_list)
2278{
2279 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 2280 u32 reg;
2281
2282 /*
2283 * Mask off any flags we are going to ignore from
2284 * the total_flags field.
2285 */
2286 *total_flags &=
2287 FIF_ALLMULTI |
2288 FIF_FCSFAIL |
2289 FIF_PLCPFAIL |
2290 FIF_CONTROL |
2291 FIF_OTHER_BSS |
2292 FIF_PROMISC_IN_BSS;
2293
2294 /*
2295 * Apply some rules to the filters:
2296 * - Some filters imply different filters to be set.
2297 * - Some things we can't filter out at all.
4150c572
JB		 2298 */
2299 if (mc_count)
2300 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 2301 if (*total_flags & FIF_OTHER_BSS ||
2302 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 2303 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 2304
2305 /*
2306 * Check if there is any work left for us.
2307 */
3c4f2085 2308 if (rt2x00dev->packet_filter == *total_flags)
4150c572 2309 return;
3c4f2085 2310 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 2311
2312 /*
2313 * Start configuration steps.
2314 * Note that the version error will always be dropped
2315 * and broadcast frames will always be accepted since
2316 * there is no filter for it at this time.
2317 */
2318 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2319 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2320 !(*total_flags & FIF_FCSFAIL));
2321 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2322 !(*total_flags & FIF_PLCPFAIL));
2323 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2324 !(*total_flags & FIF_CONTROL));
2325 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2326 !(*total_flags & FIF_PROMISC_IN_BSS));
2327 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2328 !(*total_flags & FIF_PROMISC_IN_BSS));
2329 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2330 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2331 !(*total_flags & FIF_ALLMULTI));
e542239f
ID		 2332 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
2333 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
2334 !(*total_flags & FIF_CONTROL));
4150c572
JB		 2335 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2336}
2337
95ea3627
ID		 2338static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2339 u32 short_retry, u32 long_retry)
2340{
2341 struct rt2x00_dev *rt2x00dev = hw->priv;
2342 u32 reg;
2343
2344 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2345 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2346 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2347 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2348
2349 return 0;
2350}
2351
2352static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2353{
2354 struct rt2x00_dev *rt2x00dev = hw->priv;
2355 u64 tsf;
2356 u32 reg;
2357
2358 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2359 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2360 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2361 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2362
2363 return tsf;
2364}
2365
24845910 2366static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
95ea3627
ID		 2367 struct ieee80211_tx_control *control)
2368{
2369 struct rt2x00_dev *rt2x00dev = hw->priv;
6bb40dd1 2370 struct rt2x00_intf *intf = vif_to_intf(control->vif);
181d6902 2371 struct skb_frame_desc *skbdesc;
6bb40dd1 2372 unsigned int beacon_base;
8af244cc 2373 u32 reg;
95ea3627 2374
6bb40dd1
ID		 2375 if (unlikely(!intf->beacon))
2376 return -ENOBUFS;
95ea3627
ID		 2377
2378 /*
2379 * We need to append the descriptor in front of the
2380 * beacon frame.
2381 */
6bb40dd1
ID		 2382 if (skb_headroom(skb) < intf->beacon->queue->desc_size) {
2383 if (pskb_expand_head(skb, intf->beacon->queue->desc_size,
2384 0, GFP_ATOMIC)) {
95ea3627
ID		 2385 dev_kfree_skb(skb);
2386 return -ENOMEM;
2387 }
2388 }
2389
2390 /*
08992f7f
ID		 2391 * Add the descriptor in front of the skb.
2392 */
6bb40dd1
ID		 2393 skb_push(skb, intf->beacon->queue->desc_size);
2394 memset(skb->data, 0, intf->beacon->queue->desc_size);
08992f7f
ID		 2395
2396 /*
2397 * Fill in skb descriptor
95ea3627 2398 */
181d6902
ID		 2399 skbdesc = get_skb_frame_desc(skb);
2400 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 2401 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
6bb40dd1
ID		 2402 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2403 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
181d6902 2404 skbdesc->desc = skb->data;
6bb40dd1
ID		 2405 skbdesc->desc_len = intf->beacon->queue->desc_size;
2406 skbdesc->entry = intf->beacon;
c22eb87b 2407
8af244cc
ID		 2408 /*
2409 * Disable beaconing while we are reloading the beacon data,
2410 * otherwise we might be sending out invalid data.
2411 */
2412 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2413 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2414 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2415 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2416 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2417
6bb40dd1 2418 /*
5957da4c
ID		 2419 * mac80211 doesn't provide the control->queue variable
2420 * for beacons. Set our own queue identification so
2421 * it can be used during descriptor initialization.
6bb40dd1 2422 */
5957da4c 2423 control->queue = RT2X00_BCN_QUEUE_BEACON;
08992f7f 2424 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
95ea3627
ID		 2425
2426 /*
2427 * Write entire beacon with descriptor to register,
2428 * and kick the beacon generator.
2429 */
6bb40dd1
ID		 2430 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2431 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
9ee8f57e 2432 skb->data, skb->len);
6bb40dd1 2433 rt61pci_kick_tx_queue(rt2x00dev, control->queue);
95ea3627
ID		 2434
2435 return 0;
2436}
2437
2438static const struct ieee80211_ops rt61pci_mac80211_ops = {
2439 .tx = rt2x00mac_tx,
4150c572
JB		 2440 .start = rt2x00mac_start,
2441 .stop = rt2x00mac_stop,
95ea3627
ID		 2442 .add_interface = rt2x00mac_add_interface,
2443 .remove_interface = rt2x00mac_remove_interface,
2444 .config = rt2x00mac_config,
2445 .config_interface = rt2x00mac_config_interface,
4150c572 2446 .configure_filter = rt61pci_configure_filter,
95ea3627
ID		 2447 .get_stats = rt2x00mac_get_stats,
2448 .set_retry_limit = rt61pci_set_retry_limit,
471b3efd 2449 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2450 .conf_tx = rt2x00mac_conf_tx,
2451 .get_tx_stats = rt2x00mac_get_tx_stats,
2452 .get_tsf = rt61pci_get_tsf,
95ea3627
ID		 2453 .beacon_update = rt61pci_beacon_update,
2454};
2455
2456static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2457 .irq_handler = rt61pci_interrupt,
2458 .probe_hw = rt61pci_probe_hw,
2459 .get_firmware_name = rt61pci_get_firmware_name,
2460 .load_firmware = rt61pci_load_firmware,
2461 .initialize = rt2x00pci_initialize,
2462 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 2463 .init_rxentry = rt61pci_init_rxentry,
2464 .init_txentry = rt61pci_init_txentry,
95ea3627 2465 .set_device_state = rt61pci_set_device_state,
95ea3627 2466 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2467 .link_stats = rt61pci_link_stats,
2468 .reset_tuner = rt61pci_reset_tuner,
2469 .link_tuner = rt61pci_link_tuner,
a9450b70 2470 .led_brightness = rt61pci_led_brightness,
95ea3627
ID		 2471 .write_tx_desc = rt61pci_write_tx_desc,
2472 .write_tx_data = rt2x00pci_write_tx_data,
2473 .kick_tx_queue = rt61pci_kick_tx_queue,
2474 .fill_rxdone = rt61pci_fill_rxdone,
6bb40dd1 2475 .config_intf = rt61pci_config_intf,
5c58ee51 2476 .config_preamble = rt61pci_config_preamble,
95ea3627
ID		 2477 .config = rt61pci_config,
2478};
2479
181d6902
ID		 2480static const struct data_queue_desc rt61pci_queue_rx = {
2481 .entry_num = RX_ENTRIES,
2482 .data_size = DATA_FRAME_SIZE,
2483 .desc_size = RXD_DESC_SIZE,
2484 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
2485};
2486
2487static const struct data_queue_desc rt61pci_queue_tx = {
2488 .entry_num = TX_ENTRIES,
2489 .data_size = DATA_FRAME_SIZE,
2490 .desc_size = TXD_DESC_SIZE,
2491 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2492};
2493
2494static const struct data_queue_desc rt61pci_queue_bcn = {
6bb40dd1 2495 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2496 .data_size = MGMT_FRAME_SIZE,
2497 .desc_size = TXINFO_SIZE,
2498 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2499};
2500
95ea3627 2501static const struct rt2x00_ops rt61pci_ops = {
2360157c 2502 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2503 .max_sta_intf = 1,
2504 .max_ap_intf = 4,
95ea3627
ID		 2505 .eeprom_size = EEPROM_SIZE,
2506 .rf_size = RF_SIZE,
181d6902
ID		 2507 .rx = &rt61pci_queue_rx,
2508 .tx = &rt61pci_queue_tx,
2509 .bcn = &rt61pci_queue_bcn,
95ea3627
ID		 2510 .lib = &rt61pci_rt2x00_ops,
2511 .hw = &rt61pci_mac80211_ops,
2512#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2513 .debugfs = &rt61pci_rt2x00debug,
2514#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2515};
2516
2517/*
2518 * RT61pci module information.
2519 */
2520static struct pci_device_id rt61pci_device_table[] = {
2521 /* RT2561s */
2522 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2523 /* RT2561 v2 */
2524 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2525 /* RT2661 */
2526 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2527 { 0, }
2528};
2529
2530MODULE_AUTHOR(DRV_PROJECT);
2531MODULE_VERSION(DRV_VERSION);
2532MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2533MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2534 "PCI & PCMCIA chipset based cards");
2535MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2536MODULE_FIRMWARE(FIRMWARE_RT2561);
2537MODULE_FIRMWARE(FIRMWARE_RT2561s);
2538MODULE_FIRMWARE(FIRMWARE_RT2661);
2539MODULE_LICENSE("GPL");
2540
2541static struct pci_driver rt61pci_driver = {
2360157c 2542 .name = KBUILD_MODNAME,
95ea3627
ID		 2543 .id_table = rt61pci_device_table,
2544 .probe = rt2x00pci_probe,
2545 .remove = __devexit_p(rt2x00pci_remove),
2546 .suspend = rt2x00pci_suspend,
2547 .resume = rt2x00pci_resume,
2548};
2549
2550static int __init rt61pci_init(void)
2551{
2552 return pci_register_driver(&rt61pci_driver);
2553}
2554
2555static void __exit rt61pci_exit(void)
2556{
2557 pci_unregister_driver(&rt61pci_driver);
2558}
2559
2560module_init(rt61pci_init);
2561module_exit(rt61pci_exit);
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