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mac80211: remove IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE flag
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/eeprom_93cx6.h>
35
36#include "rt2x00.h"
37#include "rt2x00pci.h"
38#include "rt61pci.h"
39
40/*
41 * Register access.
42 * BBP and RF register require indirect register access,
43 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attampt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
50 */
0e14f6d3 51static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 52{
53 u32 reg;
54 unsigned int i;
55
56 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
57 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
58 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
59 break;
60 udelay(REGISTER_BUSY_DELAY);
61 }
62
63 return reg;
64}
65
0e14f6d3 66static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 67 const unsigned int word, const u8 value)
68{
69 u32 reg;
70
71 /*
72 * Wait until the BBP becomes ready.
73 */
74 reg = rt61pci_bbp_check(rt2x00dev);
75 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
76 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
77 return;
78 }
79
80 /*
81 * Write the data into the BBP.
82 */
83 reg = 0;
84 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
85 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
86 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
87 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
88
89 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
90}
91
0e14f6d3 92static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 93 const unsigned int word, u8 *value)
94{
95 u32 reg;
96
97 /*
98 * Wait until the BBP becomes ready.
99 */
100 reg = rt61pci_bbp_check(rt2x00dev);
101 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
102 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
103 return;
104 }
105
106 /*
107 * Write the request into the BBP.
108 */
109 reg = 0;
110 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
111 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
112 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
113
114 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
115
116 /*
117 * Wait until the BBP becomes ready.
118 */
119 reg = rt61pci_bbp_check(rt2x00dev);
120 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
121 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
122 *value = 0xff;
123 return;
124 }
125
126 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
127}
128
0e14f6d3 129static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 130 const unsigned int word, const u32 value)
131{
132 u32 reg;
133 unsigned int i;
134
135 if (!word)
136 return;
137
138 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
139 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
140 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
141 goto rf_write;
142 udelay(REGISTER_BUSY_DELAY);
143 }
144
145 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
146 return;
147
148rf_write:
149 reg = 0;
150 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
151 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
152 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
153 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
154
155 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
156 rt2x00_rf_write(rt2x00dev, word, value);
157}
158
a9450b70
ID		 159#ifdef CONFIG_RT61PCI_LEDS
160/*
161 * This function is only called from rt61pci_led_brightness()
162 * make gcc happy by placing this function inside the
163 * same ifdef statement as the caller.
164 */
0e14f6d3 165static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 166 const u8 command, const u8 token,
167 const u8 arg0, const u8 arg1)
168{
169 u32 reg;
170
171 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
172
173 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
174 ERROR(rt2x00dev, "mcu request error. "
175 "Request 0x%02x failed for token 0x%02x.\n",
176 command, token);
177 return;
178 }
179
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
181 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
182 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
183 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
184 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
185
186 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
187 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
188 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
189 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
190}
a9450b70 191#endif /* CONFIG_RT61PCI_LEDS */
95ea3627
ID		 192
193static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
194{
195 struct rt2x00_dev *rt2x00dev = eeprom->data;
196 u32 reg;
197
198 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
199
200 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
201 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
202 eeprom->reg_data_clock =
203 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
204 eeprom->reg_chip_select =
205 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
206}
207
208static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
209{
210 struct rt2x00_dev *rt2x00dev = eeprom->data;
211 u32 reg = 0;
212
213 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
214 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
215 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
216 !!eeprom->reg_data_clock);
217 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
218 !!eeprom->reg_chip_select);
219
220 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
221}
222
223#ifdef CONFIG_RT2X00_LIB_DEBUGFS
224#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
225
0e14f6d3 226static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 227 const unsigned int word, u32 *data)
228{
229 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
230}
231
0e14f6d3 232static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 233 const unsigned int word, u32 data)
234{
235 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
236}
237
238static const struct rt2x00debug rt61pci_rt2x00debug = {
239 .owner = THIS_MODULE,
240 .csr = {
241 .read = rt61pci_read_csr,
242 .write = rt61pci_write_csr,
243 .word_size = sizeof(u32),
244 .word_count = CSR_REG_SIZE / sizeof(u32),
245 },
246 .eeprom = {
247 .read = rt2x00_eeprom_read,
248 .write = rt2x00_eeprom_write,
249 .word_size = sizeof(u16),
250 .word_count = EEPROM_SIZE / sizeof(u16),
251 },
252 .bbp = {
253 .read = rt61pci_bbp_read,
254 .write = rt61pci_bbp_write,
255 .word_size = sizeof(u8),
256 .word_count = BBP_SIZE / sizeof(u8),
257 },
258 .rf = {
259 .read = rt2x00_rf_read,
260 .write = rt61pci_rf_write,
261 .word_size = sizeof(u32),
262 .word_count = RF_SIZE / sizeof(u32),
263 },
264};
265#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
266
267#ifdef CONFIG_RT61PCI_RFKILL
268static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
269{
270 u32 reg;
271
272 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 273 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 274}
81873e9c
ID		 275#else
276#define rt61pci_rfkill_poll NULL
dcf5475b 277#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627 278
a9450b70 279#ifdef CONFIG_RT61PCI_LEDS
a2e1d52a 280static void rt61pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 281 enum led_brightness brightness)
282{
283 struct rt2x00_led *led =
284 container_of(led_cdev, struct rt2x00_led, led_dev);
285 unsigned int enabled = brightness != LED_OFF;
286 unsigned int a_mode =
287 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
288 unsigned int bg_mode =
289 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
290
291 if (led->type == LED_TYPE_RADIO) {
292 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
293 MCU_LEDCS_RADIO_STATUS, enabled);
294
295 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
296 (led->rt2x00dev->led_mcu_reg & 0xff),
297 ((led->rt2x00dev->led_mcu_reg >> 8)));
298 } else if (led->type == LED_TYPE_ASSOC) {
299 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
300 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
301 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
302 MCU_LEDCS_LINK_A_STATUS, a_mode);
303
304 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
305 (led->rt2x00dev->led_mcu_reg & 0xff),
306 ((led->rt2x00dev->led_mcu_reg >> 8)));
307 } else if (led->type == LED_TYPE_QUALITY) {
308 /*
309 * The brightness is divided into 6 levels (0 - 5),
310 * this means we need to convert the brightness
311 * argument into the matching level within that range.
312 */
313 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
314 brightness / (LED_FULL / 6), 0);
315 }
316}
a2e1d52a
ID		 317
318static int rt61pci_blink_set(struct led_classdev *led_cdev,
319 unsigned long *delay_on,
320 unsigned long *delay_off)
321{
322 struct rt2x00_led *led =
323 container_of(led_cdev, struct rt2x00_led, led_dev);
324 u32 reg;
325
326 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
327 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
328 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
329 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
330
331 return 0;
332}
475433be
ID		 333
334static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
335 struct rt2x00_led *led,
336 enum led_type type)
337{
338 led->rt2x00dev = rt2x00dev;
339 led->type = type;
340 led->led_dev.brightness_set = rt61pci_brightness_set;
341 led->led_dev.blink_set = rt61pci_blink_set;
342 led->flags = LED_INITIALIZED;
343}
a9450b70
ID		 344#endif /* CONFIG_RT61PCI_LEDS */
345
95ea3627
ID		 346/*
347 * Configuration handlers.
348 */
3a643d24
ID		 349static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
350 const unsigned int filter_flags)
351{
352 u32 reg;
353
354 /*
355 * Start configuration steps.
356 * Note that the version error will always be dropped
357 * and broadcast frames will always be accepted since
358 * there is no filter for it at this time.
359 */
360 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
361 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
362 !(filter_flags & FIF_FCSFAIL));
363 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
364 !(filter_flags & FIF_PLCPFAIL));
365 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
366 !(filter_flags & FIF_CONTROL));
367 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
368 !(filter_flags & FIF_PROMISC_IN_BSS));
369 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 370 !(filter_flags & FIF_PROMISC_IN_BSS) &&
371 !rt2x00dev->intf_ap_count);
3a643d24
ID		 372 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
373 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
374 !(filter_flags & FIF_ALLMULTI));
375 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
376 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
377 !(filter_flags & FIF_CONTROL));
378 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
379}
380
6bb40dd1
ID		 381static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
382 struct rt2x00_intf *intf,
383 struct rt2x00intf_conf *conf,
384 const unsigned int flags)
95ea3627 385{
6bb40dd1
ID		 386 unsigned int beacon_base;
387 u32 reg;
95ea3627 388
6bb40dd1
ID		 389 if (flags & CONFIG_UPDATE_TYPE) {
390 /*
391 * Clear current synchronisation setup.
392 * For the Beacon base registers we only need to clear
393 * the first byte since that byte contains the VALID and OWNER
394 * bits which (when set to 0) will invalidate the entire beacon.
395 */
396 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 397 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
95ea3627 398
6bb40dd1
ID		 399 /*
400 * Enable synchronisation.
401 */
402 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 403 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 404 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 405 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 406 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
407 }
95ea3627 408
6bb40dd1
ID		 409 if (flags & CONFIG_UPDATE_MAC) {
410 reg = le32_to_cpu(conf->mac[1]);
411 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
412 conf->mac[1] = cpu_to_le32(reg);
95ea3627 413
6bb40dd1
ID		 414 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
415 conf->mac, sizeof(conf->mac));
416 }
95ea3627 417
6bb40dd1
ID		 418 if (flags & CONFIG_UPDATE_BSSID) {
419 reg = le32_to_cpu(conf->bssid[1]);
420 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
421 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 422
6bb40dd1
ID		 423 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
424 conf->bssid, sizeof(conf->bssid));
425 }
95ea3627
ID		 426}
427
3a643d24
ID		 428static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
429 struct rt2x00lib_erp *erp)
95ea3627 430{
95ea3627 431 u32 reg;
95ea3627
ID		 432
433 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 434 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
95ea3627
ID		 435 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
436
437 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 438 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 439 !!erp->short_preamble);
95ea3627
ID		 440 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
441}
442
443static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 444 const int basic_rate_mask)
95ea3627 445{
5c58ee51 446 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 447}
448
5c58ee51
ID		 449static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
450 struct rf_channel *rf, const int txpower)
95ea3627
ID		 451{
452 u8 r3;
453 u8 r94;
454 u8 smart;
455
456 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
457 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
458
459 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
460 rt2x00_rf(&rt2x00dev->chip, RF2527));
461
462 rt61pci_bbp_read(rt2x00dev, 3, &r3);
463 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
464 rt61pci_bbp_write(rt2x00dev, 3, r3);
465
466 r94 = 6;
467 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
468 r94 += txpower - MAX_TXPOWER;
469 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
470 r94 += txpower;
471 rt61pci_bbp_write(rt2x00dev, 94, r94);
472
473 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
474 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
475 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
476 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
477
478 udelay(200);
479
480 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
481 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
482 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
483 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
484
485 udelay(200);
486
487 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
488 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
489 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
490 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
491
492 msleep(1);
493}
494
95ea3627
ID		 495static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
496 const int txpower)
497{
498 struct rf_channel rf;
499
500 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
501 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
502 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
503 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
504
5c58ee51 505 rt61pci_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 506}
507
508static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 509 struct antenna_setup *ant)
95ea3627
ID		 510{
511 u8 r3;
512 u8 r4;
513 u8 r77;
514
515 rt61pci_bbp_read(rt2x00dev, 3, &r3);
516 rt61pci_bbp_read(rt2x00dev, 4, &r4);
517 rt61pci_bbp_read(rt2x00dev, 77, &r77);
518
519 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 520 rt2x00_rf(&rt2x00dev->chip, RF5325));
e4cd2ff8
ID		 521
522 /*
523 * Configure the RX antenna.
524 */
addc81bd 525 switch (ant->rx) {
95ea3627 526 case ANTENNA_HW_DIVERSITY:
acaa410d 527 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 528 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 529 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 530 break;
531 case ANTENNA_A:
acaa410d 532 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 533 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 534 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 535 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
536 else
537 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 538 break;
539 case ANTENNA_B:
a4fe07d9 540 default:
acaa410d 541 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 542 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 543 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 544 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
545 else
546 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 547 break;
548 }
549
550 rt61pci_bbp_write(rt2x00dev, 77, r77);
551 rt61pci_bbp_write(rt2x00dev, 3, r3);
552 rt61pci_bbp_write(rt2x00dev, 4, r4);
553}
554
555static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 556 struct antenna_setup *ant)
95ea3627
ID		 557{
558 u8 r3;
559 u8 r4;
560 u8 r77;
561
562 rt61pci_bbp_read(rt2x00dev, 3, &r3);
563 rt61pci_bbp_read(rt2x00dev, 4, &r4);
564 rt61pci_bbp_read(rt2x00dev, 77, &r77);
565
566 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 567 rt2x00_rf(&rt2x00dev->chip, RF2529));
95ea3627
ID		 568 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
569 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
570
e4cd2ff8
ID		 571 /*
572 * Configure the RX antenna.
573 */
addc81bd 574 switch (ant->rx) {
95ea3627 575 case ANTENNA_HW_DIVERSITY:
acaa410d 576 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 577 break;
578 case ANTENNA_A:
acaa410d
MN		 579 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
580 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 581 break;
582 case ANTENNA_B:
a4fe07d9 583 default:
acaa410d
MN		 584 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
585 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 586 break;
587 }
588
589 rt61pci_bbp_write(rt2x00dev, 77, r77);
590 rt61pci_bbp_write(rt2x00dev, 3, r3);
591 rt61pci_bbp_write(rt2x00dev, 4, r4);
592}
593
594static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
595 const int p1, const int p2)
596{
597 u32 reg;
598
599 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
600
acaa410d
MN		 601 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
602 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
603
604 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
605 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
606
607 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 608}
609
610static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 611 struct antenna_setup *ant)
95ea3627 612{
95ea3627
ID		 613 u8 r3;
614 u8 r4;
615 u8 r77;
616
617 rt61pci_bbp_read(rt2x00dev, 3, &r3);
618 rt61pci_bbp_read(rt2x00dev, 4, &r4);
619 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 620
e4cd2ff8
ID		 621 /*
622 * Configure the RX antenna.
623 */
624 switch (ant->rx) {
625 case ANTENNA_A:
acaa410d
MN		 626 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
627 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
628 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8 629 break;
e4cd2ff8
ID		 630 case ANTENNA_HW_DIVERSITY:
631 /*
a4fe07d9
ID		 632 * FIXME: Antenna selection for the rf 2529 is very confusing
633 * in the legacy driver. Just default to antenna B until the
634 * legacy code can be properly translated into rt2x00 code.
e4cd2ff8
ID		 635 */
636 case ANTENNA_B:
a4fe07d9 637 default:
acaa410d
MN		 638 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
639 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
640 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 641 break;
642 }
643
e4cd2ff8 644 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 645 rt61pci_bbp_write(rt2x00dev, 3, r3);
646 rt61pci_bbp_write(rt2x00dev, 4, r4);
647}
648
649struct antenna_sel {
650 u8 word;
651 /*
652 * value[0] -> non-LNA
653 * value[1] -> LNA
654 */
655 u8 value[2];
656};
657
658static const struct antenna_sel antenna_sel_a[] = {
659 { 96, { 0x58, 0x78 } },
660 { 104, { 0x38, 0x48 } },
661 { 75, { 0xfe, 0x80 } },
662 { 86, { 0xfe, 0x80 } },
663 { 88, { 0xfe, 0x80 } },
664 { 35, { 0x60, 0x60 } },
665 { 97, { 0x58, 0x58 } },
666 { 98, { 0x58, 0x58 } },
667};
668
669static const struct antenna_sel antenna_sel_bg[] = {
670 { 96, { 0x48, 0x68 } },
671 { 104, { 0x2c, 0x3c } },
672 { 75, { 0xfe, 0x80 } },
673 { 86, { 0xfe, 0x80 } },
674 { 88, { 0xfe, 0x80 } },
675 { 35, { 0x50, 0x50 } },
676 { 97, { 0x48, 0x48 } },
677 { 98, { 0x48, 0x48 } },
678};
679
680static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 681 struct antenna_setup *ant)
95ea3627
ID		 682{
683 const struct antenna_sel *sel;
684 unsigned int lna;
685 unsigned int i;
686 u32 reg;
687
a4fe07d9
ID		 688 /*
689 * We should never come here because rt2x00lib is supposed
690 * to catch this and send us the correct antenna explicitely.
691 */
692 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
693 ant->tx == ANTENNA_SW_DIVERSITY);
694
8318d78a 695 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 696 sel = antenna_sel_a;
697 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 698 } else {
699 sel = antenna_sel_bg;
700 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 701 }
702
acaa410d
MN		 703 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
704 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
705
706 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
707
ddc827f9 708 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 709 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 710 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 711 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 712
95ea3627
ID		 713 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
714
715 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
716 rt2x00_rf(&rt2x00dev->chip, RF5325))
addc81bd 717 rt61pci_config_antenna_5x(rt2x00dev, ant);
95ea3627 718 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 719 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 720 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
721 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 722 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 723 else
addc81bd 724 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 725 }
726}
727
728static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 729 struct rt2x00lib_conf *libconf)
95ea3627
ID		 730{
731 u32 reg;
732
733 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 734 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 735 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
736
737 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 738 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 739 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 740 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 741 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
742
743 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
744 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
745 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
746
747 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
748 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
749 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
750
751 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 752 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
753 libconf->conf->beacon_int * 16);
95ea3627
ID		 754 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
755}
756
757static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 758 struct rt2x00lib_conf *libconf,
759 const unsigned int flags)
95ea3627 760{
95ea3627 761 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 762 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 763 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 764 rt61pci_config_channel(rt2x00dev, &libconf->rf,
765 libconf->conf->power_level);
95ea3627 766 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 767 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 768 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 769 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 770 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 771 rt61pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 772}
773
95ea3627
ID		 774/*
775 * Link tuning
776 */
ebcf26da
ID		 777static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
778 struct link_qual *qual)
95ea3627
ID		 779{
780 u32 reg;
781
782 /*
783 * Update FCS error count from register.
784 */
785 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 786 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 787
788 /*
789 * Update False CCA count from register.
790 */
791 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 792 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 793}
794
795static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
796{
797 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
798 rt2x00dev->link.vgc_level = 0x20;
799}
800
801static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
802{
803 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
804 u8 r17;
805 u8 up_bound;
806 u8 low_bound;
807
95ea3627
ID		 808 rt61pci_bbp_read(rt2x00dev, 17, &r17);
809
810 /*
811 * Determine r17 bounds.
812 */
1497074a 813 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 814 low_bound = 0x28;
815 up_bound = 0x48;
816 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
817 low_bound += 0x10;
818 up_bound += 0x10;
819 }
820 } else {
821 low_bound = 0x20;
822 up_bound = 0x40;
823 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
824 low_bound += 0x10;
825 up_bound += 0x10;
826 }
827 }
828
6bb40dd1
ID		 829 /*
830 * If we are not associated, we should go straight to the
831 * dynamic CCA tuning.
832 */
833 if (!rt2x00dev->intf_associated)
834 goto dynamic_cca_tune;
835
95ea3627
ID		 836 /*
837 * Special big-R17 for very short distance
838 */
839 if (rssi >= -35) {
840 if (r17 != 0x60)
841 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
842 return;
843 }
844
845 /*
846 * Special big-R17 for short distance
847 */
848 if (rssi >= -58) {
849 if (r17 != up_bound)
850 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
851 return;
852 }
853
854 /*
855 * Special big-R17 for middle-short distance
856 */
857 if (rssi >= -66) {
858 low_bound += 0x10;
859 if (r17 != low_bound)
860 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
861 return;
862 }
863
864 /*
865 * Special mid-R17 for middle distance
866 */
867 if (rssi >= -74) {
868 low_bound += 0x08;
869 if (r17 != low_bound)
870 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
871 return;
872 }
873
874 /*
875 * Special case: Change up_bound based on the rssi.
876 * Lower up_bound when rssi is weaker then -74 dBm.
877 */
878 up_bound -= 2 * (-74 - rssi);
879 if (low_bound > up_bound)
880 up_bound = low_bound;
881
882 if (r17 > up_bound) {
883 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
884 return;
885 }
886
6bb40dd1
ID		 887dynamic_cca_tune:
888
95ea3627
ID		 889 /*
890 * r17 does not yet exceed upper limit, continue and base
891 * the r17 tuning on the false CCA count.
892 */
ebcf26da 893 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 894 if (++r17 > up_bound)
895 r17 = up_bound;
896 rt61pci_bbp_write(rt2x00dev, 17, r17);
ebcf26da 897 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 898 if (--r17 < low_bound)
899 r17 = low_bound;
900 rt61pci_bbp_write(rt2x00dev, 17, r17);
901 }
902}
903
904/*
a7f3a06c 905 * Firmware functions
95ea3627
ID		 906 */
907static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
908{
909 char *fw_name;
910
911 switch (rt2x00dev->chip.rt) {
912 case RT2561:
913 fw_name = FIRMWARE_RT2561;
914 break;
915 case RT2561s:
916 fw_name = FIRMWARE_RT2561s;
917 break;
918 case RT2661:
919 fw_name = FIRMWARE_RT2661;
920 break;
921 default:
922 fw_name = NULL;
923 break;
924 }
925
926 return fw_name;
927}
928
f160ebcb 929static u16 rt61pci_get_firmware_crc(const void *data, const size_t len)
a7f3a06c
ID		 930{
931 u16 crc;
932
933 /*
934 * Use the crc itu-t algorithm.
935 * The last 2 bytes in the firmware array are the crc checksum itself,
936 * this means that we should never pass those 2 bytes to the crc
937 * algorithm.
938 */
939 crc = crc_itu_t(0, data, len - 2);
940 crc = crc_itu_t_byte(crc, 0);
941 crc = crc_itu_t_byte(crc, 0);
942
943 return crc;
944}
945
f160ebcb 946static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
95ea3627
ID		 947 const size_t len)
948{
949 int i;
950 u32 reg;
951
952 /*
953 * Wait for stable hardware.
954 */
955 for (i = 0; i < 100; i++) {
956 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
957 if (reg)
958 break;
959 msleep(1);
960 }
961
962 if (!reg) {
963 ERROR(rt2x00dev, "Unstable hardware.\n");
964 return -EBUSY;
965 }
966
967 /*
968 * Prepare MCU and mailbox for firmware loading.
969 */
970 reg = 0;
971 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
972 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
973 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
974 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
975 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
976
977 /*
978 * Write firmware to device.
979 */
980 reg = 0;
981 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
982 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
983 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
984
985 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
986 data, len);
987
988 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
989 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
990
991 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
992 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
993
994 for (i = 0; i < 100; i++) {
995 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
996 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
997 break;
998 msleep(1);
999 }
1000
1001 if (i == 100) {
1002 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1003 return -EBUSY;
1004 }
1005
1006 /*
1007 * Reset MAC and BBP registers.
1008 */
1009 reg = 0;
1010 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1011 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1012 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1013
1014 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1015 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1016 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1017 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1018
1019 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1020 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1021 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1022
1023 return 0;
1024}
1025
a7f3a06c
ID		 1026/*
1027 * Initialization functions.
1028 */
837e7f24 1029static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 1030 struct queue_entry *entry)
95ea3627 1031{
b8be63ff 1032 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
c4da0048 1033 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 1034 u32 word;
1035
b8be63ff 1036 rt2x00_desc_read(entry_priv->desc, 5, &word);
30b3a23c 1037 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
c4da0048 1038 skbdesc->skb_dma);
b8be63ff 1039 rt2x00_desc_write(entry_priv->desc, 5, word);
95ea3627 1040
b8be63ff 1041 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24 1042 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
b8be63ff 1043 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 1044}
1045
837e7f24 1046static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 1047 struct queue_entry *entry)
95ea3627 1048{
b8be63ff 1049 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1050 u32 word;
1051
b8be63ff 1052 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24
ID		 1053 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1054 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
b8be63ff 1055 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 1056}
1057
181d6902 1058static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1059{
b8be63ff 1060 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 1061 u32 reg;
1062
95ea3627
ID		 1063 /*
1064 * Initialize registers.
1065 */
1066 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1067 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1068 rt2x00dev->tx[0].limit);
95ea3627 1069 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1070 rt2x00dev->tx[1].limit);
95ea3627 1071 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1072 rt2x00dev->tx[2].limit);
95ea3627 1073 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1074 rt2x00dev->tx[3].limit);
95ea3627
ID		 1075 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1076
1077 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1078 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1079 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1080 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1081
b8be63ff 1082 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1083 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
30b3a23c 1084 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
b8be63ff 1085 entry_priv->desc_dma);
95ea3627
ID		 1086 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1087
b8be63ff 1088 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1089 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
30b3a23c 1090 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
b8be63ff 1091 entry_priv->desc_dma);
95ea3627
ID		 1092 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1093
b8be63ff 1094 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1095 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
30b3a23c 1096 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
b8be63ff 1097 entry_priv->desc_dma);
95ea3627
ID		 1098 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1099
b8be63ff 1100 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1101 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
30b3a23c 1102 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
b8be63ff 1103 entry_priv->desc_dma);
95ea3627
ID		 1104 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1105
95ea3627 1106 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1107 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1108 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1109 rt2x00dev->rx->desc_size / 4);
1110 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1111 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1112
b8be63ff 1113 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1114 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
30b3a23c 1115 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
b8be63ff 1116 entry_priv->desc_dma);
95ea3627
ID		 1117 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1118
1119 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1120 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1121 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1122 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1123 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
95ea3627
ID		 1124 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1125
1126 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1127 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1128 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1129 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1130 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
95ea3627
ID		 1131 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1132
1133 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1134 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1135 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1136
1137 return 0;
1138}
1139
1140static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1141{
1142 u32 reg;
1143
1144 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1145 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1146 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1147 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1148 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1149
1150 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1151 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1152 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1153 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1154 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1155 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1156 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1157 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1158 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1159 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1160
1161 /*
1162 * CCK TXD BBP registers
1163 */
1164 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1165 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1166 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1167 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1168 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1169 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1170 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1171 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1172 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1173 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1174
1175 /*
1176 * OFDM TXD BBP registers
1177 */
1178 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1179 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1180 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1181 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1182 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1183 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1184 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1185 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1186
1187 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1188 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1189 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1190 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1191 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1192 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1193
1194 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1195 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1196 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1197 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1198 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1199 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1200
1f909162
ID		 1201 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1202 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1203 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1204 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1205 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1206 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1207 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1208 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1209
95ea3627
ID		 1210 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1211
1212 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1213
1214 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1215 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1216 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1217
1218 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1219
1220 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1221 return -EBUSY;
1222
1223 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1224
1225 /*
1226 * Invalidate all Shared Keys (SEC_CSR0),
1227 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1228 */
1229 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1230 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1231 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1232
1233 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1234 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1235 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1236 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1237
1238 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1239
1240 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1241
1242 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1243
1244 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1245 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1246 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1247 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1248
1249 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1250 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1251 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1252 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1253
6bb40dd1
ID		 1254 /*
1255 * Clear all beacons
1256 * For the Beacon base registers we only need to clear
1257 * the first byte since that byte contains the VALID and OWNER
1258 * bits which (when set to 0) will invalidate the entire beacon.
1259 */
1260 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1261 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1262 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1263 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1264
95ea3627
ID		 1265 /*
1266 * We must clear the error counters.
1267 * These registers are cleared on read,
1268 * so we may pass a useless variable to store the value.
1269 */
1270 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1271 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1272 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1273
1274 /*
1275 * Reset MAC and BBP registers.
1276 */
1277 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1278 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1279 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1280 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1281
1282 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1283 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1284 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1285 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1286
1287 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1288 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1289 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1290
1291 return 0;
1292}
1293
2b08da3f 1294static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1295{
1296 unsigned int i;
95ea3627
ID		 1297 u8 value;
1298
1299 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1300 rt61pci_bbp_read(rt2x00dev, 0, &value);
1301 if ((value != 0xff) && (value != 0x00))
2b08da3f 1302 return 0;
95ea3627
ID		 1303 udelay(REGISTER_BUSY_DELAY);
1304 }
1305
1306 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1307 return -EACCES;
2b08da3f
ID		 1308}
1309
1310static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1311{
1312 unsigned int i;
1313 u16 eeprom;
1314 u8 reg_id;
1315 u8 value;
1316
1317 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1318 return -EACCES;
95ea3627 1319
95ea3627
ID		 1320 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1321 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1322 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1323 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1324 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1325 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1326 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1327 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1328 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1329 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1330 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1331 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1332 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1333 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1334 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1335 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1336 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1337 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1338 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1339 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1340 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1341 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1342 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1343 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1344
95ea3627
ID		 1345 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1346 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1347
1348 if (eeprom != 0xffff && eeprom != 0x0000) {
1349 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1350 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1351 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1352 }
1353 }
95ea3627
ID		 1354
1355 return 0;
1356}
1357
1358/*
1359 * Device state switch handlers.
1360 */
1361static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1362 enum dev_state state)
1363{
1364 u32 reg;
1365
1366 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1367 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1368 (state == STATE_RADIO_RX_OFF) ||
1369 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1370 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1371}
1372
1373static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1374 enum dev_state state)
1375{
1376 int mask = (state == STATE_RADIO_IRQ_OFF);
1377 u32 reg;
1378
1379 /*
1380 * When interrupts are being enabled, the interrupt registers
1381 * should clear the register to assure a clean state.
1382 */
1383 if (state == STATE_RADIO_IRQ_ON) {
1384 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1385 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1386
1387 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1388 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1389 }
1390
1391 /*
1392 * Only toggle the interrupts bits we are going to use.
1393 * Non-checked interrupt bits are disabled by default.
1394 */
1395 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1396 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1397 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1398 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1399 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1400 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1401
1402 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1403 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1404 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1405 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1406 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1407 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1408 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1409 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1410 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1411 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1412}
1413
1414static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1415{
1416 u32 reg;
1417
1418 /*
1419 * Initialize all registers.
1420 */
2b08da3f
ID		 1421 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1422 rt61pci_init_registers(rt2x00dev) ||
1423 rt61pci_init_bbp(rt2x00dev)))
95ea3627 1424 return -EIO;
95ea3627
ID		 1425
1426 /*
1427 * Enable RX.
1428 */
1429 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1430 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1431 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1432
95ea3627
ID		 1433 return 0;
1434}
1435
1436static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1437{
1438 u32 reg;
1439
95ea3627
ID		 1440 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1441
1442 /*
1443 * Disable synchronisation.
1444 */
1445 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1446
1447 /*
1448 * Cancel RX and TX.
1449 */
1450 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1451 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1452 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1453 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1454 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
95ea3627 1455 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
95ea3627
ID		 1456}
1457
1458static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1459{
1460 u32 reg;
1461 unsigned int i;
1462 char put_to_sleep;
95ea3627
ID		 1463
1464 put_to_sleep = (state != STATE_AWAKE);
1465
1466 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1467 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1468 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1469 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1470
1471 /*
1472 * Device is not guaranteed to be in the requested state yet.
1473 * We must wait until the register indicates that the
1474 * device has entered the correct state.
1475 */
1476 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1477 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1478 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1479 if (state == !put_to_sleep)
95ea3627
ID		 1480 return 0;
1481 msleep(10);
1482 }
1483
95ea3627
ID		 1484 return -EBUSY;
1485}
1486
1487static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1488 enum dev_state state)
1489{
1490 int retval = 0;
1491
1492 switch (state) {
1493 case STATE_RADIO_ON:
1494 retval = rt61pci_enable_radio(rt2x00dev);
1495 break;
1496 case STATE_RADIO_OFF:
1497 rt61pci_disable_radio(rt2x00dev);
1498 break;
1499 case STATE_RADIO_RX_ON:
61667d8d 1500 case STATE_RADIO_RX_ON_LINK:
95ea3627 1501 case STATE_RADIO_RX_OFF:
61667d8d 1502 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1503 rt61pci_toggle_rx(rt2x00dev, state);
1504 break;
1505 case STATE_RADIO_IRQ_ON:
1506 case STATE_RADIO_IRQ_OFF:
1507 rt61pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1508 break;
1509 case STATE_DEEP_SLEEP:
1510 case STATE_SLEEP:
1511 case STATE_STANDBY:
1512 case STATE_AWAKE:
1513 retval = rt61pci_set_state(rt2x00dev, state);
1514 break;
1515 default:
1516 retval = -ENOTSUPP;
1517 break;
1518 }
1519
2b08da3f
ID		 1520 if (unlikely(retval))
1521 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1522 state, retval);
1523
95ea3627
ID		 1524 return retval;
1525}
1526
1527/*
1528 * TX descriptor initialization
1529 */
1530static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1531 struct sk_buff *skb,
61486e0f 1532 struct txentry_desc *txdesc)
95ea3627 1533{
181d6902 1534 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1535 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1536 u32 word;
1537
1538 /*
1539 * Start writing the descriptor words.
1540 */
1541 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1542 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1543 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1544 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1545 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1546 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1547 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
4de36fe5 1548 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
95ea3627
ID		 1549 rt2x00_desc_write(txd, 1, word);
1550
1551 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1552 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1553 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1554 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1555 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1556 rt2x00_desc_write(txd, 2, word);
1557
1558 rt2x00_desc_read(txd, 5, &word);
4de36fe5
GW		 1559 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1560 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1561 skbdesc->entry->entry_idx);
95ea3627 1562 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1563 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1564 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1565 rt2x00_desc_write(txd, 5, word);
1566
4de36fe5
GW		 1567 rt2x00_desc_read(txd, 6, &word);
1568 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
c4da0048 1569 skbdesc->skb_dma);
4de36fe5
GW		 1570 rt2x00_desc_write(txd, 6, word);
1571
d7bafff3
AB		 1572 if (skbdesc->desc_len > TXINFO_SIZE) {
1573 rt2x00_desc_read(txd, 11, &word);
d56d453a 1574 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
d7bafff3
AB		 1575 rt2x00_desc_write(txd, 11, word);
1576 }
95ea3627
ID		 1577
1578 rt2x00_desc_read(txd, 0, &word);
1579 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1580 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1581 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1582 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1583 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1584 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1585 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1586 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1587 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1588 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1589 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1590 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1591 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627 1592 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
d56d453a 1593 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627 1594 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1595 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1596 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1597 rt2x00_desc_write(txd, 0, word);
1598}
1599
1600/*
1601 * TX data initialization
1602 */
bd88a781
ID		 1603static void rt61pci_write_beacon(struct queue_entry *entry)
1604{
1605 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1606 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1607 unsigned int beacon_base;
1608 u32 reg;
1609
1610 /*
1611 * Disable beaconing while we are reloading the beacon data,
1612 * otherwise we might be sending out invalid data.
1613 */
1614 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1615 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1616 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1617 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1618 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1619
1620 /*
1621 * Write entire beacon with descriptor to register.
1622 */
1623 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1624 rt2x00pci_register_multiwrite(rt2x00dev,
1625 beacon_base,
1626 skbdesc->desc, skbdesc->desc_len);
1627 rt2x00pci_register_multiwrite(rt2x00dev,
1628 beacon_base + skbdesc->desc_len,
1629 entry->skb->data, entry->skb->len);
1630
1631 /*
1632 * Clean up beacon skb.
1633 */
1634 dev_kfree_skb_any(entry->skb);
1635 entry->skb = NULL;
1636}
1637
95ea3627 1638static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1639 const enum data_queue_qid queue)
95ea3627
ID		 1640{
1641 u32 reg;
1642
e58c6aca 1643 if (queue == QID_BEACON) {
95ea3627
ID		 1644 /*
1645 * For Wi-Fi faily generated beacons between participating
1646 * stations. Set TBTT phase adaptive adjustment step to 8us.
1647 */
1648 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1649
1650 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1651 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1652 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1653 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1654 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1655 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1656 }
1657 return;
1658 }
1659
1660 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
e58c6aca
ID		 1661 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1662 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1663 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1664 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
95ea3627
ID		 1665 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1666}
1667
1668/*
1669 * RX control handlers
1670 */
1671static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1672{
1673 u16 eeprom;
1674 u8 offset;
1675 u8 lna;
1676
1677 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1678 switch (lna) {
1679 case 3:
1680 offset = 90;
1681 break;
1682 case 2:
1683 offset = 74;
1684 break;
1685 case 1:
1686 offset = 64;
1687 break;
1688 default:
1689 return 0;
1690 }
1691
8318d78a 1692 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1693 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1694 offset += 14;
1695
1696 if (lna == 3 || lna == 2)
1697 offset += 10;
1698
1699 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1700 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1701 } else {
1702 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1703 offset += 14;
1704
1705 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1706 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1707 }
1708
1709 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1710}
1711
181d6902
ID		 1712static void rt61pci_fill_rxdone(struct queue_entry *entry,
1713 struct rxdone_entry_desc *rxdesc)
95ea3627 1714{
b8be63ff 1715 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1716 u32 word0;
1717 u32 word1;
1718
b8be63ff
ID		 1719 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1720 rt2x00_desc_read(entry_priv->desc, 1, &word1);
95ea3627 1721
4150c572 1722 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1723 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1724
1725 /*
1726 * Obtain the status about this packet.
89993890
ID		 1727 * When frame was received with an OFDM bitrate,
1728 * the signal is the PLCP value. If it was received with
1729 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1730 */
181d6902
ID		 1731 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1732 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
181d6902 1733 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1734
19d30e02
ID		 1735 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1736 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1737 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1738 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1739}
1740
1741/*
1742 * Interrupt functions.
1743 */
1744static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1745{
181d6902
ID		 1746 struct data_queue *queue;
1747 struct queue_entry *entry;
1748 struct queue_entry *entry_done;
b8be63ff 1749 struct queue_entry_priv_pci *entry_priv;
181d6902 1750 struct txdone_entry_desc txdesc;
95ea3627
ID		 1751 u32 word;
1752 u32 reg;
1753 u32 old_reg;
1754 int type;
1755 int index;
95ea3627
ID		 1756
1757 /*
1758 * During each loop we will compare the freshly read
1759 * STA_CSR4 register value with the value read from
1760 * the previous loop. If the 2 values are equal then
1761 * we should stop processing because the chance it
1762 * quite big that the device has been unplugged and
1763 * we risk going into an endless loop.
1764 */
1765 old_reg = 0;
1766
1767 while (1) {
1768 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1769 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1770 break;
1771
1772 if (old_reg == reg)
1773 break;
1774 old_reg = reg;
1775
1776 /*
1777 * Skip this entry when it contains an invalid
181d6902 1778 * queue identication number.
95ea3627
ID		 1779 */
1780 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 1781 queue = rt2x00queue_get_queue(rt2x00dev, type);
1782 if (unlikely(!queue))
95ea3627
ID		 1783 continue;
1784
1785 /*
1786 * Skip this entry when it contains an invalid
1787 * index number.
1788 */
1789 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 1790 if (unlikely(index >= queue->limit))
95ea3627
ID		 1791 continue;
1792
181d6902 1793 entry = &queue->entries[index];
b8be63ff
ID		 1794 entry_priv = entry->priv_data;
1795 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1796
1797 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1798 !rt2x00_get_field32(word, TXD_W0_VALID))
1799 return;
1800
181d6902 1801 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 1802 while (entry != entry_done) {
181d6902
ID		 1803 /* Catch up.
1804 * Just report any entries we missed as failed.
1805 */
62bc060b 1806 WARNING(rt2x00dev,
181d6902
ID		 1807 "TX status report missed for entry %d\n",
1808 entry_done->entry_idx);
1809
fb55f4d1
ID		 1810 txdesc.flags = 0;
1811 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
181d6902
ID		 1812 txdesc.retry = 0;
1813
d74f5ba4 1814 rt2x00lib_txdone(entry_done, &txdesc);
181d6902 1815 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 1816 }
1817
95ea3627
ID		 1818 /*
1819 * Obtain the status about this packet.
1820 */
fb55f4d1
ID		 1821 txdesc.flags = 0;
1822 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
1823 case 0: /* Success, maybe with retry */
1824 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1825 break;
1826 case 6: /* Failure, excessive retries */
1827 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1828 /* Don't break, this is a failed frame! */
1829 default: /* Failure */
1830 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1831 }
181d6902 1832 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 1833
d74f5ba4 1834 rt2x00lib_txdone(entry, &txdesc);
95ea3627
ID		 1835 }
1836}
1837
1838static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1839{
1840 struct rt2x00_dev *rt2x00dev = dev_instance;
1841 u32 reg_mcu;
1842 u32 reg;
1843
1844 /*
1845 * Get the interrupt sources & saved to local variable.
1846 * Write register value back to clear pending interrupts.
1847 */
1848 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1849 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1850
1851 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1852 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1853
1854 if (!reg && !reg_mcu)
1855 return IRQ_NONE;
1856
1857 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1858 return IRQ_HANDLED;
1859
1860 /*
1861 * Handle interrupts, walk through all bits
1862 * and run the tasks, the bits are checked in order of
1863 * priority.
1864 */
1865
1866 /*
1867 * 1 - Rx ring done interrupt.
1868 */
1869 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1870 rt2x00pci_rxdone(rt2x00dev);
1871
1872 /*
1873 * 2 - Tx ring done interrupt.
1874 */
1875 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1876 rt61pci_txdone(rt2x00dev);
1877
1878 /*
1879 * 3 - Handle MCU command done.
1880 */
1881 if (reg_mcu)
1882 rt2x00pci_register_write(rt2x00dev,
1883 M2H_CMD_DONE_CSR, 0xffffffff);
1884
1885 return IRQ_HANDLED;
1886}
1887
1888/*
1889 * Device probe functions.
1890 */
1891static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1892{
1893 struct eeprom_93cx6 eeprom;
1894 u32 reg;
1895 u16 word;
1896 u8 *mac;
1897 s8 value;
1898
1899 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1900
1901 eeprom.data = rt2x00dev;
1902 eeprom.register_read = rt61pci_eepromregister_read;
1903 eeprom.register_write = rt61pci_eepromregister_write;
1904 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1905 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1906 eeprom.reg_data_in = 0;
1907 eeprom.reg_data_out = 0;
1908 eeprom.reg_data_clock = 0;
1909 eeprom.reg_chip_select = 0;
1910
1911 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1912 EEPROM_SIZE / sizeof(u16));
1913
1914 /*
1915 * Start validation of the data that has been read.
1916 */
1917 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1918 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1919 DECLARE_MAC_BUF(macbuf);
1920
95ea3627 1921 random_ether_addr(mac);
0795af57 1922 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1923 }
1924
1925 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1926 if (word == 0xffff) {
1927 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1928 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1929 ANTENNA_B);
1930 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1931 ANTENNA_B);
95ea3627
ID		 1932 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1933 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1934 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1935 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1936 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1937 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1938 }
1939
1940 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1941 if (word == 0xffff) {
1942 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1943 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1944 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1945 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1946 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1947 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1948 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1949 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1950 }
1951
1952 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1953 if (word == 0xffff) {
1954 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1955 LED_MODE_DEFAULT);
1956 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1957 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1958 }
1959
1960 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1961 if (word == 0xffff) {
1962 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1963 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1964 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1965 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1966 }
1967
1968 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1969 if (word == 0xffff) {
1970 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1971 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1972 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1973 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1974 } else {
1975 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1976 if (value < -10 || value > 10)
1977 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1978 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1979 if (value < -10 || value > 10)
1980 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1981 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1982 }
1983
1984 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1985 if (word == 0xffff) {
1986 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1987 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1988 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1989 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1990 } else {
1991 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1992 if (value < -10 || value > 10)
1993 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1994 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1995 if (value < -10 || value > 10)
1996 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1997 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1998 }
1999
2000 return 0;
2001}
2002
2003static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2004{
2005 u32 reg;
2006 u16 value;
2007 u16 eeprom;
2008 u16 device;
2009
2010 /*
2011 * Read EEPROM word for configuration.
2012 */
2013 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2014
2015 /*
2016 * Identify RF chipset.
2017 * To determine the RT chip we have to read the
2018 * PCI header of the device.
2019 */
14a3bf89 2020 pci_read_config_word(to_pci_dev(rt2x00dev->dev),
95ea3627
ID		 2021 PCI_CONFIG_HEADER_DEVICE, &device);
2022 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2023 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2024 rt2x00_set_chip(rt2x00dev, device, value, reg);
2025
2026 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2027 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2028 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2029 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2030 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2031 return -ENODEV;
2032 }
2033
e4cd2ff8
ID		 2034 /*
2035 * Determine number of antenna's.
2036 */
2037 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2038 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2039
95ea3627
ID		 2040 /*
2041 * Identify default antenna configuration.
2042 */
addc81bd 2043 rt2x00dev->default_ant.tx =
95ea3627 2044 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 2045 rt2x00dev->default_ant.rx =
95ea3627
ID		 2046 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2047
2048 /*
2049 * Read the Frame type.
2050 */
2051 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2052 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2053
95ea3627
ID		 2054 /*
2055 * Detect if this device has an hardware controlled radio.
2056 */
81873e9c 2057#ifdef CONFIG_RT61PCI_RFKILL
95ea3627 2058 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 2059 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 2060#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627
ID		 2061
2062 /*
2063 * Read frequency offset and RF programming sequence.
2064 */
2065 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2066 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2067 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2068
2069 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2070
2071 /*
2072 * Read external LNA informations.
2073 */
2074 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2075
2076 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2077 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2078 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2079 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2080
e4cd2ff8
ID		 2081 /*
2082 * When working with a RF2529 chip without double antenna
2083 * the antenna settings should be gathered from the NIC
2084 * eeprom word.
2085 */
2086 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2087 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2088 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2089 case 0:
2090 rt2x00dev->default_ant.tx = ANTENNA_B;
2091 rt2x00dev->default_ant.rx = ANTENNA_A;
2092 break;
2093 case 1:
2094 rt2x00dev->default_ant.tx = ANTENNA_B;
2095 rt2x00dev->default_ant.rx = ANTENNA_B;
2096 break;
2097 case 2:
2098 rt2x00dev->default_ant.tx = ANTENNA_A;
2099 rt2x00dev->default_ant.rx = ANTENNA_A;
2100 break;
2101 case 3:
2102 rt2x00dev->default_ant.tx = ANTENNA_A;
2103 rt2x00dev->default_ant.rx = ANTENNA_B;
2104 break;
2105 }
2106
2107 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2108 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2109 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2110 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2111 }
2112
95ea3627
ID		 2113 /*
2114 * Store led settings, for correct led behaviour.
2115 * If the eeprom value is invalid,
2116 * switch to default led mode.
2117 */
a9450b70 2118#ifdef CONFIG_RT61PCI_LEDS
95ea3627 2119 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
a9450b70
ID		 2120 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2121
475433be
ID		 2122 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2123 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2124 if (value == LED_MODE_SIGNAL_STRENGTH)
2125 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2126 LED_TYPE_QUALITY);
95ea3627 2127
a9450b70
ID		 2128 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2129 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2130 rt2x00_get_field16(eeprom,
2131 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2132 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2133 rt2x00_get_field16(eeprom,
2134 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2135 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2136 rt2x00_get_field16(eeprom,
2137 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2138 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2139 rt2x00_get_field16(eeprom,
2140 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2141 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2142 rt2x00_get_field16(eeprom,
2143 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2144 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2145 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2146 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2147 rt2x00_get_field16(eeprom,
2148 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2149 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2150 rt2x00_get_field16(eeprom,
2151 EEPROM_LED_POLARITY_RDY_A));
a9450b70 2152#endif /* CONFIG_RT61PCI_LEDS */
95ea3627
ID		 2153
2154 return 0;
2155}
2156
2157/*
2158 * RF value list for RF5225 & RF5325
2159 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2160 */
2161static const struct rf_channel rf_vals_noseq[] = {
2162 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2163 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2164 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2165 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2166 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2167 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2168 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2169 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2170 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2171 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2172 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2173 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2174 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2175 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2176
2177 /* 802.11 UNI / HyperLan 2 */
2178 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2179 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2180 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2181 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2182 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2183 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2184 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2185 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2186
2187 /* 802.11 HyperLan 2 */
2188 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2189 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2190 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2191 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2192 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2193 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2194 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2195 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2196 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2197 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2198
2199 /* 802.11 UNII */
2200 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2201 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2202 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2203 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2204 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2205 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2206
2207 /* MMAC(Japan)J52 ch 34,38,42,46 */
2208 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2209 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2210 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2211 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2212};
2213
2214/*
2215 * RF value list for RF5225 & RF5325
2216 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2217 */
2218static const struct rf_channel rf_vals_seq[] = {
2219 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2220 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2221 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2222 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2223 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2224 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2225 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2226 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2227 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2228 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2229 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2230 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2231 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2232 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2233
2234 /* 802.11 UNI / HyperLan 2 */
2235 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2236 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2237 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2238 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2239 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2240 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2241 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2242 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2243
2244 /* 802.11 HyperLan 2 */
2245 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2246 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2247 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2248 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2249 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2250 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2251 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2252 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2253 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2254 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2255
2256 /* 802.11 UNII */
2257 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2258 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2259 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2260 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2261 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2262 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2263
2264 /* MMAC(Japan)J52 ch 34,38,42,46 */
2265 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2266 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2267 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2268 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2269};
2270
2271static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2272{
2273 struct hw_mode_spec *spec = &rt2x00dev->spec;
2274 u8 *txpower;
2275 unsigned int i;
2276
2277 /*
2278 * Initialize all hw fields.
2279 */
2280 rt2x00dev->hw->flags =
566bfe5a
BR		 2281 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2282 IEEE80211_HW_SIGNAL_DBM;
95ea3627 2283 rt2x00dev->hw->extra_tx_headroom = 0;
95ea3627 2284
14a3bf89 2285 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2286 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2287 rt2x00_eeprom_addr(rt2x00dev,
2288 EEPROM_MAC_ADDR_0));
2289
2290 /*
2291 * Convert tx_power array in eeprom.
2292 */
2293 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2294 for (i = 0; i < 14; i++)
2295 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2296
2297 /*
2298 * Initialize hw_mode information.
2299 */
31562e80
ID		 2300 spec->supported_bands = SUPPORT_BAND_2GHZ;
2301 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2302 spec->tx_power_a = NULL;
2303 spec->tx_power_bg = txpower;
2304 spec->tx_power_default = DEFAULT_TXPOWER;
2305
2306 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2307 spec->num_channels = 14;
2308 spec->channels = rf_vals_noseq;
2309 } else {
2310 spec->num_channels = 14;
2311 spec->channels = rf_vals_seq;
2312 }
2313
2314 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2315 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
31562e80 2316 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2317 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2318
2319 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2320 for (i = 0; i < 14; i++)
2321 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2322
2323 spec->tx_power_a = txpower;
2324 }
2325}
2326
2327static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2328{
2329 int retval;
2330
2331 /*
2332 * Allocate eeprom data.
2333 */
2334 retval = rt61pci_validate_eeprom(rt2x00dev);
2335 if (retval)
2336 return retval;
2337
2338 retval = rt61pci_init_eeprom(rt2x00dev);
2339 if (retval)
2340 return retval;
2341
2342 /*
2343 * Initialize hw specifications.
2344 */
2345 rt61pci_probe_hw_mode(rt2x00dev);
2346
2347 /*
c4da0048 2348 * This device requires firmware and DMA mapped skbs.
95ea3627 2349 */
066cb637 2350 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
c4da0048 2351 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
95ea3627
ID		 2352
2353 /*
2354 * Set the rssi offset.
2355 */
2356 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2357
2358 return 0;
2359}
2360
2361/*
2362 * IEEE80211 stack callback functions.
2363 */
2364static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2365 u32 short_retry, u32 long_retry)
2366{
2367 struct rt2x00_dev *rt2x00dev = hw->priv;
2368 u32 reg;
2369
2370 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2371 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2372 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2373 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2374
2375 return 0;
2376}
2377
2378static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2379{
2380 struct rt2x00_dev *rt2x00dev = hw->priv;
2381 u64 tsf;
2382 u32 reg;
2383
2384 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2385 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2386 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2387 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2388
2389 return tsf;
2390}
2391
95ea3627
ID		 2392static const struct ieee80211_ops rt61pci_mac80211_ops = {
2393 .tx = rt2x00mac_tx,
4150c572
JB		 2394 .start = rt2x00mac_start,
2395 .stop = rt2x00mac_stop,
95ea3627
ID		 2396 .add_interface = rt2x00mac_add_interface,
2397 .remove_interface = rt2x00mac_remove_interface,
2398 .config = rt2x00mac_config,
2399 .config_interface = rt2x00mac_config_interface,
3a643d24 2400 .configure_filter = rt2x00mac_configure_filter,
95ea3627
ID		 2401 .get_stats = rt2x00mac_get_stats,
2402 .set_retry_limit = rt61pci_set_retry_limit,
471b3efd 2403 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2404 .conf_tx = rt2x00mac_conf_tx,
2405 .get_tx_stats = rt2x00mac_get_tx_stats,
2406 .get_tsf = rt61pci_get_tsf,
95ea3627
ID		 2407};
2408
2409static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2410 .irq_handler = rt61pci_interrupt,
2411 .probe_hw = rt61pci_probe_hw,
2412 .get_firmware_name = rt61pci_get_firmware_name,
a7f3a06c 2413 .get_firmware_crc = rt61pci_get_firmware_crc,
95ea3627
ID		 2414 .load_firmware = rt61pci_load_firmware,
2415 .initialize = rt2x00pci_initialize,
2416 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 2417 .init_rxentry = rt61pci_init_rxentry,
2418 .init_txentry = rt61pci_init_txentry,
95ea3627 2419 .set_device_state = rt61pci_set_device_state,
95ea3627 2420 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2421 .link_stats = rt61pci_link_stats,
2422 .reset_tuner = rt61pci_reset_tuner,
2423 .link_tuner = rt61pci_link_tuner,
2424 .write_tx_desc = rt61pci_write_tx_desc,
2425 .write_tx_data = rt2x00pci_write_tx_data,
bd88a781 2426 .write_beacon = rt61pci_write_beacon,
95ea3627
ID		 2427 .kick_tx_queue = rt61pci_kick_tx_queue,
2428 .fill_rxdone = rt61pci_fill_rxdone,
3a643d24 2429 .config_filter = rt61pci_config_filter,
6bb40dd1 2430 .config_intf = rt61pci_config_intf,
72810379 2431 .config_erp = rt61pci_config_erp,
95ea3627
ID		 2432 .config = rt61pci_config,
2433};
2434
181d6902
ID		 2435static const struct data_queue_desc rt61pci_queue_rx = {
2436 .entry_num = RX_ENTRIES,
2437 .data_size = DATA_FRAME_SIZE,
2438 .desc_size = RXD_DESC_SIZE,
b8be63ff 2439 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2440};
2441
2442static const struct data_queue_desc rt61pci_queue_tx = {
2443 .entry_num = TX_ENTRIES,
2444 .data_size = DATA_FRAME_SIZE,
2445 .desc_size = TXD_DESC_SIZE,
b8be63ff 2446 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2447};
2448
2449static const struct data_queue_desc rt61pci_queue_bcn = {
6bb40dd1 2450 .entry_num = 4 * BEACON_ENTRIES,
78720897 2451 .data_size = 0, /* No DMA required for beacons */
181d6902 2452 .desc_size = TXINFO_SIZE,
b8be63ff 2453 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2454};
2455
95ea3627 2456static const struct rt2x00_ops rt61pci_ops = {
2360157c 2457 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2458 .max_sta_intf = 1,
2459 .max_ap_intf = 4,
95ea3627
ID		 2460 .eeprom_size = EEPROM_SIZE,
2461 .rf_size = RF_SIZE,
61448f88 2462 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 2463 .rx = &rt61pci_queue_rx,
2464 .tx = &rt61pci_queue_tx,
2465 .bcn = &rt61pci_queue_bcn,
95ea3627
ID		 2466 .lib = &rt61pci_rt2x00_ops,
2467 .hw = &rt61pci_mac80211_ops,
2468#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2469 .debugfs = &rt61pci_rt2x00debug,
2470#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2471};
2472
2473/*
2474 * RT61pci module information.
2475 */
2476static struct pci_device_id rt61pci_device_table[] = {
2477 /* RT2561s */
2478 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2479 /* RT2561 v2 */
2480 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2481 /* RT2661 */
2482 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2483 { 0, }
2484};
2485
2486MODULE_AUTHOR(DRV_PROJECT);
2487MODULE_VERSION(DRV_VERSION);
2488MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2489MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2490 "PCI & PCMCIA chipset based cards");
2491MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2492MODULE_FIRMWARE(FIRMWARE_RT2561);
2493MODULE_FIRMWARE(FIRMWARE_RT2561s);
2494MODULE_FIRMWARE(FIRMWARE_RT2661);
2495MODULE_LICENSE("GPL");
2496
2497static struct pci_driver rt61pci_driver = {
2360157c 2498 .name = KBUILD_MODNAME,
95ea3627
ID		 2499 .id_table = rt61pci_device_table,
2500 .probe = rt2x00pci_probe,
2501 .remove = __devexit_p(rt2x00pci_remove),
2502 .suspend = rt2x00pci_suspend,
2503 .resume = rt2x00pci_resume,
2504};
2505
2506static int __init rt61pci_init(void)
2507{
2508 return pci_register_driver(&rt61pci_driver);
2509}
2510
2511static void __exit rt61pci_exit(void)
2512{
2513 pci_unregister_driver(&rt61pci_driver);
2514}
2515
2516module_init(rt61pci_init);
2517module_exit(rt61pci_exit);
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