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[PATCH] rt2x00: Implement SW diversity
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627
ID		 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27/*
28 * Set enviroment defines for rt2x00.h
29 */
30#define DRV_NAME "rt61pci"
31
32#include <linux/delay.h>
33#include <linux/etherdevice.h>
34#include <linux/init.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/eeprom_93cx6.h>
39
40#include "rt2x00.h"
41#include "rt2x00pci.h"
42#include "rt61pci.h"
43
44/*
45 * Register access.
46 * BBP and RF register require indirect register access,
47 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
48 * These indirect registers work with busy bits,
49 * and we will try maximal REGISTER_BUSY_COUNT times to access
50 * the register while taking a REGISTER_BUSY_DELAY us delay
51 * between each attampt. When the busy bit is still set at that time,
52 * the access attempt is considered to have failed,
53 * and we will print an error.
54 */
55static u32 rt61pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
56{
57 u32 reg;
58 unsigned int i;
59
60 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
61 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
62 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
63 break;
64 udelay(REGISTER_BUSY_DELAY);
65 }
66
67 return reg;
68}
69
70static void rt61pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
72{
73 u32 reg;
74
75 /*
76 * Wait until the BBP becomes ready.
77 */
78 reg = rt61pci_bbp_check(rt2x00dev);
79 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
80 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
81 return;
82 }
83
84 /*
85 * Write the data into the BBP.
86 */
87 reg = 0;
88 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
89 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
90 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
91 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
92
93 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
94}
95
96static void rt61pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
97 const unsigned int word, u8 *value)
98{
99 u32 reg;
100
101 /*
102 * Wait until the BBP becomes ready.
103 */
104 reg = rt61pci_bbp_check(rt2x00dev);
105 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
106 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
107 return;
108 }
109
110 /*
111 * Write the request into the BBP.
112 */
113 reg = 0;
114 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
115 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
116 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
117
118 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
119
120 /*
121 * Wait until the BBP becomes ready.
122 */
123 reg = rt61pci_bbp_check(rt2x00dev);
124 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
125 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
126 *value = 0xff;
127 return;
128 }
129
130 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
131}
132
133static void rt61pci_rf_write(const struct rt2x00_dev *rt2x00dev,
134 const unsigned int word, const u32 value)
135{
136 u32 reg;
137 unsigned int i;
138
139 if (!word)
140 return;
141
142 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
143 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
144 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
145 goto rf_write;
146 udelay(REGISTER_BUSY_DELAY);
147 }
148
149 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
150 return;
151
152rf_write:
153 reg = 0;
154 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
155 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
156 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
157 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
158
159 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
160 rt2x00_rf_write(rt2x00dev, word, value);
161}
162
163static void rt61pci_mcu_request(const struct rt2x00_dev *rt2x00dev,
164 const u8 command, const u8 token,
165 const u8 arg0, const u8 arg1)
166{
167 u32 reg;
168
169 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
170
171 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
172 ERROR(rt2x00dev, "mcu request error. "
173 "Request 0x%02x failed for token 0x%02x.\n",
174 command, token);
175 return;
176 }
177
178 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
179 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
181 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
182 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
183
184 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
185 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
186 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
187 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
188}
189
190static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
191{
192 struct rt2x00_dev *rt2x00dev = eeprom->data;
193 u32 reg;
194
195 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
196
197 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
198 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
199 eeprom->reg_data_clock =
200 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
201 eeprom->reg_chip_select =
202 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
203}
204
205static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
206{
207 struct rt2x00_dev *rt2x00dev = eeprom->data;
208 u32 reg = 0;
209
210 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
211 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
212 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
213 !!eeprom->reg_data_clock);
214 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
215 !!eeprom->reg_chip_select);
216
217 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
218}
219
220#ifdef CONFIG_RT2X00_LIB_DEBUGFS
221#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
222
223static void rt61pci_read_csr(const struct rt2x00_dev *rt2x00dev,
224 const unsigned int word, u32 *data)
225{
226 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
227}
228
229static void rt61pci_write_csr(const struct rt2x00_dev *rt2x00dev,
230 const unsigned int word, u32 data)
231{
232 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
233}
234
235static const struct rt2x00debug rt61pci_rt2x00debug = {
236 .owner = THIS_MODULE,
237 .csr = {
238 .read = rt61pci_read_csr,
239 .write = rt61pci_write_csr,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
242 },
243 .eeprom = {
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_size = sizeof(u16),
247 .word_count = EEPROM_SIZE / sizeof(u16),
248 },
249 .bbp = {
250 .read = rt61pci_bbp_read,
251 .write = rt61pci_bbp_write,
252 .word_size = sizeof(u8),
253 .word_count = BBP_SIZE / sizeof(u8),
254 },
255 .rf = {
256 .read = rt2x00_rf_read,
257 .write = rt61pci_rf_write,
258 .word_size = sizeof(u32),
259 .word_count = RF_SIZE / sizeof(u32),
260 },
261};
262#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
263
264#ifdef CONFIG_RT61PCI_RFKILL
265static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
266{
267 u32 reg;
268
269 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
270 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
271}
81873e9c
ID		 272#else
273#define rt61pci_rfkill_poll NULL
dcf5475b 274#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627
ID		 275
276/*
277 * Configuration handlers.
278 */
4abee4bb 279static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
95ea3627 280{
95ea3627
ID		 281 u32 tmp;
282
4abee4bb 283 tmp = le32_to_cpu(mac[1]);
95ea3627 284 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
4abee4bb 285 mac[1] = cpu_to_le32(tmp);
95ea3627 286
4abee4bb
ID		 287 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
288 (2 * sizeof(__le32)));
95ea3627
ID		 289}
290
4abee4bb 291static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
95ea3627 292{
95ea3627
ID		 293 u32 tmp;
294
4abee4bb 295 tmp = le32_to_cpu(bssid[1]);
95ea3627 296 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
4abee4bb 297 bssid[1] = cpu_to_le32(tmp);
95ea3627 298
4abee4bb
ID		 299 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
300 (2 * sizeof(__le32)));
95ea3627
ID		 301}
302
feb24691
ID		 303static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
304 const int tsf_sync)
95ea3627
ID		 305{
306 u32 reg;
307
308 /*
309 * Clear current synchronisation setup.
310 * For the Beacon base registers we only need to clear
311 * the first byte since that byte contains the VALID and OWNER
312 * bits which (when set to 0) will invalidate the entire beacon.
313 */
314 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
315 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
316 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
317 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
318 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
319
95ea3627
ID		 320 /*
321 * Enable synchronisation.
322 */
323 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
4150c572
JB		 324 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
325 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627 326 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
feb24691 327 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
95ea3627
ID		 328 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
329}
330
5c58ee51
ID		 331static void rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
332 const int short_preamble,
333 const int ack_timeout,
334 const int ack_consume_time)
95ea3627 335{
95ea3627 336 u32 reg;
95ea3627
ID		 337
338 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
5c58ee51 339 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
95ea3627
ID		 340 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
341
342 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 343 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
5c58ee51 344 !!short_preamble);
95ea3627
ID		 345 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
346}
347
348static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 349 const int basic_rate_mask)
95ea3627 350{
5c58ee51 351 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 352}
353
5c58ee51
ID		 354static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
355 struct rf_channel *rf, const int txpower)
95ea3627
ID		 356{
357 u8 r3;
358 u8 r94;
359 u8 smart;
360
361 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
362 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
363
364 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
365 rt2x00_rf(&rt2x00dev->chip, RF2527));
366
367 rt61pci_bbp_read(rt2x00dev, 3, &r3);
368 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
369 rt61pci_bbp_write(rt2x00dev, 3, r3);
370
371 r94 = 6;
372 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
373 r94 += txpower - MAX_TXPOWER;
374 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
375 r94 += txpower;
376 rt61pci_bbp_write(rt2x00dev, 94, r94);
377
378 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
379 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
380 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
381 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
382
383 udelay(200);
384
385 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
386 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
387 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
388 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
389
390 udelay(200);
391
392 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
393 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
394 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
395 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
396
397 msleep(1);
398}
399
95ea3627
ID		 400static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
401 const int txpower)
402{
403 struct rf_channel rf;
404
405 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
406 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
407 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
408 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
409
5c58ee51 410 rt61pci_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 411}
412
413static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 414 struct antenna_setup *ant)
95ea3627
ID		 415{
416 u8 r3;
417 u8 r4;
418 u8 r77;
419
420 rt61pci_bbp_read(rt2x00dev, 3, &r3);
421 rt61pci_bbp_read(rt2x00dev, 4, &r4);
422 rt61pci_bbp_read(rt2x00dev, 77, &r77);
423
424 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
425 !rt2x00_rf(&rt2x00dev->chip, RF5225));
426
addc81bd 427 switch (ant->rx) {
95ea3627
ID		 428 case ANTENNA_HW_DIVERSITY:
429 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
430 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
431 !!(rt2x00dev->curr_hwmode != HWMODE_A));
432 break;
433 case ANTENNA_A:
434 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
435 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
436
437 if (rt2x00dev->curr_hwmode == HWMODE_A)
438 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
439 else
440 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
441 break;
39e75857
ID		 442 case ANTENNA_SW_DIVERSITY:
443 /*
444 * NOTE: We should never come here because rt2x00lib is
445 * supposed to catch this and send us the correct antenna
446 * explicitely. However we are nog going to bug about this.
447 * Instead, just default to antenna B.
448 */
95ea3627
ID		 449 case ANTENNA_B:
450 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
451 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
452
453 if (rt2x00dev->curr_hwmode == HWMODE_A)
454 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
455 else
456 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
457 break;
458 }
459
460 rt61pci_bbp_write(rt2x00dev, 77, r77);
461 rt61pci_bbp_write(rt2x00dev, 3, r3);
462 rt61pci_bbp_write(rt2x00dev, 4, r4);
463}
464
465static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 466 struct antenna_setup *ant)
95ea3627
ID		 467{
468 u8 r3;
469 u8 r4;
470 u8 r77;
471
472 rt61pci_bbp_read(rt2x00dev, 3, &r3);
473 rt61pci_bbp_read(rt2x00dev, 4, &r4);
474 rt61pci_bbp_read(rt2x00dev, 77, &r77);
475
476 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
477 !rt2x00_rf(&rt2x00dev->chip, RF2527));
478 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
479 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
480
addc81bd 481 switch (ant->rx) {
95ea3627
ID		 482 case ANTENNA_HW_DIVERSITY:
483 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
484 break;
485 case ANTENNA_A:
486 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
487 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
488 break;
39e75857
ID		 489 case ANTENNA_SW_DIVERSITY:
490 /*
491 * NOTE: We should never come here because rt2x00lib is
492 * supposed to catch this and send us the correct antenna
493 * explicitely. However we are nog going to bug about this.
494 * Instead, just default to antenna B.
495 */
95ea3627
ID		 496 case ANTENNA_B:
497 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
498 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
499 break;
500 }
501
502 rt61pci_bbp_write(rt2x00dev, 77, r77);
503 rt61pci_bbp_write(rt2x00dev, 3, r3);
504 rt61pci_bbp_write(rt2x00dev, 4, r4);
505}
506
507static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
508 const int p1, const int p2)
509{
510 u32 reg;
511
512 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
513
514 if (p1 != 0xff) {
515 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, !!p1);
516 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
517 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
518 }
519 if (p2 != 0xff) {
520 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
521 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
522 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
523 }
524}
525
526static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 527 struct antenna_setup *ant)
95ea3627
ID		 528{
529 u16 eeprom;
530 u8 r3;
531 u8 r4;
532 u8 r77;
533
534 rt61pci_bbp_read(rt2x00dev, 3, &r3);
535 rt61pci_bbp_read(rt2x00dev, 4, &r4);
536 rt61pci_bbp_read(rt2x00dev, 77, &r77);
537 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
538
539 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
540
541 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
542 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
543 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
544 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 1);
545 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
546 } else if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) {
547 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED) >= 2) {
548 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
549 rt61pci_bbp_write(rt2x00dev, 77, r77);
550 }
551 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
552 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
553 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
554 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
555 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
556 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
557
558 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
559 case 0:
560 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
561 break;
562 case 1:
563 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
564 break;
565 case 2:
566 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
567 break;
568 case 3:
569 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
570 break;
571 }
572 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
573 !rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
574 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
575 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
576
577 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
578 case 0:
579 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
580 rt61pci_bbp_write(rt2x00dev, 77, r77);
581 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
582 break;
583 case 1:
584 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
585 rt61pci_bbp_write(rt2x00dev, 77, r77);
586 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
587 break;
588 case 2:
589 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
590 rt61pci_bbp_write(rt2x00dev, 77, r77);
591 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
592 break;
593 case 3:
594 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
595 rt61pci_bbp_write(rt2x00dev, 77, r77);
596 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
597 break;
598 }
599 }
600
601 rt61pci_bbp_write(rt2x00dev, 3, r3);
602 rt61pci_bbp_write(rt2x00dev, 4, r4);
603}
604
605struct antenna_sel {
606 u8 word;
607 /*
608 * value[0] -> non-LNA
609 * value[1] -> LNA
610 */
611 u8 value[2];
612};
613
614static const struct antenna_sel antenna_sel_a[] = {
615 { 96, { 0x58, 0x78 } },
616 { 104, { 0x38, 0x48 } },
617 { 75, { 0xfe, 0x80 } },
618 { 86, { 0xfe, 0x80 } },
619 { 88, { 0xfe, 0x80 } },
620 { 35, { 0x60, 0x60 } },
621 { 97, { 0x58, 0x58 } },
622 { 98, { 0x58, 0x58 } },
623};
624
625static const struct antenna_sel antenna_sel_bg[] = {
626 { 96, { 0x48, 0x68 } },
627 { 104, { 0x2c, 0x3c } },
628 { 75, { 0xfe, 0x80 } },
629 { 86, { 0xfe, 0x80 } },
630 { 88, { 0xfe, 0x80 } },
631 { 35, { 0x50, 0x50 } },
632 { 97, { 0x48, 0x48 } },
633 { 98, { 0x48, 0x48 } },
634};
635
636static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 637 struct antenna_setup *ant)
95ea3627
ID		 638{
639 const struct antenna_sel *sel;
640 unsigned int lna;
641 unsigned int i;
642 u32 reg;
643
644 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
645
646 if (rt2x00dev->curr_hwmode == HWMODE_A) {
647 sel = antenna_sel_a;
648 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
649
650 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 0);
651 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 1);
652 } else {
653 sel = antenna_sel_bg;
654 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
655
656 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 1);
657 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 0);
658 }
659
660 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
661 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
662
663 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
664
665 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
666 rt2x00_rf(&rt2x00dev->chip, RF5325))
addc81bd 667 rt61pci_config_antenna_5x(rt2x00dev, ant);
95ea3627 668 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 669 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 670 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
671 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 672 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 673 else
addc81bd 674 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 675 }
676}
677
678static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 679 struct rt2x00lib_conf *libconf)
95ea3627
ID		 680{
681 u32 reg;
682
683 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 684 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 685 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
686
687 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 688 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 689 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 690 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 691 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
692
693 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
694 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
695 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
696
697 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
698 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
699 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
700
701 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 702 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
703 libconf->conf->beacon_int * 16);
95ea3627
ID		 704 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
705}
706
707static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
708 const unsigned int flags,
5c58ee51 709 struct rt2x00lib_conf *libconf)
95ea3627 710{
95ea3627 711 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 712 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 713 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 714 rt61pci_config_channel(rt2x00dev, &libconf->rf,
715 libconf->conf->power_level);
95ea3627 716 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 717 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 718 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 719 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 720 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 721 rt61pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 722}
723
724/*
725 * LED functions.
726 */
727static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
728{
729 u32 reg;
730 u16 led_reg;
731 u8 arg0;
732 u8 arg1;
733
734 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
735 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
736 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
737 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
738
739 led_reg = rt2x00dev->led_reg;
740 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 1);
741 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
742 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 1);
743 else
744 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 1);
745
746 arg0 = led_reg & 0xff;
747 arg1 = (led_reg >> 8) & 0xff;
748
749 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
750}
751
752static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
753{
754 u16 led_reg;
755 u8 arg0;
756 u8 arg1;
757
758 led_reg = rt2x00dev->led_reg;
759 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
760 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
761 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
762
763 arg0 = led_reg & 0xff;
764 arg1 = (led_reg >> 8) & 0xff;
765
766 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
767}
768
769static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
770{
771 u8 led;
772
773 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
774 return;
775
776 /*
777 * Led handling requires a positive value for the rssi,
778 * to do that correctly we need to add the correction.
779 */
780 rssi += rt2x00dev->rssi_offset;
781
782 if (rssi <= 30)
783 led = 0;
784 else if (rssi <= 39)
785 led = 1;
786 else if (rssi <= 49)
787 led = 2;
788 else if (rssi <= 53)
789 led = 3;
790 else if (rssi <= 63)
791 led = 4;
792 else
793 led = 5;
794
795 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
796}
797
798/*
799 * Link tuning
800 */
ebcf26da
ID		 801static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
802 struct link_qual *qual)
95ea3627
ID		 803{
804 u32 reg;
805
806 /*
807 * Update FCS error count from register.
808 */
809 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 810 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 811
812 /*
813 * Update False CCA count from register.
814 */
815 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 816 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 817}
818
819static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
820{
821 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
822 rt2x00dev->link.vgc_level = 0x20;
823}
824
825static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
826{
827 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
828 u8 r17;
829 u8 up_bound;
830 u8 low_bound;
831
832 /*
833 * Update Led strength
834 */
835 rt61pci_activity_led(rt2x00dev, rssi);
836
837 rt61pci_bbp_read(rt2x00dev, 17, &r17);
838
839 /*
840 * Determine r17 bounds.
841 */
842 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
843 low_bound = 0x28;
844 up_bound = 0x48;
845 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
846 low_bound += 0x10;
847 up_bound += 0x10;
848 }
849 } else {
850 low_bound = 0x20;
851 up_bound = 0x40;
852 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
853 low_bound += 0x10;
854 up_bound += 0x10;
855 }
856 }
857
858 /*
859 * Special big-R17 for very short distance
860 */
861 if (rssi >= -35) {
862 if (r17 != 0x60)
863 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
864 return;
865 }
866
867 /*
868 * Special big-R17 for short distance
869 */
870 if (rssi >= -58) {
871 if (r17 != up_bound)
872 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
873 return;
874 }
875
876 /*
877 * Special big-R17 for middle-short distance
878 */
879 if (rssi >= -66) {
880 low_bound += 0x10;
881 if (r17 != low_bound)
882 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
883 return;
884 }
885
886 /*
887 * Special mid-R17 for middle distance
888 */
889 if (rssi >= -74) {
890 low_bound += 0x08;
891 if (r17 != low_bound)
892 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
893 return;
894 }
895
896 /*
897 * Special case: Change up_bound based on the rssi.
898 * Lower up_bound when rssi is weaker then -74 dBm.
899 */
900 up_bound -= 2 * (-74 - rssi);
901 if (low_bound > up_bound)
902 up_bound = low_bound;
903
904 if (r17 > up_bound) {
905 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
906 return;
907 }
908
909 /*
910 * r17 does not yet exceed upper limit, continue and base
911 * the r17 tuning on the false CCA count.
912 */
ebcf26da 913 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 914 if (++r17 > up_bound)
915 r17 = up_bound;
916 rt61pci_bbp_write(rt2x00dev, 17, r17);
ebcf26da 917 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 918 if (--r17 < low_bound)
919 r17 = low_bound;
920 rt61pci_bbp_write(rt2x00dev, 17, r17);
921 }
922}
923
924/*
925 * Firmware name function.
926 */
927static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
928{
929 char *fw_name;
930
931 switch (rt2x00dev->chip.rt) {
932 case RT2561:
933 fw_name = FIRMWARE_RT2561;
934 break;
935 case RT2561s:
936 fw_name = FIRMWARE_RT2561s;
937 break;
938 case RT2661:
939 fw_name = FIRMWARE_RT2661;
940 break;
941 default:
942 fw_name = NULL;
943 break;
944 }
945
946 return fw_name;
947}
948
949/*
950 * Initialization functions.
951 */
952static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
953 const size_t len)
954{
955 int i;
956 u32 reg;
957
958 /*
959 * Wait for stable hardware.
960 */
961 for (i = 0; i < 100; i++) {
962 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
963 if (reg)
964 break;
965 msleep(1);
966 }
967
968 if (!reg) {
969 ERROR(rt2x00dev, "Unstable hardware.\n");
970 return -EBUSY;
971 }
972
973 /*
974 * Prepare MCU and mailbox for firmware loading.
975 */
976 reg = 0;
977 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
978 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
979 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
980 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
981 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
982
983 /*
984 * Write firmware to device.
985 */
986 reg = 0;
987 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
988 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
989 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
990
991 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
992 data, len);
993
994 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
995 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
996
997 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
998 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
999
1000 for (i = 0; i < 100; i++) {
1001 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1002 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1003 break;
1004 msleep(1);
1005 }
1006
1007 if (i == 100) {
1008 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1009 return -EBUSY;
1010 }
1011
1012 /*
1013 * Reset MAC and BBP registers.
1014 */
1015 reg = 0;
1016 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1017 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1018 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1019
1020 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1021 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1022 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1023 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1024
1025 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1026 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1027 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1028
1029 return 0;
1030}
1031
1032static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
1033{
1034 struct data_ring *ring = rt2x00dev->rx;
1035 struct data_desc *rxd;
1036 unsigned int i;
1037 u32 word;
1038
1039 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1040
1041 for (i = 0; i < ring->stats.limit; i++) {
1042 rxd = ring->entry[i].priv;
1043
1044 rt2x00_desc_read(rxd, 5, &word);
1045 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1046 ring->entry[i].data_dma);
1047 rt2x00_desc_write(rxd, 5, word);
1048
1049 rt2x00_desc_read(rxd, 0, &word);
1050 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1051 rt2x00_desc_write(rxd, 0, word);
1052 }
1053
1054 rt2x00_ring_index_clear(rt2x00dev->rx);
1055}
1056
1057static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
1058{
1059 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1060 struct data_desc *txd;
1061 unsigned int i;
1062 u32 word;
1063
1064 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1065
1066 for (i = 0; i < ring->stats.limit; i++) {
1067 txd = ring->entry[i].priv;
1068
1069 rt2x00_desc_read(txd, 1, &word);
1070 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1071 rt2x00_desc_write(txd, 1, word);
1072
1073 rt2x00_desc_read(txd, 5, &word);
1074 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
1075 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
1076 rt2x00_desc_write(txd, 5, word);
1077
1078 rt2x00_desc_read(txd, 6, &word);
1079 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1080 ring->entry[i].data_dma);
1081 rt2x00_desc_write(txd, 6, word);
1082
1083 rt2x00_desc_read(txd, 0, &word);
1084 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1085 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1086 rt2x00_desc_write(txd, 0, word);
1087 }
1088
1089 rt2x00_ring_index_clear(ring);
1090}
1091
1092static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1093{
1094 u32 reg;
1095
1096 /*
1097 * Initialize rings.
1098 */
1099 rt61pci_init_rxring(rt2x00dev);
1100 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1101 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1102 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
1103 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
1104 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
1105
1106 /*
1107 * Initialize registers.
1108 */
1109 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1110 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1111 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
1112 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1113 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
1114 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1115 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
1116 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1117 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
1118 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1119
1120 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1121 rt2x00_set_field32(&reg, TX_RING_CSR1_MGMT_RING_SIZE,
1122 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1123 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1124 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
1125 4);
1126 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1127
1128 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1129 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1130 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1131 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1132
1133 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1134 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1135 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1136 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1137
1138 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1139 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1140 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1141 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1142
1143 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1144 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1145 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1146 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1147
1148 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, &reg);
1149 rt2x00_set_field32(&reg, MGMT_BASE_CSR_RING_REGISTER,
1150 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1151 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1152
1153 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1154 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE,
1155 rt2x00dev->rx->stats.limit);
1156 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1157 rt2x00dev->rx->desc_size / 4);
1158 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1159 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1160
1161 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1162 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1163 rt2x00dev->rx->data_dma);
1164 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1165
1166 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1167 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1168 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1169 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1170 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1171 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_MGMT, 0);
1172 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1173
1174 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1175 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1176 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1177 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1178 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1179 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
1180 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1181
1182 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1183 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1184 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1185
1186 return 0;
1187}
1188
1189static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1190{
1191 u32 reg;
1192
1193 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1194 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1195 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1196 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1197 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1198
1199 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1200 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1201 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1202 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1203 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1204 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1205 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1206 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1207 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1208 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1209
1210 /*
1211 * CCK TXD BBP registers
1212 */
1213 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1214 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1215 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1216 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1217 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1218 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1219 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1220 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1221 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1222 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1223
1224 /*
1225 * OFDM TXD BBP registers
1226 */
1227 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1228 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1229 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1230 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1231 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1232 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1233 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1234 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1235
1236 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1237 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1238 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1239 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1240 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1241 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1242
1243 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1244 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1245 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1246 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1247 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1248 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1249
1250 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1251
1252 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1253
1254 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1255 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1256 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1257
1258 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1259
1260 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1261 return -EBUSY;
1262
1263 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1264
1265 /*
1266 * Invalidate all Shared Keys (SEC_CSR0),
1267 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1268 */
1269 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1270 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1271 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1272
1273 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1274 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1275 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1276 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1277
1278 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1279
1280 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1281
1282 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1283
1284 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1285 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1286 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1287 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1288
1289 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1290 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1291 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1292 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1293
1294 /*
1295 * We must clear the error counters.
1296 * These registers are cleared on read,
1297 * so we may pass a useless variable to store the value.
1298 */
1299 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1300 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1301 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1302
1303 /*
1304 * Reset MAC and BBP registers.
1305 */
1306 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1307 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1308 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1309 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1310
1311 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1312 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1313 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1314 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1315
1316 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1317 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1318 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1319
1320 return 0;
1321}
1322
1323static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1324{
1325 unsigned int i;
1326 u16 eeprom;
1327 u8 reg_id;
1328 u8 value;
1329
1330 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1331 rt61pci_bbp_read(rt2x00dev, 0, &value);
1332 if ((value != 0xff) && (value != 0x00))
1333 goto continue_csr_init;
1334 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1335 udelay(REGISTER_BUSY_DELAY);
1336 }
1337
1338 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1339 return -EACCES;
1340
1341continue_csr_init:
1342 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1343 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1344 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1345 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1346 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1347 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1348 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1349 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1350 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1351 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1352 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1353 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1354 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1355 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1356 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1357 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1358 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1359 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1360 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1361 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1362 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1363 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1364 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1365 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1366
1367 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1368 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1369 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1370
1371 if (eeprom != 0xffff && eeprom != 0x0000) {
1372 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1373 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1374 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1375 reg_id, value);
1376 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1377 }
1378 }
1379 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1380
1381 return 0;
1382}
1383
1384/*
1385 * Device state switch handlers.
1386 */
1387static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1388 enum dev_state state)
1389{
1390 u32 reg;
1391
1392 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1393 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1394 state == STATE_RADIO_RX_OFF);
1395 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1396}
1397
1398static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1399 enum dev_state state)
1400{
1401 int mask = (state == STATE_RADIO_IRQ_OFF);
1402 u32 reg;
1403
1404 /*
1405 * When interrupts are being enabled, the interrupt registers
1406 * should clear the register to assure a clean state.
1407 */
1408 if (state == STATE_RADIO_IRQ_ON) {
1409 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1410 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1411
1412 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1413 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1414 }
1415
1416 /*
1417 * Only toggle the interrupts bits we are going to use.
1418 * Non-checked interrupt bits are disabled by default.
1419 */
1420 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1421 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1422 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1423 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1424 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1425 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1426
1427 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1428 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1429 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1430 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1431 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1432 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1433 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1434 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1435 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1436 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1437}
1438
1439static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1440{
1441 u32 reg;
1442
1443 /*
1444 * Initialize all registers.
1445 */
1446 if (rt61pci_init_rings(rt2x00dev) ||
1447 rt61pci_init_registers(rt2x00dev) ||
1448 rt61pci_init_bbp(rt2x00dev)) {
1449 ERROR(rt2x00dev, "Register initialization failed.\n");
1450 return -EIO;
1451 }
1452
1453 /*
1454 * Enable interrupts.
1455 */
1456 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1457
1458 /*
1459 * Enable RX.
1460 */
1461 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1462 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1463 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1464
1465 /*
1466 * Enable LED
1467 */
1468 rt61pci_enable_led(rt2x00dev);
1469
1470 return 0;
1471}
1472
1473static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1474{
1475 u32 reg;
1476
1477 /*
1478 * Disable LED
1479 */
1480 rt61pci_disable_led(rt2x00dev);
1481
1482 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1483
1484 /*
1485 * Disable synchronisation.
1486 */
1487 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1488
1489 /*
1490 * Cancel RX and TX.
1491 */
1492 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1493 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1494 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1495 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1496 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1497 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1498 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1499
1500 /*
1501 * Disable interrupts.
1502 */
1503 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1504}
1505
1506static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1507{
1508 u32 reg;
1509 unsigned int i;
1510 char put_to_sleep;
1511 char current_state;
1512
1513 put_to_sleep = (state != STATE_AWAKE);
1514
1515 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1516 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1517 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1518 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1519
1520 /*
1521 * Device is not guaranteed to be in the requested state yet.
1522 * We must wait until the register indicates that the
1523 * device has entered the correct state.
1524 */
1525 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1526 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1527 current_state =
1528 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1529 if (current_state == !put_to_sleep)
1530 return 0;
1531 msleep(10);
1532 }
1533
1534 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1535 "current device state %d.\n", !put_to_sleep, current_state);
1536
1537 return -EBUSY;
1538}
1539
1540static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1541 enum dev_state state)
1542{
1543 int retval = 0;
1544
1545 switch (state) {
1546 case STATE_RADIO_ON:
1547 retval = rt61pci_enable_radio(rt2x00dev);
1548 break;
1549 case STATE_RADIO_OFF:
1550 rt61pci_disable_radio(rt2x00dev);
1551 break;
1552 case STATE_RADIO_RX_ON:
1553 case STATE_RADIO_RX_OFF:
1554 rt61pci_toggle_rx(rt2x00dev, state);
1555 break;
1556 case STATE_DEEP_SLEEP:
1557 case STATE_SLEEP:
1558 case STATE_STANDBY:
1559 case STATE_AWAKE:
1560 retval = rt61pci_set_state(rt2x00dev, state);
1561 break;
1562 default:
1563 retval = -ENOTSUPP;
1564 break;
1565 }
1566
1567 return retval;
1568}
1569
1570/*
1571 * TX descriptor initialization
1572 */
1573static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1574 struct data_desc *txd,
4150c572 1575 struct txdata_entry_desc *desc,
95ea3627
ID		 1576 struct ieee80211_hdr *ieee80211hdr,
1577 unsigned int length,
1578 struct ieee80211_tx_control *control)
1579{
1580 u32 word;
1581
1582 /*
1583 * Start writing the descriptor words.
1584 */
1585 rt2x00_desc_read(txd, 1, &word);
1586 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1587 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1588 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1589 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1590 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1591 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1592 rt2x00_desc_write(txd, 1, word);
1593
1594 rt2x00_desc_read(txd, 2, &word);
1595 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1596 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1597 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1598 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1599 rt2x00_desc_write(txd, 2, word);
1600
1601 rt2x00_desc_read(txd, 5, &word);
1602 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1603 TXPOWER_TO_DEV(control->power_level));
1604 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1605 rt2x00_desc_write(txd, 5, word);
1606
1607 rt2x00_desc_read(txd, 11, &word);
1608 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
1609 rt2x00_desc_write(txd, 11, word);
1610
1611 rt2x00_desc_read(txd, 0, &word);
1612 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1613 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1614 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1615 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1616 rt2x00_set_field32(&word, TXD_W0_ACK,
1617 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1618 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1619 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1620 rt2x00_set_field32(&word, TXD_W0_OFDM,
1621 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1622 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1623 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1624 !!(control->flags &
1625 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1626 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1627 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1628 rt2x00_set_field32(&word, TXD_W0_BURST,
1629 test_bit(ENTRY_TXD_BURST, &desc->flags));
1630 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1631 rt2x00_desc_write(txd, 0, word);
1632}
1633
1634/*
1635 * TX data initialization
1636 */
1637static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1638 unsigned int queue)
1639{
1640 u32 reg;
1641
1642 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1643 /*
1644 * For Wi-Fi faily generated beacons between participating
1645 * stations. Set TBTT phase adaptive adjustment step to 8us.
1646 */
1647 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1648
1649 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1650 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1651 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1652 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1653 }
1654 return;
1655 }
1656
1657 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1658 if (queue == IEEE80211_TX_QUEUE_DATA0)
1659 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1660 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1661 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1662 else if (queue == IEEE80211_TX_QUEUE_DATA2)
1663 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1664 else if (queue == IEEE80211_TX_QUEUE_DATA3)
1665 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1666 else if (queue == IEEE80211_TX_QUEUE_DATA4)
1667 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_MGMT, 1);
1668 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1669}
1670
1671/*
1672 * RX control handlers
1673 */
1674static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1675{
1676 u16 eeprom;
1677 u8 offset;
1678 u8 lna;
1679
1680 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1681 switch (lna) {
1682 case 3:
1683 offset = 90;
1684 break;
1685 case 2:
1686 offset = 74;
1687 break;
1688 case 1:
1689 offset = 64;
1690 break;
1691 default:
1692 return 0;
1693 }
1694
1695 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1696 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1697 offset += 14;
1698
1699 if (lna == 3 || lna == 2)
1700 offset += 10;
1701
1702 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1703 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1704 } else {
1705 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1706 offset += 14;
1707
1708 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1709 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1710 }
1711
1712 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1713}
1714
4150c572
JB		 1715static void rt61pci_fill_rxdone(struct data_entry *entry,
1716 struct rxdata_entry_desc *desc)
95ea3627
ID		 1717{
1718 struct data_desc *rxd = entry->priv;
1719 u32 word0;
1720 u32 word1;
1721
1722 rt2x00_desc_read(rxd, 0, &word0);
1723 rt2x00_desc_read(rxd, 1, &word1);
1724
4150c572
JB		 1725 desc->flags = 0;
1726 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1727 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1728
1729 /*
1730 * Obtain the status about this packet.
1731 */
4150c572
JB		 1732 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1733 desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
1734 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1735 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
95ea3627 1736
4150c572 1737 return;
95ea3627
ID		 1738}
1739
1740/*
1741 * Interrupt functions.
1742 */
1743static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1744{
1745 struct data_ring *ring;
1746 struct data_entry *entry;
62bc060b 1747 struct data_entry *entry_done;
95ea3627
ID		 1748 struct data_desc *txd;
1749 u32 word;
1750 u32 reg;
1751 u32 old_reg;
1752 int type;
1753 int index;
1754 int tx_status;
1755 int retry;
1756
1757 /*
1758 * During each loop we will compare the freshly read
1759 * STA_CSR4 register value with the value read from
1760 * the previous loop. If the 2 values are equal then
1761 * we should stop processing because the chance it
1762 * quite big that the device has been unplugged and
1763 * we risk going into an endless loop.
1764 */
1765 old_reg = 0;
1766
1767 while (1) {
1768 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1769 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1770 break;
1771
1772 if (old_reg == reg)
1773 break;
1774 old_reg = reg;
1775
1776 /*
1777 * Skip this entry when it contains an invalid
1778 * ring identication number.
1779 */
1780 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1781 ring = rt2x00lib_get_ring(rt2x00dev, type);
1782 if (unlikely(!ring))
1783 continue;
1784
1785 /*
1786 * Skip this entry when it contains an invalid
1787 * index number.
1788 */
1789 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1790 if (unlikely(index >= ring->stats.limit))
1791 continue;
1792
1793 entry = &ring->entry[index];
1794 txd = entry->priv;
1795 rt2x00_desc_read(txd, 0, &word);
1796
1797 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1798 !rt2x00_get_field32(word, TXD_W0_VALID))
1799 return;
1800
62bc060b
MN		 1801 entry_done = rt2x00_get_data_entry_done(ring);
1802 while (entry != entry_done) {
1803 /* Catch up. Just report any entries we missed as
1804 * failed. */
1805 WARNING(rt2x00dev,
1806 "TX status report missed for entry %p\n",
1807 entry_done);
1808 rt2x00lib_txdone(entry_done, TX_FAIL_OTHER, 0);
1809 entry_done = rt2x00_get_data_entry_done(ring);
1810 }
1811
95ea3627
ID		 1812 /*
1813 * Obtain the status about this packet.
1814 */
1815 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1816 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1817
1818 rt2x00lib_txdone(entry, tx_status, retry);
1819
1820 /*
1821 * Make this entry available for reuse.
1822 */
1823 entry->flags = 0;
1824 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1825 rt2x00_desc_write(txd, 0, word);
1826 rt2x00_ring_index_done_inc(entry->ring);
1827
1828 /*
1829 * If the data ring was full before the txdone handler
1830 * we must make sure the packet queue in the mac80211 stack
1831 * is reenabled when the txdone handler has finished.
1832 */
1833 if (!rt2x00_ring_full(ring))
1834 ieee80211_wake_queue(rt2x00dev->hw,
1835 entry->tx_status.control.queue);
1836 }
1837}
1838
1839static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1840{
1841 struct rt2x00_dev *rt2x00dev = dev_instance;
1842 u32 reg_mcu;
1843 u32 reg;
1844
1845 /*
1846 * Get the interrupt sources & saved to local variable.
1847 * Write register value back to clear pending interrupts.
1848 */
1849 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1850 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1851
1852 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1853 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1854
1855 if (!reg && !reg_mcu)
1856 return IRQ_NONE;
1857
1858 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1859 return IRQ_HANDLED;
1860
1861 /*
1862 * Handle interrupts, walk through all bits
1863 * and run the tasks, the bits are checked in order of
1864 * priority.
1865 */
1866
1867 /*
1868 * 1 - Rx ring done interrupt.
1869 */
1870 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1871 rt2x00pci_rxdone(rt2x00dev);
1872
1873 /*
1874 * 2 - Tx ring done interrupt.
1875 */
1876 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1877 rt61pci_txdone(rt2x00dev);
1878
1879 /*
1880 * 3 - Handle MCU command done.
1881 */
1882 if (reg_mcu)
1883 rt2x00pci_register_write(rt2x00dev,
1884 M2H_CMD_DONE_CSR, 0xffffffff);
1885
1886 return IRQ_HANDLED;
1887}
1888
1889/*
1890 * Device probe functions.
1891 */
1892static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1893{
1894 struct eeprom_93cx6 eeprom;
1895 u32 reg;
1896 u16 word;
1897 u8 *mac;
1898 s8 value;
1899
1900 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1901
1902 eeprom.data = rt2x00dev;
1903 eeprom.register_read = rt61pci_eepromregister_read;
1904 eeprom.register_write = rt61pci_eepromregister_write;
1905 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1906 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1907 eeprom.reg_data_in = 0;
1908 eeprom.reg_data_out = 0;
1909 eeprom.reg_data_clock = 0;
1910 eeprom.reg_chip_select = 0;
1911
1912 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1913 EEPROM_SIZE / sizeof(u16));
1914
1915 /*
1916 * Start validation of the data that has been read.
1917 */
1918 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1919 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1920 DECLARE_MAC_BUF(macbuf);
1921
95ea3627 1922 random_ether_addr(mac);
0795af57 1923 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1924 }
1925
1926 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1927 if (word == 0xffff) {
1928 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1929 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1930 ANTENNA_B);
1931 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1932 ANTENNA_B);
95ea3627
ID		 1933 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1934 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1935 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1936 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1937 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1938 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1939 }
1940
1941 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1942 if (word == 0xffff) {
1943 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1944 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1945 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1946 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1947 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1948 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1949 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1950 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1951 }
1952
1953 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1954 if (word == 0xffff) {
1955 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1956 LED_MODE_DEFAULT);
1957 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1958 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1959 }
1960
1961 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1962 if (word == 0xffff) {
1963 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1964 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1965 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1966 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1967 }
1968
1969 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1970 if (word == 0xffff) {
1971 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1972 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1973 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1974 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1975 } else {
1976 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1977 if (value < -10 || value > 10)
1978 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1979 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1980 if (value < -10 || value > 10)
1981 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1982 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1983 }
1984
1985 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1986 if (word == 0xffff) {
1987 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1988 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1989 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1990 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1991 } else {
1992 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1993 if (value < -10 || value > 10)
1994 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1995 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1996 if (value < -10 || value > 10)
1997 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1998 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1999 }
2000
2001 return 0;
2002}
2003
2004static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2005{
2006 u32 reg;
2007 u16 value;
2008 u16 eeprom;
2009 u16 device;
2010
2011 /*
2012 * Read EEPROM word for configuration.
2013 */
2014 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2015
2016 /*
2017 * Identify RF chipset.
2018 * To determine the RT chip we have to read the
2019 * PCI header of the device.
2020 */
2021 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
2022 PCI_CONFIG_HEADER_DEVICE, &device);
2023 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2024 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2025 rt2x00_set_chip(rt2x00dev, device, value, reg);
2026
2027 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2028 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2029 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2030 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2031 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2032 return -ENODEV;
2033 }
2034
2035 /*
2036 * Identify default antenna configuration.
2037 */
addc81bd 2038 rt2x00dev->default_ant.tx =
95ea3627 2039 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 2040 rt2x00dev->default_ant.rx =
95ea3627
ID		 2041 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2042
2043 /*
2044 * Read the Frame type.
2045 */
2046 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2047 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2048
2049 /*
2050 * Determine number of antenna's.
2051 */
2052 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2053 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2054
2055 /*
2056 * Detect if this device has an hardware controlled radio.
2057 */
81873e9c 2058#ifdef CONFIG_RT61PCI_RFKILL
95ea3627 2059 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 2060 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 2061#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627
ID		 2062
2063 /*
2064 * Read frequency offset and RF programming sequence.
2065 */
2066 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2067 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2068 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2069
2070 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2071
2072 /*
2073 * Read external LNA informations.
2074 */
2075 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2076
2077 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2078 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2079 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2080 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2081
2082 /*
2083 * Store led settings, for correct led behaviour.
2084 * If the eeprom value is invalid,
2085 * switch to default led mode.
2086 */
2087 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2088
2089 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2090
2091 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2092 rt2x00dev->led_mode);
2093 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2094 rt2x00_get_field16(eeprom,
2095 EEPROM_LED_POLARITY_GPIO_0));
2096 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2097 rt2x00_get_field16(eeprom,
2098 EEPROM_LED_POLARITY_GPIO_1));
2099 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2100 rt2x00_get_field16(eeprom,
2101 EEPROM_LED_POLARITY_GPIO_2));
2102 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2103 rt2x00_get_field16(eeprom,
2104 EEPROM_LED_POLARITY_GPIO_3));
2105 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2106 rt2x00_get_field16(eeprom,
2107 EEPROM_LED_POLARITY_GPIO_4));
2108 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2109 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2110 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2111 rt2x00_get_field16(eeprom,
2112 EEPROM_LED_POLARITY_RDY_G));
2113 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2114 rt2x00_get_field16(eeprom,
2115 EEPROM_LED_POLARITY_RDY_A));
2116
2117 return 0;
2118}
2119
2120/*
2121 * RF value list for RF5225 & RF5325
2122 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2123 */
2124static const struct rf_channel rf_vals_noseq[] = {
2125 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2126 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2127 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2128 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2129 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2130 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2131 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2132 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2133 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2134 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2135 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2136 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2137 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2138 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2139
2140 /* 802.11 UNI / HyperLan 2 */
2141 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2142 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2143 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2144 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2145 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2146 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2147 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2148 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2149
2150 /* 802.11 HyperLan 2 */
2151 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2152 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2153 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2154 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2155 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2156 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2157 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2158 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2159 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2160 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2161
2162 /* 802.11 UNII */
2163 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2164 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2165 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2166 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2167 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2168 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2169
2170 /* MMAC(Japan)J52 ch 34,38,42,46 */
2171 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2172 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2173 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2174 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2175};
2176
2177/*
2178 * RF value list for RF5225 & RF5325
2179 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2180 */
2181static const struct rf_channel rf_vals_seq[] = {
2182 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2183 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2184 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2185 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2186 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2187 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2188 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2189 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2190 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2191 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2192 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2193 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2194 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2195 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2196
2197 /* 802.11 UNI / HyperLan 2 */
2198 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2199 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2200 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2201 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2202 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2203 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2204 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2205 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2206
2207 /* 802.11 HyperLan 2 */
2208 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2209 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2210 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2211 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2212 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2213 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2214 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2215 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2216 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2217 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2218
2219 /* 802.11 UNII */
2220 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2221 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2222 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2223 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2224 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2225 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2226
2227 /* MMAC(Japan)J52 ch 34,38,42,46 */
2228 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2229 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2230 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2231 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2232};
2233
2234static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2235{
2236 struct hw_mode_spec *spec = &rt2x00dev->spec;
2237 u8 *txpower;
2238 unsigned int i;
2239
2240 /*
2241 * Initialize all hw fields.
2242 */
2243 rt2x00dev->hw->flags =
2244 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 2245 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 2246 rt2x00dev->hw->extra_tx_headroom = 0;
2247 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2248 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2249 rt2x00dev->hw->queues = 5;
2250
2251 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2252 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2253 rt2x00_eeprom_addr(rt2x00dev,
2254 EEPROM_MAC_ADDR_0));
2255
2256 /*
2257 * Convert tx_power array in eeprom.
2258 */
2259 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2260 for (i = 0; i < 14; i++)
2261 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2262
2263 /*
2264 * Initialize hw_mode information.
2265 */
2266 spec->num_modes = 2;
2267 spec->num_rates = 12;
2268 spec->tx_power_a = NULL;
2269 spec->tx_power_bg = txpower;
2270 spec->tx_power_default = DEFAULT_TXPOWER;
2271
2272 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2273 spec->num_channels = 14;
2274 spec->channels = rf_vals_noseq;
2275 } else {
2276 spec->num_channels = 14;
2277 spec->channels = rf_vals_seq;
2278 }
2279
2280 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2281 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2282 spec->num_modes = 3;
2283 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2284
2285 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2286 for (i = 0; i < 14; i++)
2287 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2288
2289 spec->tx_power_a = txpower;
2290 }
2291}
2292
2293static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2294{
2295 int retval;
2296
2297 /*
2298 * Allocate eeprom data.
2299 */
2300 retval = rt61pci_validate_eeprom(rt2x00dev);
2301 if (retval)
2302 return retval;
2303
2304 retval = rt61pci_init_eeprom(rt2x00dev);
2305 if (retval)
2306 return retval;
2307
2308 /*
2309 * Initialize hw specifications.
2310 */
2311 rt61pci_probe_hw_mode(rt2x00dev);
2312
2313 /*
2314 * This device requires firmware
2315 */
066cb637 2316 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
95ea3627
ID		 2317
2318 /*
2319 * Set the rssi offset.
2320 */
2321 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2322
2323 return 0;
2324}
2325
2326/*
2327 * IEEE80211 stack callback functions.
2328 */
4150c572
JB		 2329static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2330 unsigned int changed_flags,
2331 unsigned int *total_flags,
2332 int mc_count,
2333 struct dev_addr_list *mc_list)
2334{
2335 struct rt2x00_dev *rt2x00dev = hw->priv;
2336 struct interface *intf = &rt2x00dev->interface;
2337 u32 reg;
2338
2339 /*
2340 * Mask off any flags we are going to ignore from
2341 * the total_flags field.
2342 */
2343 *total_flags &=
2344 FIF_ALLMULTI |
2345 FIF_FCSFAIL |
2346 FIF_PLCPFAIL |
2347 FIF_CONTROL |
2348 FIF_OTHER_BSS |
2349 FIF_PROMISC_IN_BSS;
2350
2351 /*
2352 * Apply some rules to the filters:
2353 * - Some filters imply different filters to be set.
2354 * - Some things we can't filter out at all.
2355 * - Some filters are set based on interface type.
2356 */
2357 if (mc_count)
2358 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 2359 if (*total_flags & FIF_OTHER_BSS ||
2360 *total_flags & FIF_PROMISC_IN_BSS)
4150c572
JB		 2361 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2362 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
2363 *total_flags |= FIF_PROMISC_IN_BSS;
2364
2365 /*
2366 * Check if there is any work left for us.
2367 */
2368 if (intf->filter == *total_flags)
2369 return;
2370 intf->filter = *total_flags;
2371
2372 /*
2373 * Start configuration steps.
2374 * Note that the version error will always be dropped
2375 * and broadcast frames will always be accepted since
2376 * there is no filter for it at this time.
2377 */
2378 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2379 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2380 !(*total_flags & FIF_FCSFAIL));
2381 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2382 !(*total_flags & FIF_PLCPFAIL));
2383 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2384 !(*total_flags & FIF_CONTROL));
2385 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2386 !(*total_flags & FIF_PROMISC_IN_BSS));
2387 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2388 !(*total_flags & FIF_PROMISC_IN_BSS));
2389 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2390 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2391 !(*total_flags & FIF_ALLMULTI));
2392 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
2393 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
2394 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2395}
2396
95ea3627
ID		 2397static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2398 u32 short_retry, u32 long_retry)
2399{
2400 struct rt2x00_dev *rt2x00dev = hw->priv;
2401 u32 reg;
2402
2403 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2404 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2405 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2406 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2407
2408 return 0;
2409}
2410
2411static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2412{
2413 struct rt2x00_dev *rt2x00dev = hw->priv;
2414 u64 tsf;
2415 u32 reg;
2416
2417 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2418 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2419 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2420 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2421
2422 return tsf;
2423}
2424
2425static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2426{
2427 struct rt2x00_dev *rt2x00dev = hw->priv;
2428
2429 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2430 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2431}
2432
24845910 2433static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
95ea3627
ID		 2434 struct ieee80211_tx_control *control)
2435{
2436 struct rt2x00_dev *rt2x00dev = hw->priv;
2437
2438 /*
2439 * Just in case the ieee80211 doesn't set this,
2440 * but we need this queue set for the descriptor
2441 * initialization.
2442 */
2443 control->queue = IEEE80211_TX_QUEUE_BEACON;
2444
2445 /*
2446 * We need to append the descriptor in front of the
2447 * beacon frame.
2448 */
2449 if (skb_headroom(skb) < TXD_DESC_SIZE) {
2450 if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
2451 dev_kfree_skb(skb);
2452 return -ENOMEM;
2453 }
2454 }
2455
2456 /*
2457 * First we create the beacon.
2458 */
2459 skb_push(skb, TXD_DESC_SIZE);
c22eb87b
ID		 2460 memset(skb->data, 0, TXD_DESC_SIZE);
2461
95ea3627
ID		 2462 rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
2463 (struct ieee80211_hdr *)(skb->data +
2464 TXD_DESC_SIZE),
2465 skb->len - TXD_DESC_SIZE, control);
2466
2467 /*
2468 * Write entire beacon with descriptor to register,
2469 * and kick the beacon generator.
2470 */
9ee8f57e
ID		 2471 rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0,
2472 skb->data, skb->len);
95ea3627
ID		 2473 rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2474
2475 return 0;
2476}
2477
2478static const struct ieee80211_ops rt61pci_mac80211_ops = {
2479 .tx = rt2x00mac_tx,
4150c572
JB		 2480 .start = rt2x00mac_start,
2481 .stop = rt2x00mac_stop,
95ea3627
ID		 2482 .add_interface = rt2x00mac_add_interface,
2483 .remove_interface = rt2x00mac_remove_interface,
2484 .config = rt2x00mac_config,
2485 .config_interface = rt2x00mac_config_interface,
4150c572 2486 .configure_filter = rt61pci_configure_filter,
95ea3627
ID		 2487 .get_stats = rt2x00mac_get_stats,
2488 .set_retry_limit = rt61pci_set_retry_limit,
5c58ee51 2489 .erp_ie_changed = rt2x00mac_erp_ie_changed,
95ea3627
ID		 2490 .conf_tx = rt2x00mac_conf_tx,
2491 .get_tx_stats = rt2x00mac_get_tx_stats,
2492 .get_tsf = rt61pci_get_tsf,
2493 .reset_tsf = rt61pci_reset_tsf,
2494 .beacon_update = rt61pci_beacon_update,
2495};
2496
2497static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2498 .irq_handler = rt61pci_interrupt,
2499 .probe_hw = rt61pci_probe_hw,
2500 .get_firmware_name = rt61pci_get_firmware_name,
2501 .load_firmware = rt61pci_load_firmware,
2502 .initialize = rt2x00pci_initialize,
2503 .uninitialize = rt2x00pci_uninitialize,
2504 .set_device_state = rt61pci_set_device_state,
95ea3627 2505 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2506 .link_stats = rt61pci_link_stats,
2507 .reset_tuner = rt61pci_reset_tuner,
2508 .link_tuner = rt61pci_link_tuner,
2509 .write_tx_desc = rt61pci_write_tx_desc,
2510 .write_tx_data = rt2x00pci_write_tx_data,
2511 .kick_tx_queue = rt61pci_kick_tx_queue,
2512 .fill_rxdone = rt61pci_fill_rxdone,
2513 .config_mac_addr = rt61pci_config_mac_addr,
2514 .config_bssid = rt61pci_config_bssid,
95ea3627 2515 .config_type = rt61pci_config_type,
5c58ee51 2516 .config_preamble = rt61pci_config_preamble,
95ea3627
ID		 2517 .config = rt61pci_config,
2518};
2519
2520static const struct rt2x00_ops rt61pci_ops = {
2521 .name = DRV_NAME,
2522 .rxd_size = RXD_DESC_SIZE,
2523 .txd_size = TXD_DESC_SIZE,
2524 .eeprom_size = EEPROM_SIZE,
2525 .rf_size = RF_SIZE,
2526 .lib = &rt61pci_rt2x00_ops,
2527 .hw = &rt61pci_mac80211_ops,
2528#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2529 .debugfs = &rt61pci_rt2x00debug,
2530#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2531};
2532
2533/*
2534 * RT61pci module information.
2535 */
2536static struct pci_device_id rt61pci_device_table[] = {
2537 /* RT2561s */
2538 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2539 /* RT2561 v2 */
2540 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2541 /* RT2661 */
2542 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2543 { 0, }
2544};
2545
2546MODULE_AUTHOR(DRV_PROJECT);
2547MODULE_VERSION(DRV_VERSION);
2548MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2549MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2550 "PCI & PCMCIA chipset based cards");
2551MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2552MODULE_FIRMWARE(FIRMWARE_RT2561);
2553MODULE_FIRMWARE(FIRMWARE_RT2561s);
2554MODULE_FIRMWARE(FIRMWARE_RT2661);
2555MODULE_LICENSE("GPL");
2556
2557static struct pci_driver rt61pci_driver = {
2558 .name = DRV_NAME,
2559 .id_table = rt61pci_device_table,
2560 .probe = rt2x00pci_probe,
2561 .remove = __devexit_p(rt2x00pci_remove),
2562 .suspend = rt2x00pci_suspend,
2563 .resume = rt2x00pci_resume,
2564};
2565
2566static int __init rt61pci_init(void)
2567{
2568 return pci_register_driver(&rt61pci_driver);
2569}
2570
2571static void __exit rt61pci_exit(void)
2572{
2573 pci_unregister_driver(&rt61pci_driver);
2574}
2575
2576module_init(rt61pci_init);
2577module_exit(rt61pci_exit);
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