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rt2x00: Make rt2x00leds_register return void
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/eeprom_93cx6.h>
35
36#include "rt2x00.h"
37#include "rt2x00pci.h"
38#include "rt61pci.h"
39
40/*
41 * Register access.
42 * BBP and RF register require indirect register access,
43 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attampt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
50 */
0e14f6d3 51static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 52{
53 u32 reg;
54 unsigned int i;
55
56 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
57 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
58 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
59 break;
60 udelay(REGISTER_BUSY_DELAY);
61 }
62
63 return reg;
64}
65
0e14f6d3 66static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 67 const unsigned int word, const u8 value)
68{
69 u32 reg;
70
71 /*
72 * Wait until the BBP becomes ready.
73 */
74 reg = rt61pci_bbp_check(rt2x00dev);
75 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
76 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
77 return;
78 }
79
80 /*
81 * Write the data into the BBP.
82 */
83 reg = 0;
84 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
85 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
86 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
87 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
88
89 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
90}
91
0e14f6d3 92static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 93 const unsigned int word, u8 *value)
94{
95 u32 reg;
96
97 /*
98 * Wait until the BBP becomes ready.
99 */
100 reg = rt61pci_bbp_check(rt2x00dev);
101 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
102 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
103 return;
104 }
105
106 /*
107 * Write the request into the BBP.
108 */
109 reg = 0;
110 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
111 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
112 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
113
114 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
115
116 /*
117 * Wait until the BBP becomes ready.
118 */
119 reg = rt61pci_bbp_check(rt2x00dev);
120 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
121 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
122 *value = 0xff;
123 return;
124 }
125
126 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
127}
128
0e14f6d3 129static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 130 const unsigned int word, const u32 value)
131{
132 u32 reg;
133 unsigned int i;
134
135 if (!word)
136 return;
137
138 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
139 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
140 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
141 goto rf_write;
142 udelay(REGISTER_BUSY_DELAY);
143 }
144
145 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
146 return;
147
148rf_write:
149 reg = 0;
150 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
151 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
152 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
153 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
154
155 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
156 rt2x00_rf_write(rt2x00dev, word, value);
157}
158
a9450b70
ID		 159#ifdef CONFIG_RT61PCI_LEDS
160/*
161 * This function is only called from rt61pci_led_brightness()
162 * make gcc happy by placing this function inside the
163 * same ifdef statement as the caller.
164 */
0e14f6d3 165static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 166 const u8 command, const u8 token,
167 const u8 arg0, const u8 arg1)
168{
169 u32 reg;
170
171 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
172
173 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
174 ERROR(rt2x00dev, "mcu request error. "
175 "Request 0x%02x failed for token 0x%02x.\n",
176 command, token);
177 return;
178 }
179
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
181 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
182 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
183 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
184 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
185
186 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
187 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
188 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
189 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
190}
a9450b70 191#endif /* CONFIG_RT61PCI_LEDS */
95ea3627
ID		 192
193static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
194{
195 struct rt2x00_dev *rt2x00dev = eeprom->data;
196 u32 reg;
197
198 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
199
200 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
201 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
202 eeprom->reg_data_clock =
203 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
204 eeprom->reg_chip_select =
205 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
206}
207
208static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
209{
210 struct rt2x00_dev *rt2x00dev = eeprom->data;
211 u32 reg = 0;
212
213 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
214 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
215 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
216 !!eeprom->reg_data_clock);
217 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
218 !!eeprom->reg_chip_select);
219
220 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
221}
222
223#ifdef CONFIG_RT2X00_LIB_DEBUGFS
224#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
225
0e14f6d3 226static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 227 const unsigned int word, u32 *data)
228{
229 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
230}
231
0e14f6d3 232static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 233 const unsigned int word, u32 data)
234{
235 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
236}
237
238static const struct rt2x00debug rt61pci_rt2x00debug = {
239 .owner = THIS_MODULE,
240 .csr = {
241 .read = rt61pci_read_csr,
242 .write = rt61pci_write_csr,
243 .word_size = sizeof(u32),
244 .word_count = CSR_REG_SIZE / sizeof(u32),
245 },
246 .eeprom = {
247 .read = rt2x00_eeprom_read,
248 .write = rt2x00_eeprom_write,
249 .word_size = sizeof(u16),
250 .word_count = EEPROM_SIZE / sizeof(u16),
251 },
252 .bbp = {
253 .read = rt61pci_bbp_read,
254 .write = rt61pci_bbp_write,
255 .word_size = sizeof(u8),
256 .word_count = BBP_SIZE / sizeof(u8),
257 },
258 .rf = {
259 .read = rt2x00_rf_read,
260 .write = rt61pci_rf_write,
261 .word_size = sizeof(u32),
262 .word_count = RF_SIZE / sizeof(u32),
263 },
264};
265#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
266
267#ifdef CONFIG_RT61PCI_RFKILL
268static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
269{
270 u32 reg;
271
272 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 273 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 274}
81873e9c
ID		 275#else
276#define rt61pci_rfkill_poll NULL
dcf5475b 277#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627 278
a9450b70
ID		 279#ifdef CONFIG_RT61PCI_LEDS
280static void rt61pci_led_brightness(struct led_classdev *led_cdev,
281 enum led_brightness brightness)
282{
283 struct rt2x00_led *led =
284 container_of(led_cdev, struct rt2x00_led, led_dev);
285 unsigned int enabled = brightness != LED_OFF;
286 unsigned int a_mode =
287 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
288 unsigned int bg_mode =
289 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
290
291 if (led->type == LED_TYPE_RADIO) {
292 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
293 MCU_LEDCS_RADIO_STATUS, enabled);
294
295 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
296 (led->rt2x00dev->led_mcu_reg & 0xff),
297 ((led->rt2x00dev->led_mcu_reg >> 8)));
298 } else if (led->type == LED_TYPE_ASSOC) {
299 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
300 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
301 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
302 MCU_LEDCS_LINK_A_STATUS, a_mode);
303
304 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
305 (led->rt2x00dev->led_mcu_reg & 0xff),
306 ((led->rt2x00dev->led_mcu_reg >> 8)));
307 } else if (led->type == LED_TYPE_QUALITY) {
308 /*
309 * The brightness is divided into 6 levels (0 - 5),
310 * this means we need to convert the brightness
311 * argument into the matching level within that range.
312 */
313 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
314 brightness / (LED_FULL / 6), 0);
315 }
316}
317#else
318#define rt61pci_led_brightness NULL
319#endif /* CONFIG_RT61PCI_LEDS */
320
95ea3627
ID		 321/*
322 * Configuration handlers.
323 */
6bb40dd1
ID		 324static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
325 struct rt2x00_intf *intf,
326 struct rt2x00intf_conf *conf,
327 const unsigned int flags)
95ea3627 328{
6bb40dd1
ID		 329 unsigned int beacon_base;
330 u32 reg;
95ea3627 331
6bb40dd1
ID		 332 if (flags & CONFIG_UPDATE_TYPE) {
333 /*
334 * Clear current synchronisation setup.
335 * For the Beacon base registers we only need to clear
336 * the first byte since that byte contains the VALID and OWNER
337 * bits which (when set to 0) will invalidate the entire beacon.
338 */
339 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 340 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
95ea3627 341
6bb40dd1
ID		 342 /*
343 * Enable synchronisation.
344 */
345 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
6bb40dd1
ID		 346 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
347 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
348 }
95ea3627 349
6bb40dd1
ID		 350 if (flags & CONFIG_UPDATE_MAC) {
351 reg = le32_to_cpu(conf->mac[1]);
352 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
353 conf->mac[1] = cpu_to_le32(reg);
95ea3627 354
6bb40dd1
ID		 355 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
356 conf->mac, sizeof(conf->mac));
357 }
95ea3627 358
6bb40dd1
ID		 359 if (flags & CONFIG_UPDATE_BSSID) {
360 reg = le32_to_cpu(conf->bssid[1]);
361 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
362 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 363
6bb40dd1
ID		 364 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
365 conf->bssid, sizeof(conf->bssid));
366 }
95ea3627
ID		 367}
368
72810379
ID		 369static int rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
370 struct rt2x00lib_erp *erp)
95ea3627 371{
95ea3627 372 u32 reg;
95ea3627
ID		 373
374 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 375 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
95ea3627
ID		 376 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
377
378 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 379 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 380 !!erp->short_preamble);
95ea3627 381 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
6bb40dd1
ID		 382
383 return 0;
95ea3627
ID		 384}
385
386static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 387 const int basic_rate_mask)
95ea3627 388{
5c58ee51 389 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 390}
391
5c58ee51
ID		 392static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
393 struct rf_channel *rf, const int txpower)
95ea3627
ID		 394{
395 u8 r3;
396 u8 r94;
397 u8 smart;
398
399 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
400 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
401
402 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
403 rt2x00_rf(&rt2x00dev->chip, RF2527));
404
405 rt61pci_bbp_read(rt2x00dev, 3, &r3);
406 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
407 rt61pci_bbp_write(rt2x00dev, 3, r3);
408
409 r94 = 6;
410 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
411 r94 += txpower - MAX_TXPOWER;
412 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
413 r94 += txpower;
414 rt61pci_bbp_write(rt2x00dev, 94, r94);
415
416 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
417 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
418 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
419 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
420
421 udelay(200);
422
423 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
424 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
425 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
426 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
427
428 udelay(200);
429
430 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
431 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
432 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
433 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
434
435 msleep(1);
436}
437
95ea3627
ID		 438static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
439 const int txpower)
440{
441 struct rf_channel rf;
442
443 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
444 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
445 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
446 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
447
5c58ee51 448 rt61pci_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 449}
450
451static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 452 struct antenna_setup *ant)
95ea3627
ID		 453{
454 u8 r3;
455 u8 r4;
456 u8 r77;
457
458 rt61pci_bbp_read(rt2x00dev, 3, &r3);
459 rt61pci_bbp_read(rt2x00dev, 4, &r4);
460 rt61pci_bbp_read(rt2x00dev, 77, &r77);
461
462 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 463 rt2x00_rf(&rt2x00dev->chip, RF5325));
e4cd2ff8
ID		 464
465 /*
466 * Configure the RX antenna.
467 */
addc81bd 468 switch (ant->rx) {
95ea3627 469 case ANTENNA_HW_DIVERSITY:
acaa410d 470 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 471 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 472 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 473 break;
474 case ANTENNA_A:
acaa410d 475 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 476 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 477 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 478 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
479 else
480 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 481 break;
482 case ANTENNA_B:
a4fe07d9 483 default:
acaa410d 484 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 485 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 486 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 487 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
488 else
489 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 490 break;
491 }
492
493 rt61pci_bbp_write(rt2x00dev, 77, r77);
494 rt61pci_bbp_write(rt2x00dev, 3, r3);
495 rt61pci_bbp_write(rt2x00dev, 4, r4);
496}
497
498static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 499 struct antenna_setup *ant)
95ea3627
ID		 500{
501 u8 r3;
502 u8 r4;
503 u8 r77;
504
505 rt61pci_bbp_read(rt2x00dev, 3, &r3);
506 rt61pci_bbp_read(rt2x00dev, 4, &r4);
507 rt61pci_bbp_read(rt2x00dev, 77, &r77);
508
509 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 510 rt2x00_rf(&rt2x00dev->chip, RF2529));
95ea3627
ID		 511 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
512 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
513
e4cd2ff8
ID		 514 /*
515 * Configure the RX antenna.
516 */
addc81bd 517 switch (ant->rx) {
95ea3627 518 case ANTENNA_HW_DIVERSITY:
acaa410d 519 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 520 break;
521 case ANTENNA_A:
acaa410d
MN		 522 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
523 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 524 break;
525 case ANTENNA_B:
a4fe07d9 526 default:
acaa410d
MN		 527 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
528 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 529 break;
530 }
531
532 rt61pci_bbp_write(rt2x00dev, 77, r77);
533 rt61pci_bbp_write(rt2x00dev, 3, r3);
534 rt61pci_bbp_write(rt2x00dev, 4, r4);
535}
536
537static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
538 const int p1, const int p2)
539{
540 u32 reg;
541
542 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
543
acaa410d
MN		 544 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
545 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
546
547 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
548 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
549
550 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 551}
552
553static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 554 struct antenna_setup *ant)
95ea3627 555{
95ea3627
ID		 556 u8 r3;
557 u8 r4;
558 u8 r77;
559
560 rt61pci_bbp_read(rt2x00dev, 3, &r3);
561 rt61pci_bbp_read(rt2x00dev, 4, &r4);
562 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 563
e4cd2ff8
ID		 564 /*
565 * Configure the RX antenna.
566 */
567 switch (ant->rx) {
568 case ANTENNA_A:
acaa410d
MN		 569 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
570 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
571 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8 572 break;
e4cd2ff8
ID		 573 case ANTENNA_HW_DIVERSITY:
574 /*
a4fe07d9
ID		 575 * FIXME: Antenna selection for the rf 2529 is very confusing
576 * in the legacy driver. Just default to antenna B until the
577 * legacy code can be properly translated into rt2x00 code.
e4cd2ff8
ID		 578 */
579 case ANTENNA_B:
a4fe07d9 580 default:
acaa410d
MN		 581 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
582 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
583 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 584 break;
585 }
586
e4cd2ff8 587 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 588 rt61pci_bbp_write(rt2x00dev, 3, r3);
589 rt61pci_bbp_write(rt2x00dev, 4, r4);
590}
591
592struct antenna_sel {
593 u8 word;
594 /*
595 * value[0] -> non-LNA
596 * value[1] -> LNA
597 */
598 u8 value[2];
599};
600
601static const struct antenna_sel antenna_sel_a[] = {
602 { 96, { 0x58, 0x78 } },
603 { 104, { 0x38, 0x48 } },
604 { 75, { 0xfe, 0x80 } },
605 { 86, { 0xfe, 0x80 } },
606 { 88, { 0xfe, 0x80 } },
607 { 35, { 0x60, 0x60 } },
608 { 97, { 0x58, 0x58 } },
609 { 98, { 0x58, 0x58 } },
610};
611
612static const struct antenna_sel antenna_sel_bg[] = {
613 { 96, { 0x48, 0x68 } },
614 { 104, { 0x2c, 0x3c } },
615 { 75, { 0xfe, 0x80 } },
616 { 86, { 0xfe, 0x80 } },
617 { 88, { 0xfe, 0x80 } },
618 { 35, { 0x50, 0x50 } },
619 { 97, { 0x48, 0x48 } },
620 { 98, { 0x48, 0x48 } },
621};
622
623static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 624 struct antenna_setup *ant)
95ea3627
ID		 625{
626 const struct antenna_sel *sel;
627 unsigned int lna;
628 unsigned int i;
629 u32 reg;
630
a4fe07d9
ID		 631 /*
632 * We should never come here because rt2x00lib is supposed
633 * to catch this and send us the correct antenna explicitely.
634 */
635 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
636 ant->tx == ANTENNA_SW_DIVERSITY);
637
8318d78a 638 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 639 sel = antenna_sel_a;
640 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 641 } else {
642 sel = antenna_sel_bg;
643 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 644 }
645
acaa410d
MN		 646 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
647 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
648
649 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
650
ddc827f9 651 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 652 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 653 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 654 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 655
95ea3627
ID		 656 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
657
658 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
659 rt2x00_rf(&rt2x00dev->chip, RF5325))
addc81bd 660 rt61pci_config_antenna_5x(rt2x00dev, ant);
95ea3627 661 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 662 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 663 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
664 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 665 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 666 else
addc81bd 667 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 668 }
669}
670
671static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 672 struct rt2x00lib_conf *libconf)
95ea3627
ID		 673{
674 u32 reg;
675
676 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 677 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 678 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
679
680 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 681 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 682 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 683 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 684 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
685
686 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
687 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
688 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
689
690 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
691 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
692 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
693
694 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 695 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
696 libconf->conf->beacon_int * 16);
95ea3627
ID		 697 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
698}
699
700static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 701 struct rt2x00lib_conf *libconf,
702 const unsigned int flags)
95ea3627 703{
95ea3627 704 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 705 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 706 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 707 rt61pci_config_channel(rt2x00dev, &libconf->rf,
708 libconf->conf->power_level);
95ea3627 709 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 710 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 711 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 712 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 713 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 714 rt61pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 715}
716
95ea3627
ID		 717/*
718 * Link tuning
719 */
ebcf26da
ID		 720static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
721 struct link_qual *qual)
95ea3627
ID		 722{
723 u32 reg;
724
725 /*
726 * Update FCS error count from register.
727 */
728 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 729 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 730
731 /*
732 * Update False CCA count from register.
733 */
734 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 735 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 736}
737
738static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
739{
740 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
741 rt2x00dev->link.vgc_level = 0x20;
742}
743
744static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
745{
746 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
747 u8 r17;
748 u8 up_bound;
749 u8 low_bound;
750
95ea3627
ID		 751 rt61pci_bbp_read(rt2x00dev, 17, &r17);
752
753 /*
754 * Determine r17 bounds.
755 */
1497074a 756 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 757 low_bound = 0x28;
758 up_bound = 0x48;
759 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
760 low_bound += 0x10;
761 up_bound += 0x10;
762 }
763 } else {
764 low_bound = 0x20;
765 up_bound = 0x40;
766 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
767 low_bound += 0x10;
768 up_bound += 0x10;
769 }
770 }
771
6bb40dd1
ID		 772 /*
773 * If we are not associated, we should go straight to the
774 * dynamic CCA tuning.
775 */
776 if (!rt2x00dev->intf_associated)
777 goto dynamic_cca_tune;
778
95ea3627
ID		 779 /*
780 * Special big-R17 for very short distance
781 */
782 if (rssi >= -35) {
783 if (r17 != 0x60)
784 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
785 return;
786 }
787
788 /*
789 * Special big-R17 for short distance
790 */
791 if (rssi >= -58) {
792 if (r17 != up_bound)
793 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
794 return;
795 }
796
797 /*
798 * Special big-R17 for middle-short distance
799 */
800 if (rssi >= -66) {
801 low_bound += 0x10;
802 if (r17 != low_bound)
803 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
804 return;
805 }
806
807 /*
808 * Special mid-R17 for middle distance
809 */
810 if (rssi >= -74) {
811 low_bound += 0x08;
812 if (r17 != low_bound)
813 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
814 return;
815 }
816
817 /*
818 * Special case: Change up_bound based on the rssi.
819 * Lower up_bound when rssi is weaker then -74 dBm.
820 */
821 up_bound -= 2 * (-74 - rssi);
822 if (low_bound > up_bound)
823 up_bound = low_bound;
824
825 if (r17 > up_bound) {
826 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
827 return;
828 }
829
6bb40dd1
ID		 830dynamic_cca_tune:
831
95ea3627
ID		 832 /*
833 * r17 does not yet exceed upper limit, continue and base
834 * the r17 tuning on the false CCA count.
835 */
ebcf26da 836 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 837 if (++r17 > up_bound)
838 r17 = up_bound;
839 rt61pci_bbp_write(rt2x00dev, 17, r17);
ebcf26da 840 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 841 if (--r17 < low_bound)
842 r17 = low_bound;
843 rt61pci_bbp_write(rt2x00dev, 17, r17);
844 }
845}
846
847/*
a7f3a06c 848 * Firmware functions
95ea3627
ID		 849 */
850static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
851{
852 char *fw_name;
853
854 switch (rt2x00dev->chip.rt) {
855 case RT2561:
856 fw_name = FIRMWARE_RT2561;
857 break;
858 case RT2561s:
859 fw_name = FIRMWARE_RT2561s;
860 break;
861 case RT2661:
862 fw_name = FIRMWARE_RT2661;
863 break;
864 default:
865 fw_name = NULL;
866 break;
867 }
868
869 return fw_name;
870}
871
a7f3a06c
ID		 872static u16 rt61pci_get_firmware_crc(void *data, const size_t len)
873{
874 u16 crc;
875
876 /*
877 * Use the crc itu-t algorithm.
878 * The last 2 bytes in the firmware array are the crc checksum itself,
879 * this means that we should never pass those 2 bytes to the crc
880 * algorithm.
881 */
882 crc = crc_itu_t(0, data, len - 2);
883 crc = crc_itu_t_byte(crc, 0);
884 crc = crc_itu_t_byte(crc, 0);
885
886 return crc;
887}
888
95ea3627
ID		 889static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
890 const size_t len)
891{
892 int i;
893 u32 reg;
894
895 /*
896 * Wait for stable hardware.
897 */
898 for (i = 0; i < 100; i++) {
899 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
900 if (reg)
901 break;
902 msleep(1);
903 }
904
905 if (!reg) {
906 ERROR(rt2x00dev, "Unstable hardware.\n");
907 return -EBUSY;
908 }
909
910 /*
911 * Prepare MCU and mailbox for firmware loading.
912 */
913 reg = 0;
914 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
915 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
916 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
917 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
918 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
919
920 /*
921 * Write firmware to device.
922 */
923 reg = 0;
924 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
925 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
926 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
927
928 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
929 data, len);
930
931 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
932 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
933
934 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
935 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
936
937 for (i = 0; i < 100; i++) {
938 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
939 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
940 break;
941 msleep(1);
942 }
943
944 if (i == 100) {
945 ERROR(rt2x00dev, "MCU Control register not ready.\n");
946 return -EBUSY;
947 }
948
949 /*
950 * Reset MAC and BBP registers.
951 */
952 reg = 0;
953 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
954 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
955 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
956
957 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
958 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
959 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
960 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
961
962 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
963 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
964 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
965
966 return 0;
967}
968
a7f3a06c
ID		 969/*
970 * Initialization functions.
971 */
837e7f24 972static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 973 struct queue_entry *entry)
95ea3627 974{
181d6902 975 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 976 u32 word;
977
181d6902 978 rt2x00_desc_read(priv_rx->desc, 5, &word);
30b3a23c
ID		 979 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
980 priv_rx->data_dma);
181d6902 981 rt2x00_desc_write(priv_rx->desc, 5, word);
95ea3627 982
181d6902 983 rt2x00_desc_read(priv_rx->desc, 0, &word);
837e7f24 984 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
181d6902 985 rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627
ID		 986}
987
837e7f24 988static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 989 struct queue_entry *entry)
95ea3627 990{
181d6902 991 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
95ea3627
ID		 992 u32 word;
993
181d6902 994 rt2x00_desc_read(priv_tx->desc, 1, &word);
837e7f24 995 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
181d6902 996 rt2x00_desc_write(priv_tx->desc, 1, word);
95ea3627 997
181d6902
ID		 998 rt2x00_desc_read(priv_tx->desc, 5, &word);
999 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
837e7f24 1000 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
181d6902 1001 rt2x00_desc_write(priv_tx->desc, 5, word);
95ea3627 1002
181d6902 1003 rt2x00_desc_read(priv_tx->desc, 6, &word);
30b3a23c
ID		 1004 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1005 priv_tx->data_dma);
181d6902 1006 rt2x00_desc_write(priv_tx->desc, 6, word);
95ea3627 1007
181d6902 1008 rt2x00_desc_read(priv_tx->desc, 0, &word);
837e7f24
ID		 1009 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1010 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
181d6902 1011 rt2x00_desc_write(priv_tx->desc, 0, word);
95ea3627
ID		 1012}
1013
181d6902 1014static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1015{
181d6902
ID		 1016 struct queue_entry_priv_pci_rx *priv_rx;
1017 struct queue_entry_priv_pci_tx *priv_tx;
95ea3627
ID		 1018 u32 reg;
1019
95ea3627
ID		 1020 /*
1021 * Initialize registers.
1022 */
1023 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1024 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1025 rt2x00dev->tx[0].limit);
95ea3627 1026 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1027 rt2x00dev->tx[1].limit);
95ea3627 1028 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1029 rt2x00dev->tx[2].limit);
95ea3627 1030 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1031 rt2x00dev->tx[3].limit);
95ea3627
ID		 1032 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1033
1034 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1035 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1036 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1037 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1038
181d6902 1039 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1040 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
30b3a23c
ID		 1041 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1042 priv_tx->desc_dma);
95ea3627
ID		 1043 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1044
181d6902 1045 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1046 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
30b3a23c
ID		 1047 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1048 priv_tx->desc_dma);
95ea3627
ID		 1049 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1050
181d6902 1051 priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1052 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
30b3a23c
ID		 1053 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1054 priv_tx->desc_dma);
95ea3627
ID		 1055 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1056
181d6902 1057 priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1058 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
30b3a23c
ID		 1059 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1060 priv_tx->desc_dma);
95ea3627
ID		 1061 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1062
95ea3627 1063 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1064 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1065 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1066 rt2x00dev->rx->desc_size / 4);
1067 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1068 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1069
181d6902 1070 priv_rx = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1071 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
30b3a23c
ID		 1072 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1073 priv_rx->desc_dma);
95ea3627
ID		 1074 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1075
1076 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1077 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1078 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1079 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1080 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
95ea3627
ID		 1081 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1082
1083 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1084 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1085 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1086 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1087 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
95ea3627
ID		 1088 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1089
1090 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1091 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1092 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1093
1094 return 0;
1095}
1096
1097static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1098{
1099 u32 reg;
1100
1101 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1102 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1103 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1104 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1105 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1106
1107 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1108 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1109 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1110 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1111 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1112 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1113 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1114 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1115 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1116 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1117
1118 /*
1119 * CCK TXD BBP registers
1120 */
1121 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1122 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1123 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1124 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1125 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1126 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1127 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1128 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1129 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1130 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1131
1132 /*
1133 * OFDM TXD BBP registers
1134 */
1135 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1136 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1137 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1138 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1139 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1140 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1141 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1142 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1143
1144 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1145 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1146 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1147 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1148 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1149 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1150
1151 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1152 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1153 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1154 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1155 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1156 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1157
1158 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1159
1160 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1161
1162 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1163 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1164 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1165
1166 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1167
1168 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1169 return -EBUSY;
1170
1171 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1172
a9450b70
ID		 1173 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
1174 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
1175 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
1176 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
1177
95ea3627
ID		 1178 /*
1179 * Invalidate all Shared Keys (SEC_CSR0),
1180 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1181 */
1182 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1183 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1184 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1185
1186 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1187 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1188 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1189 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1190
1191 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1192
1193 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1194
1195 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1196
1197 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1198 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1199 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1200 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1201
1202 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1203 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1204 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1205 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1206
6bb40dd1
ID		 1207 /*
1208 * Clear all beacons
1209 * For the Beacon base registers we only need to clear
1210 * the first byte since that byte contains the VALID and OWNER
1211 * bits which (when set to 0) will invalidate the entire beacon.
1212 */
1213 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1214 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1215 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1216 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1217
95ea3627
ID		 1218 /*
1219 * We must clear the error counters.
1220 * These registers are cleared on read,
1221 * so we may pass a useless variable to store the value.
1222 */
1223 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1224 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1225 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1226
1227 /*
1228 * Reset MAC and BBP registers.
1229 */
1230 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1231 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1232 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1233 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1234
1235 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1236 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1237 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1238 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1239
1240 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1241 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1242 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1243
1244 return 0;
1245}
1246
1247static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1248{
1249 unsigned int i;
1250 u16 eeprom;
1251 u8 reg_id;
1252 u8 value;
1253
1254 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1255 rt61pci_bbp_read(rt2x00dev, 0, &value);
1256 if ((value != 0xff) && (value != 0x00))
1257 goto continue_csr_init;
1258 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1259 udelay(REGISTER_BUSY_DELAY);
1260 }
1261
1262 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1263 return -EACCES;
1264
1265continue_csr_init:
1266 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1267 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1268 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1269 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1270 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1271 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1272 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1273 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1274 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1275 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1276 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1277 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1278 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1279 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1280 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1281 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1282 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1283 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1284 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1285 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1286 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1287 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1288 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1289 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1290
95ea3627
ID		 1291 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1292 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1293
1294 if (eeprom != 0xffff && eeprom != 0x0000) {
1295 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1296 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1297 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1298 }
1299 }
95ea3627
ID		 1300
1301 return 0;
1302}
1303
1304/*
1305 * Device state switch handlers.
1306 */
1307static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1308 enum dev_state state)
1309{
1310 u32 reg;
1311
1312 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1313 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1314 state == STATE_RADIO_RX_OFF);
1315 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1316}
1317
1318static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1319 enum dev_state state)
1320{
1321 int mask = (state == STATE_RADIO_IRQ_OFF);
1322 u32 reg;
1323
1324 /*
1325 * When interrupts are being enabled, the interrupt registers
1326 * should clear the register to assure a clean state.
1327 */
1328 if (state == STATE_RADIO_IRQ_ON) {
1329 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1330 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1331
1332 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1333 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1334 }
1335
1336 /*
1337 * Only toggle the interrupts bits we are going to use.
1338 * Non-checked interrupt bits are disabled by default.
1339 */
1340 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1341 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1342 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1343 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1344 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1345 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1346
1347 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1348 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1349 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1350 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1351 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1352 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1353 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1354 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1355 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1356 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1357}
1358
1359static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1360{
1361 u32 reg;
1362
1363 /*
1364 * Initialize all registers.
1365 */
181d6902 1366 if (rt61pci_init_queues(rt2x00dev) ||
95ea3627
ID		 1367 rt61pci_init_registers(rt2x00dev) ||
1368 rt61pci_init_bbp(rt2x00dev)) {
1369 ERROR(rt2x00dev, "Register initialization failed.\n");
1370 return -EIO;
1371 }
1372
1373 /*
1374 * Enable interrupts.
1375 */
1376 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1377
1378 /*
1379 * Enable RX.
1380 */
1381 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1382 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1383 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1384
95ea3627
ID		 1385 return 0;
1386}
1387
1388static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1389{
1390 u32 reg;
1391
95ea3627
ID		 1392 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1393
1394 /*
1395 * Disable synchronisation.
1396 */
1397 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1398
1399 /*
1400 * Cancel RX and TX.
1401 */
1402 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1403 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1404 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1405 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1406 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
95ea3627
ID		 1407 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1408
1409 /*
1410 * Disable interrupts.
1411 */
1412 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1413}
1414
1415static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1416{
1417 u32 reg;
1418 unsigned int i;
1419 char put_to_sleep;
1420 char current_state;
1421
1422 put_to_sleep = (state != STATE_AWAKE);
1423
1424 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1425 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1426 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1427 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1428
1429 /*
1430 * Device is not guaranteed to be in the requested state yet.
1431 * We must wait until the register indicates that the
1432 * device has entered the correct state.
1433 */
1434 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1435 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1436 current_state =
1437 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1438 if (current_state == !put_to_sleep)
1439 return 0;
1440 msleep(10);
1441 }
1442
1443 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1444 "current device state %d.\n", !put_to_sleep, current_state);
1445
1446 return -EBUSY;
1447}
1448
1449static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1450 enum dev_state state)
1451{
1452 int retval = 0;
1453
1454 switch (state) {
1455 case STATE_RADIO_ON:
1456 retval = rt61pci_enable_radio(rt2x00dev);
1457 break;
1458 case STATE_RADIO_OFF:
1459 rt61pci_disable_radio(rt2x00dev);
1460 break;
1461 case STATE_RADIO_RX_ON:
61667d8d
ID		 1462 case STATE_RADIO_RX_ON_LINK:
1463 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1464 break;
95ea3627 1465 case STATE_RADIO_RX_OFF:
61667d8d
ID		 1466 case STATE_RADIO_RX_OFF_LINK:
1467 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 1468 break;
1469 case STATE_DEEP_SLEEP:
1470 case STATE_SLEEP:
1471 case STATE_STANDBY:
1472 case STATE_AWAKE:
1473 retval = rt61pci_set_state(rt2x00dev, state);
1474 break;
1475 default:
1476 retval = -ENOTSUPP;
1477 break;
1478 }
1479
1480 return retval;
1481}
1482
1483/*
1484 * TX descriptor initialization
1485 */
1486static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1487 struct sk_buff *skb,
181d6902 1488 struct txentry_desc *txdesc,
dd3193e1 1489 struct ieee80211_tx_control *control)
95ea3627 1490{
181d6902 1491 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1492 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1493 u32 word;
1494
1495 /*
1496 * Start writing the descriptor words.
1497 */
1498 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1499 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1500 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1501 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1502 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1503 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1504 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1505 rt2x00_desc_write(txd, 1, word);
1506
1507 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1508 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1509 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1510 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1511 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1512 rt2x00_desc_write(txd, 2, word);
1513
1514 rt2x00_desc_read(txd, 5, &word);
1515 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1516 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1517 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1518 rt2x00_desc_write(txd, 5, word);
1519
d7bafff3
AB		 1520 if (skbdesc->desc_len > TXINFO_SIZE) {
1521 rt2x00_desc_read(txd, 11, &word);
1522 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1523 rt2x00_desc_write(txd, 11, word);
1524 }
95ea3627
ID		 1525
1526 rt2x00_desc_read(txd, 0, &word);
1527 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1528 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1529 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1530 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1531 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1532 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1533 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1534 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1535 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1536 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1537 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1538 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1539 !!(control->flags &
1540 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1541 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
dd3193e1 1542 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627 1543 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1544 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1545 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1546 rt2x00_desc_write(txd, 0, word);
1547}
1548
1549/*
1550 * TX data initialization
1551 */
1552static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1553 const unsigned int queue)
95ea3627
ID		 1554{
1555 u32 reg;
1556
5957da4c 1557 if (queue == RT2X00_BCN_QUEUE_BEACON) {
95ea3627
ID		 1558 /*
1559 * For Wi-Fi faily generated beacons between participating
1560 * stations. Set TBTT phase adaptive adjustment step to 8us.
1561 */
1562 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1563
1564 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1565 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1566 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1567 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1568 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1569 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1570 }
1571 return;
1572 }
1573
1574 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
ddc827f9
ID		 1575 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0,
1576 (queue == IEEE80211_TX_QUEUE_DATA0));
1577 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1,
1578 (queue == IEEE80211_TX_QUEUE_DATA1));
1579 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
1580 (queue == IEEE80211_TX_QUEUE_DATA2));
1581 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1582 (queue == IEEE80211_TX_QUEUE_DATA3));
95ea3627
ID		 1583 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1584}
1585
1586/*
1587 * RX control handlers
1588 */
1589static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1590{
1591 u16 eeprom;
1592 u8 offset;
1593 u8 lna;
1594
1595 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1596 switch (lna) {
1597 case 3:
1598 offset = 90;
1599 break;
1600 case 2:
1601 offset = 74;
1602 break;
1603 case 1:
1604 offset = 64;
1605 break;
1606 default:
1607 return 0;
1608 }
1609
8318d78a 1610 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1611 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1612 offset += 14;
1613
1614 if (lna == 3 || lna == 2)
1615 offset += 10;
1616
1617 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1618 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1619 } else {
1620 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1621 offset += 14;
1622
1623 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1624 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1625 }
1626
1627 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1628}
1629
181d6902
ID		 1630static void rt61pci_fill_rxdone(struct queue_entry *entry,
1631 struct rxdone_entry_desc *rxdesc)
95ea3627 1632{
181d6902 1633 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 1634 u32 word0;
1635 u32 word1;
1636
181d6902
ID		 1637 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1638 rt2x00_desc_read(priv_rx->desc, 1, &word1);
95ea3627 1639
181d6902 1640 rxdesc->flags = 0;
4150c572 1641 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1642 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1643
1644 /*
1645 * Obtain the status about this packet.
1646 */
181d6902
ID		 1647 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1648 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1649 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1650 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1651 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
95ea3627
ID		 1652}
1653
1654/*
1655 * Interrupt functions.
1656 */
1657static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1658{
181d6902
ID		 1659 struct data_queue *queue;
1660 struct queue_entry *entry;
1661 struct queue_entry *entry_done;
1662 struct queue_entry_priv_pci_tx *priv_tx;
1663 struct txdone_entry_desc txdesc;
95ea3627
ID		 1664 u32 word;
1665 u32 reg;
1666 u32 old_reg;
1667 int type;
1668 int index;
95ea3627
ID		 1669
1670 /*
1671 * During each loop we will compare the freshly read
1672 * STA_CSR4 register value with the value read from
1673 * the previous loop. If the 2 values are equal then
1674 * we should stop processing because the chance it
1675 * quite big that the device has been unplugged and
1676 * we risk going into an endless loop.
1677 */
1678 old_reg = 0;
1679
1680 while (1) {
1681 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1682 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1683 break;
1684
1685 if (old_reg == reg)
1686 break;
1687 old_reg = reg;
1688
1689 /*
1690 * Skip this entry when it contains an invalid
181d6902 1691 * queue identication number.
95ea3627
ID		 1692 */
1693 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 1694 queue = rt2x00queue_get_queue(rt2x00dev, type);
1695 if (unlikely(!queue))
95ea3627
ID		 1696 continue;
1697
1698 /*
1699 * Skip this entry when it contains an invalid
1700 * index number.
1701 */
1702 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 1703 if (unlikely(index >= queue->limit))
95ea3627
ID		 1704 continue;
1705
181d6902
ID		 1706 entry = &queue->entries[index];
1707 priv_tx = entry->priv_data;
1708 rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627
ID		 1709
1710 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1711 !rt2x00_get_field32(word, TXD_W0_VALID))
1712 return;
1713
181d6902 1714 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 1715 while (entry != entry_done) {
181d6902
ID		 1716 /* Catch up.
1717 * Just report any entries we missed as failed.
1718 */
62bc060b 1719 WARNING(rt2x00dev,
181d6902
ID		 1720 "TX status report missed for entry %d\n",
1721 entry_done->entry_idx);
1722
1723 txdesc.status = TX_FAIL_OTHER;
1724 txdesc.retry = 0;
1725
1726 rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1727 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 1728 }
1729
95ea3627
ID		 1730 /*
1731 * Obtain the status about this packet.
1732 */
181d6902
ID		 1733 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1734 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 1735
181d6902 1736 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627
ID		 1737 }
1738}
1739
1740static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1741{
1742 struct rt2x00_dev *rt2x00dev = dev_instance;
1743 u32 reg_mcu;
1744 u32 reg;
1745
1746 /*
1747 * Get the interrupt sources & saved to local variable.
1748 * Write register value back to clear pending interrupts.
1749 */
1750 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1751 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1752
1753 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1754 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1755
1756 if (!reg && !reg_mcu)
1757 return IRQ_NONE;
1758
1759 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1760 return IRQ_HANDLED;
1761
1762 /*
1763 * Handle interrupts, walk through all bits
1764 * and run the tasks, the bits are checked in order of
1765 * priority.
1766 */
1767
1768 /*
1769 * 1 - Rx ring done interrupt.
1770 */
1771 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1772 rt2x00pci_rxdone(rt2x00dev);
1773
1774 /*
1775 * 2 - Tx ring done interrupt.
1776 */
1777 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1778 rt61pci_txdone(rt2x00dev);
1779
1780 /*
1781 * 3 - Handle MCU command done.
1782 */
1783 if (reg_mcu)
1784 rt2x00pci_register_write(rt2x00dev,
1785 M2H_CMD_DONE_CSR, 0xffffffff);
1786
1787 return IRQ_HANDLED;
1788}
1789
1790/*
1791 * Device probe functions.
1792 */
1793static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1794{
1795 struct eeprom_93cx6 eeprom;
1796 u32 reg;
1797 u16 word;
1798 u8 *mac;
1799 s8 value;
1800
1801 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1802
1803 eeprom.data = rt2x00dev;
1804 eeprom.register_read = rt61pci_eepromregister_read;
1805 eeprom.register_write = rt61pci_eepromregister_write;
1806 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1807 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1808 eeprom.reg_data_in = 0;
1809 eeprom.reg_data_out = 0;
1810 eeprom.reg_data_clock = 0;
1811 eeprom.reg_chip_select = 0;
1812
1813 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1814 EEPROM_SIZE / sizeof(u16));
1815
1816 /*
1817 * Start validation of the data that has been read.
1818 */
1819 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1820 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1821 DECLARE_MAC_BUF(macbuf);
1822
95ea3627 1823 random_ether_addr(mac);
0795af57 1824 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1825 }
1826
1827 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1828 if (word == 0xffff) {
1829 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1830 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1831 ANTENNA_B);
1832 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1833 ANTENNA_B);
95ea3627
ID		 1834 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1835 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1836 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1837 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1838 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1839 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1840 }
1841
1842 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1843 if (word == 0xffff) {
1844 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1845 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1846 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1847 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1848 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1849 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1850 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1851 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1852 }
1853
1854 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1855 if (word == 0xffff) {
1856 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1857 LED_MODE_DEFAULT);
1858 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1859 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1860 }
1861
1862 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1863 if (word == 0xffff) {
1864 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1865 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1866 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1867 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1868 }
1869
1870 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1871 if (word == 0xffff) {
1872 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1873 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1874 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1875 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1876 } else {
1877 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1878 if (value < -10 || value > 10)
1879 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1880 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1881 if (value < -10 || value > 10)
1882 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1883 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1884 }
1885
1886 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1887 if (word == 0xffff) {
1888 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1889 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1890 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1891 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1892 } else {
1893 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1894 if (value < -10 || value > 10)
1895 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1896 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1897 if (value < -10 || value > 10)
1898 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1899 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1900 }
1901
1902 return 0;
1903}
1904
1905static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1906{
1907 u32 reg;
1908 u16 value;
1909 u16 eeprom;
1910 u16 device;
1911
1912 /*
1913 * Read EEPROM word for configuration.
1914 */
1915 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1916
1917 /*
1918 * Identify RF chipset.
1919 * To determine the RT chip we have to read the
1920 * PCI header of the device.
1921 */
1922 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1923 PCI_CONFIG_HEADER_DEVICE, &device);
1924 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1925 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1926 rt2x00_set_chip(rt2x00dev, device, value, reg);
1927
1928 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1929 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1930 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1931 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1932 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1933 return -ENODEV;
1934 }
1935
e4cd2ff8
ID		 1936 /*
1937 * Determine number of antenna's.
1938 */
1939 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1940 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1941
95ea3627
ID		 1942 /*
1943 * Identify default antenna configuration.
1944 */
addc81bd 1945 rt2x00dev->default_ant.tx =
95ea3627 1946 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1947 rt2x00dev->default_ant.rx =
95ea3627
ID		 1948 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1949
1950 /*
1951 * Read the Frame type.
1952 */
1953 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1954 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1955
95ea3627
ID		 1956 /*
1957 * Detect if this device has an hardware controlled radio.
1958 */
81873e9c 1959#ifdef CONFIG_RT61PCI_RFKILL
95ea3627 1960 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1961 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1962#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627
ID		 1963
1964 /*
1965 * Read frequency offset and RF programming sequence.
1966 */
1967 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1968 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
1969 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
1970
1971 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1972
1973 /*
1974 * Read external LNA informations.
1975 */
1976 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1977
1978 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1979 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1980 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1981 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1982
e4cd2ff8
ID		 1983 /*
1984 * When working with a RF2529 chip without double antenna
1985 * the antenna settings should be gathered from the NIC
1986 * eeprom word.
1987 */
1988 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
1989 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
1990 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
1991 case 0:
1992 rt2x00dev->default_ant.tx = ANTENNA_B;
1993 rt2x00dev->default_ant.rx = ANTENNA_A;
1994 break;
1995 case 1:
1996 rt2x00dev->default_ant.tx = ANTENNA_B;
1997 rt2x00dev->default_ant.rx = ANTENNA_B;
1998 break;
1999 case 2:
2000 rt2x00dev->default_ant.tx = ANTENNA_A;
2001 rt2x00dev->default_ant.rx = ANTENNA_A;
2002 break;
2003 case 3:
2004 rt2x00dev->default_ant.tx = ANTENNA_A;
2005 rt2x00dev->default_ant.rx = ANTENNA_B;
2006 break;
2007 }
2008
2009 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2010 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2011 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2012 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2013 }
2014
95ea3627
ID		 2015 /*
2016 * Store led settings, for correct led behaviour.
2017 * If the eeprom value is invalid,
2018 * switch to default led mode.
2019 */
a9450b70 2020#ifdef CONFIG_RT61PCI_LEDS
95ea3627
ID		 2021 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2022
a9450b70
ID		 2023 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2024
2025 switch (value) {
2026 case LED_MODE_TXRX_ACTIVITY:
2027 case LED_MODE_ASUS:
2028 case LED_MODE_ALPHA:
2029 case LED_MODE_DEFAULT:
2030 rt2x00dev->led_flags =
2031 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
2032 break;
2033 case LED_MODE_SIGNAL_STRENGTH:
2034 rt2x00dev->led_flags =
2035 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
2036 LED_SUPPORT_QUALITY;
2037 break;
2038 }
95ea3627 2039
a9450b70
ID		 2040 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2041 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2042 rt2x00_get_field16(eeprom,
2043 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2044 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2045 rt2x00_get_field16(eeprom,
2046 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2047 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2048 rt2x00_get_field16(eeprom,
2049 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2050 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2051 rt2x00_get_field16(eeprom,
2052 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2053 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2054 rt2x00_get_field16(eeprom,
2055 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2056 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2057 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2058 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2059 rt2x00_get_field16(eeprom,
2060 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2061 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2062 rt2x00_get_field16(eeprom,
2063 EEPROM_LED_POLARITY_RDY_A));
a9450b70 2064#endif /* CONFIG_RT61PCI_LEDS */
95ea3627
ID		 2065
2066 return 0;
2067}
2068
2069/*
2070 * RF value list for RF5225 & RF5325
2071 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2072 */
2073static const struct rf_channel rf_vals_noseq[] = {
2074 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2075 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2076 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2077 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2078 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2079 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2080 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2081 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2082 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2083 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2084 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2085 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2086 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2087 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2088
2089 /* 802.11 UNI / HyperLan 2 */
2090 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2091 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2092 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2093 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2094 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2095 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2096 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2097 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2098
2099 /* 802.11 HyperLan 2 */
2100 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2101 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2102 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2103 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2104 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2105 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2106 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2107 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2108 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2109 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2110
2111 /* 802.11 UNII */
2112 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2113 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2114 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2115 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2116 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2117 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2118
2119 /* MMAC(Japan)J52 ch 34,38,42,46 */
2120 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2121 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2122 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2123 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2124};
2125
2126/*
2127 * RF value list for RF5225 & RF5325
2128 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2129 */
2130static const struct rf_channel rf_vals_seq[] = {
2131 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2132 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2133 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2134 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2135 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2136 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2137 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2138 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2139 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2140 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2141 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2142 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2143 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2144 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2145
2146 /* 802.11 UNI / HyperLan 2 */
2147 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2148 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2149 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2150 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2151 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2152 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2153 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2154 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2155
2156 /* 802.11 HyperLan 2 */
2157 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2158 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2159 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2160 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2161 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2162 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2163 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2164 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2165 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2166 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2167
2168 /* 802.11 UNII */
2169 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2170 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2171 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2172 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2173 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2174 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2175
2176 /* MMAC(Japan)J52 ch 34,38,42,46 */
2177 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2178 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2179 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2180 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2181};
2182
2183static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2184{
2185 struct hw_mode_spec *spec = &rt2x00dev->spec;
2186 u8 *txpower;
2187 unsigned int i;
2188
2189 /*
2190 * Initialize all hw fields.
2191 */
2192 rt2x00dev->hw->flags =
2193 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 2194 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 2195 rt2x00dev->hw->extra_tx_headroom = 0;
2196 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2197 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
871ff6ed 2198 rt2x00dev->hw->queues = 4;
95ea3627
ID		 2199
2200 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2201 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2202 rt2x00_eeprom_addr(rt2x00dev,
2203 EEPROM_MAC_ADDR_0));
2204
2205 /*
2206 * Convert tx_power array in eeprom.
2207 */
2208 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2209 for (i = 0; i < 14; i++)
2210 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2211
2212 /*
2213 * Initialize hw_mode information.
2214 */
31562e80
ID		 2215 spec->supported_bands = SUPPORT_BAND_2GHZ;
2216 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2217 spec->tx_power_a = NULL;
2218 spec->tx_power_bg = txpower;
2219 spec->tx_power_default = DEFAULT_TXPOWER;
2220
2221 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2222 spec->num_channels = 14;
2223 spec->channels = rf_vals_noseq;
2224 } else {
2225 spec->num_channels = 14;
2226 spec->channels = rf_vals_seq;
2227 }
2228
2229 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2230 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
31562e80 2231 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2232 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2233
2234 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2235 for (i = 0; i < 14; i++)
2236 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2237
2238 spec->tx_power_a = txpower;
2239 }
2240}
2241
2242static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2243{
2244 int retval;
2245
2246 /*
2247 * Allocate eeprom data.
2248 */
2249 retval = rt61pci_validate_eeprom(rt2x00dev);
2250 if (retval)
2251 return retval;
2252
2253 retval = rt61pci_init_eeprom(rt2x00dev);
2254 if (retval)
2255 return retval;
2256
2257 /*
2258 * Initialize hw specifications.
2259 */
2260 rt61pci_probe_hw_mode(rt2x00dev);
2261
2262 /*
9404ef34 2263 * This device requires firmware.
95ea3627 2264 */
066cb637 2265 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
95ea3627
ID		 2266
2267 /*
2268 * Set the rssi offset.
2269 */
2270 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2271
2272 return 0;
2273}
2274
2275/*
2276 * IEEE80211 stack callback functions.
2277 */
4150c572
JB		 2278static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2279 unsigned int changed_flags,
2280 unsigned int *total_flags,
2281 int mc_count,
2282 struct dev_addr_list *mc_list)
2283{
2284 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 2285 u32 reg;
2286
2287 /*
2288 * Mask off any flags we are going to ignore from
2289 * the total_flags field.
2290 */
2291 *total_flags &=
2292 FIF_ALLMULTI |
2293 FIF_FCSFAIL |
2294 FIF_PLCPFAIL |
2295 FIF_CONTROL |
2296 FIF_OTHER_BSS |
2297 FIF_PROMISC_IN_BSS;
2298
2299 /*
2300 * Apply some rules to the filters:
2301 * - Some filters imply different filters to be set.
2302 * - Some things we can't filter out at all.
4150c572
JB		 2303 */
2304 if (mc_count)
2305 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 2306 if (*total_flags & FIF_OTHER_BSS ||
2307 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 2308 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 2309
2310 /*
2311 * Check if there is any work left for us.
2312 */
3c4f2085 2313 if (rt2x00dev->packet_filter == *total_flags)
4150c572 2314 return;
3c4f2085 2315 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 2316
2317 /*
2318 * Start configuration steps.
2319 * Note that the version error will always be dropped
2320 * and broadcast frames will always be accepted since
2321 * there is no filter for it at this time.
2322 */
2323 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2324 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2325 !(*total_flags & FIF_FCSFAIL));
2326 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2327 !(*total_flags & FIF_PLCPFAIL));
2328 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2329 !(*total_flags & FIF_CONTROL));
2330 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2331 !(*total_flags & FIF_PROMISC_IN_BSS));
2332 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2333 !(*total_flags & FIF_PROMISC_IN_BSS));
2334 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2335 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2336 !(*total_flags & FIF_ALLMULTI));
e542239f
ID		 2337 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
2338 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
2339 !(*total_flags & FIF_CONTROL));
4150c572
JB		 2340 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2341}
2342
95ea3627
ID		 2343static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2344 u32 short_retry, u32 long_retry)
2345{
2346 struct rt2x00_dev *rt2x00dev = hw->priv;
2347 u32 reg;
2348
2349 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2350 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2351 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2352 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2353
2354 return 0;
2355}
2356
2357static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2358{
2359 struct rt2x00_dev *rt2x00dev = hw->priv;
2360 u64 tsf;
2361 u32 reg;
2362
2363 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2364 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2365 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2366 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2367
2368 return tsf;
2369}
2370
24845910 2371static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
95ea3627
ID		 2372 struct ieee80211_tx_control *control)
2373{
2374 struct rt2x00_dev *rt2x00dev = hw->priv;
6bb40dd1 2375 struct rt2x00_intf *intf = vif_to_intf(control->vif);
181d6902 2376 struct skb_frame_desc *skbdesc;
6bb40dd1 2377 unsigned int beacon_base;
8af244cc 2378 u32 reg;
95ea3627 2379
6bb40dd1
ID		 2380 if (unlikely(!intf->beacon))
2381 return -ENOBUFS;
95ea3627
ID		 2382
2383 /*
2384 * We need to append the descriptor in front of the
2385 * beacon frame.
2386 */
6bb40dd1
ID		 2387 if (skb_headroom(skb) < intf->beacon->queue->desc_size) {
2388 if (pskb_expand_head(skb, intf->beacon->queue->desc_size,
2389 0, GFP_ATOMIC)) {
95ea3627
ID		 2390 dev_kfree_skb(skb);
2391 return -ENOMEM;
2392 }
2393 }
2394
2395 /*
08992f7f
ID		 2396 * Add the descriptor in front of the skb.
2397 */
6bb40dd1
ID		 2398 skb_push(skb, intf->beacon->queue->desc_size);
2399 memset(skb->data, 0, intf->beacon->queue->desc_size);
08992f7f
ID		 2400
2401 /*
2402 * Fill in skb descriptor
95ea3627 2403 */
181d6902
ID		 2404 skbdesc = get_skb_frame_desc(skb);
2405 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 2406 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
6bb40dd1
ID		 2407 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2408 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
181d6902 2409 skbdesc->desc = skb->data;
6bb40dd1
ID		 2410 skbdesc->desc_len = intf->beacon->queue->desc_size;
2411 skbdesc->entry = intf->beacon;
c22eb87b 2412
8af244cc
ID		 2413 /*
2414 * Disable beaconing while we are reloading the beacon data,
2415 * otherwise we might be sending out invalid data.
2416 */
2417 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2418 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2419 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2420 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2421 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2422
6bb40dd1 2423 /*
5957da4c
ID		 2424 * mac80211 doesn't provide the control->queue variable
2425 * for beacons. Set our own queue identification so
2426 * it can be used during descriptor initialization.
6bb40dd1 2427 */
5957da4c 2428 control->queue = RT2X00_BCN_QUEUE_BEACON;
08992f7f 2429 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
95ea3627
ID		 2430
2431 /*
2432 * Write entire beacon with descriptor to register,
2433 * and kick the beacon generator.
2434 */
6bb40dd1
ID		 2435 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2436 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
9ee8f57e 2437 skb->data, skb->len);
6bb40dd1 2438 rt61pci_kick_tx_queue(rt2x00dev, control->queue);
95ea3627
ID		 2439
2440 return 0;
2441}
2442
2443static const struct ieee80211_ops rt61pci_mac80211_ops = {
2444 .tx = rt2x00mac_tx,
4150c572
JB		 2445 .start = rt2x00mac_start,
2446 .stop = rt2x00mac_stop,
95ea3627
ID		 2447 .add_interface = rt2x00mac_add_interface,
2448 .remove_interface = rt2x00mac_remove_interface,
2449 .config = rt2x00mac_config,
2450 .config_interface = rt2x00mac_config_interface,
4150c572 2451 .configure_filter = rt61pci_configure_filter,
95ea3627
ID		 2452 .get_stats = rt2x00mac_get_stats,
2453 .set_retry_limit = rt61pci_set_retry_limit,
471b3efd 2454 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2455 .conf_tx = rt2x00mac_conf_tx,
2456 .get_tx_stats = rt2x00mac_get_tx_stats,
2457 .get_tsf = rt61pci_get_tsf,
95ea3627
ID		 2458 .beacon_update = rt61pci_beacon_update,
2459};
2460
2461static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2462 .irq_handler = rt61pci_interrupt,
2463 .probe_hw = rt61pci_probe_hw,
2464 .get_firmware_name = rt61pci_get_firmware_name,
a7f3a06c 2465 .get_firmware_crc = rt61pci_get_firmware_crc,
95ea3627
ID		 2466 .load_firmware = rt61pci_load_firmware,
2467 .initialize = rt2x00pci_initialize,
2468 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 2469 .init_rxentry = rt61pci_init_rxentry,
2470 .init_txentry = rt61pci_init_txentry,
95ea3627 2471 .set_device_state = rt61pci_set_device_state,
95ea3627 2472 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2473 .link_stats = rt61pci_link_stats,
2474 .reset_tuner = rt61pci_reset_tuner,
2475 .link_tuner = rt61pci_link_tuner,
a9450b70 2476 .led_brightness = rt61pci_led_brightness,
95ea3627
ID		 2477 .write_tx_desc = rt61pci_write_tx_desc,
2478 .write_tx_data = rt2x00pci_write_tx_data,
2479 .kick_tx_queue = rt61pci_kick_tx_queue,
2480 .fill_rxdone = rt61pci_fill_rxdone,
6bb40dd1 2481 .config_intf = rt61pci_config_intf,
72810379 2482 .config_erp = rt61pci_config_erp,
95ea3627
ID		 2483 .config = rt61pci_config,
2484};
2485
181d6902
ID		 2486static const struct data_queue_desc rt61pci_queue_rx = {
2487 .entry_num = RX_ENTRIES,
2488 .data_size = DATA_FRAME_SIZE,
2489 .desc_size = RXD_DESC_SIZE,
2490 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
2491};
2492
2493static const struct data_queue_desc rt61pci_queue_tx = {
2494 .entry_num = TX_ENTRIES,
2495 .data_size = DATA_FRAME_SIZE,
2496 .desc_size = TXD_DESC_SIZE,
2497 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2498};
2499
2500static const struct data_queue_desc rt61pci_queue_bcn = {
6bb40dd1 2501 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2502 .data_size = MGMT_FRAME_SIZE,
2503 .desc_size = TXINFO_SIZE,
2504 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2505};
2506
95ea3627 2507static const struct rt2x00_ops rt61pci_ops = {
2360157c 2508 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2509 .max_sta_intf = 1,
2510 .max_ap_intf = 4,
95ea3627
ID		 2511 .eeprom_size = EEPROM_SIZE,
2512 .rf_size = RF_SIZE,
181d6902
ID		 2513 .rx = &rt61pci_queue_rx,
2514 .tx = &rt61pci_queue_tx,
2515 .bcn = &rt61pci_queue_bcn,
95ea3627
ID		 2516 .lib = &rt61pci_rt2x00_ops,
2517 .hw = &rt61pci_mac80211_ops,
2518#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2519 .debugfs = &rt61pci_rt2x00debug,
2520#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2521};
2522
2523/*
2524 * RT61pci module information.
2525 */
2526static struct pci_device_id rt61pci_device_table[] = {
2527 /* RT2561s */
2528 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2529 /* RT2561 v2 */
2530 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2531 /* RT2661 */
2532 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2533 { 0, }
2534};
2535
2536MODULE_AUTHOR(DRV_PROJECT);
2537MODULE_VERSION(DRV_VERSION);
2538MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2539MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2540 "PCI & PCMCIA chipset based cards");
2541MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2542MODULE_FIRMWARE(FIRMWARE_RT2561);
2543MODULE_FIRMWARE(FIRMWARE_RT2561s);
2544MODULE_FIRMWARE(FIRMWARE_RT2661);
2545MODULE_LICENSE("GPL");
2546
2547static struct pci_driver rt61pci_driver = {
2360157c 2548 .name = KBUILD_MODNAME,
95ea3627
ID		 2549 .id_table = rt61pci_device_table,
2550 .probe = rt2x00pci_probe,
2551 .remove = __devexit_p(rt2x00pci_remove),
2552 .suspend = rt2x00pci_suspend,
2553 .resume = rt2x00pci_resume,
2554};
2555
2556static int __init rt61pci_init(void)
2557{
2558 return pci_register_driver(&rt61pci_driver);
2559}
2560
2561static void __exit rt61pci_exit(void)
2562{
2563 pci_unregister_driver(&rt61pci_driver);
2564}
2565
2566module_init(rt61pci_init);
2567module_exit(rt61pci_exit);
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