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rt2x00: Merge PCI and USB versions of write_tx_data into single function.
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
95ea3627
ID		 34#include <linux/pci.h>
35#include <linux/eeprom_93cx6.h>
36
37#include "rt2x00.h"
38#include "rt2x00pci.h"
39#include "rt61pci.h"
40
008c4482
ID		 41/*
42 * Allow hardware encryption to be disabled.
43 */
44static int modparam_nohwcrypt = 0;
45module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
46MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
47
95ea3627
ID		 48/*
49 * Register access.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
b34e620f 55 * between each attempt. When the busy bit is still set at that time,
95ea3627
ID		 56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 */
c9c3b1a5
ID		 59#define WAIT_FOR_BBP(__dev, __reg) \
60 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
61#define WAIT_FOR_RF(__dev, __reg) \
62 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
63#define WAIT_FOR_MCU(__dev, __reg) \
64 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
65 H2M_MAILBOX_CSR_OWNER, (__reg))
95ea3627 66
0e14f6d3 67static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
8ff48a8b
ID		 72 mutex_lock(&rt2x00dev->csr_mutex);
73
95ea3627 74 /*
c9c3b1a5
ID		 75 * Wait until the BBP becomes available, afterwards we
76 * can safely write the new data into the register.
95ea3627 77 */
c9c3b1a5
ID		 78 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
79 reg = 0;
80 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
81 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
82 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
83 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
84
85 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
86 }
8ff48a8b 87
8ff48a8b 88 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 89}
90
0e14f6d3 91static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 92 const unsigned int word, u8 *value)
93{
94 u32 reg;
95
8ff48a8b
ID		 96 mutex_lock(&rt2x00dev->csr_mutex);
97
95ea3627 98 /*
c9c3b1a5
ID		 99 * Wait until the BBP becomes available, afterwards we
100 * can safely write the read request into the register.
101 * After the data has been written, we wait until hardware
102 * returns the correct value, if at any time the register
103 * doesn't become available in time, reg will be 0xffffffff
104 * which means we return 0xff to the caller.
95ea3627 105 */
c9c3b1a5
ID		 106 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
107 reg = 0;
108 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
109 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
110 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 111
c9c3b1a5 112 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
95ea3627 113
c9c3b1a5
ID		 114 WAIT_FOR_BBP(rt2x00dev, &reg);
115 }
95ea3627
ID		 116
117 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
8ff48a8b 118
8ff48a8b 119 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 120}
121
0e14f6d3 122static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 123 const unsigned int word, const u32 value)
124{
125 u32 reg;
95ea3627 126
8ff48a8b
ID		 127 mutex_lock(&rt2x00dev->csr_mutex);
128
c9c3b1a5
ID		 129 /*
130 * Wait until the RF becomes available, afterwards we
131 * can safely write the new data into the register.
132 */
133 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
134 reg = 0;
135 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
136 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
137 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
138 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
139
140 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
141 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 142 }
143
8ff48a8b 144 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 145}
146
0e14f6d3 147static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 148 const u8 command, const u8 token,
149 const u8 arg0, const u8 arg1)
150{
151 u32 reg;
152
8ff48a8b
ID		 153 mutex_lock(&rt2x00dev->csr_mutex);
154
c9c3b1a5
ID		 155 /*
156 * Wait until the MCU becomes available, afterwards we
157 * can safely write the new data into the register.
158 */
159 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
160 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
161 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
162 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
163 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
164 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
165
166 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
167 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
168 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
169 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
170 }
8ff48a8b 171
8ff48a8b
ID		 172 mutex_unlock(&rt2x00dev->csr_mutex);
173
95ea3627
ID		 174}
175
176static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
177{
178 struct rt2x00_dev *rt2x00dev = eeprom->data;
179 u32 reg;
180
181 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
182
183 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
184 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
185 eeprom->reg_data_clock =
186 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
187 eeprom->reg_chip_select =
188 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
189}
190
191static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
192{
193 struct rt2x00_dev *rt2x00dev = eeprom->data;
194 u32 reg = 0;
195
196 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
197 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
198 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
199 !!eeprom->reg_data_clock);
200 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
201 !!eeprom->reg_chip_select);
202
203 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
204}
205
206#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 207static const struct rt2x00debug rt61pci_rt2x00debug = {
208 .owner = THIS_MODULE,
209 .csr = {
743b97ca
ID		 210 .read = rt2x00pci_register_read,
211 .write = rt2x00pci_register_write,
212 .flags = RT2X00DEBUGFS_OFFSET,
213 .word_base = CSR_REG_BASE,
95ea3627
ID		 214 .word_size = sizeof(u32),
215 .word_count = CSR_REG_SIZE / sizeof(u32),
216 },
217 .eeprom = {
218 .read = rt2x00_eeprom_read,
219 .write = rt2x00_eeprom_write,
743b97ca 220 .word_base = EEPROM_BASE,
95ea3627
ID		 221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
223 },
224 .bbp = {
225 .read = rt61pci_bbp_read,
226 .write = rt61pci_bbp_write,
743b97ca 227 .word_base = BBP_BASE,
95ea3627
ID		 228 .word_size = sizeof(u8),
229 .word_count = BBP_SIZE / sizeof(u8),
230 },
231 .rf = {
232 .read = rt2x00_rf_read,
233 .write = rt61pci_rf_write,
743b97ca 234 .word_base = RF_BASE,
95ea3627
ID		 235 .word_size = sizeof(u32),
236 .word_count = RF_SIZE / sizeof(u32),
237 },
238};
239#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
240
95ea3627
ID		 241static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
242{
243 u32 reg;
244
245 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 246 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 247}
95ea3627 248
771fd565 249#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 250static void rt61pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 251 enum led_brightness brightness)
252{
253 struct rt2x00_led *led =
254 container_of(led_cdev, struct rt2x00_led, led_dev);
255 unsigned int enabled = brightness != LED_OFF;
256 unsigned int a_mode =
257 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
258 unsigned int bg_mode =
259 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
260
261 if (led->type == LED_TYPE_RADIO) {
262 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
263 MCU_LEDCS_RADIO_STATUS, enabled);
264
265 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
266 (led->rt2x00dev->led_mcu_reg & 0xff),
267 ((led->rt2x00dev->led_mcu_reg >> 8)));
268 } else if (led->type == LED_TYPE_ASSOC) {
269 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
270 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
271 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
272 MCU_LEDCS_LINK_A_STATUS, a_mode);
273
274 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
275 (led->rt2x00dev->led_mcu_reg & 0xff),
276 ((led->rt2x00dev->led_mcu_reg >> 8)));
277 } else if (led->type == LED_TYPE_QUALITY) {
278 /*
279 * The brightness is divided into 6 levels (0 - 5),
280 * this means we need to convert the brightness
281 * argument into the matching level within that range.
282 */
283 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
284 brightness / (LED_FULL / 6), 0);
285 }
286}
a2e1d52a
ID		 287
288static int rt61pci_blink_set(struct led_classdev *led_cdev,
289 unsigned long *delay_on,
290 unsigned long *delay_off)
291{
292 struct rt2x00_led *led =
293 container_of(led_cdev, struct rt2x00_led, led_dev);
294 u32 reg;
295
296 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
297 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
298 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
299 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
300
301 return 0;
302}
475433be
ID		 303
304static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
305 struct rt2x00_led *led,
306 enum led_type type)
307{
308 led->rt2x00dev = rt2x00dev;
309 led->type = type;
310 led->led_dev.brightness_set = rt61pci_brightness_set;
311 led->led_dev.blink_set = rt61pci_blink_set;
312 led->flags = LED_INITIALIZED;
313}
771fd565 314#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 315
95ea3627
ID		 316/*
317 * Configuration handlers.
318 */
61e754f4
ID		 319static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
320 struct rt2x00lib_crypto *crypto,
321 struct ieee80211_key_conf *key)
322{
323 struct hw_key_entry key_entry;
324 struct rt2x00_field32 field;
325 u32 mask;
326 u32 reg;
327
328 if (crypto->cmd == SET_KEY) {
329 /*
330 * rt2x00lib can't determine the correct free
331 * key_idx for shared keys. We have 1 register
332 * with key valid bits. The goal is simple, read
333 * the register, if that is full we have no slots
334 * left.
335 * Note that each BSS is allowed to have up to 4
336 * shared keys, so put a mask over the allowed
337 * entries.
338 */
339 mask = (0xf << crypto->bssidx);
340
341 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
342 reg &= mask;
343
344 if (reg && reg == mask)
345 return -ENOSPC;
346
acaf908d 347 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 348
349 /*
350 * Upload key to hardware
351 */
352 memcpy(key_entry.key, crypto->key,
353 sizeof(key_entry.key));
354 memcpy(key_entry.tx_mic, crypto->tx_mic,
355 sizeof(key_entry.tx_mic));
356 memcpy(key_entry.rx_mic, crypto->rx_mic,
357 sizeof(key_entry.rx_mic));
358
359 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
360 rt2x00pci_register_multiwrite(rt2x00dev, reg,
361 &key_entry, sizeof(key_entry));
362
363 /*
364 * The cipher types are stored over 2 registers.
365 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
366 * bssidx 1 and 2 keys are stored in SEC_CSR5.
367 * Using the correct defines correctly will cause overhead,
368 * so just calculate the correct offset.
369 */
370 if (key->hw_key_idx < 8) {
371 field.bit_offset = (3 * key->hw_key_idx);
372 field.bit_mask = 0x7 << field.bit_offset;
373
374 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
375 rt2x00_set_field32(&reg, field, crypto->cipher);
376 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
377 } else {
378 field.bit_offset = (3 * (key->hw_key_idx - 8));
379 field.bit_mask = 0x7 << field.bit_offset;
380
381 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
382 rt2x00_set_field32(&reg, field, crypto->cipher);
383 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
384 }
385
386 /*
387 * The driver does not support the IV/EIV generation
388 * in hardware. However it doesn't support the IV/EIV
389 * inside the ieee80211 frame either, but requires it
b34e620f 390 * to be provided separately for the descriptor.
61e754f4
ID		 391 * rt2x00lib will cut the IV/EIV data out of all frames
392 * given to us by mac80211, but we must tell mac80211
393 * to generate the IV/EIV data.
394 */
395 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
396 }
397
398 /*
399 * SEC_CSR0 contains only single-bit fields to indicate
400 * a particular key is valid. Because using the FIELD32()
b34e620f 401 * defines directly will cause a lot of overhead, we use
61e754f4
ID		 402 * a calculation to determine the correct bit directly.
403 */
404 mask = 1 << key->hw_key_idx;
405
406 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
407 if (crypto->cmd == SET_KEY)
408 reg |= mask;
409 else if (crypto->cmd == DISABLE_KEY)
410 reg &= ~mask;
411 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
412
413 return 0;
414}
415
416static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
417 struct rt2x00lib_crypto *crypto,
418 struct ieee80211_key_conf *key)
419{
420 struct hw_pairwise_ta_entry addr_entry;
421 struct hw_key_entry key_entry;
422 u32 mask;
423 u32 reg;
424
425 if (crypto->cmd == SET_KEY) {
426 /*
427 * rt2x00lib can't determine the correct free
428 * key_idx for pairwise keys. We have 2 registers
b34e620f
TLSC		 429 * with key valid bits. The goal is simple: read
430 * the first register. If that is full, move to
61e754f4 431 * the next register.
b34e620f
TLSC		 432 * When both registers are full, we drop the key.
433 * Otherwise, we use the first invalid entry.
61e754f4
ID		 434 */
435 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
436 if (reg && reg == ~0) {
437 key->hw_key_idx = 32;
438 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
439 if (reg && reg == ~0)
440 return -ENOSPC;
441 }
442
acaf908d 443 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 444
445 /*
446 * Upload key to hardware
447 */
448 memcpy(key_entry.key, crypto->key,
449 sizeof(key_entry.key));
450 memcpy(key_entry.tx_mic, crypto->tx_mic,
451 sizeof(key_entry.tx_mic));
452 memcpy(key_entry.rx_mic, crypto->rx_mic,
453 sizeof(key_entry.rx_mic));
454
455 memset(&addr_entry, 0, sizeof(addr_entry));
456 memcpy(&addr_entry, crypto->address, ETH_ALEN);
457 addr_entry.cipher = crypto->cipher;
458
459 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
460 rt2x00pci_register_multiwrite(rt2x00dev, reg,
461 &key_entry, sizeof(key_entry));
462
463 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
464 rt2x00pci_register_multiwrite(rt2x00dev, reg,
465 &addr_entry, sizeof(addr_entry));
466
467 /*
b34e620f
TLSC		 468 * Enable pairwise lookup table for given BSS idx.
469 * Without this, received frames will not be decrypted
61e754f4
ID		 470 * by the hardware.
471 */
472 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
473 reg |= (1 << crypto->bssidx);
474 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
475
476 /*
477 * The driver does not support the IV/EIV generation
478 * in hardware. However it doesn't support the IV/EIV
479 * inside the ieee80211 frame either, but requires it
3ad2f3fb 480 * to be provided separately for the descriptor.
61e754f4
ID		 481 * rt2x00lib will cut the IV/EIV data out of all frames
482 * given to us by mac80211, but we must tell mac80211
483 * to generate the IV/EIV data.
484 */
485 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
486 }
487
488 /*
489 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
490 * a particular key is valid. Because using the FIELD32()
b34e620f 491 * defines directly will cause a lot of overhead, we use
61e754f4
ID		 492 * a calculation to determine the correct bit directly.
493 */
494 if (key->hw_key_idx < 32) {
495 mask = 1 << key->hw_key_idx;
496
497 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
498 if (crypto->cmd == SET_KEY)
499 reg |= mask;
500 else if (crypto->cmd == DISABLE_KEY)
501 reg &= ~mask;
502 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
503 } else {
504 mask = 1 << (key->hw_key_idx - 32);
505
506 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
507 if (crypto->cmd == SET_KEY)
508 reg |= mask;
509 else if (crypto->cmd == DISABLE_KEY)
510 reg &= ~mask;
511 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
512 }
513
514 return 0;
515}
516
3a643d24
ID		 517static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
518 const unsigned int filter_flags)
519{
520 u32 reg;
521
522 /*
523 * Start configuration steps.
524 * Note that the version error will always be dropped
525 * and broadcast frames will always be accepted since
526 * there is no filter for it at this time.
527 */
528 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
529 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
530 !(filter_flags & FIF_FCSFAIL));
531 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
532 !(filter_flags & FIF_PLCPFAIL));
533 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1afcfd54 534 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
3a643d24
ID		 535 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
536 !(filter_flags & FIF_PROMISC_IN_BSS));
537 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 538 !(filter_flags & FIF_PROMISC_IN_BSS) &&
539 !rt2x00dev->intf_ap_count);
3a643d24
ID		 540 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
541 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
542 !(filter_flags & FIF_ALLMULTI));
543 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
544 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
545 !(filter_flags & FIF_CONTROL));
546 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
547}
548
6bb40dd1
ID		 549static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
550 struct rt2x00_intf *intf,
551 struct rt2x00intf_conf *conf,
552 const unsigned int flags)
95ea3627 553{
6bb40dd1
ID		 554 unsigned int beacon_base;
555 u32 reg;
95ea3627 556
6bb40dd1
ID		 557 if (flags & CONFIG_UPDATE_TYPE) {
558 /*
559 * Clear current synchronisation setup.
b34e620f 560 * For the Beacon base registers, we only need to clear
6bb40dd1
ID		 561 * the first byte since that byte contains the VALID and OWNER
562 * bits which (when set to 0) will invalidate the entire beacon.
563 */
564 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 565 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
95ea3627 566
6bb40dd1
ID		 567 /*
568 * Enable synchronisation.
569 */
570 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 571 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 572 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 573 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 574 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
575 }
95ea3627 576
6bb40dd1
ID		 577 if (flags & CONFIG_UPDATE_MAC) {
578 reg = le32_to_cpu(conf->mac[1]);
579 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
580 conf->mac[1] = cpu_to_le32(reg);
95ea3627 581
6bb40dd1
ID		 582 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
583 conf->mac, sizeof(conf->mac));
584 }
95ea3627 585
6bb40dd1
ID		 586 if (flags & CONFIG_UPDATE_BSSID) {
587 reg = le32_to_cpu(conf->bssid[1]);
588 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
589 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 590
6bb40dd1
ID		 591 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
592 conf->bssid, sizeof(conf->bssid));
593 }
95ea3627
ID		 594}
595
3a643d24
ID		 596static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
597 struct rt2x00lib_erp *erp)
95ea3627 598{
95ea3627 599 u32 reg;
95ea3627
ID		 600
601 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
4789666e 602 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
8a566afe 603 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
95ea3627
ID		 604 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
605
606 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
8a566afe 607 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
4f5af6eb 608 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 609 !!erp->short_preamble);
95ea3627 610 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 611
e4ea1c40 612 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 613
8a566afe
ID		 614 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
615 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
616 erp->beacon_int * 16);
617 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
618
e4ea1c40
ID		 619 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
620 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
621 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 622
e4ea1c40
ID		 623 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
624 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
625 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
626 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
627 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 628}
629
630static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 631 struct antenna_setup *ant)
95ea3627
ID		 632{
633 u8 r3;
634 u8 r4;
635 u8 r77;
636
637 rt61pci_bbp_read(rt2x00dev, 3, &r3);
638 rt61pci_bbp_read(rt2x00dev, 4, &r4);
639 rt61pci_bbp_read(rt2x00dev, 77, &r77);
640
5122d898 641 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
e4cd2ff8
ID		 642
643 /*
644 * Configure the RX antenna.
645 */
addc81bd 646 switch (ant->rx) {
95ea3627 647 case ANTENNA_HW_DIVERSITY:
acaa410d 648 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 649 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 650 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 651 break;
652 case ANTENNA_A:
acaa410d 653 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 654 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 655 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 656 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
657 else
658 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 659 break;
660 case ANTENNA_B:
a4fe07d9 661 default:
acaa410d 662 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 663 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 664 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 665 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
666 else
667 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 668 break;
669 }
670
671 rt61pci_bbp_write(rt2x00dev, 77, r77);
672 rt61pci_bbp_write(rt2x00dev, 3, r3);
673 rt61pci_bbp_write(rt2x00dev, 4, r4);
674}
675
676static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 677 struct antenna_setup *ant)
95ea3627
ID		 678{
679 u8 r3;
680 u8 r4;
681 u8 r77;
682
683 rt61pci_bbp_read(rt2x00dev, 3, &r3);
684 rt61pci_bbp_read(rt2x00dev, 4, &r4);
685 rt61pci_bbp_read(rt2x00dev, 77, &r77);
686
5122d898 687 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
95ea3627
ID		 688 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
689 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
690
e4cd2ff8
ID		 691 /*
692 * Configure the RX antenna.
693 */
addc81bd 694 switch (ant->rx) {
95ea3627 695 case ANTENNA_HW_DIVERSITY:
acaa410d 696 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 697 break;
698 case ANTENNA_A:
acaa410d
MN		 699 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
700 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 701 break;
702 case ANTENNA_B:
a4fe07d9 703 default:
acaa410d
MN		 704 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
705 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 706 break;
707 }
708
709 rt61pci_bbp_write(rt2x00dev, 77, r77);
710 rt61pci_bbp_write(rt2x00dev, 3, r3);
711 rt61pci_bbp_write(rt2x00dev, 4, r4);
712}
713
714static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
715 const int p1, const int p2)
716{
717 u32 reg;
718
719 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
720
acaa410d
MN		 721 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
722 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
723
724 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
725 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
726
727 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 728}
729
730static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 731 struct antenna_setup *ant)
95ea3627 732{
95ea3627
ID		 733 u8 r3;
734 u8 r4;
735 u8 r77;
736
737 rt61pci_bbp_read(rt2x00dev, 3, &r3);
738 rt61pci_bbp_read(rt2x00dev, 4, &r4);
739 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 740
e4cd2ff8
ID		 741 /*
742 * Configure the RX antenna.
743 */
744 switch (ant->rx) {
745 case ANTENNA_A:
acaa410d
MN		 746 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
747 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
748 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8 749 break;
e4cd2ff8
ID		 750 case ANTENNA_HW_DIVERSITY:
751 /*
a4fe07d9
ID		 752 * FIXME: Antenna selection for the rf 2529 is very confusing
753 * in the legacy driver. Just default to antenna B until the
754 * legacy code can be properly translated into rt2x00 code.
e4cd2ff8
ID		 755 */
756 case ANTENNA_B:
a4fe07d9 757 default:
acaa410d
MN		 758 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
759 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
760 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 761 break;
762 }
763
e4cd2ff8 764 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 765 rt61pci_bbp_write(rt2x00dev, 3, r3);
766 rt61pci_bbp_write(rt2x00dev, 4, r4);
767}
768
769struct antenna_sel {
770 u8 word;
771 /*
772 * value[0] -> non-LNA
773 * value[1] -> LNA
774 */
775 u8 value[2];
776};
777
778static const struct antenna_sel antenna_sel_a[] = {
779 { 96, { 0x58, 0x78 } },
780 { 104, { 0x38, 0x48 } },
781 { 75, { 0xfe, 0x80 } },
782 { 86, { 0xfe, 0x80 } },
783 { 88, { 0xfe, 0x80 } },
784 { 35, { 0x60, 0x60 } },
785 { 97, { 0x58, 0x58 } },
786 { 98, { 0x58, 0x58 } },
787};
788
789static const struct antenna_sel antenna_sel_bg[] = {
790 { 96, { 0x48, 0x68 } },
791 { 104, { 0x2c, 0x3c } },
792 { 75, { 0xfe, 0x80 } },
793 { 86, { 0xfe, 0x80 } },
794 { 88, { 0xfe, 0x80 } },
795 { 35, { 0x50, 0x50 } },
796 { 97, { 0x48, 0x48 } },
797 { 98, { 0x48, 0x48 } },
798};
799
e4ea1c40
ID		 800static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
801 struct antenna_setup *ant)
95ea3627
ID		 802{
803 const struct antenna_sel *sel;
804 unsigned int lna;
805 unsigned int i;
806 u32 reg;
807
a4fe07d9
ID		 808 /*
809 * We should never come here because rt2x00lib is supposed
810 * to catch this and send us the correct antenna explicitely.
811 */
812 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
813 ant->tx == ANTENNA_SW_DIVERSITY);
814
8318d78a 815 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 816 sel = antenna_sel_a;
817 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 818 } else {
819 sel = antenna_sel_bg;
820 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 821 }
822
acaa410d
MN		 823 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
824 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
825
826 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
827
ddc827f9 828 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 829 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 830 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 831 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 832
95ea3627
ID		 833 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
834
5122d898 835 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
addc81bd 836 rt61pci_config_antenna_5x(rt2x00dev, ant);
5122d898 837 else if (rt2x00_rf(rt2x00dev, RF2527))
addc81bd 838 rt61pci_config_antenna_2x(rt2x00dev, ant);
5122d898 839 else if (rt2x00_rf(rt2x00dev, RF2529)) {
95ea3627 840 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 841 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 842 else
addc81bd 843 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 844 }
845}
846
e4ea1c40
ID		 847static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
848 struct rt2x00lib_conf *libconf)
849{
850 u16 eeprom;
851 short lna_gain = 0;
852
853 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
854 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
855 lna_gain += 14;
856
857 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
858 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
859 } else {
860 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
861 lna_gain += 14;
862
863 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
864 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
865 }
866
867 rt2x00dev->lna_gain = lna_gain;
868}
869
870static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
871 struct rf_channel *rf, const int txpower)
872{
873 u8 r3;
874 u8 r94;
875 u8 smart;
876
877 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
878 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
879
5122d898 880 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
e4ea1c40
ID		 881
882 rt61pci_bbp_read(rt2x00dev, 3, &r3);
883 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
884 rt61pci_bbp_write(rt2x00dev, 3, r3);
885
886 r94 = 6;
887 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
888 r94 += txpower - MAX_TXPOWER;
889 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
890 r94 += txpower;
891 rt61pci_bbp_write(rt2x00dev, 94, r94);
892
893 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
894 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
895 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
896 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
897
898 udelay(200);
899
900 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
901 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
902 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
903 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
904
905 udelay(200);
906
907 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
908 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
909 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
910 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
911
912 msleep(1);
913}
914
915static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
916 const int txpower)
917{
918 struct rf_channel rf;
919
920 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
921 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
922 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
923 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
924
925 rt61pci_config_channel(rt2x00dev, &rf, txpower);
926}
927
928static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5c58ee51 929 struct rt2x00lib_conf *libconf)
95ea3627
ID		 930{
931 u32 reg;
932
e4ea1c40 933 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
e1b4d7b7
ID		 934 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
935 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
936 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
e4ea1c40
ID		 937 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
938 libconf->conf->long_frame_max_tx_count);
939 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
940 libconf->conf->short_frame_max_tx_count);
941 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
942}
95ea3627 943
7d7f19cc
ID		 944static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
945 struct rt2x00lib_conf *libconf)
946{
947 enum dev_state state =
948 (libconf->conf->flags & IEEE80211_CONF_PS) ?
949 STATE_SLEEP : STATE_AWAKE;
950 u32 reg;
951
952 if (state == STATE_SLEEP) {
953 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
954 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 955 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 956 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
957 libconf->conf->listen_interval - 1);
958 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
959
960 /* We must first disable autowake before it can be enabled */
961 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
962 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
963
964 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
965 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
966
967 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
968 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
969 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
970
971 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
972 } else {
973 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
974 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
975 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
976 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
977 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
978 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
979
980 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
981 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
982 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
983
984 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
985 }
986}
987
95ea3627 988static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 989 struct rt2x00lib_conf *libconf,
990 const unsigned int flags)
95ea3627 991{
ba2ab471
ID		 992 /* Always recalculate LNA gain before changing configuration */
993 rt61pci_config_lna_gain(rt2x00dev, libconf);
994
e4ea1c40 995 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 996 rt61pci_config_channel(rt2x00dev, &libconf->rf,
997 libconf->conf->power_level);
e4ea1c40
ID		 998 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
999 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 1000 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 1001 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1002 rt61pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 1003 if (flags & IEEE80211_CONF_CHANGE_PS)
1004 rt61pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 1005}
1006
95ea3627
ID		 1007/*
1008 * Link tuning
1009 */
ebcf26da
ID		 1010static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1011 struct link_qual *qual)
95ea3627
ID		 1012{
1013 u32 reg;
1014
1015 /*
1016 * Update FCS error count from register.
1017 */
1018 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 1019 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 1020
1021 /*
1022 * Update False CCA count from register.
1023 */
1024 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 1025 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 1026}
1027
5352ff65
ID		 1028static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1029 struct link_qual *qual, u8 vgc_level)
eb20b4e8 1030{
5352ff65 1031 if (qual->vgc_level != vgc_level) {
eb20b4e8 1032 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 1033 qual->vgc_level = vgc_level;
1034 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 1035 }
1036}
1037
5352ff65
ID		 1038static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1039 struct link_qual *qual)
95ea3627 1040{
5352ff65 1041 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 1042}
1043
5352ff65
ID		 1044static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1045 struct link_qual *qual, const u32 count)
95ea3627 1046{
95ea3627
ID		 1047 u8 up_bound;
1048 u8 low_bound;
1049
95ea3627
ID		 1050 /*
1051 * Determine r17 bounds.
1052 */
1497074a 1053 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1054 low_bound = 0x28;
1055 up_bound = 0x48;
1056 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1057 low_bound += 0x10;
1058 up_bound += 0x10;
1059 }
1060 } else {
1061 low_bound = 0x20;
1062 up_bound = 0x40;
1063 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1064 low_bound += 0x10;
1065 up_bound += 0x10;
1066 }
1067 }
1068
6bb40dd1
ID		 1069 /*
1070 * If we are not associated, we should go straight to the
1071 * dynamic CCA tuning.
1072 */
1073 if (!rt2x00dev->intf_associated)
1074 goto dynamic_cca_tune;
1075
95ea3627
ID		 1076 /*
1077 * Special big-R17 for very short distance
1078 */
5352ff65
ID		 1079 if (qual->rssi >= -35) {
1080 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 1081 return;
1082 }
1083
1084 /*
1085 * Special big-R17 for short distance
1086 */
5352ff65
ID		 1087 if (qual->rssi >= -58) {
1088 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1089 return;
1090 }
1091
1092 /*
1093 * Special big-R17 for middle-short distance
1094 */
5352ff65
ID		 1095 if (qual->rssi >= -66) {
1096 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 1097 return;
1098 }
1099
1100 /*
1101 * Special mid-R17 for middle distance
1102 */
5352ff65
ID		 1103 if (qual->rssi >= -74) {
1104 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 1105 return;
1106 }
1107
1108 /*
1109 * Special case: Change up_bound based on the rssi.
1110 * Lower up_bound when rssi is weaker then -74 dBm.
1111 */
5352ff65 1112 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1113 if (low_bound > up_bound)
1114 up_bound = low_bound;
1115
5352ff65
ID		 1116 if (qual->vgc_level > up_bound) {
1117 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1118 return;
1119 }
1120
6bb40dd1
ID		 1121dynamic_cca_tune:
1122
95ea3627
ID		 1123 /*
1124 * r17 does not yet exceed upper limit, continue and base
1125 * the r17 tuning on the false CCA count.
1126 */
5352ff65
ID		 1127 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1128 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1129 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1130 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 1131}
1132
1133/*
a7f3a06c 1134 * Firmware functions
95ea3627
ID		 1135 */
1136static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1137{
49e721ec 1138 u16 chip;
95ea3627
ID		 1139 char *fw_name;
1140
49e721ec
GW		 1141 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1142 switch (chip) {
1143 case RT2561_PCI_ID:
95ea3627
ID		 1144 fw_name = FIRMWARE_RT2561;
1145 break;
49e721ec 1146 case RT2561s_PCI_ID:
95ea3627
ID		 1147 fw_name = FIRMWARE_RT2561s;
1148 break;
49e721ec 1149 case RT2661_PCI_ID:
95ea3627
ID		 1150 fw_name = FIRMWARE_RT2661;
1151 break;
1152 default:
1153 fw_name = NULL;
1154 break;
1155 }
1156
1157 return fw_name;
1158}
1159
0cbe0064
ID		 1160static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1161 const u8 *data, const size_t len)
a7f3a06c 1162{
0cbe0064 1163 u16 fw_crc;
a7f3a06c
ID		 1164 u16 crc;
1165
1166 /*
0cbe0064
ID		 1167 * Only support 8kb firmware files.
1168 */
1169 if (len != 8192)
1170 return FW_BAD_LENGTH;
1171
1172 /*
b34e620f
TLSC		 1173 * The last 2 bytes in the firmware array are the crc checksum itself.
1174 * This means that we should never pass those 2 bytes to the crc
a7f3a06c
ID		 1175 * algorithm.
1176 */
0cbe0064
ID		 1177 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1178
1179 /*
1180 * Use the crc itu-t algorithm.
1181 */
a7f3a06c
ID		 1182 crc = crc_itu_t(0, data, len - 2);
1183 crc = crc_itu_t_byte(crc, 0);
1184 crc = crc_itu_t_byte(crc, 0);
1185
0cbe0064 1186 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1187}
1188
0cbe0064
ID		 1189static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1190 const u8 *data, const size_t len)
95ea3627
ID		 1191{
1192 int i;
1193 u32 reg;
1194
1195 /*
1196 * Wait for stable hardware.
1197 */
1198 for (i = 0; i < 100; i++) {
1199 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1200 if (reg)
1201 break;
1202 msleep(1);
1203 }
1204
1205 if (!reg) {
1206 ERROR(rt2x00dev, "Unstable hardware.\n");
1207 return -EBUSY;
1208 }
1209
1210 /*
1211 * Prepare MCU and mailbox for firmware loading.
1212 */
1213 reg = 0;
1214 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1215 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1216 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1217 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1218 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1219
1220 /*
1221 * Write firmware to device.
1222 */
1223 reg = 0;
1224 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1225 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1226 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1227
1228 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1229 data, len);
1230
1231 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1232 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1233
1234 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1235 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1236
1237 for (i = 0; i < 100; i++) {
1238 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1239 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1240 break;
1241 msleep(1);
1242 }
1243
1244 if (i == 100) {
1245 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1246 return -EBUSY;
1247 }
1248
e6d3e902
ID		 1249 /*
1250 * Hardware needs another millisecond before it is ready.
1251 */
1252 msleep(1);
1253
95ea3627
ID		 1254 /*
1255 * Reset MAC and BBP registers.
1256 */
1257 reg = 0;
1258 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1259 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1260 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1261
1262 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1263 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1264 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1265 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1266
1267 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1268 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1269 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1270
1271 return 0;
1272}
1273
a7f3a06c
ID		 1274/*
1275 * Initialization functions.
1276 */
798b7adb 1277static bool rt61pci_get_entry_state(struct queue_entry *entry)
95ea3627 1278{
b8be63ff 1279 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1280 u32 word;
1281
798b7adb
ID		 1282 if (entry->queue->qid == QID_RX) {
1283 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 1284
798b7adb
ID		 1285 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1286 } else {
1287 rt2x00_desc_read(entry_priv->desc, 0, &word);
1288
1289 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1290 rt2x00_get_field32(word, TXD_W0_VALID));
1291 }
95ea3627
ID		 1292}
1293
798b7adb 1294static void rt61pci_clear_entry(struct queue_entry *entry)
95ea3627 1295{
b8be63ff 1296 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 1297 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 1298 u32 word;
1299
798b7adb
ID		 1300 if (entry->queue->qid == QID_RX) {
1301 rt2x00_desc_read(entry_priv->desc, 5, &word);
1302 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1303 skbdesc->skb_dma);
1304 rt2x00_desc_write(entry_priv->desc, 5, word);
1305
1306 rt2x00_desc_read(entry_priv->desc, 0, &word);
1307 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1308 rt2x00_desc_write(entry_priv->desc, 0, word);
1309 } else {
1310 rt2x00_desc_read(entry_priv->desc, 0, &word);
1311 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1312 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1313 rt2x00_desc_write(entry_priv->desc, 0, word);
1314 }
95ea3627
ID		 1315}
1316
181d6902 1317static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1318{
b8be63ff 1319 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 1320 u32 reg;
1321
95ea3627
ID		 1322 /*
1323 * Initialize registers.
1324 */
1325 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1326 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1327 rt2x00dev->tx[0].limit);
95ea3627 1328 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1329 rt2x00dev->tx[1].limit);
95ea3627 1330 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1331 rt2x00dev->tx[2].limit);
95ea3627 1332 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1333 rt2x00dev->tx[3].limit);
95ea3627
ID		 1334 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1335
1336 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1337 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1338 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1339 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1340
b8be63ff 1341 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1342 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
30b3a23c 1343 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
b8be63ff 1344 entry_priv->desc_dma);
95ea3627
ID		 1345 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1346
b8be63ff 1347 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1348 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
30b3a23c 1349 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
b8be63ff 1350 entry_priv->desc_dma);
95ea3627
ID		 1351 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1352
b8be63ff 1353 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1354 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
30b3a23c 1355 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
b8be63ff 1356 entry_priv->desc_dma);
95ea3627
ID		 1357 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1358
b8be63ff 1359 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1360 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
30b3a23c 1361 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
b8be63ff 1362 entry_priv->desc_dma);
95ea3627
ID		 1363 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1364
95ea3627 1365 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1366 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1367 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1368 rt2x00dev->rx->desc_size / 4);
1369 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1370 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1371
b8be63ff 1372 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1373 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
30b3a23c 1374 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
b8be63ff 1375 entry_priv->desc_dma);
95ea3627
ID		 1376 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1377
1378 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1379 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1380 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1381 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1382 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
95ea3627
ID		 1383 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1384
1385 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1386 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1387 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1388 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1389 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
95ea3627
ID		 1390 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1391
1392 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1393 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1394 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1395
1396 return 0;
1397}
1398
1399static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1400{
1401 u32 reg;
1402
1403 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1404 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1405 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1406 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1407 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1408
1409 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1410 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1411 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1412 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1413 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1414 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1415 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1416 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1417 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1418 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1419
1420 /*
1421 * CCK TXD BBP registers
1422 */
1423 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1424 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1425 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1426 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1427 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1428 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1429 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1430 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1431 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1432 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1433
1434 /*
1435 * OFDM TXD BBP registers
1436 */
1437 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1438 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1439 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1440 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1441 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1442 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1443 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1444 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1445
1446 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1447 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1448 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1449 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1450 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1451 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1452
1453 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1454 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1455 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1456 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1457 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1458 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1459
1f909162
ID		 1460 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1461 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1462 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1463 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1464 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1465 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1466 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1467 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1468
95ea3627
ID		 1469 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1470
1471 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1472
1473 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1474 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1475 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1476
1477 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1478
1479 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1480 return -EBUSY;
1481
1482 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1483
1484 /*
1485 * Invalidate all Shared Keys (SEC_CSR0),
1486 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1487 */
1488 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1489 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1490 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1491
1492 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1493 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1494 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1495 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1496
1497 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1498
1499 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1500
1501 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1502
6bb40dd1
ID		 1503 /*
1504 * Clear all beacons
1505 * For the Beacon base registers we only need to clear
1506 * the first byte since that byte contains the VALID and OWNER
1507 * bits which (when set to 0) will invalidate the entire beacon.
1508 */
1509 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1510 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1511 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1512 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1513
95ea3627
ID		 1514 /*
1515 * We must clear the error counters.
1516 * These registers are cleared on read,
1517 * so we may pass a useless variable to store the value.
1518 */
1519 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1520 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1521 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1522
1523 /*
1524 * Reset MAC and BBP registers.
1525 */
1526 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1527 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1528 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1529 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1530
1531 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1532 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1533 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1534 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1535
1536 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1537 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1538 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1539
1540 return 0;
1541}
1542
2b08da3f 1543static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1544{
1545 unsigned int i;
95ea3627
ID		 1546 u8 value;
1547
1548 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1549 rt61pci_bbp_read(rt2x00dev, 0, &value);
1550 if ((value != 0xff) && (value != 0x00))
2b08da3f 1551 return 0;
95ea3627
ID		 1552 udelay(REGISTER_BUSY_DELAY);
1553 }
1554
1555 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1556 return -EACCES;
2b08da3f
ID		 1557}
1558
1559static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1560{
1561 unsigned int i;
1562 u16 eeprom;
1563 u8 reg_id;
1564 u8 value;
1565
1566 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1567 return -EACCES;
95ea3627 1568
95ea3627
ID		 1569 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1570 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1571 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1572 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1573 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1574 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1575 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1576 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1577 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1578 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1579 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1580 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1581 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1582 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1583 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1584 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1585 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1586 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1587 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1588 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1589 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1590 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1591 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1592 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1593
95ea3627
ID		 1594 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1595 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1596
1597 if (eeprom != 0xffff && eeprom != 0x0000) {
1598 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1599 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1600 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1601 }
1602 }
95ea3627
ID		 1603
1604 return 0;
1605}
1606
1607/*
1608 * Device state switch handlers.
1609 */
1610static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1611 enum dev_state state)
1612{
1613 u32 reg;
1614
1615 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1616 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1617 (state == STATE_RADIO_RX_OFF) ||
1618 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1619 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1620}
1621
1622static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1623 enum dev_state state)
1624{
1625 int mask = (state == STATE_RADIO_IRQ_OFF);
1626 u32 reg;
1627
1628 /*
1629 * When interrupts are being enabled, the interrupt registers
1630 * should clear the register to assure a clean state.
1631 */
1632 if (state == STATE_RADIO_IRQ_ON) {
1633 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1634 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1635
1636 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1637 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1638 }
1639
1640 /*
1641 * Only toggle the interrupts bits we are going to use.
1642 * Non-checked interrupt bits are disabled by default.
1643 */
1644 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1645 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1646 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1647 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1648 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1649 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1650
1651 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1652 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1653 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1654 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1655 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1656 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1657 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1658 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1659 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1660 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1661}
1662
1663static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1664{
1665 u32 reg;
1666
1667 /*
1668 * Initialize all registers.
1669 */
2b08da3f
ID		 1670 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1671 rt61pci_init_registers(rt2x00dev) ||
1672 rt61pci_init_bbp(rt2x00dev)))
95ea3627 1673 return -EIO;
95ea3627
ID		 1674
1675 /*
1676 * Enable RX.
1677 */
1678 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1679 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1680 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1681
95ea3627
ID		 1682 return 0;
1683}
1684
1685static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1686{
95ea3627 1687 /*
a2c9b652 1688 * Disable power
95ea3627 1689 */
a2c9b652 1690 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1691}
1692
1693static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1694{
9655a6ec 1695 u32 reg, reg2;
95ea3627
ID		 1696 unsigned int i;
1697 char put_to_sleep;
95ea3627
ID		 1698
1699 put_to_sleep = (state != STATE_AWAKE);
1700
1701 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1702 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1703 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1704 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1705
1706 /*
1707 * Device is not guaranteed to be in the requested state yet.
1708 * We must wait until the register indicates that the
1709 * device has entered the correct state.
1710 */
1711 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 1712 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg2);
1713 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
2b08da3f 1714 if (state == !put_to_sleep)
95ea3627 1715 return 0;
9655a6ec 1716 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1717 msleep(10);
1718 }
1719
95ea3627
ID		 1720 return -EBUSY;
1721}
1722
1723static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1724 enum dev_state state)
1725{
1726 int retval = 0;
1727
1728 switch (state) {
1729 case STATE_RADIO_ON:
1730 retval = rt61pci_enable_radio(rt2x00dev);
1731 break;
1732 case STATE_RADIO_OFF:
1733 rt61pci_disable_radio(rt2x00dev);
1734 break;
1735 case STATE_RADIO_RX_ON:
61667d8d 1736 case STATE_RADIO_RX_ON_LINK:
95ea3627 1737 case STATE_RADIO_RX_OFF:
61667d8d 1738 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1739 rt61pci_toggle_rx(rt2x00dev, state);
1740 break;
1741 case STATE_RADIO_IRQ_ON:
1742 case STATE_RADIO_IRQ_OFF:
1743 rt61pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1744 break;
1745 case STATE_DEEP_SLEEP:
1746 case STATE_SLEEP:
1747 case STATE_STANDBY:
1748 case STATE_AWAKE:
1749 retval = rt61pci_set_state(rt2x00dev, state);
1750 break;
1751 default:
1752 retval = -ENOTSUPP;
1753 break;
1754 }
1755
2b08da3f
ID		 1756 if (unlikely(retval))
1757 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1758 state, retval);
1759
95ea3627
ID		 1760 return retval;
1761}
1762
1763/*
1764 * TX descriptor initialization
1765 */
1766static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
61e754f4
ID		 1767 struct sk_buff *skb,
1768 struct txentry_desc *txdesc)
95ea3627 1769{
181d6902 1770 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
85b7a8b3
GW		 1771 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1772 __le32 *txd = entry_priv->desc;
95ea3627
ID		 1773 u32 word;
1774
1775 /*
1776 * Start writing the descriptor words.
1777 */
1778 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1779 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1780 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1781 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1782 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
61e754f4 1783 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1784 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1785 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
4de36fe5 1786 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
95ea3627
ID		 1787 rt2x00_desc_write(txd, 1, word);
1788
1789 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1790 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1791 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1792 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1793 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1794 rt2x00_desc_write(txd, 2, word);
1795
61e754f4 1796 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1797 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1798 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
61e754f4
ID		 1799 }
1800
95ea3627 1801 rt2x00_desc_read(txd, 5, &word);
4de36fe5
GW		 1802 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1803 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1804 skbdesc->entry->entry_idx);
95ea3627 1805 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1806 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1807 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1808 rt2x00_desc_write(txd, 5, word);
1809
6b97cb04
GW		 1810 if (txdesc->queue != QID_BEACON) {
1811 rt2x00_desc_read(txd, 6, &word);
1812 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1813 skbdesc->skb_dma);
1814 rt2x00_desc_write(txd, 6, word);
4de36fe5 1815
d7bafff3 1816 rt2x00_desc_read(txd, 11, &word);
df624ca5
GW		 1817 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1818 txdesc->length);
d7bafff3
AB		 1819 rt2x00_desc_write(txd, 11, word);
1820 }
95ea3627 1821
e01f1ec3
GW		 1822 /*
1823 * Writing TXD word 0 must the last to prevent a race condition with
1824 * the device, whereby the device may take hold of the TXD before we
1825 * finished updating it.
1826 */
95ea3627
ID		 1827 rt2x00_desc_read(txd, 0, &word);
1828 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1829 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1830 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1831 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1832 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1833 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1834 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1835 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1836 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1837 (txdesc->rate_mode == RATE_MODE_OFDM));
181d6902 1838 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1839 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1840 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
61e754f4
ID		 1841 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1842 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1843 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1844 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1845 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
df624ca5 1846 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
95ea3627 1847 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1848 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
61e754f4 1849 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627 1850 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1851
1852 /*
1853 * Register descriptor details in skb frame descriptor.
1854 */
1855 skbdesc->desc = txd;
1856 skbdesc->desc_len =
1857 (txdesc->queue == QID_BEACON) ? TXINFO_SIZE : TXD_DESC_SIZE;
95ea3627
ID		 1858}
1859
1860/*
1861 * TX data initialization
1862 */
f224f4ef
GW		 1863static void rt61pci_write_beacon(struct queue_entry *entry,
1864 struct txentry_desc *txdesc)
bd88a781
ID		 1865{
1866 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
85b7a8b3 1867 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
bd88a781
ID		 1868 unsigned int beacon_base;
1869 u32 reg;
1870
1871 /*
1872 * Disable beaconing while we are reloading the beacon data,
1873 * otherwise we might be sending out invalid data.
1874 */
1875 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781
ID		 1876 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1877 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1878
5c3b685c
GW		 1879 /*
1880 * Write the TX descriptor for the beacon.
1881 */
1882 rt61pci_write_tx_desc(rt2x00dev, entry->skb, txdesc);
1883
1884 /*
1885 * Dump beacon to userspace through debugfs.
1886 */
1887 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1888
bd88a781
ID		 1889 /*
1890 * Write entire beacon with descriptor to register.
1891 */
1892 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
85b7a8b3
GW		 1893 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
1894 entry_priv->desc, TXINFO_SIZE);
1895 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
bd88a781
ID		 1896 entry->skb->data, entry->skb->len);
1897
d61cb266
GW		 1898 /*
1899 * Enable beaconing again.
1900 *
1901 * For Wi-Fi faily generated beacons between participating
1902 * stations. Set TBTT phase adaptive adjustment step to 8us.
1903 */
1904 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1905
1906 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1907 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1908 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1909 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1910
bd88a781
ID		 1911 /*
1912 * Clean up beacon skb.
1913 */
1914 dev_kfree_skb_any(entry->skb);
1915 entry->skb = NULL;
1916}
1917
95ea3627 1918static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1919 const enum data_queue_qid queue)
95ea3627
ID		 1920{
1921 u32 reg;
1922
95ea3627 1923 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
e58c6aca
ID		 1924 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1925 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1926 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1927 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
95ea3627
ID		 1928 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1929}
1930
a2c9b652
ID		 1931static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1932 const enum data_queue_qid qid)
1933{
1934 u32 reg;
1935
1936 if (qid == QID_BEACON) {
1937 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1938 return;
1939 }
1940
1941 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1942 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE));
1943 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK));
1944 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI));
1945 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO));
1946 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1947}
1948
95ea3627
ID		 1949/*
1950 * RX control handlers
1951 */
1952static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1953{
ba2ab471 1954 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1955 u8 lna;
1956
1957 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1958 switch (lna) {
1959 case 3:
ba2ab471 1960 offset += 90;
95ea3627
ID		 1961 break;
1962 case 2:
ba2ab471 1963 offset += 74;
95ea3627
ID		 1964 break;
1965 case 1:
ba2ab471 1966 offset += 64;
95ea3627
ID		 1967 break;
1968 default:
1969 return 0;
1970 }
1971
8318d78a 1972 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1973 if (lna == 3 || lna == 2)
1974 offset += 10;
95ea3627
ID		 1975 }
1976
1977 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1978}
1979
181d6902 1980static void rt61pci_fill_rxdone(struct queue_entry *entry,
55887511 1981 struct rxdone_entry_desc *rxdesc)
95ea3627 1982{
61e754f4 1983 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1984 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1985 u32 word0;
1986 u32 word1;
1987
b8be63ff
ID		 1988 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1989 rt2x00_desc_read(entry_priv->desc, 1, &word1);
95ea3627 1990
4150c572 1991 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1992 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1993
78b8f3b0
GW		 1994 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1995 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
61e754f4
ID		 1996
1997 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 1998 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
1999 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
74415edb
ID		 2000 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
2001
61e754f4 2002 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
74415edb 2003 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
61e754f4
ID		 2004
2005 /*
2006 * Hardware has stripped IV/EIV data from 802.11 frame during
b34e620f 2007 * decryption. It has provided the data separately but rt2x00lib
61e754f4
ID		 2008 * should decide if it should be reinserted.
2009 */
2010 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2011
2012 /*
2013 * FIXME: Legacy driver indicates that the frame does
2014 * contain the Michael Mic. Unfortunately, in rt2x00
2015 * the MIC seems to be missing completely...
2016 */
2017 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2018
2019 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2020 rxdesc->flags |= RX_FLAG_DECRYPTED;
2021 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2022 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2023 }
2024
95ea3627
ID		 2025 /*
2026 * Obtain the status about this packet.
89993890
ID		 2027 * When frame was received with an OFDM bitrate,
2028 * the signal is the PLCP value. If it was received with
2029 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 2030 */
181d6902 2031 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
61e754f4 2032 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
181d6902 2033 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 2034
19d30e02
ID		 2035 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2036 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 2037 else
2038 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 2039 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2040 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 2041}
2042
2043/*
2044 * Interrupt functions.
2045 */
2046static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2047{
181d6902
ID		 2048 struct data_queue *queue;
2049 struct queue_entry *entry;
2050 struct queue_entry *entry_done;
b8be63ff 2051 struct queue_entry_priv_pci *entry_priv;
181d6902 2052 struct txdone_entry_desc txdesc;
95ea3627
ID		 2053 u32 word;
2054 u32 reg;
95ea3627
ID		 2055 int type;
2056 int index;
e6474c3c 2057 int i;
95ea3627
ID		 2058
2059 /*
e6474c3c
ID		 2060 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2061 * at most X times and also stop processing once the TX_STA_FIFO_VALID
2062 * flag is not set anymore.
2063 *
2064 * The legacy drivers use X=TX_RING_SIZE but state in a comment
2065 * that the TX_STA_FIFO stack has a size of 16. We stick to our
2066 * tx ring size for now.
95ea3627 2067 */
e6474c3c 2068 for (i = 0; i < TX_ENTRIES; i++) {
95ea3627
ID		 2069 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2070 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2071 break;
2072
95ea3627
ID		 2073 /*
2074 * Skip this entry when it contains an invalid
181d6902 2075 * queue identication number.
95ea3627
ID		 2076 */
2077 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 2078 queue = rt2x00queue_get_queue(rt2x00dev, type);
2079 if (unlikely(!queue))
95ea3627
ID		 2080 continue;
2081
2082 /*
2083 * Skip this entry when it contains an invalid
2084 * index number.
2085 */
2086 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 2087 if (unlikely(index >= queue->limit))
95ea3627
ID		 2088 continue;
2089
181d6902 2090 entry = &queue->entries[index];
b8be63ff
ID		 2091 entry_priv = entry->priv_data;
2092 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 2093
2094 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2095 !rt2x00_get_field32(word, TXD_W0_VALID))
2096 return;
2097
181d6902 2098 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 2099 while (entry != entry_done) {
181d6902
ID		 2100 /* Catch up.
2101 * Just report any entries we missed as failed.
2102 */
62bc060b 2103 WARNING(rt2x00dev,
181d6902
ID		 2104 "TX status report missed for entry %d\n",
2105 entry_done->entry_idx);
2106
fb55f4d1
ID		 2107 txdesc.flags = 0;
2108 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
181d6902
ID		 2109 txdesc.retry = 0;
2110
0b8004aa 2111 rt2x00pci_txdone(entry_done, &txdesc);
181d6902 2112 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 2113 }
2114
95ea3627
ID		 2115 /*
2116 * Obtain the status about this packet.
2117 */
fb55f4d1
ID		 2118 txdesc.flags = 0;
2119 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2120 case 0: /* Success, maybe with retry */
2121 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2122 break;
2123 case 6: /* Failure, excessive retries */
2124 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2125 /* Don't break, this is a failed frame! */
2126 default: /* Failure */
2127 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2128 }
181d6902 2129 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 2130
e1b4d7b7
ID		 2131 /*
2132 * the frame was retried at least once
2133 * -> hw used fallback rates
2134 */
2135 if (txdesc.retry)
2136 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2137
0b8004aa 2138 rt2x00pci_txdone(entry, &txdesc);
95ea3627
ID		 2139 }
2140}
2141
9e189446
GW		 2142static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2143{
2144 struct ieee80211_conf conf = { .flags = 0 };
2145 struct rt2x00lib_conf libconf = { .conf = &conf };
2146
2147 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2148}
2149
95ea3627
ID		 2150static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2151{
2152 struct rt2x00_dev *rt2x00dev = dev_instance;
2153 u32 reg_mcu;
2154 u32 reg;
2155
2156 /*
2157 * Get the interrupt sources & saved to local variable.
2158 * Write register value back to clear pending interrupts.
2159 */
2160 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2161 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2162
2163 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2164 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2165
2166 if (!reg && !reg_mcu)
2167 return IRQ_NONE;
2168
0262ab0d 2169 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
95ea3627
ID		 2170 return IRQ_HANDLED;
2171
2172 /*
2173 * Handle interrupts, walk through all bits
2174 * and run the tasks, the bits are checked in order of
2175 * priority.
2176 */
2177
2178 /*
2179 * 1 - Rx ring done interrupt.
2180 */
2181 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2182 rt2x00pci_rxdone(rt2x00dev);
2183
2184 /*
2185 * 2 - Tx ring done interrupt.
2186 */
2187 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2188 rt61pci_txdone(rt2x00dev);
2189
2190 /*
2191 * 3 - Handle MCU command done.
2192 */
2193 if (reg_mcu)
2194 rt2x00pci_register_write(rt2x00dev,
2195 M2H_CMD_DONE_CSR, 0xffffffff);
2196
9e189446
GW		 2197 /*
2198 * 4 - MCU Autowakeup interrupt.
2199 */
2200 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2201 rt61pci_wakeup(rt2x00dev);
2202
95ea3627
ID		 2203 return IRQ_HANDLED;
2204}
2205
2206/*
2207 * Device probe functions.
2208 */
2209static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2210{
2211 struct eeprom_93cx6 eeprom;
2212 u32 reg;
2213 u16 word;
2214 u8 *mac;
2215 s8 value;
2216
2217 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2218
2219 eeprom.data = rt2x00dev;
2220 eeprom.register_read = rt61pci_eepromregister_read;
2221 eeprom.register_write = rt61pci_eepromregister_write;
2222 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2223 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2224 eeprom.reg_data_in = 0;
2225 eeprom.reg_data_out = 0;
2226 eeprom.reg_data_clock = 0;
2227 eeprom.reg_chip_select = 0;
2228
2229 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2230 EEPROM_SIZE / sizeof(u16));
2231
2232 /*
2233 * Start validation of the data that has been read.
2234 */
2235 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2236 if (!is_valid_ether_addr(mac)) {
2237 random_ether_addr(mac);
e174961c 2238 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 2239 }
2240
2241 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2242 if (word == 0xffff) {
2243 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 2244 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2245 ANTENNA_B);
2246 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2247 ANTENNA_B);
95ea3627
ID		 2248 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2249 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2250 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2251 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2252 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2253 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2254 }
2255
2256 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2257 if (word == 0xffff) {
2258 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2259 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
91581b62
ID		 2260 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2261 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
95ea3627
ID		 2262 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2263 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2264 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2265 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2266 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2267 }
2268
2269 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2270 if (word == 0xffff) {
2271 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2272 LED_MODE_DEFAULT);
2273 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2274 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2275 }
2276
2277 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2278 if (word == 0xffff) {
2279 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2280 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2281 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2282 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2283 }
2284
2285 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2286 if (word == 0xffff) {
2287 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2288 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2289 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2290 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2291 } else {
2292 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2293 if (value < -10 || value > 10)
2294 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2295 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2296 if (value < -10 || value > 10)
2297 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2298 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2299 }
2300
2301 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2302 if (word == 0xffff) {
2303 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2304 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2305 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 2306 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 2307 } else {
2308 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2309 if (value < -10 || value > 10)
2310 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2311 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2312 if (value < -10 || value > 10)
2313 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2314 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2315 }
2316
2317 return 0;
2318}
2319
2320static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2321{
2322 u32 reg;
2323 u16 value;
2324 u16 eeprom;
95ea3627
ID		 2325
2326 /*
2327 * Read EEPROM word for configuration.
2328 */
2329 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2330
2331 /*
2332 * Identify RF chipset.
95ea3627 2333 */
95ea3627
ID		 2334 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2335 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
49e721ec
GW		 2336 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2337 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
95ea3627 2338
5122d898
GW		 2339 if (!rt2x00_rf(rt2x00dev, RF5225) &&
2340 !rt2x00_rf(rt2x00dev, RF5325) &&
2341 !rt2x00_rf(rt2x00dev, RF2527) &&
2342 !rt2x00_rf(rt2x00dev, RF2529)) {
95ea3627
ID		 2343 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2344 return -ENODEV;
2345 }
2346
e4cd2ff8 2347 /*
49513481 2348 * Determine number of antennas.
e4cd2ff8
ID		 2349 */
2350 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2351 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2352
95ea3627
ID		 2353 /*
2354 * Identify default antenna configuration.
2355 */
addc81bd 2356 rt2x00dev->default_ant.tx =
95ea3627 2357 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 2358 rt2x00dev->default_ant.rx =
95ea3627
ID		 2359 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2360
2361 /*
2362 * Read the Frame type.
2363 */
2364 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2365 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2366
95ea3627 2367 /*
b34e620f 2368 * Detect if this device has a hardware controlled radio.
95ea3627
ID		 2369 */
2370 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 2371 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 2372
2373 /*
2374 * Read frequency offset and RF programming sequence.
2375 */
2376 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2377 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2378 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2379
2380 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2381
2382 /*
2383 * Read external LNA informations.
2384 */
2385 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2386
2387 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2388 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2389 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2390 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2391
e4cd2ff8 2392 /*
b34e620f 2393 * When working with a RF2529 chip without double antenna,
e4cd2ff8
ID		 2394 * the antenna settings should be gathered from the NIC
2395 * eeprom word.
2396 */
5122d898 2397 if (rt2x00_rf(rt2x00dev, RF2529) &&
e4cd2ff8 2398 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
91581b62
ID		 2399 rt2x00dev->default_ant.rx =
2400 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2401 rt2x00dev->default_ant.tx =
2402 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
e4cd2ff8
ID		 2403
2404 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2405 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2406 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2407 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2408 }
2409
95ea3627
ID		 2410 /*
2411 * Store led settings, for correct led behaviour.
2412 * If the eeprom value is invalid,
2413 * switch to default led mode.
2414 */
771fd565 2415#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627 2416 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
a9450b70
ID		 2417 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2418
475433be
ID		 2419 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2420 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2421 if (value == LED_MODE_SIGNAL_STRENGTH)
2422 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2423 LED_TYPE_QUALITY);
95ea3627 2424
a9450b70
ID		 2425 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2426 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2427 rt2x00_get_field16(eeprom,
2428 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2429 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2430 rt2x00_get_field16(eeprom,
2431 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2432 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2433 rt2x00_get_field16(eeprom,
2434 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2435 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2436 rt2x00_get_field16(eeprom,
2437 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2438 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2439 rt2x00_get_field16(eeprom,
2440 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2441 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2442 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2443 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2444 rt2x00_get_field16(eeprom,
2445 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2446 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2447 rt2x00_get_field16(eeprom,
2448 EEPROM_LED_POLARITY_RDY_A));
771fd565 2449#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 2450
2451 return 0;
2452}
2453
2454/*
2455 * RF value list for RF5225 & RF5325
2456 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2457 */
2458static const struct rf_channel rf_vals_noseq[] = {
2459 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2460 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2461 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2462 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2463 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2464 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2465 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2466 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2467 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2468 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2469 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2470 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2471 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2472 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2473
2474 /* 802.11 UNI / HyperLan 2 */
2475 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2476 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2477 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2478 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2479 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2480 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2481 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2482 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2483
2484 /* 802.11 HyperLan 2 */
2485 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2486 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2487 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2488 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2489 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2490 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2491 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2492 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2493 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2494 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2495
2496 /* 802.11 UNII */
2497 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2498 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2499 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2500 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2501 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2502 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2503
2504 /* MMAC(Japan)J52 ch 34,38,42,46 */
2505 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2506 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2507 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2508 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2509};
2510
2511/*
2512 * RF value list for RF5225 & RF5325
2513 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2514 */
2515static const struct rf_channel rf_vals_seq[] = {
2516 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2517 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2518 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2519 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2520 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2521 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2522 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2523 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2524 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2525 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2526 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2527 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2528 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2529 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2530
2531 /* 802.11 UNI / HyperLan 2 */
2532 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2533 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2534 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2535 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2536 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2537 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2538 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2539 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2540
2541 /* 802.11 HyperLan 2 */
2542 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2543 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2544 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2545 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2546 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2547 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2548 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2549 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2550 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2551 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2552
2553 /* 802.11 UNII */
2554 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2555 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2556 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2557 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2558 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2559 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2560
2561 /* MMAC(Japan)J52 ch 34,38,42,46 */
2562 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2563 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2564 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2565 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2566};
2567
8c5e7a5f 2568static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2569{
2570 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2571 struct channel_info *info;
2572 char *tx_power;
95ea3627
ID		 2573 unsigned int i;
2574
93b6bd26
GW		 2575 /*
2576 * Disable powersaving as default.
2577 */
2578 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2579
95ea3627
ID		 2580 /*
2581 * Initialize all hw fields.
2582 */
2583 rt2x00dev->hw->flags =
566bfe5a 2584 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2585 IEEE80211_HW_SIGNAL_DBM |
2586 IEEE80211_HW_SUPPORTS_PS |
2587 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2588
14a3bf89 2589 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2590 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2591 rt2x00_eeprom_addr(rt2x00dev,
2592 EEPROM_MAC_ADDR_0));
2593
95ea3627 2594 /*
e1b4d7b7
ID		 2595 * As rt61 has a global fallback table we cannot specify
2596 * more then one tx rate per frame but since the hw will
2597 * try several rates (based on the fallback table) we should
2598 * still initialize max_rates to the maximum number of rates
2599 * we are going to try. Otherwise mac80211 will truncate our
2600 * reported tx rates and the rc algortihm will end up with
2601 * incorrect data.
2602 */
2603 rt2x00dev->hw->max_rates = 7;
2604 rt2x00dev->hw->max_rate_tries = 1;
2605
2606 /*
95ea3627
ID		 2607 * Initialize hw_mode information.
2608 */
31562e80
ID		 2609 spec->supported_bands = SUPPORT_BAND_2GHZ;
2610 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2611
2612 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2613 spec->num_channels = 14;
2614 spec->channels = rf_vals_noseq;
2615 } else {
2616 spec->num_channels = 14;
2617 spec->channels = rf_vals_seq;
2618 }
2619
5122d898 2620 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
31562e80 2621 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627 2622 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
8c5e7a5f
ID		 2623 }
2624
2625 /*
2626 * Create channel information array
2627 */
2628 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2629 if (!info)
2630 return -ENOMEM;
2631
2632 spec->channels_info = info;
95ea3627 2633
8c5e7a5f
ID		 2634 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2635 for (i = 0; i < 14; i++)
2636 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2637
8c5e7a5f
ID		 2638 if (spec->num_channels > 14) {
2639 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2640 for (i = 14; i < spec->num_channels; i++)
2641 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2642 }
8c5e7a5f
ID		 2643
2644 return 0;
95ea3627
ID		 2645}
2646
2647static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2648{
2649 int retval;
2650
117839bd
PR		 2651 /*
2652 * Disable power saving.
2653 */
2654 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2655
95ea3627
ID		 2656 /*
2657 * Allocate eeprom data.
2658 */
2659 retval = rt61pci_validate_eeprom(rt2x00dev);
2660 if (retval)
2661 return retval;
2662
2663 retval = rt61pci_init_eeprom(rt2x00dev);
2664 if (retval)
2665 return retval;
2666
2667 /*
2668 * Initialize hw specifications.
2669 */
8c5e7a5f
ID		 2670 retval = rt61pci_probe_hw_mode(rt2x00dev);
2671 if (retval)
2672 return retval;
95ea3627 2673
1afcfd54
IP		 2674 /*
2675 * This device has multiple filters for control frames,
2676 * but has no a separate filter for PS Poll frames.
2677 */
2678 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2679
95ea3627 2680 /*
c4da0048 2681 * This device requires firmware and DMA mapped skbs.
95ea3627 2682 */
066cb637 2683 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
c4da0048 2684 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
008c4482
ID		 2685 if (!modparam_nohwcrypt)
2686 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
95ea3627
ID		 2687
2688 /*
2689 * Set the rssi offset.
2690 */
2691 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2692
2693 return 0;
2694}
2695
2696/*
2697 * IEEE80211 stack callback functions.
2698 */
2af0a570
ID		 2699static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2700 const struct ieee80211_tx_queue_params *params)
2701{
2702 struct rt2x00_dev *rt2x00dev = hw->priv;
2703 struct data_queue *queue;
2704 struct rt2x00_field32 field;
2705 int retval;
2706 u32 reg;
5e790023 2707 u32 offset;
2af0a570
ID		 2708
2709 /*
2710 * First pass the configuration through rt2x00lib, that will
2711 * update the queue settings and validate the input. After that
2712 * we are free to update the registers based on the value
2713 * in the queue parameter.
2714 */
2715 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2716 if (retval)
2717 return retval;
2718
5e790023
ID		 2719 /*
2720 * We only need to perform additional register initialization
b34e620f 2721 * for WMM queues.
5e790023
ID		 2722 */
2723 if (queue_idx >= 4)
2724 return 0;
2725
2af0a570
ID		 2726 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2727
2728 /* Update WMM TXOP register */
5e790023
ID		 2729 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2730 field.bit_offset = (queue_idx & 1) * 16;
2731 field.bit_mask = 0xffff << field.bit_offset;
2732
2733 rt2x00pci_register_read(rt2x00dev, offset, &reg);
2734 rt2x00_set_field32(&reg, field, queue->txop);
2735 rt2x00pci_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2736
2737 /* Update WMM registers */
2738 field.bit_offset = queue_idx * 4;
2739 field.bit_mask = 0xf << field.bit_offset;
2740
2741 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2742 rt2x00_set_field32(&reg, field, queue->aifs);
2743 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2744
2745 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2746 rt2x00_set_field32(&reg, field, queue->cw_min);
2747 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2748
2749 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2750 rt2x00_set_field32(&reg, field, queue->cw_max);
2751 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2752
2753 return 0;
2754}
2755
95ea3627
ID		 2756static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2757{
2758 struct rt2x00_dev *rt2x00dev = hw->priv;
2759 u64 tsf;
2760 u32 reg;
2761
2762 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2763 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2764 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2765 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2766
2767 return tsf;
2768}
2769
95ea3627
ID		 2770static const struct ieee80211_ops rt61pci_mac80211_ops = {
2771 .tx = rt2x00mac_tx,
4150c572
JB		 2772 .start = rt2x00mac_start,
2773 .stop = rt2x00mac_stop,
95ea3627
ID		 2774 .add_interface = rt2x00mac_add_interface,
2775 .remove_interface = rt2x00mac_remove_interface,
2776 .config = rt2x00mac_config,
3a643d24 2777 .configure_filter = rt2x00mac_configure_filter,
930c06f2 2778 .set_tim = rt2x00mac_set_tim,
61e754f4 2779 .set_key = rt2x00mac_set_key,
95ea3627 2780 .get_stats = rt2x00mac_get_stats,
471b3efd 2781 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2782 .conf_tx = rt61pci_conf_tx,
95ea3627 2783 .get_tsf = rt61pci_get_tsf,
e47a5cdd 2784 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 2785};
2786
2787static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2788 .irq_handler = rt61pci_interrupt,
2789 .probe_hw = rt61pci_probe_hw,
2790 .get_firmware_name = rt61pci_get_firmware_name,
0cbe0064 2791 .check_firmware = rt61pci_check_firmware,
95ea3627
ID		 2792 .load_firmware = rt61pci_load_firmware,
2793 .initialize = rt2x00pci_initialize,
2794 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 2795 .get_entry_state = rt61pci_get_entry_state,
2796 .clear_entry = rt61pci_clear_entry,
95ea3627 2797 .set_device_state = rt61pci_set_device_state,
95ea3627 2798 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2799 .link_stats = rt61pci_link_stats,
2800 .reset_tuner = rt61pci_reset_tuner,
2801 .link_tuner = rt61pci_link_tuner,
2802 .write_tx_desc = rt61pci_write_tx_desc,
bd88a781 2803 .write_beacon = rt61pci_write_beacon,
95ea3627 2804 .kick_tx_queue = rt61pci_kick_tx_queue,
a2c9b652 2805 .kill_tx_queue = rt61pci_kill_tx_queue,
95ea3627 2806 .fill_rxdone = rt61pci_fill_rxdone,
61e754f4
ID		 2807 .config_shared_key = rt61pci_config_shared_key,
2808 .config_pairwise_key = rt61pci_config_pairwise_key,
3a643d24 2809 .config_filter = rt61pci_config_filter,
6bb40dd1 2810 .config_intf = rt61pci_config_intf,
72810379 2811 .config_erp = rt61pci_config_erp,
e4ea1c40 2812 .config_ant = rt61pci_config_ant,
95ea3627
ID		 2813 .config = rt61pci_config,
2814};
2815
181d6902
ID		 2816static const struct data_queue_desc rt61pci_queue_rx = {
2817 .entry_num = RX_ENTRIES,
2818 .data_size = DATA_FRAME_SIZE,
2819 .desc_size = RXD_DESC_SIZE,
b8be63ff 2820 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2821};
2822
2823static const struct data_queue_desc rt61pci_queue_tx = {
2824 .entry_num = TX_ENTRIES,
2825 .data_size = DATA_FRAME_SIZE,
2826 .desc_size = TXD_DESC_SIZE,
b8be63ff 2827 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2828};
2829
2830static const struct data_queue_desc rt61pci_queue_bcn = {
6bb40dd1 2831 .entry_num = 4 * BEACON_ENTRIES,
78720897 2832 .data_size = 0, /* No DMA required for beacons */
181d6902 2833 .desc_size = TXINFO_SIZE,
b8be63ff 2834 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2835};
2836
95ea3627 2837static const struct rt2x00_ops rt61pci_ops = {
04d0362e
GW		 2838 .name = KBUILD_MODNAME,
2839 .max_sta_intf = 1,
2840 .max_ap_intf = 4,
2841 .eeprom_size = EEPROM_SIZE,
2842 .rf_size = RF_SIZE,
2843 .tx_queues = NUM_TX_QUEUES,
e6218cc4 2844 .extra_tx_headroom = 0,
04d0362e
GW		 2845 .rx = &rt61pci_queue_rx,
2846 .tx = &rt61pci_queue_tx,
2847 .bcn = &rt61pci_queue_bcn,
2848 .lib = &rt61pci_rt2x00_ops,
2849 .hw = &rt61pci_mac80211_ops,
95ea3627 2850#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 2851 .debugfs = &rt61pci_rt2x00debug,
95ea3627
ID		 2852#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2853};
2854
2855/*
2856 * RT61pci module information.
2857 */
a3aa1884 2858static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
95ea3627
ID		 2859 /* RT2561s */
2860 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2861 /* RT2561 v2 */
2862 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2863 /* RT2661 */
2864 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2865 { 0, }
2866};
2867
2868MODULE_AUTHOR(DRV_PROJECT);
2869MODULE_VERSION(DRV_VERSION);
2870MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2871MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2872 "PCI & PCMCIA chipset based cards");
2873MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2874MODULE_FIRMWARE(FIRMWARE_RT2561);
2875MODULE_FIRMWARE(FIRMWARE_RT2561s);
2876MODULE_FIRMWARE(FIRMWARE_RT2661);
2877MODULE_LICENSE("GPL");
2878
2879static struct pci_driver rt61pci_driver = {
2360157c 2880 .name = KBUILD_MODNAME,
95ea3627
ID		 2881 .id_table = rt61pci_device_table,
2882 .probe = rt2x00pci_probe,
2883 .remove = __devexit_p(rt2x00pci_remove),
2884 .suspend = rt2x00pci_suspend,
2885 .resume = rt2x00pci_resume,
2886};
2887
2888static int __init rt61pci_init(void)
2889{
2890 return pci_register_driver(&rt61pci_driver);
2891}
2892
2893static void __exit rt61pci_exit(void)
2894{
2895 pci_unregister_driver(&rt61pci_driver);
2896}
2897
2898module_init(rt61pci_init);
2899module_exit(rt61pci_exit);
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