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rtlwifi: rtl8192ce: Rework rtl8192ce/phy.c
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rt2x00 / rt61pci.c
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95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
95ea3627
ID		 34#include <linux/pci.h>
35#include <linux/eeprom_93cx6.h>
36
37#include "rt2x00.h"
38#include "rt2x00pci.h"
39#include "rt61pci.h"
40
008c4482
ID		 41/*
42 * Allow hardware encryption to be disabled.
43 */
44static int modparam_nohwcrypt = 0;
45module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
46MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
47
95ea3627
ID		 48/*
49 * Register access.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
b34e620f 55 * between each attempt. When the busy bit is still set at that time,
95ea3627
ID		 56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 */
c9c3b1a5
ID		 59#define WAIT_FOR_BBP(__dev, __reg) \
60 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
61#define WAIT_FOR_RF(__dev, __reg) \
62 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
63#define WAIT_FOR_MCU(__dev, __reg) \
64 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
65 H2M_MAILBOX_CSR_OWNER, (__reg))
95ea3627 66
0e14f6d3 67static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
8ff48a8b
ID		 72 mutex_lock(&rt2x00dev->csr_mutex);
73
95ea3627 74 /*
c9c3b1a5
ID		 75 * Wait until the BBP becomes available, afterwards we
76 * can safely write the new data into the register.
95ea3627 77 */
c9c3b1a5
ID		 78 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
79 reg = 0;
80 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
81 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
82 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
83 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
84
85 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
86 }
8ff48a8b 87
8ff48a8b 88 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 89}
90
0e14f6d3 91static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 92 const unsigned int word, u8 *value)
93{
94 u32 reg;
95
8ff48a8b
ID		 96 mutex_lock(&rt2x00dev->csr_mutex);
97
95ea3627 98 /*
c9c3b1a5
ID		 99 * Wait until the BBP becomes available, afterwards we
100 * can safely write the read request into the register.
101 * After the data has been written, we wait until hardware
102 * returns the correct value, if at any time the register
103 * doesn't become available in time, reg will be 0xffffffff
104 * which means we return 0xff to the caller.
95ea3627 105 */
c9c3b1a5
ID		 106 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
107 reg = 0;
108 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
109 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
110 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 111
c9c3b1a5 112 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
95ea3627 113
c9c3b1a5
ID		 114 WAIT_FOR_BBP(rt2x00dev, &reg);
115 }
95ea3627
ID		 116
117 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
8ff48a8b 118
8ff48a8b 119 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 120}
121
0e14f6d3 122static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 123 const unsigned int word, const u32 value)
124{
125 u32 reg;
95ea3627 126
8ff48a8b
ID		 127 mutex_lock(&rt2x00dev->csr_mutex);
128
c9c3b1a5
ID		 129 /*
130 * Wait until the RF becomes available, afterwards we
131 * can safely write the new data into the register.
132 */
133 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
134 reg = 0;
135 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
136 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
137 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
138 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
139
140 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
141 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 142 }
143
8ff48a8b 144 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 145}
146
0e14f6d3 147static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 148 const u8 command, const u8 token,
149 const u8 arg0, const u8 arg1)
150{
151 u32 reg;
152
8ff48a8b
ID		 153 mutex_lock(&rt2x00dev->csr_mutex);
154
c9c3b1a5
ID		 155 /*
156 * Wait until the MCU becomes available, afterwards we
157 * can safely write the new data into the register.
158 */
159 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
160 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
161 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
162 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
163 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
164 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
165
166 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
167 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
168 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
169 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
170 }
8ff48a8b 171
8ff48a8b
ID		 172 mutex_unlock(&rt2x00dev->csr_mutex);
173
95ea3627
ID		 174}
175
176static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
177{
178 struct rt2x00_dev *rt2x00dev = eeprom->data;
179 u32 reg;
180
181 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
182
183 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
184 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
185 eeprom->reg_data_clock =
186 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
187 eeprom->reg_chip_select =
188 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
189}
190
191static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
192{
193 struct rt2x00_dev *rt2x00dev = eeprom->data;
194 u32 reg = 0;
195
196 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
197 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
198 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
199 !!eeprom->reg_data_clock);
200 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
201 !!eeprom->reg_chip_select);
202
203 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
204}
205
206#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 207static const struct rt2x00debug rt61pci_rt2x00debug = {
208 .owner = THIS_MODULE,
209 .csr = {
743b97ca
ID		 210 .read = rt2x00pci_register_read,
211 .write = rt2x00pci_register_write,
212 .flags = RT2X00DEBUGFS_OFFSET,
213 .word_base = CSR_REG_BASE,
95ea3627
ID		 214 .word_size = sizeof(u32),
215 .word_count = CSR_REG_SIZE / sizeof(u32),
216 },
217 .eeprom = {
218 .read = rt2x00_eeprom_read,
219 .write = rt2x00_eeprom_write,
743b97ca 220 .word_base = EEPROM_BASE,
95ea3627
ID		 221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
223 },
224 .bbp = {
225 .read = rt61pci_bbp_read,
226 .write = rt61pci_bbp_write,
743b97ca 227 .word_base = BBP_BASE,
95ea3627
ID		 228 .word_size = sizeof(u8),
229 .word_count = BBP_SIZE / sizeof(u8),
230 },
231 .rf = {
232 .read = rt2x00_rf_read,
233 .write = rt61pci_rf_write,
743b97ca 234 .word_base = RF_BASE,
95ea3627
ID		 235 .word_size = sizeof(u32),
236 .word_count = RF_SIZE / sizeof(u32),
237 },
238};
239#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
240
95ea3627
ID		 241static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
242{
243 u32 reg;
244
245 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 246 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 247}
95ea3627 248
771fd565 249#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 250static void rt61pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 251 enum led_brightness brightness)
252{
253 struct rt2x00_led *led =
254 container_of(led_cdev, struct rt2x00_led, led_dev);
255 unsigned int enabled = brightness != LED_OFF;
256 unsigned int a_mode =
257 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
258 unsigned int bg_mode =
259 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
260
261 if (led->type == LED_TYPE_RADIO) {
262 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
263 MCU_LEDCS_RADIO_STATUS, enabled);
264
265 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
266 (led->rt2x00dev->led_mcu_reg & 0xff),
267 ((led->rt2x00dev->led_mcu_reg >> 8)));
268 } else if (led->type == LED_TYPE_ASSOC) {
269 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
270 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
271 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
272 MCU_LEDCS_LINK_A_STATUS, a_mode);
273
274 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
275 (led->rt2x00dev->led_mcu_reg & 0xff),
276 ((led->rt2x00dev->led_mcu_reg >> 8)));
277 } else if (led->type == LED_TYPE_QUALITY) {
278 /*
279 * The brightness is divided into 6 levels (0 - 5),
280 * this means we need to convert the brightness
281 * argument into the matching level within that range.
282 */
283 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
284 brightness / (LED_FULL / 6), 0);
285 }
286}
a2e1d52a
ID		 287
288static int rt61pci_blink_set(struct led_classdev *led_cdev,
289 unsigned long *delay_on,
290 unsigned long *delay_off)
291{
292 struct rt2x00_led *led =
293 container_of(led_cdev, struct rt2x00_led, led_dev);
294 u32 reg;
295
296 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
297 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
298 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
299 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
300
301 return 0;
302}
475433be
ID		 303
304static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
305 struct rt2x00_led *led,
306 enum led_type type)
307{
308 led->rt2x00dev = rt2x00dev;
309 led->type = type;
310 led->led_dev.brightness_set = rt61pci_brightness_set;
311 led->led_dev.blink_set = rt61pci_blink_set;
312 led->flags = LED_INITIALIZED;
313}
771fd565 314#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 315
95ea3627
ID		 316/*
317 * Configuration handlers.
318 */
61e754f4
ID		 319static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
320 struct rt2x00lib_crypto *crypto,
321 struct ieee80211_key_conf *key)
322{
323 struct hw_key_entry key_entry;
324 struct rt2x00_field32 field;
325 u32 mask;
326 u32 reg;
327
328 if (crypto->cmd == SET_KEY) {
329 /*
330 * rt2x00lib can't determine the correct free
331 * key_idx for shared keys. We have 1 register
332 * with key valid bits. The goal is simple, read
333 * the register, if that is full we have no slots
334 * left.
335 * Note that each BSS is allowed to have up to 4
336 * shared keys, so put a mask over the allowed
337 * entries.
338 */
339 mask = (0xf << crypto->bssidx);
340
341 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
342 reg &= mask;
343
344 if (reg && reg == mask)
345 return -ENOSPC;
346
acaf908d 347 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 348
349 /*
350 * Upload key to hardware
351 */
352 memcpy(key_entry.key, crypto->key,
353 sizeof(key_entry.key));
354 memcpy(key_entry.tx_mic, crypto->tx_mic,
355 sizeof(key_entry.tx_mic));
356 memcpy(key_entry.rx_mic, crypto->rx_mic,
357 sizeof(key_entry.rx_mic));
358
359 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
360 rt2x00pci_register_multiwrite(rt2x00dev, reg,
361 &key_entry, sizeof(key_entry));
362
363 /*
364 * The cipher types are stored over 2 registers.
365 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
366 * bssidx 1 and 2 keys are stored in SEC_CSR5.
367 * Using the correct defines correctly will cause overhead,
368 * so just calculate the correct offset.
369 */
370 if (key->hw_key_idx < 8) {
371 field.bit_offset = (3 * key->hw_key_idx);
372 field.bit_mask = 0x7 << field.bit_offset;
373
374 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
375 rt2x00_set_field32(&reg, field, crypto->cipher);
376 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
377 } else {
378 field.bit_offset = (3 * (key->hw_key_idx - 8));
379 field.bit_mask = 0x7 << field.bit_offset;
380
381 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
382 rt2x00_set_field32(&reg, field, crypto->cipher);
383 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
384 }
385
386 /*
387 * The driver does not support the IV/EIV generation
388 * in hardware. However it doesn't support the IV/EIV
389 * inside the ieee80211 frame either, but requires it
b34e620f 390 * to be provided separately for the descriptor.
61e754f4
ID		 391 * rt2x00lib will cut the IV/EIV data out of all frames
392 * given to us by mac80211, but we must tell mac80211
393 * to generate the IV/EIV data.
394 */
395 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
396 }
397
398 /*
399 * SEC_CSR0 contains only single-bit fields to indicate
400 * a particular key is valid. Because using the FIELD32()
b34e620f 401 * defines directly will cause a lot of overhead, we use
61e754f4
ID		 402 * a calculation to determine the correct bit directly.
403 */
404 mask = 1 << key->hw_key_idx;
405
406 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
407 if (crypto->cmd == SET_KEY)
408 reg |= mask;
409 else if (crypto->cmd == DISABLE_KEY)
410 reg &= ~mask;
411 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
412
413 return 0;
414}
415
416static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
417 struct rt2x00lib_crypto *crypto,
418 struct ieee80211_key_conf *key)
419{
420 struct hw_pairwise_ta_entry addr_entry;
421 struct hw_key_entry key_entry;
422 u32 mask;
423 u32 reg;
424
425 if (crypto->cmd == SET_KEY) {
426 /*
427 * rt2x00lib can't determine the correct free
428 * key_idx for pairwise keys. We have 2 registers
b34e620f
TLSC		 429 * with key valid bits. The goal is simple: read
430 * the first register. If that is full, move to
61e754f4 431 * the next register.
b34e620f
TLSC		 432 * When both registers are full, we drop the key.
433 * Otherwise, we use the first invalid entry.
61e754f4
ID		 434 */
435 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
436 if (reg && reg == ~0) {
437 key->hw_key_idx = 32;
438 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
439 if (reg && reg == ~0)
440 return -ENOSPC;
441 }
442
acaf908d 443 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 444
445 /*
446 * Upload key to hardware
447 */
448 memcpy(key_entry.key, crypto->key,
449 sizeof(key_entry.key));
450 memcpy(key_entry.tx_mic, crypto->tx_mic,
451 sizeof(key_entry.tx_mic));
452 memcpy(key_entry.rx_mic, crypto->rx_mic,
453 sizeof(key_entry.rx_mic));
454
455 memset(&addr_entry, 0, sizeof(addr_entry));
456 memcpy(&addr_entry, crypto->address, ETH_ALEN);
457 addr_entry.cipher = crypto->cipher;
458
459 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
460 rt2x00pci_register_multiwrite(rt2x00dev, reg,
461 &key_entry, sizeof(key_entry));
462
463 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
464 rt2x00pci_register_multiwrite(rt2x00dev, reg,
465 &addr_entry, sizeof(addr_entry));
466
467 /*
b34e620f
TLSC		 468 * Enable pairwise lookup table for given BSS idx.
469 * Without this, received frames will not be decrypted
61e754f4
ID		 470 * by the hardware.
471 */
472 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
473 reg |= (1 << crypto->bssidx);
474 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
475
476 /*
477 * The driver does not support the IV/EIV generation
478 * in hardware. However it doesn't support the IV/EIV
479 * inside the ieee80211 frame either, but requires it
3ad2f3fb 480 * to be provided separately for the descriptor.
61e754f4
ID		 481 * rt2x00lib will cut the IV/EIV data out of all frames
482 * given to us by mac80211, but we must tell mac80211
483 * to generate the IV/EIV data.
484 */
485 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
486 }
487
488 /*
489 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
490 * a particular key is valid. Because using the FIELD32()
b34e620f 491 * defines directly will cause a lot of overhead, we use
61e754f4
ID		 492 * a calculation to determine the correct bit directly.
493 */
494 if (key->hw_key_idx < 32) {
495 mask = 1 << key->hw_key_idx;
496
497 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
498 if (crypto->cmd == SET_KEY)
499 reg |= mask;
500 else if (crypto->cmd == DISABLE_KEY)
501 reg &= ~mask;
502 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
503 } else {
504 mask = 1 << (key->hw_key_idx - 32);
505
506 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
507 if (crypto->cmd == SET_KEY)
508 reg |= mask;
509 else if (crypto->cmd == DISABLE_KEY)
510 reg &= ~mask;
511 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
512 }
513
514 return 0;
515}
516
3a643d24
ID		 517static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
518 const unsigned int filter_flags)
519{
520 u32 reg;
521
522 /*
523 * Start configuration steps.
524 * Note that the version error will always be dropped
525 * and broadcast frames will always be accepted since
526 * there is no filter for it at this time.
527 */
528 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
529 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
530 !(filter_flags & FIF_FCSFAIL));
531 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
532 !(filter_flags & FIF_PLCPFAIL));
533 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1afcfd54 534 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
3a643d24
ID		 535 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
536 !(filter_flags & FIF_PROMISC_IN_BSS));
537 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 538 !(filter_flags & FIF_PROMISC_IN_BSS) &&
539 !rt2x00dev->intf_ap_count);
3a643d24
ID		 540 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
541 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
542 !(filter_flags & FIF_ALLMULTI));
543 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
544 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
545 !(filter_flags & FIF_CONTROL));
546 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
547}
548
6bb40dd1
ID		 549static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
550 struct rt2x00_intf *intf,
551 struct rt2x00intf_conf *conf,
552 const unsigned int flags)
95ea3627 553{
6bb40dd1 554 u32 reg;
95ea3627 555
6bb40dd1 556 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 557 /*
558 * Enable synchronisation.
559 */
560 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
6bb40dd1
ID		 561 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
562 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
563 }
95ea3627 564
6bb40dd1
ID		 565 if (flags & CONFIG_UPDATE_MAC) {
566 reg = le32_to_cpu(conf->mac[1]);
567 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
568 conf->mac[1] = cpu_to_le32(reg);
95ea3627 569
6bb40dd1
ID		 570 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
571 conf->mac, sizeof(conf->mac));
572 }
95ea3627 573
6bb40dd1
ID		 574 if (flags & CONFIG_UPDATE_BSSID) {
575 reg = le32_to_cpu(conf->bssid[1]);
576 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
577 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 578
6bb40dd1
ID		 579 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
580 conf->bssid, sizeof(conf->bssid));
581 }
95ea3627
ID		 582}
583
3a643d24 584static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
02044643
HS		 585 struct rt2x00lib_erp *erp,
586 u32 changed)
95ea3627 587{
95ea3627 588 u32 reg;
95ea3627
ID		 589
590 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
4789666e 591 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
8a566afe 592 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
95ea3627
ID		 593 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
594
02044643
HS		 595 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
596 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
597 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
598 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
599 !!erp->short_preamble);
600 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
601 }
95ea3627 602
02044643
HS		 603 if (changed & BSS_CHANGED_BASIC_RATES)
604 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5,
605 erp->basic_rates);
95ea3627 606
02044643
HS		 607 if (changed & BSS_CHANGED_BEACON_INT) {
608 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
609 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
610 erp->beacon_int * 16);
611 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
612 }
8a566afe 613
02044643
HS		 614 if (changed & BSS_CHANGED_ERP_SLOT) {
615 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
616 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
617 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 618
02044643
HS		 619 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
620 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
621 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
622 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
623 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
624 }
95ea3627
ID		 625}
626
627static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 628 struct antenna_setup *ant)
95ea3627
ID		 629{
630 u8 r3;
631 u8 r4;
632 u8 r77;
633
634 rt61pci_bbp_read(rt2x00dev, 3, &r3);
635 rt61pci_bbp_read(rt2x00dev, 4, &r4);
636 rt61pci_bbp_read(rt2x00dev, 77, &r77);
637
5122d898 638 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
e4cd2ff8
ID		 639
640 /*
641 * Configure the RX antenna.
642 */
addc81bd 643 switch (ant->rx) {
95ea3627 644 case ANTENNA_HW_DIVERSITY:
acaa410d 645 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 646 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 647 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 648 break;
649 case ANTENNA_A:
acaa410d 650 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 651 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 652 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 653 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
654 else
655 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 656 break;
657 case ANTENNA_B:
a4fe07d9 658 default:
acaa410d 659 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 660 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 661 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 662 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
663 else
664 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 665 break;
666 }
667
668 rt61pci_bbp_write(rt2x00dev, 77, r77);
669 rt61pci_bbp_write(rt2x00dev, 3, r3);
670 rt61pci_bbp_write(rt2x00dev, 4, r4);
671}
672
673static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 674 struct antenna_setup *ant)
95ea3627
ID		 675{
676 u8 r3;
677 u8 r4;
678 u8 r77;
679
680 rt61pci_bbp_read(rt2x00dev, 3, &r3);
681 rt61pci_bbp_read(rt2x00dev, 4, &r4);
682 rt61pci_bbp_read(rt2x00dev, 77, &r77);
683
5122d898 684 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
95ea3627
ID		 685 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
686 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
687
e4cd2ff8
ID		 688 /*
689 * Configure the RX antenna.
690 */
addc81bd 691 switch (ant->rx) {
95ea3627 692 case ANTENNA_HW_DIVERSITY:
acaa410d 693 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 694 break;
695 case ANTENNA_A:
acaa410d
MN		 696 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
697 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 698 break;
699 case ANTENNA_B:
a4fe07d9 700 default:
acaa410d
MN		 701 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
702 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 703 break;
704 }
705
706 rt61pci_bbp_write(rt2x00dev, 77, r77);
707 rt61pci_bbp_write(rt2x00dev, 3, r3);
708 rt61pci_bbp_write(rt2x00dev, 4, r4);
709}
710
711static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
712 const int p1, const int p2)
713{
714 u32 reg;
715
716 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
717
acaa410d
MN		 718 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
719 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
720
721 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
722 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
723
724 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 725}
726
727static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 728 struct antenna_setup *ant)
95ea3627 729{
95ea3627
ID		 730 u8 r3;
731 u8 r4;
732 u8 r77;
733
734 rt61pci_bbp_read(rt2x00dev, 3, &r3);
735 rt61pci_bbp_read(rt2x00dev, 4, &r4);
736 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 737
e4cd2ff8
ID		 738 /*
739 * Configure the RX antenna.
740 */
741 switch (ant->rx) {
742 case ANTENNA_A:
acaa410d
MN		 743 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
744 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
745 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8 746 break;
e4cd2ff8
ID		 747 case ANTENNA_HW_DIVERSITY:
748 /*
a4fe07d9
ID		 749 * FIXME: Antenna selection for the rf 2529 is very confusing
750 * in the legacy driver. Just default to antenna B until the
751 * legacy code can be properly translated into rt2x00 code.
e4cd2ff8
ID		 752 */
753 case ANTENNA_B:
a4fe07d9 754 default:
acaa410d
MN		 755 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
756 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
757 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 758 break;
759 }
760
e4cd2ff8 761 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 762 rt61pci_bbp_write(rt2x00dev, 3, r3);
763 rt61pci_bbp_write(rt2x00dev, 4, r4);
764}
765
766struct antenna_sel {
767 u8 word;
768 /*
769 * value[0] -> non-LNA
770 * value[1] -> LNA
771 */
772 u8 value[2];
773};
774
775static const struct antenna_sel antenna_sel_a[] = {
776 { 96, { 0x58, 0x78 } },
777 { 104, { 0x38, 0x48 } },
778 { 75, { 0xfe, 0x80 } },
779 { 86, { 0xfe, 0x80 } },
780 { 88, { 0xfe, 0x80 } },
781 { 35, { 0x60, 0x60 } },
782 { 97, { 0x58, 0x58 } },
783 { 98, { 0x58, 0x58 } },
784};
785
786static const struct antenna_sel antenna_sel_bg[] = {
787 { 96, { 0x48, 0x68 } },
788 { 104, { 0x2c, 0x3c } },
789 { 75, { 0xfe, 0x80 } },
790 { 86, { 0xfe, 0x80 } },
791 { 88, { 0xfe, 0x80 } },
792 { 35, { 0x50, 0x50 } },
793 { 97, { 0x48, 0x48 } },
794 { 98, { 0x48, 0x48 } },
795};
796
e4ea1c40
ID		 797static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
798 struct antenna_setup *ant)
95ea3627
ID		 799{
800 const struct antenna_sel *sel;
801 unsigned int lna;
802 unsigned int i;
803 u32 reg;
804
a4fe07d9
ID		 805 /*
806 * We should never come here because rt2x00lib is supposed
807 * to catch this and send us the correct antenna explicitely.
808 */
809 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
810 ant->tx == ANTENNA_SW_DIVERSITY);
811
8318d78a 812 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 813 sel = antenna_sel_a;
814 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 815 } else {
816 sel = antenna_sel_bg;
817 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 818 }
819
acaa410d
MN		 820 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
821 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
822
823 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
824
ddc827f9 825 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 826 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 827 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 828 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 829
95ea3627
ID		 830 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
831
5122d898 832 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
addc81bd 833 rt61pci_config_antenna_5x(rt2x00dev, ant);
5122d898 834 else if (rt2x00_rf(rt2x00dev, RF2527))
addc81bd 835 rt61pci_config_antenna_2x(rt2x00dev, ant);
5122d898 836 else if (rt2x00_rf(rt2x00dev, RF2529)) {
95ea3627 837 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 838 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 839 else
addc81bd 840 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 841 }
842}
843
e4ea1c40
ID		 844static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
845 struct rt2x00lib_conf *libconf)
846{
847 u16 eeprom;
848 short lna_gain = 0;
849
850 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
851 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
852 lna_gain += 14;
853
854 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
855 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
856 } else {
857 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
858 lna_gain += 14;
859
860 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
861 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
862 }
863
864 rt2x00dev->lna_gain = lna_gain;
865}
866
867static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
868 struct rf_channel *rf, const int txpower)
869{
870 u8 r3;
871 u8 r94;
872 u8 smart;
873
874 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
875 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
876
5122d898 877 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
e4ea1c40
ID		 878
879 rt61pci_bbp_read(rt2x00dev, 3, &r3);
880 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
881 rt61pci_bbp_write(rt2x00dev, 3, r3);
882
883 r94 = 6;
884 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
885 r94 += txpower - MAX_TXPOWER;
886 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
887 r94 += txpower;
888 rt61pci_bbp_write(rt2x00dev, 94, r94);
889
890 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
891 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
892 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
893 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
894
895 udelay(200);
896
897 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
898 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
899 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
900 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
901
902 udelay(200);
903
904 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
905 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
906 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
907 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
908
909 msleep(1);
910}
911
912static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
913 const int txpower)
914{
915 struct rf_channel rf;
916
917 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
918 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
919 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
920 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
921
922 rt61pci_config_channel(rt2x00dev, &rf, txpower);
923}
924
925static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5c58ee51 926 struct rt2x00lib_conf *libconf)
95ea3627
ID		 927{
928 u32 reg;
929
e4ea1c40 930 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
e1b4d7b7
ID		 931 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
932 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
933 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
e4ea1c40
ID		 934 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
935 libconf->conf->long_frame_max_tx_count);
936 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
937 libconf->conf->short_frame_max_tx_count);
938 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
939}
95ea3627 940
7d7f19cc
ID		 941static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
942 struct rt2x00lib_conf *libconf)
943{
944 enum dev_state state =
945 (libconf->conf->flags & IEEE80211_CONF_PS) ?
946 STATE_SLEEP : STATE_AWAKE;
947 u32 reg;
948
949 if (state == STATE_SLEEP) {
950 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
951 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 952 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 953 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
954 libconf->conf->listen_interval - 1);
955 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
956
957 /* We must first disable autowake before it can be enabled */
958 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
959 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
960
961 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
962 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
963
964 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
965 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
966 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
967
968 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
969 } else {
970 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
971 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
972 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
973 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
974 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
975 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
976
977 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
978 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
979 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
980
981 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
982 }
983}
984
95ea3627 985static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 986 struct rt2x00lib_conf *libconf,
987 const unsigned int flags)
95ea3627 988{
ba2ab471
ID		 989 /* Always recalculate LNA gain before changing configuration */
990 rt61pci_config_lna_gain(rt2x00dev, libconf);
991
e4ea1c40 992 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 993 rt61pci_config_channel(rt2x00dev, &libconf->rf,
994 libconf->conf->power_level);
e4ea1c40
ID		 995 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
996 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 997 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 998 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
999 rt61pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 1000 if (flags & IEEE80211_CONF_CHANGE_PS)
1001 rt61pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 1002}
1003
95ea3627
ID		 1004/*
1005 * Link tuning
1006 */
ebcf26da
ID		 1007static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1008 struct link_qual *qual)
95ea3627
ID		 1009{
1010 u32 reg;
1011
1012 /*
1013 * Update FCS error count from register.
1014 */
1015 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 1016 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 1017
1018 /*
1019 * Update False CCA count from register.
1020 */
1021 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 1022 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 1023}
1024
5352ff65
ID		 1025static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1026 struct link_qual *qual, u8 vgc_level)
eb20b4e8 1027{
5352ff65 1028 if (qual->vgc_level != vgc_level) {
eb20b4e8 1029 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 1030 qual->vgc_level = vgc_level;
1031 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 1032 }
1033}
1034
5352ff65
ID		 1035static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1036 struct link_qual *qual)
95ea3627 1037{
5352ff65 1038 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 1039}
1040
5352ff65
ID		 1041static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1042 struct link_qual *qual, const u32 count)
95ea3627 1043{
95ea3627
ID		 1044 u8 up_bound;
1045 u8 low_bound;
1046
95ea3627
ID		 1047 /*
1048 * Determine r17 bounds.
1049 */
e5ef5bad 1050 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1051 low_bound = 0x28;
1052 up_bound = 0x48;
1053 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1054 low_bound += 0x10;
1055 up_bound += 0x10;
1056 }
1057 } else {
1058 low_bound = 0x20;
1059 up_bound = 0x40;
1060 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1061 low_bound += 0x10;
1062 up_bound += 0x10;
1063 }
1064 }
1065
6bb40dd1
ID		 1066 /*
1067 * If we are not associated, we should go straight to the
1068 * dynamic CCA tuning.
1069 */
1070 if (!rt2x00dev->intf_associated)
1071 goto dynamic_cca_tune;
1072
95ea3627
ID		 1073 /*
1074 * Special big-R17 for very short distance
1075 */
5352ff65
ID		 1076 if (qual->rssi >= -35) {
1077 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 1078 return;
1079 }
1080
1081 /*
1082 * Special big-R17 for short distance
1083 */
5352ff65
ID		 1084 if (qual->rssi >= -58) {
1085 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1086 return;
1087 }
1088
1089 /*
1090 * Special big-R17 for middle-short distance
1091 */
5352ff65
ID		 1092 if (qual->rssi >= -66) {
1093 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 1094 return;
1095 }
1096
1097 /*
1098 * Special mid-R17 for middle distance
1099 */
5352ff65
ID		 1100 if (qual->rssi >= -74) {
1101 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 1102 return;
1103 }
1104
1105 /*
1106 * Special case: Change up_bound based on the rssi.
1107 * Lower up_bound when rssi is weaker then -74 dBm.
1108 */
5352ff65 1109 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1110 if (low_bound > up_bound)
1111 up_bound = low_bound;
1112
5352ff65
ID		 1113 if (qual->vgc_level > up_bound) {
1114 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1115 return;
1116 }
1117
6bb40dd1
ID		 1118dynamic_cca_tune:
1119
95ea3627
ID		 1120 /*
1121 * r17 does not yet exceed upper limit, continue and base
1122 * the r17 tuning on the false CCA count.
1123 */
5352ff65
ID		 1124 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1125 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1126 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1127 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 1128}
1129
5450b7e2
ID		 1130/*
1131 * Queue handlers.
1132 */
1133static void rt61pci_start_queue(struct data_queue *queue)
1134{
1135 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1136 u32 reg;
1137
1138 switch (queue->qid) {
1139 case QID_RX:
1140 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1141 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1142 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1143 break;
1144 case QID_BEACON:
5846a550
HS		 1145 /*
1146 * Allow the tbtt tasklet to be scheduled.
1147 */
1148 tasklet_enable(&rt2x00dev->tbtt_tasklet);
1149
5450b7e2
ID		 1150 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1151 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1152 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1153 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1154 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1155 break;
1156 default:
1157 break;
1158 }
1159}
1160
1161static void rt61pci_kick_queue(struct data_queue *queue)
1162{
1163 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1164 u32 reg;
1165
1166 switch (queue->qid) {
f615e9a3 1167 case QID_AC_VO:
5450b7e2
ID		 1168 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1169 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1170 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1171 break;
f615e9a3 1172 case QID_AC_VI:
5450b7e2
ID		 1173 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1174 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1175 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1176 break;
f615e9a3 1177 case QID_AC_BE:
5450b7e2
ID		 1178 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1179 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1180 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1181 break;
f615e9a3 1182 case QID_AC_BK:
5450b7e2
ID		 1183 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1184 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1185 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1186 break;
1187 default:
1188 break;
1189 }
1190}
1191
1192static void rt61pci_stop_queue(struct data_queue *queue)
1193{
1194 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1195 u32 reg;
1196
1197 switch (queue->qid) {
f615e9a3 1198 case QID_AC_VO:
5450b7e2
ID		 1199 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1200 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1201 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1202 break;
f615e9a3 1203 case QID_AC_VI:
5450b7e2
ID		 1204 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1205 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1206 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1207 break;
f615e9a3 1208 case QID_AC_BE:
5450b7e2
ID		 1209 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1210 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1211 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1212 break;
f615e9a3 1213 case QID_AC_BK:
5450b7e2
ID		 1214 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1215 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1216 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1217 break;
1218 case QID_RX:
1219 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1220 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1221 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1222 break;
1223 case QID_BEACON:
1224 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1225 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1226 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1227 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1228 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
5846a550
HS		 1229
1230 /*
1231 * Wait for possibly running tbtt tasklets.
1232 */
1233 tasklet_disable(&rt2x00dev->tbtt_tasklet);
5450b7e2
ID		 1234 break;
1235 default:
1236 break;
1237 }
1238}
1239
95ea3627 1240/*
a7f3a06c 1241 * Firmware functions
95ea3627
ID		 1242 */
1243static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1244{
49e721ec 1245 u16 chip;
95ea3627
ID		 1246 char *fw_name;
1247
49e721ec
GW		 1248 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1249 switch (chip) {
1250 case RT2561_PCI_ID:
95ea3627
ID		 1251 fw_name = FIRMWARE_RT2561;
1252 break;
49e721ec 1253 case RT2561s_PCI_ID:
95ea3627
ID		 1254 fw_name = FIRMWARE_RT2561s;
1255 break;
49e721ec 1256 case RT2661_PCI_ID:
95ea3627
ID		 1257 fw_name = FIRMWARE_RT2661;
1258 break;
1259 default:
1260 fw_name = NULL;
1261 break;
1262 }
1263
1264 return fw_name;
1265}
1266
0cbe0064
ID		 1267static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1268 const u8 *data, const size_t len)
a7f3a06c 1269{
0cbe0064 1270 u16 fw_crc;
a7f3a06c
ID		 1271 u16 crc;
1272
1273 /*
0cbe0064
ID		 1274 * Only support 8kb firmware files.
1275 */
1276 if (len != 8192)
1277 return FW_BAD_LENGTH;
1278
1279 /*
b34e620f
TLSC		 1280 * The last 2 bytes in the firmware array are the crc checksum itself.
1281 * This means that we should never pass those 2 bytes to the crc
a7f3a06c
ID		 1282 * algorithm.
1283 */
0cbe0064
ID		 1284 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1285
1286 /*
1287 * Use the crc itu-t algorithm.
1288 */
a7f3a06c
ID		 1289 crc = crc_itu_t(0, data, len - 2);
1290 crc = crc_itu_t_byte(crc, 0);
1291 crc = crc_itu_t_byte(crc, 0);
1292
0cbe0064 1293 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1294}
1295
0cbe0064
ID		 1296static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1297 const u8 *data, const size_t len)
95ea3627
ID		 1298{
1299 int i;
1300 u32 reg;
1301
1302 /*
1303 * Wait for stable hardware.
1304 */
1305 for (i = 0; i < 100; i++) {
1306 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1307 if (reg)
1308 break;
1309 msleep(1);
1310 }
1311
1312 if (!reg) {
1313 ERROR(rt2x00dev, "Unstable hardware.\n");
1314 return -EBUSY;
1315 }
1316
1317 /*
1318 * Prepare MCU and mailbox for firmware loading.
1319 */
1320 reg = 0;
1321 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1322 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1323 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1324 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1325 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1326
1327 /*
1328 * Write firmware to device.
1329 */
1330 reg = 0;
1331 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1332 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1333 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1334
1335 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1336 data, len);
1337
1338 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1339 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1340
1341 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1342 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1343
1344 for (i = 0; i < 100; i++) {
1345 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1346 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1347 break;
1348 msleep(1);
1349 }
1350
1351 if (i == 100) {
1352 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1353 return -EBUSY;
1354 }
1355
e6d3e902
ID		 1356 /*
1357 * Hardware needs another millisecond before it is ready.
1358 */
1359 msleep(1);
1360
95ea3627
ID		 1361 /*
1362 * Reset MAC and BBP registers.
1363 */
1364 reg = 0;
1365 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1366 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1367 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1368
1369 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1370 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1371 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1372 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1373
1374 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1375 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1376 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1377
1378 return 0;
1379}
1380
a7f3a06c
ID		 1381/*
1382 * Initialization functions.
1383 */
798b7adb 1384static bool rt61pci_get_entry_state(struct queue_entry *entry)
95ea3627 1385{
b8be63ff 1386 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1387 u32 word;
1388
798b7adb
ID		 1389 if (entry->queue->qid == QID_RX) {
1390 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 1391
798b7adb
ID		 1392 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1393 } else {
1394 rt2x00_desc_read(entry_priv->desc, 0, &word);
1395
1396 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1397 rt2x00_get_field32(word, TXD_W0_VALID));
1398 }
95ea3627
ID		 1399}
1400
798b7adb 1401static void rt61pci_clear_entry(struct queue_entry *entry)
95ea3627 1402{
b8be63ff 1403 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 1404 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 1405 u32 word;
1406
798b7adb
ID		 1407 if (entry->queue->qid == QID_RX) {
1408 rt2x00_desc_read(entry_priv->desc, 5, &word);
1409 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1410 skbdesc->skb_dma);
1411 rt2x00_desc_write(entry_priv->desc, 5, word);
1412
1413 rt2x00_desc_read(entry_priv->desc, 0, &word);
1414 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1415 rt2x00_desc_write(entry_priv->desc, 0, word);
1416 } else {
1417 rt2x00_desc_read(entry_priv->desc, 0, &word);
1418 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1419 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1420 rt2x00_desc_write(entry_priv->desc, 0, word);
1421 }
95ea3627
ID		 1422}
1423
181d6902 1424static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1425{
b8be63ff 1426 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 1427 u32 reg;
1428
95ea3627
ID		 1429 /*
1430 * Initialize registers.
1431 */
1432 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1433 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1434 rt2x00dev->tx[0].limit);
95ea3627 1435 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1436 rt2x00dev->tx[1].limit);
95ea3627 1437 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1438 rt2x00dev->tx[2].limit);
95ea3627 1439 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1440 rt2x00dev->tx[3].limit);
95ea3627
ID		 1441 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1442
1443 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1444 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1445 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1446 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1447
b8be63ff 1448 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1449 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
30b3a23c 1450 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
b8be63ff 1451 entry_priv->desc_dma);
95ea3627
ID		 1452 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1453
b8be63ff 1454 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1455 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
30b3a23c 1456 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
b8be63ff 1457 entry_priv->desc_dma);
95ea3627
ID		 1458 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1459
b8be63ff 1460 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1461 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
30b3a23c 1462 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
b8be63ff 1463 entry_priv->desc_dma);
95ea3627
ID		 1464 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1465
b8be63ff 1466 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1467 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
30b3a23c 1468 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
b8be63ff 1469 entry_priv->desc_dma);
95ea3627
ID		 1470 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1471
95ea3627 1472 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1473 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1474 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1475 rt2x00dev->rx->desc_size / 4);
1476 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1477 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1478
b8be63ff 1479 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1480 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
30b3a23c 1481 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
b8be63ff 1482 entry_priv->desc_dma);
95ea3627
ID		 1483 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1484
1485 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1486 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1487 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1488 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1489 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
95ea3627
ID		 1490 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1491
1492 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1493 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1494 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1495 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1496 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
95ea3627
ID		 1497 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1498
1499 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1500 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1501 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1502
1503 return 0;
1504}
1505
1506static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1507{
1508 u32 reg;
1509
1510 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1511 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1512 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1513 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1514 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1515
1516 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1517 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1518 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1519 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1520 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1521 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1522 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1523 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1524 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1525 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1526
1527 /*
1528 * CCK TXD BBP registers
1529 */
1530 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1531 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1532 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1533 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1534 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1535 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1536 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1537 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1538 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1539 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1540
1541 /*
1542 * OFDM TXD BBP registers
1543 */
1544 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1545 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1546 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1547 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1548 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1549 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1550 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1551 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1552
1553 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1554 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1555 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1556 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1557 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1558 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1559
1560 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1561 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1562 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1563 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1564 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1565 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1566
1f909162
ID		 1567 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1568 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1569 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1570 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1571 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1572 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1573 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1574 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1575
95ea3627
ID		 1576 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1577
1578 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1579
1580 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1581 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1582 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1583
1584 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1585
1586 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1587 return -EBUSY;
1588
1589 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1590
1591 /*
1592 * Invalidate all Shared Keys (SEC_CSR0),
1593 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1594 */
1595 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1596 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1597 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1598
1599 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1600 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1601 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1602 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1603
1604 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1605
1606 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1607
1608 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1609
6bb40dd1
ID		 1610 /*
1611 * Clear all beacons
1612 * For the Beacon base registers we only need to clear
1613 * the first byte since that byte contains the VALID and OWNER
1614 * bits which (when set to 0) will invalidate the entire beacon.
1615 */
1616 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1617 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1618 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1619 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1620
95ea3627
ID		 1621 /*
1622 * We must clear the error counters.
1623 * These registers are cleared on read,
1624 * so we may pass a useless variable to store the value.
1625 */
1626 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1627 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1628 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1629
1630 /*
1631 * Reset MAC and BBP registers.
1632 */
1633 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1634 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1635 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1636 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1637
1638 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1639 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1640 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1641 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1642
1643 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1644 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1645 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1646
1647 return 0;
1648}
1649
2b08da3f 1650static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1651{
1652 unsigned int i;
95ea3627
ID		 1653 u8 value;
1654
1655 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1656 rt61pci_bbp_read(rt2x00dev, 0, &value);
1657 if ((value != 0xff) && (value != 0x00))
2b08da3f 1658 return 0;
95ea3627
ID		 1659 udelay(REGISTER_BUSY_DELAY);
1660 }
1661
1662 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1663 return -EACCES;
2b08da3f
ID		 1664}
1665
1666static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1667{
1668 unsigned int i;
1669 u16 eeprom;
1670 u8 reg_id;
1671 u8 value;
1672
1673 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1674 return -EACCES;
95ea3627 1675
95ea3627
ID		 1676 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1677 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1678 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1679 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1680 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1681 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1682 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1683 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1684 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1685 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1686 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1687 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1688 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1689 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1690 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1691 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1692 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1693 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1694 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1695 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1696 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1697 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1698 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1699 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1700
95ea3627
ID		 1701 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1702 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1703
1704 if (eeprom != 0xffff && eeprom != 0x0000) {
1705 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1706 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1707 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1708 }
1709 }
95ea3627
ID		 1710
1711 return 0;
1712}
1713
1714/*
1715 * Device state switch handlers.
1716 */
95ea3627
ID		 1717static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1718 enum dev_state state)
1719{
b550911a 1720 int mask = (state == STATE_RADIO_IRQ_OFF);
95ea3627 1721 u32 reg;
5846a550 1722 unsigned long flags;
95ea3627
ID		 1723
1724 /*
1725 * When interrupts are being enabled, the interrupt registers
1726 * should clear the register to assure a clean state.
1727 */
1728 if (state == STATE_RADIO_IRQ_ON) {
1729 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1730 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1731
1732 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1733 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
5846a550
HS		 1734
1735 /*
1736 * Enable tasklets.
1737 */
1738 tasklet_enable(&rt2x00dev->txstatus_tasklet);
1739 tasklet_enable(&rt2x00dev->rxdone_tasklet);
1740 tasklet_enable(&rt2x00dev->autowake_tasklet);
95ea3627
ID		 1741 }
1742
1743 /*
1744 * Only toggle the interrupts bits we are going to use.
1745 * Non-checked interrupt bits are disabled by default.
1746 */
5846a550
HS		 1747 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1748
95ea3627
ID		 1749 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1750 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1751 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
6646505d 1752 rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask);
95ea3627
ID		 1753 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1754 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1755 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1756
1757 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1758 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1759 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1760 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1761 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1762 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1763 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1764 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1765 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
6646505d 1766 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask);
95ea3627 1767 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
5846a550
HS		 1768
1769 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1770
1771 if (state == STATE_RADIO_IRQ_OFF) {
1772 /*
1773 * Ensure that all tasklets are finished.
1774 */
1775 tasklet_disable(&rt2x00dev->txstatus_tasklet);
1776 tasklet_disable(&rt2x00dev->rxdone_tasklet);
1777 tasklet_disable(&rt2x00dev->autowake_tasklet);
1778 }
95ea3627
ID		 1779}
1780
1781static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1782{
1783 u32 reg;
1784
1785 /*
1786 * Initialize all registers.
1787 */
2b08da3f
ID		 1788 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1789 rt61pci_init_registers(rt2x00dev) ||
1790 rt61pci_init_bbp(rt2x00dev)))
95ea3627 1791 return -EIO;
95ea3627
ID		 1792
1793 /*
1794 * Enable RX.
1795 */
1796 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1797 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1798 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1799
95ea3627
ID		 1800 return 0;
1801}
1802
1803static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1804{
95ea3627 1805 /*
a2c9b652 1806 * Disable power
95ea3627 1807 */
a2c9b652 1808 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1809}
1810
1811static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1812{
9655a6ec 1813 u32 reg, reg2;
95ea3627
ID		 1814 unsigned int i;
1815 char put_to_sleep;
95ea3627
ID		 1816
1817 put_to_sleep = (state != STATE_AWAKE);
1818
1819 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1820 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1821 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1822 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1823
1824 /*
1825 * Device is not guaranteed to be in the requested state yet.
1826 * We must wait until the register indicates that the
1827 * device has entered the correct state.
1828 */
1829 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 1830 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg2);
1831 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
2b08da3f 1832 if (state == !put_to_sleep)
95ea3627 1833 return 0;
9655a6ec 1834 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1835 msleep(10);
1836 }
1837
95ea3627
ID		 1838 return -EBUSY;
1839}
1840
1841static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1842 enum dev_state state)
1843{
1844 int retval = 0;
1845
1846 switch (state) {
1847 case STATE_RADIO_ON:
1848 retval = rt61pci_enable_radio(rt2x00dev);
1849 break;
1850 case STATE_RADIO_OFF:
1851 rt61pci_disable_radio(rt2x00dev);
1852 break;
2b08da3f
ID		 1853 case STATE_RADIO_IRQ_ON:
1854 case STATE_RADIO_IRQ_OFF:
1855 rt61pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1856 break;
1857 case STATE_DEEP_SLEEP:
1858 case STATE_SLEEP:
1859 case STATE_STANDBY:
1860 case STATE_AWAKE:
1861 retval = rt61pci_set_state(rt2x00dev, state);
1862 break;
1863 default:
1864 retval = -ENOTSUPP;
1865 break;
1866 }
1867
2b08da3f
ID		 1868 if (unlikely(retval))
1869 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1870 state, retval);
1871
95ea3627
ID		 1872 return retval;
1873}
1874
1875/*
1876 * TX descriptor initialization
1877 */
93331458 1878static void rt61pci_write_tx_desc(struct queue_entry *entry,
61e754f4 1879 struct txentry_desc *txdesc)
95ea3627 1880{
93331458
ID		 1881 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1882 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 1883 __le32 *txd = entry_priv->desc;
95ea3627
ID		 1884 u32 word;
1885
1886 /*
1887 * Start writing the descriptor words.
1888 */
1889 rt2x00_desc_read(txd, 1, &word);
2b23cdaa
HS		 1890 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1891 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1892 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1893 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
61e754f4 1894 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1895 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1896 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
4de36fe5 1897 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
95ea3627
ID		 1898 rt2x00_desc_write(txd, 1, word);
1899
1900 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1901 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1902 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1903 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1904 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1905 rt2x00_desc_write(txd, 2, word);
1906
61e754f4 1907 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1908 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1909 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
61e754f4
ID		 1910 }
1911
95ea3627 1912 rt2x00_desc_read(txd, 5, &word);
93331458 1913 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
4de36fe5
GW		 1914 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1915 skbdesc->entry->entry_idx);
95ea3627 1916 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
93331458 1917 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
95ea3627
ID		 1918 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1919 rt2x00_desc_write(txd, 5, word);
1920
2b23cdaa 1921 if (entry->queue->qid != QID_BEACON) {
6b97cb04
GW		 1922 rt2x00_desc_read(txd, 6, &word);
1923 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1924 skbdesc->skb_dma);
1925 rt2x00_desc_write(txd, 6, word);
4de36fe5 1926
d7bafff3 1927 rt2x00_desc_read(txd, 11, &word);
df624ca5
GW		 1928 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1929 txdesc->length);
d7bafff3
AB		 1930 rt2x00_desc_write(txd, 11, word);
1931 }
95ea3627 1932
e01f1ec3
GW		 1933 /*
1934 * Writing TXD word 0 must the last to prevent a race condition with
1935 * the device, whereby the device may take hold of the TXD before we
1936 * finished updating it.
1937 */
95ea3627
ID		 1938 rt2x00_desc_read(txd, 0, &word);
1939 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1940 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1941 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1942 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1943 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1944 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1945 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1946 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1947 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1948 (txdesc->rate_mode == RATE_MODE_OFDM));
181d6902 1949 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1950 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1951 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
61e754f4
ID		 1952 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1953 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1954 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1955 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1956 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
df624ca5 1957 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
95ea3627 1958 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1959 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
61e754f4 1960 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627 1961 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1962
1963 /*
1964 * Register descriptor details in skb frame descriptor.
1965 */
1966 skbdesc->desc = txd;
2b23cdaa
HS		 1967 skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
1968 TXD_DESC_SIZE;
95ea3627
ID		 1969}
1970
1971/*
1972 * TX data initialization
1973 */
f224f4ef
GW		 1974static void rt61pci_write_beacon(struct queue_entry *entry,
1975 struct txentry_desc *txdesc)
bd88a781
ID		 1976{
1977 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
85b7a8b3 1978 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
bd88a781 1979 unsigned int beacon_base;
739fd940 1980 unsigned int padding_len;
bd88a781
ID		 1981 u32 reg;
1982
1983 /*
1984 * Disable beaconing while we are reloading the beacon data,
1985 * otherwise we might be sending out invalid data.
1986 */
1987 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781
ID		 1988 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1989 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1990
5c3b685c
GW		 1991 /*
1992 * Write the TX descriptor for the beacon.
1993 */
93331458 1994 rt61pci_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1995
1996 /*
1997 * Dump beacon to userspace through debugfs.
1998 */
1999 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
2000
bd88a781 2001 /*
739fd940 2002 * Write entire beacon with descriptor and padding to register.
bd88a781 2003 */
739fd940
WK		 2004 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
2005 skb_pad(entry->skb, padding_len);
bd88a781 2006 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
85b7a8b3
GW		 2007 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2008 entry_priv->desc, TXINFO_SIZE);
2009 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
739fd940
WK		 2010 entry->skb->data,
2011 entry->skb->len + padding_len);
bd88a781 2012
d61cb266
GW		 2013 /*
2014 * Enable beaconing again.
2015 *
2016 * For Wi-Fi faily generated beacons between participating
2017 * stations. Set TBTT phase adaptive adjustment step to 8us.
2018 */
2019 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
2020
d61cb266
GW		 2021 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2022 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2023
bd88a781
ID		 2024 /*
2025 * Clean up beacon skb.
2026 */
2027 dev_kfree_skb_any(entry->skb);
2028 entry->skb = NULL;
2029}
2030
69cf36a4
HS		 2031static void rt61pci_clear_beacon(struct queue_entry *entry)
2032{
2033 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2034 u32 reg;
2035
2036 /*
2037 * Disable beaconing while we are reloading the beacon data,
2038 * otherwise we might be sending out invalid data.
2039 */
2040 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2041 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2042 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2043
2044 /*
2045 * Clear beacon.
2046 */
2047 rt2x00pci_register_write(rt2x00dev,
2048 HW_BEACON_OFFSET(entry->entry_idx), 0);
2049
2050 /*
2051 * Enable beaconing again.
2052 */
2053 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2054 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2055}
2056
95ea3627
ID		 2057/*
2058 * RX control handlers
2059 */
2060static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
2061{
ba2ab471 2062 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 2063 u8 lna;
2064
2065 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
2066 switch (lna) {
2067 case 3:
ba2ab471 2068 offset += 90;
95ea3627
ID		 2069 break;
2070 case 2:
ba2ab471 2071 offset += 74;
95ea3627
ID		 2072 break;
2073 case 1:
ba2ab471 2074 offset += 64;
95ea3627
ID		 2075 break;
2076 default:
2077 return 0;
2078 }
2079
e5ef5bad 2080 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 2081 if (lna == 3 || lna == 2)
2082 offset += 10;
95ea3627
ID		 2083 }
2084
2085 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
2086}
2087
181d6902 2088static void rt61pci_fill_rxdone(struct queue_entry *entry,
55887511 2089 struct rxdone_entry_desc *rxdesc)
95ea3627 2090{
61e754f4 2091 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 2092 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 2093 u32 word0;
2094 u32 word1;
2095
b8be63ff
ID		 2096 rt2x00_desc_read(entry_priv->desc, 0, &word0);
2097 rt2x00_desc_read(entry_priv->desc, 1, &word1);
95ea3627 2098
4150c572 2099 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 2100 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 2101
78b8f3b0
GW		 2102 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
2103 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
61e754f4
ID		 2104
2105 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 2106 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
2107 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
74415edb
ID		 2108 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
2109
61e754f4 2110 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
74415edb 2111 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
61e754f4
ID		 2112
2113 /*
2114 * Hardware has stripped IV/EIV data from 802.11 frame during
b34e620f 2115 * decryption. It has provided the data separately but rt2x00lib
61e754f4
ID		 2116 * should decide if it should be reinserted.
2117 */
2118 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2119
2120 /*
a0aff623
GW		 2121 * The hardware has already checked the Michael Mic and has
2122 * stripped it from the frame. Signal this to mac80211.
61e754f4
ID		 2123 */
2124 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2125
2126 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2127 rxdesc->flags |= RX_FLAG_DECRYPTED;
2128 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2129 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2130 }
2131
95ea3627
ID		 2132 /*
2133 * Obtain the status about this packet.
89993890
ID		 2134 * When frame was received with an OFDM bitrate,
2135 * the signal is the PLCP value. If it was received with
2136 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 2137 */
181d6902 2138 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
61e754f4 2139 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
181d6902 2140 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 2141
19d30e02
ID		 2142 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2143 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 2144 else
2145 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 2146 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2147 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 2148}
2149
2150/*
2151 * Interrupt functions.
2152 */
2153static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2154{
181d6902
ID		 2155 struct data_queue *queue;
2156 struct queue_entry *entry;
2157 struct queue_entry *entry_done;
b8be63ff 2158 struct queue_entry_priv_pci *entry_priv;
181d6902 2159 struct txdone_entry_desc txdesc;
95ea3627
ID		 2160 u32 word;
2161 u32 reg;
95ea3627
ID		 2162 int type;
2163 int index;
e6474c3c 2164 int i;
95ea3627
ID		 2165
2166 /*
e6474c3c
ID		 2167 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2168 * at most X times and also stop processing once the TX_STA_FIFO_VALID
2169 * flag is not set anymore.
2170 *
2171 * The legacy drivers use X=TX_RING_SIZE but state in a comment
2172 * that the TX_STA_FIFO stack has a size of 16. We stick to our
2173 * tx ring size for now.
95ea3627 2174 */
efd2f271 2175 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
95ea3627
ID		 2176 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2177 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2178 break;
2179
95ea3627
ID		 2180 /*
2181 * Skip this entry when it contains an invalid
181d6902 2182 * queue identication number.
95ea3627
ID		 2183 */
2184 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 2185 queue = rt2x00queue_get_queue(rt2x00dev, type);
2186 if (unlikely(!queue))
95ea3627
ID		 2187 continue;
2188
2189 /*
2190 * Skip this entry when it contains an invalid
2191 * index number.
2192 */
2193 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 2194 if (unlikely(index >= queue->limit))
95ea3627
ID		 2195 continue;
2196
181d6902 2197 entry = &queue->entries[index];
b8be63ff
ID		 2198 entry_priv = entry->priv_data;
2199 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 2200
2201 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2202 !rt2x00_get_field32(word, TXD_W0_VALID))
2203 return;
2204
181d6902 2205 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 2206 while (entry != entry_done) {
181d6902
ID		 2207 /* Catch up.
2208 * Just report any entries we missed as failed.
2209 */
62bc060b 2210 WARNING(rt2x00dev,
181d6902
ID		 2211 "TX status report missed for entry %d\n",
2212 entry_done->entry_idx);
2213
65b7fc97 2214 rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN);
181d6902 2215 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 2216 }
2217
95ea3627
ID		 2218 /*
2219 * Obtain the status about this packet.
2220 */
fb55f4d1
ID		 2221 txdesc.flags = 0;
2222 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2223 case 0: /* Success, maybe with retry */
2224 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2225 break;
2226 case 6: /* Failure, excessive retries */
2227 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2228 /* Don't break, this is a failed frame! */
2229 default: /* Failure */
2230 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2231 }
181d6902 2232 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 2233
e1b4d7b7
ID		 2234 /*
2235 * the frame was retried at least once
2236 * -> hw used fallback rates
2237 */
2238 if (txdesc.retry)
2239 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2240
e513a0b6 2241 rt2x00lib_txdone(entry, &txdesc);
95ea3627
ID		 2242 }
2243}
2244
9e189446
GW		 2245static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2246{
2247 struct ieee80211_conf conf = { .flags = 0 };
2248 struct rt2x00lib_conf libconf = { .conf = &conf };
2249
2250 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2251}
2252
5846a550
HS		 2253static void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
2254 struct rt2x00_field32 irq_field)
95ea3627 2255{
5846a550
HS		 2256 unsigned long flags;
2257 u32 reg;
95ea3627
ID		 2258
2259 /*
5846a550
HS		 2260 * Enable a single interrupt. The interrupt mask register
2261 * access needs locking.
95ea3627 2262 */
5846a550 2263 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
95ea3627 2264
5846a550
HS		 2265 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2266 rt2x00_set_field32(&reg, irq_field, 0);
2267 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
95ea3627 2268
5846a550
HS		 2269 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
2270}
95ea3627 2271
5846a550
HS		 2272static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,
2273 struct rt2x00_field32 irq_field)
2274{
2275 unsigned long flags;
2276 u32 reg;
95ea3627 2277
9e189446 2278 /*
5846a550
HS		 2279 * Enable a single MCU interrupt. The interrupt mask register
2280 * access needs locking.
9e189446 2281 */
5846a550 2282 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
9e189446 2283
5846a550
HS		 2284 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2285 rt2x00_set_field32(&reg, irq_field, 0);
2286 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
fa43750f 2287
5846a550 2288 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
95ea3627
ID		 2289}
2290
5846a550
HS		 2291static void rt61pci_txstatus_tasklet(unsigned long data)
2292{
2293 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2294 rt61pci_txdone(rt2x00dev);
2295 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE);
2296}
2297
2298static void rt61pci_tbtt_tasklet(unsigned long data)
2299{
2300 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2301 rt2x00lib_beacondone(rt2x00dev);
2302 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE);
2303}
2304
2305static void rt61pci_rxdone_tasklet(unsigned long data)
2306{
2307 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2308 rt2x00pci_rxdone(rt2x00dev);
2309 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE);
2310}
2311
2312static void rt61pci_autowake_tasklet(unsigned long data)
2313{
2314 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2315 rt61pci_wakeup(rt2x00dev);
2316 rt2x00pci_register_write(rt2x00dev,
2317 M2H_CMD_DONE_CSR, 0xffffffff);
2318 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP);
2319}
78e256c9
HS		 2320
2321static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2322{
2323 struct rt2x00_dev *rt2x00dev = dev_instance;
5846a550
HS		 2324 u32 reg_mcu, mask_mcu;
2325 u32 reg, mask;
2326 unsigned long flags;
78e256c9
HS		 2327
2328 /*
2329 * Get the interrupt sources & saved to local variable.
2330 * Write register value back to clear pending interrupts.
2331 */
2332 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2333 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2334
2335 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2336 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2337
2338 if (!reg && !reg_mcu)
2339 return IRQ_NONE;
2340
2341 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2342 return IRQ_HANDLED;
2343
5846a550
HS		 2344 /*
2345 * Schedule tasklets for interrupt handling.
2346 */
2347 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2348 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2349
2350 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2351 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
2352
2353 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2354 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
2355
2356 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2357 tasklet_schedule(&rt2x00dev->autowake_tasklet);
2358
2359 /*
2360 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
2361 * for interrupts and interrupt masks we can just use the value of
2362 * INT_SOURCE_CSR to create the interrupt mask.
2363 */
2364 mask = reg;
2365 mask_mcu = reg_mcu;
2366
2367 /*
2368 * Disable all interrupts for which a tasklet was scheduled right now,
2369 * the tasklet will reenable the appropriate interrupts.
2370 */
2371 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
2372
2373 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2374 reg |= mask;
2375 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
78e256c9 2376
5846a550
HS		 2377 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2378 reg |= mask_mcu;
2379 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2380
2381 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
2382
2383 return IRQ_HANDLED;
78e256c9
HS		 2384}
2385
95ea3627
ID		 2386/*
2387 * Device probe functions.
2388 */
2389static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2390{
2391 struct eeprom_93cx6 eeprom;
2392 u32 reg;
2393 u16 word;
2394 u8 *mac;
2395 s8 value;
2396
2397 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2398
2399 eeprom.data = rt2x00dev;
2400 eeprom.register_read = rt61pci_eepromregister_read;
2401 eeprom.register_write = rt61pci_eepromregister_write;
2402 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2403 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2404 eeprom.reg_data_in = 0;
2405 eeprom.reg_data_out = 0;
2406 eeprom.reg_data_clock = 0;
2407 eeprom.reg_chip_select = 0;
2408
2409 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2410 EEPROM_SIZE / sizeof(u16));
2411
2412 /*
2413 * Start validation of the data that has been read.
2414 */
2415 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2416 if (!is_valid_ether_addr(mac)) {
2417 random_ether_addr(mac);
e174961c 2418 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 2419 }
2420
2421 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2422 if (word == 0xffff) {
2423 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 2424 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2425 ANTENNA_B);
2426 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2427 ANTENNA_B);
95ea3627
ID		 2428 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2429 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2430 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2431 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2432 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2433 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2434 }
2435
2436 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2437 if (word == 0xffff) {
2438 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2439 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
91581b62
ID		 2440 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2441 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
95ea3627
ID		 2442 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2443 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2444 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2445 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2446 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2447 }
2448
2449 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2450 if (word == 0xffff) {
2451 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2452 LED_MODE_DEFAULT);
2453 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2454 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2455 }
2456
2457 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2458 if (word == 0xffff) {
2459 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2460 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2461 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2462 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2463 }
2464
2465 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2466 if (word == 0xffff) {
2467 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2468 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2469 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2470 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2471 } else {
2472 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2473 if (value < -10 || value > 10)
2474 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2475 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2476 if (value < -10 || value > 10)
2477 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2478 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2479 }
2480
2481 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2482 if (word == 0xffff) {
2483 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2484 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2485 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 2486 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 2487 } else {
2488 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2489 if (value < -10 || value > 10)
2490 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2491 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2492 if (value < -10 || value > 10)
2493 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2494 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2495 }
2496
2497 return 0;
2498}
2499
2500static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2501{
2502 u32 reg;
2503 u16 value;
2504 u16 eeprom;
95ea3627
ID		 2505
2506 /*
2507 * Read EEPROM word for configuration.
2508 */
2509 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2510
2511 /*
2512 * Identify RF chipset.
95ea3627 2513 */
95ea3627
ID		 2514 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2515 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
49e721ec
GW		 2516 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2517 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
95ea3627 2518
5122d898
GW		 2519 if (!rt2x00_rf(rt2x00dev, RF5225) &&
2520 !rt2x00_rf(rt2x00dev, RF5325) &&
2521 !rt2x00_rf(rt2x00dev, RF2527) &&
2522 !rt2x00_rf(rt2x00dev, RF2529)) {
95ea3627
ID		 2523 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2524 return -ENODEV;
2525 }
2526
e4cd2ff8 2527 /*
49513481 2528 * Determine number of antennas.
e4cd2ff8
ID		 2529 */
2530 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2531 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2532
95ea3627
ID		 2533 /*
2534 * Identify default antenna configuration.
2535 */
addc81bd 2536 rt2x00dev->default_ant.tx =
95ea3627 2537 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 2538 rt2x00dev->default_ant.rx =
95ea3627
ID		 2539 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2540
2541 /*
2542 * Read the Frame type.
2543 */
2544 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2545 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2546
95ea3627 2547 /*
b34e620f 2548 * Detect if this device has a hardware controlled radio.
95ea3627
ID		 2549 */
2550 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 2551 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 2552
2553 /*
2554 * Read frequency offset and RF programming sequence.
2555 */
2556 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2557 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2558 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2559
2560 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2561
2562 /*
2563 * Read external LNA informations.
2564 */
2565 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2566
2567 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2568 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2569 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2570 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2571
e4cd2ff8 2572 /*
b34e620f 2573 * When working with a RF2529 chip without double antenna,
e4cd2ff8
ID		 2574 * the antenna settings should be gathered from the NIC
2575 * eeprom word.
2576 */
5122d898 2577 if (rt2x00_rf(rt2x00dev, RF2529) &&
e4cd2ff8 2578 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
91581b62
ID		 2579 rt2x00dev->default_ant.rx =
2580 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2581 rt2x00dev->default_ant.tx =
2582 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
e4cd2ff8
ID		 2583
2584 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2585 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2586 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2587 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2588 }
2589
95ea3627
ID		 2590 /*
2591 * Store led settings, for correct led behaviour.
2592 * If the eeprom value is invalid,
2593 * switch to default led mode.
2594 */
771fd565 2595#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627 2596 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
a9450b70
ID		 2597 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2598
475433be
ID		 2599 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2600 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2601 if (value == LED_MODE_SIGNAL_STRENGTH)
2602 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2603 LED_TYPE_QUALITY);
95ea3627 2604
a9450b70
ID		 2605 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2606 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2607 rt2x00_get_field16(eeprom,
2608 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2609 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2610 rt2x00_get_field16(eeprom,
2611 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2612 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2613 rt2x00_get_field16(eeprom,
2614 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2615 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2616 rt2x00_get_field16(eeprom,
2617 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2618 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2619 rt2x00_get_field16(eeprom,
2620 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2621 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2622 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2623 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2624 rt2x00_get_field16(eeprom,
2625 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2626 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2627 rt2x00_get_field16(eeprom,
2628 EEPROM_LED_POLARITY_RDY_A));
771fd565 2629#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 2630
2631 return 0;
2632}
2633
2634/*
2635 * RF value list for RF5225 & RF5325
2636 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2637 */
2638static const struct rf_channel rf_vals_noseq[] = {
2639 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2640 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2641 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2642 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2643 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2644 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2645 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2646 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2647 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2648 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2649 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2650 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2651 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2652 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2653
2654 /* 802.11 UNI / HyperLan 2 */
2655 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2656 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2657 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2658 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2659 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2660 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2661 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2662 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2663
2664 /* 802.11 HyperLan 2 */
2665 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2666 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2667 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2668 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2669 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2670 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2671 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2672 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2673 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2674 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2675
2676 /* 802.11 UNII */
2677 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2678 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2679 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2680 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2681 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2682 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2683
2684 /* MMAC(Japan)J52 ch 34,38,42,46 */
2685 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2686 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2687 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2688 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2689};
2690
2691/*
2692 * RF value list for RF5225 & RF5325
2693 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2694 */
2695static const struct rf_channel rf_vals_seq[] = {
2696 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2697 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2698 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2699 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2700 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2701 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2702 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2703 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2704 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2705 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2706 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2707 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2708 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2709 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2710
2711 /* 802.11 UNI / HyperLan 2 */
2712 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2713 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2714 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2715 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2716 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2717 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2718 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2719 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2720
2721 /* 802.11 HyperLan 2 */
2722 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2723 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2724 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2725 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2726 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2727 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2728 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2729 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2730 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2731 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2732
2733 /* 802.11 UNII */
2734 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2735 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2736 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2737 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2738 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2739 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2740
2741 /* MMAC(Japan)J52 ch 34,38,42,46 */
2742 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2743 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2744 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2745 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2746};
2747
8c5e7a5f 2748static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2749{
2750 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2751 struct channel_info *info;
2752 char *tx_power;
95ea3627
ID		 2753 unsigned int i;
2754
93b6bd26
GW		 2755 /*
2756 * Disable powersaving as default.
2757 */
2758 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2759
95ea3627
ID		 2760 /*
2761 * Initialize all hw fields.
2762 */
2763 rt2x00dev->hw->flags =
566bfe5a 2764 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2765 IEEE80211_HW_SIGNAL_DBM |
2766 IEEE80211_HW_SUPPORTS_PS |
2767 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2768
14a3bf89 2769 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2770 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2771 rt2x00_eeprom_addr(rt2x00dev,
2772 EEPROM_MAC_ADDR_0));
2773
95ea3627 2774 /*
e1b4d7b7
ID		 2775 * As rt61 has a global fallback table we cannot specify
2776 * more then one tx rate per frame but since the hw will
2777 * try several rates (based on the fallback table) we should
ba3b9e5e 2778 * initialize max_report_rates to the maximum number of rates
e1b4d7b7
ID		 2779 * we are going to try. Otherwise mac80211 will truncate our
2780 * reported tx rates and the rc algortihm will end up with
2781 * incorrect data.
2782 */
ba3b9e5e
HS		 2783 rt2x00dev->hw->max_rates = 1;
2784 rt2x00dev->hw->max_report_rates = 7;
e1b4d7b7
ID		 2785 rt2x00dev->hw->max_rate_tries = 1;
2786
2787 /*
95ea3627
ID		 2788 * Initialize hw_mode information.
2789 */
31562e80
ID		 2790 spec->supported_bands = SUPPORT_BAND_2GHZ;
2791 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2792
2793 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2794 spec->num_channels = 14;
2795 spec->channels = rf_vals_noseq;
2796 } else {
2797 spec->num_channels = 14;
2798 spec->channels = rf_vals_seq;
2799 }
2800
5122d898 2801 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
31562e80 2802 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627 2803 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
8c5e7a5f
ID		 2804 }
2805
2806 /*
2807 * Create channel information array
2808 */
baeb2ffa 2809 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 2810 if (!info)
2811 return -ENOMEM;
2812
2813 spec->channels_info = info;
95ea3627 2814
8c5e7a5f 2815 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
8d1331b3
ID		 2816 for (i = 0; i < 14; i++) {
2817 info[i].max_power = MAX_TXPOWER;
2818 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2819 }
95ea3627 2820
8c5e7a5f
ID		 2821 if (spec->num_channels > 14) {
2822 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
8d1331b3
ID		 2823 for (i = 14; i < spec->num_channels; i++) {
2824 info[i].max_power = MAX_TXPOWER;
2825 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2826 }
95ea3627 2827 }
8c5e7a5f
ID		 2828
2829 return 0;
95ea3627
ID		 2830}
2831
2832static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2833{
2834 int retval;
2835
117839bd
PR		 2836 /*
2837 * Disable power saving.
2838 */
2839 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2840
95ea3627
ID		 2841 /*
2842 * Allocate eeprom data.
2843 */
2844 retval = rt61pci_validate_eeprom(rt2x00dev);
2845 if (retval)
2846 return retval;
2847
2848 retval = rt61pci_init_eeprom(rt2x00dev);
2849 if (retval)
2850 return retval;
2851
2852 /*
2853 * Initialize hw specifications.
2854 */
8c5e7a5f
ID		 2855 retval = rt61pci_probe_hw_mode(rt2x00dev);
2856 if (retval)
2857 return retval;
95ea3627 2858
1afcfd54
IP		 2859 /*
2860 * This device has multiple filters for control frames,
2861 * but has no a separate filter for PS Poll frames.
2862 */
2863 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2864
95ea3627 2865 /*
c4da0048 2866 * This device requires firmware and DMA mapped skbs.
95ea3627 2867 */
066cb637 2868 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
c4da0048 2869 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
008c4482
ID		 2870 if (!modparam_nohwcrypt)
2871 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
27df2a9c 2872 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
95ea3627
ID		 2873
2874 /*
2875 * Set the rssi offset.
2876 */
2877 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2878
2879 return 0;
2880}
2881
2882/*
2883 * IEEE80211 stack callback functions.
2884 */
2af0a570
ID		 2885static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2886 const struct ieee80211_tx_queue_params *params)
2887{
2888 struct rt2x00_dev *rt2x00dev = hw->priv;
2889 struct data_queue *queue;
2890 struct rt2x00_field32 field;
2891 int retval;
2892 u32 reg;
5e790023 2893 u32 offset;
2af0a570
ID		 2894
2895 /*
2896 * First pass the configuration through rt2x00lib, that will
2897 * update the queue settings and validate the input. After that
2898 * we are free to update the registers based on the value
2899 * in the queue parameter.
2900 */
2901 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2902 if (retval)
2903 return retval;
2904
5e790023
ID		 2905 /*
2906 * We only need to perform additional register initialization
b34e620f 2907 * for WMM queues.
5e790023
ID		 2908 */
2909 if (queue_idx >= 4)
2910 return 0;
2911
2af0a570
ID		 2912 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2913
2914 /* Update WMM TXOP register */
5e790023
ID		 2915 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2916 field.bit_offset = (queue_idx & 1) * 16;
2917 field.bit_mask = 0xffff << field.bit_offset;
2918
2919 rt2x00pci_register_read(rt2x00dev, offset, &reg);
2920 rt2x00_set_field32(&reg, field, queue->txop);
2921 rt2x00pci_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2922
2923 /* Update WMM registers */
2924 field.bit_offset = queue_idx * 4;
2925 field.bit_mask = 0xf << field.bit_offset;
2926
2927 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2928 rt2x00_set_field32(&reg, field, queue->aifs);
2929 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2930
2931 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2932 rt2x00_set_field32(&reg, field, queue->cw_min);
2933 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2934
2935 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2936 rt2x00_set_field32(&reg, field, queue->cw_max);
2937 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2938
2939 return 0;
2940}
2941
95ea3627
ID		 2942static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2943{
2944 struct rt2x00_dev *rt2x00dev = hw->priv;
2945 u64 tsf;
2946 u32 reg;
2947
2948 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2949 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2950 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2951 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2952
2953 return tsf;
2954}
2955
95ea3627
ID		 2956static const struct ieee80211_ops rt61pci_mac80211_ops = {
2957 .tx = rt2x00mac_tx,
4150c572
JB		 2958 .start = rt2x00mac_start,
2959 .stop = rt2x00mac_stop,
95ea3627
ID		 2960 .add_interface = rt2x00mac_add_interface,
2961 .remove_interface = rt2x00mac_remove_interface,
2962 .config = rt2x00mac_config,
3a643d24 2963 .configure_filter = rt2x00mac_configure_filter,
61e754f4 2964 .set_key = rt2x00mac_set_key,
d8147f9d
ID		 2965 .sw_scan_start = rt2x00mac_sw_scan_start,
2966 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 2967 .get_stats = rt2x00mac_get_stats,
471b3efd 2968 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2969 .conf_tx = rt61pci_conf_tx,
95ea3627 2970 .get_tsf = rt61pci_get_tsf,
e47a5cdd 2971 .rfkill_poll = rt2x00mac_rfkill_poll,
f44df18c 2972 .flush = rt2x00mac_flush,
95ea3627
ID		 2973};
2974
2975static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2976 .irq_handler = rt61pci_interrupt,
5846a550
HS		 2977 .txstatus_tasklet = rt61pci_txstatus_tasklet,
2978 .tbtt_tasklet = rt61pci_tbtt_tasklet,
2979 .rxdone_tasklet = rt61pci_rxdone_tasklet,
2980 .autowake_tasklet = rt61pci_autowake_tasklet,
95ea3627
ID		 2981 .probe_hw = rt61pci_probe_hw,
2982 .get_firmware_name = rt61pci_get_firmware_name,
0cbe0064 2983 .check_firmware = rt61pci_check_firmware,
95ea3627
ID		 2984 .load_firmware = rt61pci_load_firmware,
2985 .initialize = rt2x00pci_initialize,
2986 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 2987 .get_entry_state = rt61pci_get_entry_state,
2988 .clear_entry = rt61pci_clear_entry,
95ea3627 2989 .set_device_state = rt61pci_set_device_state,
95ea3627 2990 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2991 .link_stats = rt61pci_link_stats,
2992 .reset_tuner = rt61pci_reset_tuner,
2993 .link_tuner = rt61pci_link_tuner,
dbba306f
ID		 2994 .start_queue = rt61pci_start_queue,
2995 .kick_queue = rt61pci_kick_queue,
2996 .stop_queue = rt61pci_stop_queue,
95ea3627 2997 .write_tx_desc = rt61pci_write_tx_desc,
bd88a781 2998 .write_beacon = rt61pci_write_beacon,
69cf36a4 2999 .clear_beacon = rt61pci_clear_beacon,
95ea3627 3000 .fill_rxdone = rt61pci_fill_rxdone,
61e754f4
ID		 3001 .config_shared_key = rt61pci_config_shared_key,
3002 .config_pairwise_key = rt61pci_config_pairwise_key,
3a643d24 3003 .config_filter = rt61pci_config_filter,
6bb40dd1 3004 .config_intf = rt61pci_config_intf,
72810379 3005 .config_erp = rt61pci_config_erp,
e4ea1c40 3006 .config_ant = rt61pci_config_ant,
95ea3627
ID		 3007 .config = rt61pci_config,
3008};
3009
181d6902 3010static const struct data_queue_desc rt61pci_queue_rx = {
efd2f271 3011 .entry_num = 32,
181d6902
ID		 3012 .data_size = DATA_FRAME_SIZE,
3013 .desc_size = RXD_DESC_SIZE,
b8be63ff 3014 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 3015};
3016
3017static const struct data_queue_desc rt61pci_queue_tx = {
efd2f271 3018 .entry_num = 32,
181d6902
ID		 3019 .data_size = DATA_FRAME_SIZE,
3020 .desc_size = TXD_DESC_SIZE,
b8be63ff 3021 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 3022};
3023
3024static const struct data_queue_desc rt61pci_queue_bcn = {
efd2f271 3025 .entry_num = 4,
78720897 3026 .data_size = 0, /* No DMA required for beacons */
181d6902 3027 .desc_size = TXINFO_SIZE,
b8be63ff 3028 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 3029};
3030
95ea3627 3031static const struct rt2x00_ops rt61pci_ops = {
04d0362e
GW		 3032 .name = KBUILD_MODNAME,
3033 .max_sta_intf = 1,
3034 .max_ap_intf = 4,
3035 .eeprom_size = EEPROM_SIZE,
3036 .rf_size = RF_SIZE,
3037 .tx_queues = NUM_TX_QUEUES,
e6218cc4 3038 .extra_tx_headroom = 0,
04d0362e
GW		 3039 .rx = &rt61pci_queue_rx,
3040 .tx = &rt61pci_queue_tx,
3041 .bcn = &rt61pci_queue_bcn,
3042 .lib = &rt61pci_rt2x00_ops,
3043 .hw = &rt61pci_mac80211_ops,
95ea3627 3044#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 3045 .debugfs = &rt61pci_rt2x00debug,
95ea3627
ID		 3046#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3047};
3048
3049/*
3050 * RT61pci module information.
3051 */
a3aa1884 3052static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
95ea3627
ID		 3053 /* RT2561s */
3054 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
3055 /* RT2561 v2 */
3056 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
3057 /* RT2661 */
3058 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
3059 { 0, }
3060};
3061
3062MODULE_AUTHOR(DRV_PROJECT);
3063MODULE_VERSION(DRV_VERSION);
3064MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
3065MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
3066 "PCI & PCMCIA chipset based cards");
3067MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
3068MODULE_FIRMWARE(FIRMWARE_RT2561);
3069MODULE_FIRMWARE(FIRMWARE_RT2561s);
3070MODULE_FIRMWARE(FIRMWARE_RT2661);
3071MODULE_LICENSE("GPL");
3072
3073static struct pci_driver rt61pci_driver = {
2360157c 3074 .name = KBUILD_MODNAME,
95ea3627
ID		 3075 .id_table = rt61pci_device_table,
3076 .probe = rt2x00pci_probe,
3077 .remove = __devexit_p(rt2x00pci_remove),
3078 .suspend = rt2x00pci_suspend,
3079 .resume = rt2x00pci_resume,
3080};
3081
3082static int __init rt61pci_init(void)
3083{
3084 return pci_register_driver(&rt61pci_driver);
3085}
3086
3087static void __exit rt61pci_exit(void)
3088{
3089 pci_unregister_driver(&rt61pci_driver);
3090}
3091
3092module_init(rt61pci_init);
3093module_exit(rt61pci_exit);
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