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rt2x00: Enable master and adhoc mode again
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt61pci.h"
38
39/*
40 * Register access.
41 * BBP and RF register require indirect register access,
42 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
43 * These indirect registers work with busy bits,
44 * and we will try maximal REGISTER_BUSY_COUNT times to access
45 * the register while taking a REGISTER_BUSY_DELAY us delay
46 * between each attampt. When the busy bit is still set at that time,
47 * the access attempt is considered to have failed,
48 * and we will print an error.
49 */
0e14f6d3 50static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 51{
52 u32 reg;
53 unsigned int i;
54
55 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
56 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
57 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
58 break;
59 udelay(REGISTER_BUSY_DELAY);
60 }
61
62 return reg;
63}
64
0e14f6d3 65static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 66 const unsigned int word, const u8 value)
67{
68 u32 reg;
69
70 /*
71 * Wait until the BBP becomes ready.
72 */
73 reg = rt61pci_bbp_check(rt2x00dev);
74 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
75 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
76 return;
77 }
78
79 /*
80 * Write the data into the BBP.
81 */
82 reg = 0;
83 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
84 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
85 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
86 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
87
88 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
89}
90
0e14f6d3 91static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 92 const unsigned int word, u8 *value)
93{
94 u32 reg;
95
96 /*
97 * Wait until the BBP becomes ready.
98 */
99 reg = rt61pci_bbp_check(rt2x00dev);
100 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
101 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
102 return;
103 }
104
105 /*
106 * Write the request into the BBP.
107 */
108 reg = 0;
109 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
110 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
111 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
112
113 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
114
115 /*
116 * Wait until the BBP becomes ready.
117 */
118 reg = rt61pci_bbp_check(rt2x00dev);
119 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
120 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
121 *value = 0xff;
122 return;
123 }
124
125 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
126}
127
0e14f6d3 128static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 129 const unsigned int word, const u32 value)
130{
131 u32 reg;
132 unsigned int i;
133
134 if (!word)
135 return;
136
137 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
138 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
139 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
140 goto rf_write;
141 udelay(REGISTER_BUSY_DELAY);
142 }
143
144 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
145 return;
146
147rf_write:
148 reg = 0;
149 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
150 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
151 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
152 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
153
154 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
155 rt2x00_rf_write(rt2x00dev, word, value);
156}
157
0e14f6d3 158static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 159 const u8 command, const u8 token,
160 const u8 arg0, const u8 arg1)
161{
162 u32 reg;
163
164 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
165
166 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
167 ERROR(rt2x00dev, "mcu request error. "
168 "Request 0x%02x failed for token 0x%02x.\n",
169 command, token);
170 return;
171 }
172
173 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
174 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
175 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
176 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
177 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
178
179 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
180 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
181 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
182 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
183}
184
185static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
186{
187 struct rt2x00_dev *rt2x00dev = eeprom->data;
188 u32 reg;
189
190 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
191
192 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
193 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
194 eeprom->reg_data_clock =
195 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
196 eeprom->reg_chip_select =
197 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
198}
199
200static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
201{
202 struct rt2x00_dev *rt2x00dev = eeprom->data;
203 u32 reg = 0;
204
205 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
206 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
207 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
208 !!eeprom->reg_data_clock);
209 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
210 !!eeprom->reg_chip_select);
211
212 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
213}
214
215#ifdef CONFIG_RT2X00_LIB_DEBUGFS
216#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
217
0e14f6d3 218static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 219 const unsigned int word, u32 *data)
220{
221 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
222}
223
0e14f6d3 224static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 225 const unsigned int word, u32 data)
226{
227 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
228}
229
230static const struct rt2x00debug rt61pci_rt2x00debug = {
231 .owner = THIS_MODULE,
232 .csr = {
233 .read = rt61pci_read_csr,
234 .write = rt61pci_write_csr,
235 .word_size = sizeof(u32),
236 .word_count = CSR_REG_SIZE / sizeof(u32),
237 },
238 .eeprom = {
239 .read = rt2x00_eeprom_read,
240 .write = rt2x00_eeprom_write,
241 .word_size = sizeof(u16),
242 .word_count = EEPROM_SIZE / sizeof(u16),
243 },
244 .bbp = {
245 .read = rt61pci_bbp_read,
246 .write = rt61pci_bbp_write,
247 .word_size = sizeof(u8),
248 .word_count = BBP_SIZE / sizeof(u8),
249 },
250 .rf = {
251 .read = rt2x00_rf_read,
252 .write = rt61pci_rf_write,
253 .word_size = sizeof(u32),
254 .word_count = RF_SIZE / sizeof(u32),
255 },
256};
257#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
258
259#ifdef CONFIG_RT61PCI_RFKILL
260static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
261{
262 u32 reg;
263
264 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 265 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 266}
81873e9c
ID		 267#else
268#define rt61pci_rfkill_poll NULL
dcf5475b 269#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627
ID		 270
271/*
272 * Configuration handlers.
273 */
4abee4bb 274static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
95ea3627 275{
95ea3627
ID		 276 u32 tmp;
277
4abee4bb 278 tmp = le32_to_cpu(mac[1]);
95ea3627 279 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
4abee4bb 280 mac[1] = cpu_to_le32(tmp);
95ea3627 281
4abee4bb
ID		 282 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
283 (2 * sizeof(__le32)));
95ea3627
ID		 284}
285
4abee4bb 286static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
95ea3627 287{
95ea3627
ID		 288 u32 tmp;
289
4abee4bb 290 tmp = le32_to_cpu(bssid[1]);
95ea3627 291 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
4abee4bb 292 bssid[1] = cpu_to_le32(tmp);
95ea3627 293
4abee4bb
ID		 294 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
295 (2 * sizeof(__le32)));
95ea3627
ID		 296}
297
feb24691
ID		 298static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
299 const int tsf_sync)
95ea3627
ID		 300{
301 u32 reg;
302
303 /*
304 * Clear current synchronisation setup.
305 * For the Beacon base registers we only need to clear
306 * the first byte since that byte contains the VALID and OWNER
307 * bits which (when set to 0) will invalidate the entire beacon.
308 */
309 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
310 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
311 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
312 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
313 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
314
95ea3627
ID		 315 /*
316 * Enable synchronisation.
317 */
318 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
4150c572 319 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
3867705b
ID		 320 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE,
321 (tsf_sync == TSF_SYNC_BEACON));
95ea3627 322 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
feb24691 323 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
95ea3627
ID		 324 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
325}
326
5c58ee51
ID		 327static void rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
328 const int short_preamble,
329 const int ack_timeout,
330 const int ack_consume_time)
95ea3627 331{
95ea3627 332 u32 reg;
95ea3627
ID		 333
334 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
5c58ee51 335 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
95ea3627
ID		 336 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
337
338 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 339 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
5c58ee51 340 !!short_preamble);
95ea3627
ID		 341 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
342}
343
344static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 345 const int basic_rate_mask)
95ea3627 346{
5c58ee51 347 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 348}
349
5c58ee51
ID		 350static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
351 struct rf_channel *rf, const int txpower)
95ea3627
ID		 352{
353 u8 r3;
354 u8 r94;
355 u8 smart;
356
357 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
358 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
359
360 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
361 rt2x00_rf(&rt2x00dev->chip, RF2527));
362
363 rt61pci_bbp_read(rt2x00dev, 3, &r3);
364 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
365 rt61pci_bbp_write(rt2x00dev, 3, r3);
366
367 r94 = 6;
368 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
369 r94 += txpower - MAX_TXPOWER;
370 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
371 r94 += txpower;
372 rt61pci_bbp_write(rt2x00dev, 94, r94);
373
374 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
375 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
376 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
377 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
378
379 udelay(200);
380
381 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
382 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
383 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
384 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
385
386 udelay(200);
387
388 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
389 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
390 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
391 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
392
393 msleep(1);
394}
395
95ea3627
ID		 396static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
397 const int txpower)
398{
399 struct rf_channel rf;
400
401 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
402 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
403 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
404 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
405
5c58ee51 406 rt61pci_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 407}
408
409static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 410 struct antenna_setup *ant)
95ea3627
ID		 411{
412 u8 r3;
413 u8 r4;
414 u8 r77;
415
416 rt61pci_bbp_read(rt2x00dev, 3, &r3);
417 rt61pci_bbp_read(rt2x00dev, 4, &r4);
418 rt61pci_bbp_read(rt2x00dev, 77, &r77);
419
420 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 421 rt2x00_rf(&rt2x00dev->chip, RF5325));
e4cd2ff8
ID		 422
423 /*
424 * Configure the RX antenna.
425 */
addc81bd 426 switch (ant->rx) {
95ea3627 427 case ANTENNA_HW_DIVERSITY:
acaa410d 428 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 429 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
ddc827f9 430 (rt2x00dev->curr_hwmode != HWMODE_A));
95ea3627
ID		 431 break;
432 case ANTENNA_A:
acaa410d 433 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 434 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
acaa410d
MN		 435 if (rt2x00dev->curr_hwmode == HWMODE_A)
436 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
437 else
438 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627 439 break;
39e75857
ID		 440 case ANTENNA_SW_DIVERSITY:
441 /*
442 * NOTE: We should never come here because rt2x00lib is
443 * supposed to catch this and send us the correct antenna
444 * explicitely. However we are nog going to bug about this.
445 * Instead, just default to antenna B.
446 */
95ea3627 447 case ANTENNA_B:
acaa410d 448 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 449 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
acaa410d
MN		 450 if (rt2x00dev->curr_hwmode == HWMODE_A)
451 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
452 else
453 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 454 break;
455 }
456
457 rt61pci_bbp_write(rt2x00dev, 77, r77);
458 rt61pci_bbp_write(rt2x00dev, 3, r3);
459 rt61pci_bbp_write(rt2x00dev, 4, r4);
460}
461
462static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 463 struct antenna_setup *ant)
95ea3627
ID		 464{
465 u8 r3;
466 u8 r4;
467 u8 r77;
468
469 rt61pci_bbp_read(rt2x00dev, 3, &r3);
470 rt61pci_bbp_read(rt2x00dev, 4, &r4);
471 rt61pci_bbp_read(rt2x00dev, 77, &r77);
472
473 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 474 rt2x00_rf(&rt2x00dev->chip, RF2529));
95ea3627
ID		 475 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
476 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
477
e4cd2ff8
ID		 478 /*
479 * Configure the RX antenna.
480 */
addc81bd 481 switch (ant->rx) {
95ea3627 482 case ANTENNA_HW_DIVERSITY:
acaa410d 483 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 484 break;
485 case ANTENNA_A:
acaa410d
MN		 486 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
487 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627 488 break;
39e75857
ID		 489 case ANTENNA_SW_DIVERSITY:
490 /*
491 * NOTE: We should never come here because rt2x00lib is
492 * supposed to catch this and send us the correct antenna
493 * explicitely. However we are nog going to bug about this.
494 * Instead, just default to antenna B.
495 */
95ea3627 496 case ANTENNA_B:
acaa410d
MN		 497 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
498 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 499 break;
500 }
501
502 rt61pci_bbp_write(rt2x00dev, 77, r77);
503 rt61pci_bbp_write(rt2x00dev, 3, r3);
504 rt61pci_bbp_write(rt2x00dev, 4, r4);
505}
506
507static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
508 const int p1, const int p2)
509{
510 u32 reg;
511
512 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
513
acaa410d
MN		 514 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
515 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
516
517 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
518 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
519
520 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 521}
522
523static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 524 struct antenna_setup *ant)
95ea3627 525{
95ea3627
ID		 526 u8 r3;
527 u8 r4;
528 u8 r77;
529
530 rt61pci_bbp_read(rt2x00dev, 3, &r3);
531 rt61pci_bbp_read(rt2x00dev, 4, &r4);
532 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 533
acaa410d
MN		 534 /* FIXME: Antenna selection for the rf 2529 is very confusing in the
535 * legacy driver. The code below should be ok for non-diversity setups.
e4cd2ff8 536 */
95ea3627 537
e4cd2ff8
ID		 538 /*
539 * Configure the RX antenna.
540 */
541 switch (ant->rx) {
542 case ANTENNA_A:
acaa410d
MN		 543 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
544 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
545 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8
ID		 546 break;
547 case ANTENNA_SW_DIVERSITY:
548 case ANTENNA_HW_DIVERSITY:
549 /*
550 * NOTE: We should never come here because rt2x00lib is
551 * supposed to catch this and send us the correct antenna
552 * explicitely. However we are nog going to bug about this.
553 * Instead, just default to antenna B.
554 */
555 case ANTENNA_B:
acaa410d
MN		 556 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
557 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
558 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 559 break;
560 }
561
e4cd2ff8 562 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 563 rt61pci_bbp_write(rt2x00dev, 3, r3);
564 rt61pci_bbp_write(rt2x00dev, 4, r4);
565}
566
567struct antenna_sel {
568 u8 word;
569 /*
570 * value[0] -> non-LNA
571 * value[1] -> LNA
572 */
573 u8 value[2];
574};
575
576static const struct antenna_sel antenna_sel_a[] = {
577 { 96, { 0x58, 0x78 } },
578 { 104, { 0x38, 0x48 } },
579 { 75, { 0xfe, 0x80 } },
580 { 86, { 0xfe, 0x80 } },
581 { 88, { 0xfe, 0x80 } },
582 { 35, { 0x60, 0x60 } },
583 { 97, { 0x58, 0x58 } },
584 { 98, { 0x58, 0x58 } },
585};
586
587static const struct antenna_sel antenna_sel_bg[] = {
588 { 96, { 0x48, 0x68 } },
589 { 104, { 0x2c, 0x3c } },
590 { 75, { 0xfe, 0x80 } },
591 { 86, { 0xfe, 0x80 } },
592 { 88, { 0xfe, 0x80 } },
593 { 35, { 0x50, 0x50 } },
594 { 97, { 0x48, 0x48 } },
595 { 98, { 0x48, 0x48 } },
596};
597
598static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 599 struct antenna_setup *ant)
95ea3627
ID		 600{
601 const struct antenna_sel *sel;
602 unsigned int lna;
603 unsigned int i;
604 u32 reg;
605
95ea3627
ID		 606 if (rt2x00dev->curr_hwmode == HWMODE_A) {
607 sel = antenna_sel_a;
608 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 609 } else {
610 sel = antenna_sel_bg;
611 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 612 }
613
acaa410d
MN		 614 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
615 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
616
617 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
618
ddc827f9
ID		 619 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
620 (rt2x00dev->curr_hwmode == HWMODE_B ||
621 rt2x00dev->curr_hwmode == HWMODE_G));
622 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
623 (rt2x00dev->curr_hwmode == HWMODE_A));
624
95ea3627
ID		 625 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
626
627 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
628 rt2x00_rf(&rt2x00dev->chip, RF5325))
addc81bd 629 rt61pci_config_antenna_5x(rt2x00dev, ant);
95ea3627 630 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 631 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 632 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
633 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 634 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 635 else
addc81bd 636 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 637 }
638}
639
640static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 641 struct rt2x00lib_conf *libconf)
95ea3627
ID		 642{
643 u32 reg;
644
645 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 646 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 647 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
648
649 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 650 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 651 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 652 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 653 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
654
655 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
656 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
657 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
658
659 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
660 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
661 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
662
663 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 664 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
665 libconf->conf->beacon_int * 16);
95ea3627
ID		 666 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
667}
668
669static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
670 const unsigned int flags,
5c58ee51 671 struct rt2x00lib_conf *libconf)
95ea3627 672{
95ea3627 673 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 674 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 675 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 676 rt61pci_config_channel(rt2x00dev, &libconf->rf,
677 libconf->conf->power_level);
95ea3627 678 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 679 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 680 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 681 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 682 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 683 rt61pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 684}
685
686/*
687 * LED functions.
688 */
689static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
690{
691 u32 reg;
95ea3627
ID		 692 u8 arg0;
693 u8 arg1;
694
695 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
696 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
697 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
698 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
699
ddc827f9
ID		 700 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
701 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
702 (rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
703 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
704 (rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
95ea3627 705
ddc827f9
ID		 706 arg0 = rt2x00dev->led_reg & 0xff;
707 arg1 = (rt2x00dev->led_reg >> 8) & 0xff;
95ea3627
ID		 708
709 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
710}
711
712static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
713{
714 u16 led_reg;
715 u8 arg0;
716 u8 arg1;
717
718 led_reg = rt2x00dev->led_reg;
719 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
720 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
721 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
722
723 arg0 = led_reg & 0xff;
724 arg1 = (led_reg >> 8) & 0xff;
725
726 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
727}
728
729static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
730{
731 u8 led;
732
733 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
734 return;
735
736 /*
737 * Led handling requires a positive value for the rssi,
738 * to do that correctly we need to add the correction.
739 */
740 rssi += rt2x00dev->rssi_offset;
741
742 if (rssi <= 30)
743 led = 0;
744 else if (rssi <= 39)
745 led = 1;
746 else if (rssi <= 49)
747 led = 2;
748 else if (rssi <= 53)
749 led = 3;
750 else if (rssi <= 63)
751 led = 4;
752 else
753 led = 5;
754
755 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
756}
757
758/*
759 * Link tuning
760 */
ebcf26da
ID		 761static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
762 struct link_qual *qual)
95ea3627
ID		 763{
764 u32 reg;
765
766 /*
767 * Update FCS error count from register.
768 */
769 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 770 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 771
772 /*
773 * Update False CCA count from register.
774 */
775 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 776 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 777}
778
779static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
780{
781 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
782 rt2x00dev->link.vgc_level = 0x20;
783}
784
785static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
786{
787 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
788 u8 r17;
789 u8 up_bound;
790 u8 low_bound;
791
792 /*
793 * Update Led strength
794 */
795 rt61pci_activity_led(rt2x00dev, rssi);
796
797 rt61pci_bbp_read(rt2x00dev, 17, &r17);
798
799 /*
800 * Determine r17 bounds.
801 */
802 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
803 low_bound = 0x28;
804 up_bound = 0x48;
805 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
806 low_bound += 0x10;
807 up_bound += 0x10;
808 }
809 } else {
810 low_bound = 0x20;
811 up_bound = 0x40;
812 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
813 low_bound += 0x10;
814 up_bound += 0x10;
815 }
816 }
817
818 /*
819 * Special big-R17 for very short distance
820 */
821 if (rssi >= -35) {
822 if (r17 != 0x60)
823 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
824 return;
825 }
826
827 /*
828 * Special big-R17 for short distance
829 */
830 if (rssi >= -58) {
831 if (r17 != up_bound)
832 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
833 return;
834 }
835
836 /*
837 * Special big-R17 for middle-short distance
838 */
839 if (rssi >= -66) {
840 low_bound += 0x10;
841 if (r17 != low_bound)
842 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
843 return;
844 }
845
846 /*
847 * Special mid-R17 for middle distance
848 */
849 if (rssi >= -74) {
850 low_bound += 0x08;
851 if (r17 != low_bound)
852 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
853 return;
854 }
855
856 /*
857 * Special case: Change up_bound based on the rssi.
858 * Lower up_bound when rssi is weaker then -74 dBm.
859 */
860 up_bound -= 2 * (-74 - rssi);
861 if (low_bound > up_bound)
862 up_bound = low_bound;
863
864 if (r17 > up_bound) {
865 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
866 return;
867 }
868
869 /*
870 * r17 does not yet exceed upper limit, continue and base
871 * the r17 tuning on the false CCA count.
872 */
ebcf26da 873 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 874 if (++r17 > up_bound)
875 r17 = up_bound;
876 rt61pci_bbp_write(rt2x00dev, 17, r17);
ebcf26da 877 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 878 if (--r17 < low_bound)
879 r17 = low_bound;
880 rt61pci_bbp_write(rt2x00dev, 17, r17);
881 }
882}
883
884/*
885 * Firmware name function.
886 */
887static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
888{
889 char *fw_name;
890
891 switch (rt2x00dev->chip.rt) {
892 case RT2561:
893 fw_name = FIRMWARE_RT2561;
894 break;
895 case RT2561s:
896 fw_name = FIRMWARE_RT2561s;
897 break;
898 case RT2661:
899 fw_name = FIRMWARE_RT2661;
900 break;
901 default:
902 fw_name = NULL;
903 break;
904 }
905
906 return fw_name;
907}
908
909/*
910 * Initialization functions.
911 */
912static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
913 const size_t len)
914{
915 int i;
916 u32 reg;
917
918 /*
919 * Wait for stable hardware.
920 */
921 for (i = 0; i < 100; i++) {
922 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
923 if (reg)
924 break;
925 msleep(1);
926 }
927
928 if (!reg) {
929 ERROR(rt2x00dev, "Unstable hardware.\n");
930 return -EBUSY;
931 }
932
933 /*
934 * Prepare MCU and mailbox for firmware loading.
935 */
936 reg = 0;
937 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
938 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
939 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
940 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
941 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
942
943 /*
944 * Write firmware to device.
945 */
946 reg = 0;
947 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
948 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
949 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
950
951 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
952 data, len);
953
954 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
955 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
956
957 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
958 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
959
960 for (i = 0; i < 100; i++) {
961 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
962 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
963 break;
964 msleep(1);
965 }
966
967 if (i == 100) {
968 ERROR(rt2x00dev, "MCU Control register not ready.\n");
969 return -EBUSY;
970 }
971
972 /*
973 * Reset MAC and BBP registers.
974 */
975 reg = 0;
976 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
977 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
978 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
979
980 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
981 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
982 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
983 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
984
985 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
986 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
987 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
988
989 return 0;
990}
991
837e7f24 992static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 993 struct queue_entry *entry)
95ea3627 994{
181d6902 995 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 996 u32 word;
997
181d6902
ID		 998 rt2x00_desc_read(priv_rx->desc, 5, &word);
999 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, priv_rx->dma);
1000 rt2x00_desc_write(priv_rx->desc, 5, word);
95ea3627 1001
181d6902 1002 rt2x00_desc_read(priv_rx->desc, 0, &word);
837e7f24 1003 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
181d6902 1004 rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627
ID		 1005}
1006
837e7f24 1007static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 1008 struct queue_entry *entry)
95ea3627 1009{
181d6902 1010 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
95ea3627
ID		 1011 u32 word;
1012
181d6902 1013 rt2x00_desc_read(priv_tx->desc, 1, &word);
837e7f24 1014 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
181d6902 1015 rt2x00_desc_write(priv_tx->desc, 1, word);
95ea3627 1016
181d6902
ID		 1017 rt2x00_desc_read(priv_tx->desc, 5, &word);
1018 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
837e7f24 1019 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
181d6902 1020 rt2x00_desc_write(priv_tx->desc, 5, word);
95ea3627 1021
181d6902
ID		 1022 rt2x00_desc_read(priv_tx->desc, 6, &word);
1023 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, priv_tx->dma);
1024 rt2x00_desc_write(priv_tx->desc, 6, word);
95ea3627 1025
181d6902 1026 rt2x00_desc_read(priv_tx->desc, 0, &word);
837e7f24
ID		 1027 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1028 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
181d6902 1029 rt2x00_desc_write(priv_tx->desc, 0, word);
95ea3627
ID		 1030}
1031
181d6902 1032static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1033{
181d6902
ID		 1034 struct queue_entry_priv_pci_rx *priv_rx;
1035 struct queue_entry_priv_pci_tx *priv_tx;
95ea3627
ID		 1036 u32 reg;
1037
95ea3627
ID		 1038 /*
1039 * Initialize registers.
1040 */
1041 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1042 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1043 rt2x00dev->tx[0].limit);
95ea3627 1044 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1045 rt2x00dev->tx[1].limit);
95ea3627 1046 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1047 rt2x00dev->tx[2].limit);
95ea3627 1048 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1049 rt2x00dev->tx[3].limit);
95ea3627
ID		 1050 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1051
1052 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1053 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1054 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1055 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1056
181d6902 1057 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1058 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
181d6902 1059 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 1060 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1061
181d6902 1062 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1063 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
181d6902 1064 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 1065 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1066
181d6902 1067 priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1068 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
181d6902 1069 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 1070 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1071
181d6902 1072 priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1073 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
181d6902 1074 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 1075 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1076
95ea3627 1077 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1078 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1079 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1080 rt2x00dev->rx->desc_size / 4);
1081 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1082 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1083
181d6902 1084 priv_rx = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1085 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
181d6902 1086 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER, priv_rx->dma);
95ea3627
ID		 1087 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1088
1089 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1090 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1091 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1092 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1093 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1094 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_MGMT, 0);
1095 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1096
1097 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1098 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1099 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1100 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1101 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
181d6902 1102 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 0);
95ea3627
ID		 1103 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1104
1105 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1106 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1107 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1108
1109 return 0;
1110}
1111
1112static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1113{
1114 u32 reg;
1115
1116 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1117 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1118 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1119 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1120 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1121
1122 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1123 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1124 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1125 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1126 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1127 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1128 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1129 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1130 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1131 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1132
1133 /*
1134 * CCK TXD BBP registers
1135 */
1136 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1137 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1138 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1139 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1140 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1141 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1142 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1143 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1144 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1145 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1146
1147 /*
1148 * OFDM TXD BBP registers
1149 */
1150 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1151 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1152 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1153 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1154 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1155 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1156 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1157 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1158
1159 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1160 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1161 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1162 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1163 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1164 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1165
1166 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1167 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1168 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1169 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1170 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1171 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1172
1173 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1174
1175 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1176
1177 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1178 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1179 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1180
1181 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1182
1183 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1184 return -EBUSY;
1185
1186 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1187
1188 /*
1189 * Invalidate all Shared Keys (SEC_CSR0),
1190 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1191 */
1192 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1193 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1194 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1195
1196 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1197 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1198 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1199 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1200
1201 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1202
1203 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1204
1205 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1206
1207 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1208 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1209 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1210 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1211
1212 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1213 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1214 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1215 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1216
1217 /*
1218 * We must clear the error counters.
1219 * These registers are cleared on read,
1220 * so we may pass a useless variable to store the value.
1221 */
1222 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1223 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1224 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1225
1226 /*
1227 * Reset MAC and BBP registers.
1228 */
1229 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1230 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1231 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1232 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1233
1234 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1235 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1236 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1237 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1238
1239 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1240 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1241 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1242
1243 return 0;
1244}
1245
1246static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1247{
1248 unsigned int i;
1249 u16 eeprom;
1250 u8 reg_id;
1251 u8 value;
1252
1253 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1254 rt61pci_bbp_read(rt2x00dev, 0, &value);
1255 if ((value != 0xff) && (value != 0x00))
1256 goto continue_csr_init;
1257 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1258 udelay(REGISTER_BUSY_DELAY);
1259 }
1260
1261 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1262 return -EACCES;
1263
1264continue_csr_init:
1265 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1266 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1267 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1268 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1269 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1270 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1271 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1272 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1273 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1274 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1275 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1276 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1277 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1278 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1279 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1280 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1281 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1282 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1283 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1284 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1285 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1286 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1287 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1288 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1289
1290 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1291 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1292 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1293
1294 if (eeprom != 0xffff && eeprom != 0x0000) {
1295 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1296 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1297 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1298 reg_id, value);
1299 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1300 }
1301 }
1302 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1303
1304 return 0;
1305}
1306
1307/*
1308 * Device state switch handlers.
1309 */
1310static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1311 enum dev_state state)
1312{
1313 u32 reg;
1314
1315 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1316 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1317 state == STATE_RADIO_RX_OFF);
1318 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1319}
1320
1321static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1322 enum dev_state state)
1323{
1324 int mask = (state == STATE_RADIO_IRQ_OFF);
1325 u32 reg;
1326
1327 /*
1328 * When interrupts are being enabled, the interrupt registers
1329 * should clear the register to assure a clean state.
1330 */
1331 if (state == STATE_RADIO_IRQ_ON) {
1332 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1333 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1334
1335 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1336 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1337 }
1338
1339 /*
1340 * Only toggle the interrupts bits we are going to use.
1341 * Non-checked interrupt bits are disabled by default.
1342 */
1343 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1344 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1345 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1346 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1347 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1348 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1349
1350 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1351 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1352 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1353 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1354 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1355 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1356 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1357 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1358 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1359 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1360}
1361
1362static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1363{
1364 u32 reg;
1365
1366 /*
1367 * Initialize all registers.
1368 */
181d6902 1369 if (rt61pci_init_queues(rt2x00dev) ||
95ea3627
ID		 1370 rt61pci_init_registers(rt2x00dev) ||
1371 rt61pci_init_bbp(rt2x00dev)) {
1372 ERROR(rt2x00dev, "Register initialization failed.\n");
1373 return -EIO;
1374 }
1375
1376 /*
1377 * Enable interrupts.
1378 */
1379 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1380
1381 /*
1382 * Enable RX.
1383 */
1384 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1385 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1386 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1387
1388 /*
1389 * Enable LED
1390 */
1391 rt61pci_enable_led(rt2x00dev);
1392
1393 return 0;
1394}
1395
1396static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1397{
1398 u32 reg;
1399
1400 /*
1401 * Disable LED
1402 */
1403 rt61pci_disable_led(rt2x00dev);
1404
1405 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1406
1407 /*
1408 * Disable synchronisation.
1409 */
1410 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1411
1412 /*
1413 * Cancel RX and TX.
1414 */
1415 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1416 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1417 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1418 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1419 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1420 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1421 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1422
1423 /*
1424 * Disable interrupts.
1425 */
1426 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1427}
1428
1429static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1430{
1431 u32 reg;
1432 unsigned int i;
1433 char put_to_sleep;
1434 char current_state;
1435
1436 put_to_sleep = (state != STATE_AWAKE);
1437
1438 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1439 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1440 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1441 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1442
1443 /*
1444 * Device is not guaranteed to be in the requested state yet.
1445 * We must wait until the register indicates that the
1446 * device has entered the correct state.
1447 */
1448 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1449 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1450 current_state =
1451 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1452 if (current_state == !put_to_sleep)
1453 return 0;
1454 msleep(10);
1455 }
1456
1457 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1458 "current device state %d.\n", !put_to_sleep, current_state);
1459
1460 return -EBUSY;
1461}
1462
1463static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1464 enum dev_state state)
1465{
1466 int retval = 0;
1467
1468 switch (state) {
1469 case STATE_RADIO_ON:
1470 retval = rt61pci_enable_radio(rt2x00dev);
1471 break;
1472 case STATE_RADIO_OFF:
1473 rt61pci_disable_radio(rt2x00dev);
1474 break;
1475 case STATE_RADIO_RX_ON:
61667d8d
ID		 1476 case STATE_RADIO_RX_ON_LINK:
1477 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1478 break;
95ea3627 1479 case STATE_RADIO_RX_OFF:
61667d8d
ID		 1480 case STATE_RADIO_RX_OFF_LINK:
1481 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 1482 break;
1483 case STATE_DEEP_SLEEP:
1484 case STATE_SLEEP:
1485 case STATE_STANDBY:
1486 case STATE_AWAKE:
1487 retval = rt61pci_set_state(rt2x00dev, state);
1488 break;
1489 default:
1490 retval = -ENOTSUPP;
1491 break;
1492 }
1493
1494 return retval;
1495}
1496
1497/*
1498 * TX descriptor initialization
1499 */
1500static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1501 struct sk_buff *skb,
181d6902 1502 struct txentry_desc *txdesc,
dd3193e1 1503 struct ieee80211_tx_control *control)
95ea3627 1504{
181d6902 1505 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1506 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1507 u32 word;
1508
1509 /*
1510 * Start writing the descriptor words.
1511 */
1512 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1513 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1514 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1515 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1516 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1517 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1518 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1519 rt2x00_desc_write(txd, 1, word);
1520
1521 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1522 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1523 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1524 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1525 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1526 rt2x00_desc_write(txd, 2, word);
1527
1528 rt2x00_desc_read(txd, 5, &word);
1529 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1530 TXPOWER_TO_DEV(control->power_level));
1531 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1532 rt2x00_desc_write(txd, 5, word);
1533
d7bafff3
AB		 1534 if (skbdesc->desc_len > TXINFO_SIZE) {
1535 rt2x00_desc_read(txd, 11, &word);
1536 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1537 rt2x00_desc_write(txd, 11, word);
1538 }
95ea3627
ID		 1539
1540 rt2x00_desc_read(txd, 0, &word);
1541 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1542 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1543 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1544 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1545 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1546 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1547 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1548 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1549 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1550 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1551 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1552 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1553 !!(control->flags &
1554 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1555 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
dd3193e1 1556 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627 1557 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1558 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1559 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1560 rt2x00_desc_write(txd, 0, word);
1561}
1562
1563/*
1564 * TX data initialization
1565 */
1566static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1567 unsigned int queue)
1568{
1569 u32 reg;
1570
1571 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1572 /*
1573 * For Wi-Fi faily generated beacons between participating
1574 * stations. Set TBTT phase adaptive adjustment step to 8us.
1575 */
1576 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1577
1578 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1579 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1580 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1581 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1582 }
1583 return;
1584 }
1585
1586 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
ddc827f9
ID		 1587 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0,
1588 (queue == IEEE80211_TX_QUEUE_DATA0));
1589 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1,
1590 (queue == IEEE80211_TX_QUEUE_DATA1));
1591 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
1592 (queue == IEEE80211_TX_QUEUE_DATA2));
1593 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1594 (queue == IEEE80211_TX_QUEUE_DATA3));
1595 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_MGMT,
1596 (queue == IEEE80211_TX_QUEUE_DATA4));
95ea3627
ID		 1597 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1598}
1599
1600/*
1601 * RX control handlers
1602 */
1603static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1604{
1605 u16 eeprom;
1606 u8 offset;
1607 u8 lna;
1608
1609 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1610 switch (lna) {
1611 case 3:
1612 offset = 90;
1613 break;
1614 case 2:
1615 offset = 74;
1616 break;
1617 case 1:
1618 offset = 64;
1619 break;
1620 default:
1621 return 0;
1622 }
1623
1624 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1625 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1626 offset += 14;
1627
1628 if (lna == 3 || lna == 2)
1629 offset += 10;
1630
1631 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1632 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1633 } else {
1634 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1635 offset += 14;
1636
1637 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1638 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1639 }
1640
1641 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1642}
1643
181d6902
ID		 1644static void rt61pci_fill_rxdone(struct queue_entry *entry,
1645 struct rxdone_entry_desc *rxdesc)
95ea3627 1646{
181d6902 1647 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 1648 u32 word0;
1649 u32 word1;
1650
181d6902
ID		 1651 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1652 rt2x00_desc_read(priv_rx->desc, 1, &word1);
95ea3627 1653
181d6902 1654 rxdesc->flags = 0;
4150c572 1655 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1656 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1657
1658 /*
1659 * Obtain the status about this packet.
1660 */
181d6902
ID		 1661 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1662 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1663 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1664 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1665 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
95ea3627
ID		 1666}
1667
1668/*
1669 * Interrupt functions.
1670 */
1671static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1672{
181d6902
ID		 1673 struct data_queue *queue;
1674 struct queue_entry *entry;
1675 struct queue_entry *entry_done;
1676 struct queue_entry_priv_pci_tx *priv_tx;
1677 struct txdone_entry_desc txdesc;
95ea3627
ID		 1678 u32 word;
1679 u32 reg;
1680 u32 old_reg;
1681 int type;
1682 int index;
95ea3627
ID		 1683
1684 /*
1685 * During each loop we will compare the freshly read
1686 * STA_CSR4 register value with the value read from
1687 * the previous loop. If the 2 values are equal then
1688 * we should stop processing because the chance it
1689 * quite big that the device has been unplugged and
1690 * we risk going into an endless loop.
1691 */
1692 old_reg = 0;
1693
1694 while (1) {
1695 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1696 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1697 break;
1698
1699 if (old_reg == reg)
1700 break;
1701 old_reg = reg;
1702
1703 /*
1704 * Skip this entry when it contains an invalid
181d6902 1705 * queue identication number.
95ea3627
ID		 1706 */
1707 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 1708 queue = rt2x00queue_get_queue(rt2x00dev, type);
1709 if (unlikely(!queue))
95ea3627
ID		 1710 continue;
1711
1712 /*
1713 * Skip this entry when it contains an invalid
1714 * index number.
1715 */
1716 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 1717 if (unlikely(index >= queue->limit))
95ea3627
ID		 1718 continue;
1719
181d6902
ID		 1720 entry = &queue->entries[index];
1721 priv_tx = entry->priv_data;
1722 rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627
ID		 1723
1724 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1725 !rt2x00_get_field32(word, TXD_W0_VALID))
1726 return;
1727
181d6902 1728 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 1729 while (entry != entry_done) {
181d6902
ID		 1730 /* Catch up.
1731 * Just report any entries we missed as failed.
1732 */
62bc060b 1733 WARNING(rt2x00dev,
181d6902
ID		 1734 "TX status report missed for entry %d\n",
1735 entry_done->entry_idx);
1736
1737 txdesc.status = TX_FAIL_OTHER;
1738 txdesc.retry = 0;
1739
1740 rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1741 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 1742 }
1743
95ea3627
ID		 1744 /*
1745 * Obtain the status about this packet.
1746 */
181d6902
ID		 1747 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1748 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 1749
181d6902 1750 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627
ID		 1751 }
1752}
1753
1754static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1755{
1756 struct rt2x00_dev *rt2x00dev = dev_instance;
1757 u32 reg_mcu;
1758 u32 reg;
1759
1760 /*
1761 * Get the interrupt sources & saved to local variable.
1762 * Write register value back to clear pending interrupts.
1763 */
1764 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1765 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1766
1767 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1768 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1769
1770 if (!reg && !reg_mcu)
1771 return IRQ_NONE;
1772
1773 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1774 return IRQ_HANDLED;
1775
1776 /*
1777 * Handle interrupts, walk through all bits
1778 * and run the tasks, the bits are checked in order of
1779 * priority.
1780 */
1781
1782 /*
1783 * 1 - Rx ring done interrupt.
1784 */
1785 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1786 rt2x00pci_rxdone(rt2x00dev);
1787
1788 /*
1789 * 2 - Tx ring done interrupt.
1790 */
1791 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1792 rt61pci_txdone(rt2x00dev);
1793
1794 /*
1795 * 3 - Handle MCU command done.
1796 */
1797 if (reg_mcu)
1798 rt2x00pci_register_write(rt2x00dev,
1799 M2H_CMD_DONE_CSR, 0xffffffff);
1800
1801 return IRQ_HANDLED;
1802}
1803
1804/*
1805 * Device probe functions.
1806 */
1807static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1808{
1809 struct eeprom_93cx6 eeprom;
1810 u32 reg;
1811 u16 word;
1812 u8 *mac;
1813 s8 value;
1814
1815 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1816
1817 eeprom.data = rt2x00dev;
1818 eeprom.register_read = rt61pci_eepromregister_read;
1819 eeprom.register_write = rt61pci_eepromregister_write;
1820 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1821 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1822 eeprom.reg_data_in = 0;
1823 eeprom.reg_data_out = 0;
1824 eeprom.reg_data_clock = 0;
1825 eeprom.reg_chip_select = 0;
1826
1827 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1828 EEPROM_SIZE / sizeof(u16));
1829
1830 /*
1831 * Start validation of the data that has been read.
1832 */
1833 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1834 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1835 DECLARE_MAC_BUF(macbuf);
1836
95ea3627 1837 random_ether_addr(mac);
0795af57 1838 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1839 }
1840
1841 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1842 if (word == 0xffff) {
1843 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1844 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1845 ANTENNA_B);
1846 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1847 ANTENNA_B);
95ea3627
ID		 1848 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1849 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1850 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1851 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1852 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1853 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1854 }
1855
1856 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1857 if (word == 0xffff) {
1858 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1859 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1860 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1861 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1862 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1863 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1864 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1865 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1866 }
1867
1868 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1869 if (word == 0xffff) {
1870 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1871 LED_MODE_DEFAULT);
1872 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1873 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1874 }
1875
1876 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1877 if (word == 0xffff) {
1878 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1879 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1880 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1881 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1882 }
1883
1884 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1885 if (word == 0xffff) {
1886 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1887 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1888 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1889 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1890 } else {
1891 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1892 if (value < -10 || value > 10)
1893 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1894 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1895 if (value < -10 || value > 10)
1896 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1897 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1898 }
1899
1900 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1901 if (word == 0xffff) {
1902 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1903 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1904 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1905 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1906 } else {
1907 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1908 if (value < -10 || value > 10)
1909 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1910 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1911 if (value < -10 || value > 10)
1912 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1913 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1914 }
1915
1916 return 0;
1917}
1918
1919static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1920{
1921 u32 reg;
1922 u16 value;
1923 u16 eeprom;
1924 u16 device;
1925
1926 /*
1927 * Read EEPROM word for configuration.
1928 */
1929 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1930
1931 /*
1932 * Identify RF chipset.
1933 * To determine the RT chip we have to read the
1934 * PCI header of the device.
1935 */
1936 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1937 PCI_CONFIG_HEADER_DEVICE, &device);
1938 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1939 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1940 rt2x00_set_chip(rt2x00dev, device, value, reg);
1941
1942 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1943 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1944 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1945 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1946 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1947 return -ENODEV;
1948 }
1949
e4cd2ff8
ID		 1950 /*
1951 * Determine number of antenna's.
1952 */
1953 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1954 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1955
95ea3627
ID		 1956 /*
1957 * Identify default antenna configuration.
1958 */
addc81bd 1959 rt2x00dev->default_ant.tx =
95ea3627 1960 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1961 rt2x00dev->default_ant.rx =
95ea3627
ID		 1962 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1963
1964 /*
1965 * Read the Frame type.
1966 */
1967 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1968 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1969
95ea3627
ID		 1970 /*
1971 * Detect if this device has an hardware controlled radio.
1972 */
81873e9c 1973#ifdef CONFIG_RT61PCI_RFKILL
95ea3627 1974 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1975 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1976#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627
ID		 1977
1978 /*
1979 * Read frequency offset and RF programming sequence.
1980 */
1981 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1982 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
1983 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
1984
1985 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1986
1987 /*
1988 * Read external LNA informations.
1989 */
1990 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1991
1992 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1993 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1994 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1995 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1996
e4cd2ff8
ID		 1997 /*
1998 * When working with a RF2529 chip without double antenna
1999 * the antenna settings should be gathered from the NIC
2000 * eeprom word.
2001 */
2002 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2003 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2004 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2005 case 0:
2006 rt2x00dev->default_ant.tx = ANTENNA_B;
2007 rt2x00dev->default_ant.rx = ANTENNA_A;
2008 break;
2009 case 1:
2010 rt2x00dev->default_ant.tx = ANTENNA_B;
2011 rt2x00dev->default_ant.rx = ANTENNA_B;
2012 break;
2013 case 2:
2014 rt2x00dev->default_ant.tx = ANTENNA_A;
2015 rt2x00dev->default_ant.rx = ANTENNA_A;
2016 break;
2017 case 3:
2018 rt2x00dev->default_ant.tx = ANTENNA_A;
2019 rt2x00dev->default_ant.rx = ANTENNA_B;
2020 break;
2021 }
2022
2023 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2024 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2025 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2026 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2027 }
2028
95ea3627
ID		 2029 /*
2030 * Store led settings, for correct led behaviour.
2031 * If the eeprom value is invalid,
2032 * switch to default led mode.
2033 */
2034 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2035
2036 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2037
2038 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2039 rt2x00dev->led_mode);
2040 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2041 rt2x00_get_field16(eeprom,
2042 EEPROM_LED_POLARITY_GPIO_0));
2043 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2044 rt2x00_get_field16(eeprom,
2045 EEPROM_LED_POLARITY_GPIO_1));
2046 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2047 rt2x00_get_field16(eeprom,
2048 EEPROM_LED_POLARITY_GPIO_2));
2049 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2050 rt2x00_get_field16(eeprom,
2051 EEPROM_LED_POLARITY_GPIO_3));
2052 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2053 rt2x00_get_field16(eeprom,
2054 EEPROM_LED_POLARITY_GPIO_4));
2055 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2056 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2057 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2058 rt2x00_get_field16(eeprom,
2059 EEPROM_LED_POLARITY_RDY_G));
2060 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2061 rt2x00_get_field16(eeprom,
2062 EEPROM_LED_POLARITY_RDY_A));
2063
2064 return 0;
2065}
2066
2067/*
2068 * RF value list for RF5225 & RF5325
2069 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2070 */
2071static const struct rf_channel rf_vals_noseq[] = {
2072 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2073 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2074 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2075 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2076 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2077 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2078 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2079 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2080 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2081 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2082 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2083 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2084 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2085 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2086
2087 /* 802.11 UNI / HyperLan 2 */
2088 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2089 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2090 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2091 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2092 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2093 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2094 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2095 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2096
2097 /* 802.11 HyperLan 2 */
2098 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2099 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2100 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2101 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2102 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2103 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2104 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2105 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2106 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2107 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2108
2109 /* 802.11 UNII */
2110 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2111 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2112 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2113 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2114 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2115 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2116
2117 /* MMAC(Japan)J52 ch 34,38,42,46 */
2118 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2119 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2120 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2121 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2122};
2123
2124/*
2125 * RF value list for RF5225 & RF5325
2126 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2127 */
2128static const struct rf_channel rf_vals_seq[] = {
2129 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2130 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2131 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2132 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2133 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2134 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2135 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2136 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2137 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2138 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2139 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2140 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2141 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2142 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2143
2144 /* 802.11 UNI / HyperLan 2 */
2145 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2146 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2147 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2148 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2149 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2150 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2151 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2152 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2153
2154 /* 802.11 HyperLan 2 */
2155 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2156 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2157 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2158 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2159 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2160 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2161 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2162 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2163 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2164 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2165
2166 /* 802.11 UNII */
2167 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2168 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2169 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2170 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2171 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2172 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2173
2174 /* MMAC(Japan)J52 ch 34,38,42,46 */
2175 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2176 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2177 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2178 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2179};
2180
2181static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2182{
2183 struct hw_mode_spec *spec = &rt2x00dev->spec;
2184 u8 *txpower;
2185 unsigned int i;
2186
2187 /*
2188 * Initialize all hw fields.
2189 */
2190 rt2x00dev->hw->flags =
2191 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 2192 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 2193 rt2x00dev->hw->extra_tx_headroom = 0;
2194 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2195 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2196 rt2x00dev->hw->queues = 5;
2197
2198 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2199 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2200 rt2x00_eeprom_addr(rt2x00dev,
2201 EEPROM_MAC_ADDR_0));
2202
2203 /*
2204 * Convert tx_power array in eeprom.
2205 */
2206 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2207 for (i = 0; i < 14; i++)
2208 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2209
2210 /*
2211 * Initialize hw_mode information.
2212 */
2213 spec->num_modes = 2;
2214 spec->num_rates = 12;
2215 spec->tx_power_a = NULL;
2216 spec->tx_power_bg = txpower;
2217 spec->tx_power_default = DEFAULT_TXPOWER;
2218
2219 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2220 spec->num_channels = 14;
2221 spec->channels = rf_vals_noseq;
2222 } else {
2223 spec->num_channels = 14;
2224 spec->channels = rf_vals_seq;
2225 }
2226
2227 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2228 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2229 spec->num_modes = 3;
2230 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2231
2232 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2233 for (i = 0; i < 14; i++)
2234 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2235
2236 spec->tx_power_a = txpower;
2237 }
2238}
2239
2240static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2241{
2242 int retval;
2243
2244 /*
2245 * Allocate eeprom data.
2246 */
2247 retval = rt61pci_validate_eeprom(rt2x00dev);
2248 if (retval)
2249 return retval;
2250
2251 retval = rt61pci_init_eeprom(rt2x00dev);
2252 if (retval)
2253 return retval;
2254
2255 /*
2256 * Initialize hw specifications.
2257 */
2258 rt61pci_probe_hw_mode(rt2x00dev);
2259
2260 /*
2261 * This device requires firmware
2262 */
066cb637 2263 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
95ea3627
ID		 2264
2265 /*
2266 * Set the rssi offset.
2267 */
2268 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2269
2270 return 0;
2271}
2272
2273/*
2274 * IEEE80211 stack callback functions.
2275 */
4150c572
JB		 2276static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2277 unsigned int changed_flags,
2278 unsigned int *total_flags,
2279 int mc_count,
2280 struct dev_addr_list *mc_list)
2281{
2282 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 2283 u32 reg;
2284
2285 /*
2286 * Mask off any flags we are going to ignore from
2287 * the total_flags field.
2288 */
2289 *total_flags &=
2290 FIF_ALLMULTI |
2291 FIF_FCSFAIL |
2292 FIF_PLCPFAIL |
2293 FIF_CONTROL |
2294 FIF_OTHER_BSS |
2295 FIF_PROMISC_IN_BSS;
2296
2297 /*
2298 * Apply some rules to the filters:
2299 * - Some filters imply different filters to be set.
2300 * - Some things we can't filter out at all.
4150c572
JB		 2301 */
2302 if (mc_count)
2303 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 2304 if (*total_flags & FIF_OTHER_BSS ||
2305 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 2306 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 2307
2308 /*
2309 * Check if there is any work left for us.
2310 */
3c4f2085 2311 if (rt2x00dev->packet_filter == *total_flags)
4150c572 2312 return;
3c4f2085 2313 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 2314
2315 /*
2316 * Start configuration steps.
2317 * Note that the version error will always be dropped
2318 * and broadcast frames will always be accepted since
2319 * there is no filter for it at this time.
2320 */
2321 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2322 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2323 !(*total_flags & FIF_FCSFAIL));
2324 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2325 !(*total_flags & FIF_PLCPFAIL));
2326 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2327 !(*total_flags & FIF_CONTROL));
2328 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2329 !(*total_flags & FIF_PROMISC_IN_BSS));
2330 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2331 !(*total_flags & FIF_PROMISC_IN_BSS));
2332 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2333 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2334 !(*total_flags & FIF_ALLMULTI));
2335 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
2336 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
2337 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2338}
2339
95ea3627
ID		 2340static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2341 u32 short_retry, u32 long_retry)
2342{
2343 struct rt2x00_dev *rt2x00dev = hw->priv;
2344 u32 reg;
2345
2346 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2347 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2348 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2349 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2350
2351 return 0;
2352}
2353
2354static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2355{
2356 struct rt2x00_dev *rt2x00dev = hw->priv;
2357 u64 tsf;
2358 u32 reg;
2359
2360 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2361 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2362 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2363 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2364
2365 return tsf;
2366}
2367
2368static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2369{
2370 struct rt2x00_dev *rt2x00dev = hw->priv;
2371
2372 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2373 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2374}
2375
24845910 2376static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
95ea3627
ID		 2377 struct ieee80211_tx_control *control)
2378{
2379 struct rt2x00_dev *rt2x00dev = hw->priv;
181d6902
ID		 2380 struct skb_frame_desc *skbdesc;
2381 struct data_queue *queue;
2382 struct queue_entry *entry;
95ea3627
ID		 2383
2384 /*
2385 * Just in case the ieee80211 doesn't set this,
2386 * but we need this queue set for the descriptor
2387 * initialization.
2388 */
2389 control->queue = IEEE80211_TX_QUEUE_BEACON;
181d6902
ID		 2390 queue = rt2x00queue_get_queue(rt2x00dev, control->queue);
2391 entry = rt2x00queue_get_entry(queue, Q_INDEX);
95ea3627
ID		 2392
2393 /*
2394 * We need to append the descriptor in front of the
2395 * beacon frame.
2396 */
181d6902
ID		 2397 if (skb_headroom(skb) < queue->desc_size) {
2398 if (pskb_expand_head(skb, queue->desc_size, 0, GFP_ATOMIC)) {
95ea3627
ID		 2399 dev_kfree_skb(skb);
2400 return -ENOMEM;
2401 }
2402 }
2403
2404 /*
08992f7f
ID		 2405 * Add the descriptor in front of the skb.
2406 */
181d6902
ID		 2407 skb_push(skb, queue->desc_size);
2408 memset(skb->data, 0, queue->desc_size);
08992f7f
ID		 2409
2410 /*
2411 * Fill in skb descriptor
95ea3627 2412 */
181d6902
ID		 2413 skbdesc = get_skb_frame_desc(skb);
2414 memset(skbdesc, 0, sizeof(*skbdesc));
2415 skbdesc->data = skb->data + queue->desc_size;
2416 skbdesc->data_len = queue->data_size;
2417 skbdesc->desc = skb->data;
2418 skbdesc->desc_len = queue->desc_size;
2419 skbdesc->entry = entry;
c22eb87b 2420
08992f7f 2421 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
95ea3627
ID		 2422
2423 /*
2424 * Write entire beacon with descriptor to register,
2425 * and kick the beacon generator.
2426 */
9ee8f57e
ID		 2427 rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0,
2428 skb->data, skb->len);
95ea3627
ID		 2429 rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2430
2431 return 0;
2432}
2433
2434static const struct ieee80211_ops rt61pci_mac80211_ops = {
2435 .tx = rt2x00mac_tx,
4150c572
JB		 2436 .start = rt2x00mac_start,
2437 .stop = rt2x00mac_stop,
95ea3627
ID		 2438 .add_interface = rt2x00mac_add_interface,
2439 .remove_interface = rt2x00mac_remove_interface,
2440 .config = rt2x00mac_config,
2441 .config_interface = rt2x00mac_config_interface,
4150c572 2442 .configure_filter = rt61pci_configure_filter,
95ea3627
ID		 2443 .get_stats = rt2x00mac_get_stats,
2444 .set_retry_limit = rt61pci_set_retry_limit,
471b3efd 2445 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2446 .conf_tx = rt2x00mac_conf_tx,
2447 .get_tx_stats = rt2x00mac_get_tx_stats,
2448 .get_tsf = rt61pci_get_tsf,
2449 .reset_tsf = rt61pci_reset_tsf,
2450 .beacon_update = rt61pci_beacon_update,
2451};
2452
2453static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2454 .irq_handler = rt61pci_interrupt,
2455 .probe_hw = rt61pci_probe_hw,
2456 .get_firmware_name = rt61pci_get_firmware_name,
2457 .load_firmware = rt61pci_load_firmware,
2458 .initialize = rt2x00pci_initialize,
2459 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 2460 .init_rxentry = rt61pci_init_rxentry,
2461 .init_txentry = rt61pci_init_txentry,
95ea3627 2462 .set_device_state = rt61pci_set_device_state,
95ea3627 2463 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2464 .link_stats = rt61pci_link_stats,
2465 .reset_tuner = rt61pci_reset_tuner,
2466 .link_tuner = rt61pci_link_tuner,
2467 .write_tx_desc = rt61pci_write_tx_desc,
2468 .write_tx_data = rt2x00pci_write_tx_data,
2469 .kick_tx_queue = rt61pci_kick_tx_queue,
2470 .fill_rxdone = rt61pci_fill_rxdone,
2471 .config_mac_addr = rt61pci_config_mac_addr,
2472 .config_bssid = rt61pci_config_bssid,
95ea3627 2473 .config_type = rt61pci_config_type,
5c58ee51 2474 .config_preamble = rt61pci_config_preamble,
95ea3627
ID		 2475 .config = rt61pci_config,
2476};
2477
181d6902
ID		 2478static const struct data_queue_desc rt61pci_queue_rx = {
2479 .entry_num = RX_ENTRIES,
2480 .data_size = DATA_FRAME_SIZE,
2481 .desc_size = RXD_DESC_SIZE,
2482 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
2483};
2484
2485static const struct data_queue_desc rt61pci_queue_tx = {
2486 .entry_num = TX_ENTRIES,
2487 .data_size = DATA_FRAME_SIZE,
2488 .desc_size = TXD_DESC_SIZE,
2489 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2490};
2491
2492static const struct data_queue_desc rt61pci_queue_bcn = {
2493 .entry_num = BEACON_ENTRIES,
2494 .data_size = MGMT_FRAME_SIZE,
2495 .desc_size = TXINFO_SIZE,
2496 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2497};
2498
95ea3627 2499static const struct rt2x00_ops rt61pci_ops = {
2360157c 2500 .name = KBUILD_MODNAME,
95ea3627
ID		 2501 .eeprom_size = EEPROM_SIZE,
2502 .rf_size = RF_SIZE,
181d6902
ID		 2503 .rx = &rt61pci_queue_rx,
2504 .tx = &rt61pci_queue_tx,
2505 .bcn = &rt61pci_queue_bcn,
95ea3627
ID		 2506 .lib = &rt61pci_rt2x00_ops,
2507 .hw = &rt61pci_mac80211_ops,
2508#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2509 .debugfs = &rt61pci_rt2x00debug,
2510#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2511};
2512
2513/*
2514 * RT61pci module information.
2515 */
2516static struct pci_device_id rt61pci_device_table[] = {
2517 /* RT2561s */
2518 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2519 /* RT2561 v2 */
2520 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2521 /* RT2661 */
2522 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2523 { 0, }
2524};
2525
2526MODULE_AUTHOR(DRV_PROJECT);
2527MODULE_VERSION(DRV_VERSION);
2528MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2529MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2530 "PCI & PCMCIA chipset based cards");
2531MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2532MODULE_FIRMWARE(FIRMWARE_RT2561);
2533MODULE_FIRMWARE(FIRMWARE_RT2561s);
2534MODULE_FIRMWARE(FIRMWARE_RT2661);
2535MODULE_LICENSE("GPL");
2536
2537static struct pci_driver rt61pci_driver = {
2360157c 2538 .name = KBUILD_MODNAME,
95ea3627
ID		 2539 .id_table = rt61pci_device_table,
2540 .probe = rt2x00pci_probe,
2541 .remove = __devexit_p(rt2x00pci_remove),
2542 .suspend = rt2x00pci_suspend,
2543 .resume = rt2x00pci_resume,
2544};
2545
2546static int __init rt61pci_init(void)
2547{
2548 return pci_register_driver(&rt61pci_driver);
2549}
2550
2551static void __exit rt61pci_exit(void)
2552{
2553 pci_unregister_driver(&rt61pci_driver);
2554}
2555
2556module_init(rt61pci_init);
2557module_exit(rt61pci_exit);
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