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rt2x00: Fix in_atomic() usage
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt73usb.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt73usb_register_read and rt73usb_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
3d82346c 51 * The _lock versions must be used if you already hold the usb_cache_mutex
95ea3627 52 */
0e14f6d3 53static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 54 const unsigned int offset, u32 *value)
55{
56 __le32 reg;
57 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
58 USB_VENDOR_REQUEST_IN, offset,
59 &reg, sizeof(u32), REGISTER_TIMEOUT);
60 *value = le32_to_cpu(reg);
61}
62
3d82346c
AB		 63static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
64 const unsigned int offset, u32 *value)
65{
66 __le32 reg;
67 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
68 USB_VENDOR_REQUEST_IN, offset,
69 &reg, sizeof(u32), REGISTER_TIMEOUT);
70 *value = le32_to_cpu(reg);
71}
72
0e14f6d3 73static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 74 const unsigned int offset,
75 void *value, const u32 length)
76{
77 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
78 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
79 USB_VENDOR_REQUEST_IN, offset,
80 value, length, timeout);
81}
82
0e14f6d3 83static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 84 const unsigned int offset, u32 value)
85{
86 __le32 reg = cpu_to_le32(value);
87 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
88 USB_VENDOR_REQUEST_OUT, offset,
89 &reg, sizeof(u32), REGISTER_TIMEOUT);
90}
91
3d82346c
AB		 92static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
93 const unsigned int offset, u32 value)
94{
95 __le32 reg = cpu_to_le32(value);
96 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
97 USB_VENDOR_REQUEST_OUT, offset,
98 &reg, sizeof(u32), REGISTER_TIMEOUT);
99}
100
0e14f6d3 101static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 102 const unsigned int offset,
103 void *value, const u32 length)
104{
105 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
106 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
107 USB_VENDOR_REQUEST_OUT, offset,
108 value, length, timeout);
109}
110
0e14f6d3 111static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 112{
113 u32 reg;
114 unsigned int i;
115
116 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 117 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
95ea3627
ID		 118 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
119 break;
120 udelay(REGISTER_BUSY_DELAY);
121 }
122
123 return reg;
124}
125
0e14f6d3 126static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 127 const unsigned int word, const u8 value)
128{
129 u32 reg;
130
3d82346c
AB		 131 mutex_lock(&rt2x00dev->usb_cache_mutex);
132
95ea3627
ID		 133 /*
134 * Wait until the BBP becomes ready.
135 */
136 reg = rt73usb_bbp_check(rt2x00dev);
137 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
138 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
3d82346c 139 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 140 return;
141 }
142
143 /*
144 * Write the data into the BBP.
145 */
146 reg = 0;
147 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
148 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
149 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
150 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
151
3d82346c
AB		 152 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
153 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 154}
155
0e14f6d3 156static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 157 const unsigned int word, u8 *value)
158{
159 u32 reg;
160
3d82346c
AB		 161 mutex_lock(&rt2x00dev->usb_cache_mutex);
162
95ea3627
ID		 163 /*
164 * Wait until the BBP becomes ready.
165 */
166 reg = rt73usb_bbp_check(rt2x00dev);
167 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
168 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
3d82346c 169 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 170 return;
171 }
172
173 /*
174 * Write the request into the BBP.
175 */
176 reg = 0;
177 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
178 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
179 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
180
3d82346c 181 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627
ID		 182
183 /*
184 * Wait until the BBP becomes ready.
185 */
186 reg = rt73usb_bbp_check(rt2x00dev);
187 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
188 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
189 *value = 0xff;
190 return;
191 }
192
193 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
3d82346c 194 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 195}
196
0e14f6d3 197static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 198 const unsigned int word, const u32 value)
199{
200 u32 reg;
201 unsigned int i;
202
203 if (!word)
204 return;
205
3d82346c
AB		 206 mutex_lock(&rt2x00dev->usb_cache_mutex);
207
95ea3627 208 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 209 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
95ea3627
ID		 210 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
211 goto rf_write;
212 udelay(REGISTER_BUSY_DELAY);
213 }
214
3d82346c 215 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 216 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
217 return;
218
219rf_write:
220 reg = 0;
221 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
222
4f5af6eb
ID		 223 /*
224 * RF5225 and RF2527 contain 21 bits per RF register value,
225 * all others contain 20 bits.
226 */
227 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
ddc827f9
ID		 228 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
229 rt2x00_rf(&rt2x00dev->chip, RF2527)));
95ea3627
ID		 230 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
231 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
232
3d82346c 233 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
95ea3627 234 rt2x00_rf_write(rt2x00dev, word, value);
3d82346c 235 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 236}
237
238#ifdef CONFIG_RT2X00_LIB_DEBUGFS
239#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
240
0e14f6d3 241static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 242 const unsigned int word, u32 *data)
243{
244 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
245}
246
0e14f6d3 247static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 248 const unsigned int word, u32 data)
249{
250 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
251}
252
253static const struct rt2x00debug rt73usb_rt2x00debug = {
254 .owner = THIS_MODULE,
255 .csr = {
256 .read = rt73usb_read_csr,
257 .write = rt73usb_write_csr,
258 .word_size = sizeof(u32),
259 .word_count = CSR_REG_SIZE / sizeof(u32),
260 },
261 .eeprom = {
262 .read = rt2x00_eeprom_read,
263 .write = rt2x00_eeprom_write,
264 .word_size = sizeof(u16),
265 .word_count = EEPROM_SIZE / sizeof(u16),
266 },
267 .bbp = {
268 .read = rt73usb_bbp_read,
269 .write = rt73usb_bbp_write,
270 .word_size = sizeof(u8),
271 .word_count = BBP_SIZE / sizeof(u8),
272 },
273 .rf = {
274 .read = rt2x00_rf_read,
275 .write = rt73usb_rf_write,
276 .word_size = sizeof(u32),
277 .word_count = RF_SIZE / sizeof(u32),
278 },
279};
280#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
281
a9450b70
ID		 282#ifdef CONFIG_RT73USB_LEDS
283static void rt73usb_led_brightness(struct led_classdev *led_cdev,
284 enum led_brightness brightness)
285{
286 struct rt2x00_led *led =
287 container_of(led_cdev, struct rt2x00_led, led_dev);
288 unsigned int enabled = brightness != LED_OFF;
289 unsigned int a_mode =
290 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
291 unsigned int bg_mode =
292 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
293
47b10cd1
ID		 294 if (in_atomic()) {
295 NOTICE(led->rt2x00dev,
61191fb2
LC		 296 "Ignoring LED brightness command for led %d\n",
297 led->type);
47b10cd1
ID		 298 return;
299 }
300
a9450b70
ID		 301 if (led->type == LED_TYPE_RADIO) {
302 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
303 MCU_LEDCS_RADIO_STATUS, enabled);
304
47b10cd1
ID		 305 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
306 0, led->rt2x00dev->led_mcu_reg,
307 REGISTER_TIMEOUT);
a9450b70
ID		 308 } else if (led->type == LED_TYPE_ASSOC) {
309 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
310 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
311 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
312 MCU_LEDCS_LINK_A_STATUS, a_mode);
313
47b10cd1
ID		 314 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
315 0, led->rt2x00dev->led_mcu_reg,
316 REGISTER_TIMEOUT);
a9450b70
ID		 317 } else if (led->type == LED_TYPE_QUALITY) {
318 /*
319 * The brightness is divided into 6 levels (0 - 5),
320 * this means we need to convert the brightness
321 * argument into the matching level within that range.
322 */
47b10cd1
ID		 323 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
324 brightness / (LED_FULL / 6),
325 led->rt2x00dev->led_mcu_reg,
326 REGISTER_TIMEOUT);
a9450b70
ID		 327 }
328}
329#else
330#define rt73usb_led_brightness NULL
331#endif /* CONFIG_RT73USB_LEDS */
332
95ea3627
ID		 333/*
334 * Configuration handlers.
335 */
3a643d24
ID		 336static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
337 const unsigned int filter_flags)
338{
339 u32 reg;
340
341 /*
342 * Start configuration steps.
343 * Note that the version error will always be dropped
344 * and broadcast frames will always be accepted since
345 * there is no filter for it at this time.
346 */
347 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
348 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
349 !(filter_flags & FIF_FCSFAIL));
350 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
351 !(filter_flags & FIF_PLCPFAIL));
352 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
353 !(filter_flags & FIF_CONTROL));
354 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
355 !(filter_flags & FIF_PROMISC_IN_BSS));
356 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
357 !(filter_flags & FIF_PROMISC_IN_BSS));
358 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
359 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
360 !(filter_flags & FIF_ALLMULTI));
361 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
362 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
363 !(filter_flags & FIF_CONTROL));
364 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
365}
366
6bb40dd1
ID		 367static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
368 struct rt2x00_intf *intf,
369 struct rt2x00intf_conf *conf,
370 const unsigned int flags)
95ea3627 371{
6bb40dd1
ID		 372 unsigned int beacon_base;
373 u32 reg;
95ea3627 374
6bb40dd1
ID		 375 if (flags & CONFIG_UPDATE_TYPE) {
376 /*
377 * Clear current synchronisation setup.
378 * For the Beacon base registers we only need to clear
379 * the first byte since that byte contains the VALID and OWNER
380 * bits which (when set to 0) will invalidate the entire beacon.
381 */
382 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 383 rt73usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 384
6bb40dd1
ID		 385 /*
386 * Enable synchronisation.
387 */
388 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 389 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 390 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 391 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 392 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
393 }
95ea3627 394
6bb40dd1
ID		 395 if (flags & CONFIG_UPDATE_MAC) {
396 reg = le32_to_cpu(conf->mac[1]);
397 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
398 conf->mac[1] = cpu_to_le32(reg);
95ea3627 399
6bb40dd1
ID		 400 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
401 conf->mac, sizeof(conf->mac));
402 }
95ea3627 403
6bb40dd1
ID		 404 if (flags & CONFIG_UPDATE_BSSID) {
405 reg = le32_to_cpu(conf->bssid[1]);
406 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
407 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 408
6bb40dd1
ID		 409 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
410 conf->bssid, sizeof(conf->bssid));
411 }
95ea3627
ID		 412}
413
3a643d24
ID		 414static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
415 struct rt2x00lib_erp *erp)
95ea3627 416{
95ea3627 417 u32 reg;
95ea3627 418
95ea3627 419 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 420 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
95ea3627
ID		 421 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
422
423 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 424 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 425 !!erp->short_preamble);
95ea3627
ID		 426 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
427}
428
429static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 430 const int basic_rate_mask)
95ea3627 431{
5c58ee51 432 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 433}
434
5c58ee51
ID		 435static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
436 struct rf_channel *rf, const int txpower)
95ea3627
ID		 437{
438 u8 r3;
439 u8 r94;
440 u8 smart;
441
442 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
443 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
444
445 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
446 rt2x00_rf(&rt2x00dev->chip, RF2527));
447
448 rt73usb_bbp_read(rt2x00dev, 3, &r3);
449 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
450 rt73usb_bbp_write(rt2x00dev, 3, r3);
451
452 r94 = 6;
453 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
454 r94 += txpower - MAX_TXPOWER;
455 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
456 r94 += txpower;
457 rt73usb_bbp_write(rt2x00dev, 94, r94);
458
459 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
460 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
461 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
462 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
463
464 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
465 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
466 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
467 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
468
469 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
470 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
471 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
472 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
473
474 udelay(10);
475}
476
95ea3627
ID		 477static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
478 const int txpower)
479{
480 struct rf_channel rf;
481
482 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
483 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
484 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
485 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
486
5c58ee51 487 rt73usb_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 488}
489
490static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 491 struct antenna_setup *ant)
95ea3627
ID		 492{
493 u8 r3;
494 u8 r4;
495 u8 r77;
2676c94d 496 u8 temp;
95ea3627
ID		 497
498 rt73usb_bbp_read(rt2x00dev, 3, &r3);
499 rt73usb_bbp_read(rt2x00dev, 4, &r4);
500 rt73usb_bbp_read(rt2x00dev, 77, &r77);
501
502 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
503
e4cd2ff8
ID		 504 /*
505 * Configure the RX antenna.
506 */
addc81bd 507 switch (ant->rx) {
95ea3627 508 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 509 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
510 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 511 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 512 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 513 break;
514 case ANTENNA_A:
2676c94d 515 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 516 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 517 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 518 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
519 else
520 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 521 break;
522 case ANTENNA_B:
a4fe07d9 523 default:
2676c94d 524 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 525 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 526 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 527 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
528 else
529 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 530 break;
531 }
532
533 rt73usb_bbp_write(rt2x00dev, 77, r77);
534 rt73usb_bbp_write(rt2x00dev, 3, r3);
535 rt73usb_bbp_write(rt2x00dev, 4, r4);
536}
537
538static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 539 struct antenna_setup *ant)
95ea3627
ID		 540{
541 u8 r3;
542 u8 r4;
543 u8 r77;
544
545 rt73usb_bbp_read(rt2x00dev, 3, &r3);
546 rt73usb_bbp_read(rt2x00dev, 4, &r4);
547 rt73usb_bbp_read(rt2x00dev, 77, &r77);
548
549 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
550 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
551 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
552
e4cd2ff8
ID		 553 /*
554 * Configure the RX antenna.
555 */
addc81bd 556 switch (ant->rx) {
95ea3627 557 case ANTENNA_HW_DIVERSITY:
2676c94d 558 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 559 break;
560 case ANTENNA_A:
2676c94d
MN		 561 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
562 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 563 break;
564 case ANTENNA_B:
a4fe07d9 565 default:
2676c94d
MN		 566 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
567 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 568 break;
569 }
570
571 rt73usb_bbp_write(rt2x00dev, 77, r77);
572 rt73usb_bbp_write(rt2x00dev, 3, r3);
573 rt73usb_bbp_write(rt2x00dev, 4, r4);
574}
575
576struct antenna_sel {
577 u8 word;
578 /*
579 * value[0] -> non-LNA
580 * value[1] -> LNA
581 */
582 u8 value[2];
583};
584
585static const struct antenna_sel antenna_sel_a[] = {
586 { 96, { 0x58, 0x78 } },
587 { 104, { 0x38, 0x48 } },
588 { 75, { 0xfe, 0x80 } },
589 { 86, { 0xfe, 0x80 } },
590 { 88, { 0xfe, 0x80 } },
591 { 35, { 0x60, 0x60 } },
592 { 97, { 0x58, 0x58 } },
593 { 98, { 0x58, 0x58 } },
594};
595
596static const struct antenna_sel antenna_sel_bg[] = {
597 { 96, { 0x48, 0x68 } },
598 { 104, { 0x2c, 0x3c } },
599 { 75, { 0xfe, 0x80 } },
600 { 86, { 0xfe, 0x80 } },
601 { 88, { 0xfe, 0x80 } },
602 { 35, { 0x50, 0x50 } },
603 { 97, { 0x48, 0x48 } },
604 { 98, { 0x48, 0x48 } },
605};
606
607static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 608 struct antenna_setup *ant)
95ea3627
ID		 609{
610 const struct antenna_sel *sel;
611 unsigned int lna;
612 unsigned int i;
613 u32 reg;
614
a4fe07d9
ID		 615 /*
616 * We should never come here because rt2x00lib is supposed
617 * to catch this and send us the correct antenna explicitely.
618 */
619 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
620 ant->tx == ANTENNA_SW_DIVERSITY);
621
8318d78a 622 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 623 sel = antenna_sel_a;
624 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 625 } else {
626 sel = antenna_sel_bg;
627 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 628 }
629
2676c94d
MN		 630 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
631 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
632
633 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
634
ddc827f9 635 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 636 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 637 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 638 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 639
95ea3627
ID		 640 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
641
642 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
643 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 644 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 645 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
646 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 647 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 648}
649
650static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 651 struct rt2x00lib_conf *libconf)
95ea3627
ID		 652{
653 u32 reg;
654
655 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 656 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 657 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
658
659 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 660 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 661 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 662 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 663 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
664
665 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
666 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
667 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
668
669 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
670 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
671 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
672
673 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 674 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
675 libconf->conf->beacon_int * 16);
95ea3627
ID		 676 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
677}
678
679static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 680 struct rt2x00lib_conf *libconf,
681 const unsigned int flags)
95ea3627 682{
95ea3627 683 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 684 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 685 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 686 rt73usb_config_channel(rt2x00dev, &libconf->rf,
687 libconf->conf->power_level);
95ea3627 688 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 689 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 690 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 691 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 692 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 693 rt73usb_config_duration(rt2x00dev, libconf);
95ea3627
ID		 694}
695
95ea3627
ID		 696/*
697 * Link tuning
698 */
ebcf26da
ID		 699static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
700 struct link_qual *qual)
95ea3627
ID		 701{
702 u32 reg;
703
704 /*
705 * Update FCS error count from register.
706 */
707 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 708 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 709
710 /*
711 * Update False CCA count from register.
712 */
713 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 714 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 715}
716
717static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
718{
719 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
720 rt2x00dev->link.vgc_level = 0x20;
721}
722
723static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
724{
725 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
726 u8 r17;
727 u8 up_bound;
728 u8 low_bound;
729
95ea3627
ID		 730 rt73usb_bbp_read(rt2x00dev, 17, &r17);
731
732 /*
733 * Determine r17 bounds.
734 */
8318d78a 735 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 736 low_bound = 0x28;
737 up_bound = 0x48;
738
739 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
740 low_bound += 0x10;
741 up_bound += 0x10;
742 }
743 } else {
744 if (rssi > -82) {
745 low_bound = 0x1c;
746 up_bound = 0x40;
747 } else if (rssi > -84) {
748 low_bound = 0x1c;
749 up_bound = 0x20;
750 } else {
751 low_bound = 0x1c;
752 up_bound = 0x1c;
753 }
754
755 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
756 low_bound += 0x14;
757 up_bound += 0x10;
758 }
759 }
760
6bb40dd1
ID		 761 /*
762 * If we are not associated, we should go straight to the
763 * dynamic CCA tuning.
764 */
765 if (!rt2x00dev->intf_associated)
766 goto dynamic_cca_tune;
767
95ea3627
ID		 768 /*
769 * Special big-R17 for very short distance
770 */
771 if (rssi > -35) {
772 if (r17 != 0x60)
773 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
774 return;
775 }
776
777 /*
778 * Special big-R17 for short distance
779 */
780 if (rssi >= -58) {
781 if (r17 != up_bound)
782 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
783 return;
784 }
785
786 /*
787 * Special big-R17 for middle-short distance
788 */
789 if (rssi >= -66) {
790 low_bound += 0x10;
791 if (r17 != low_bound)
792 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
793 return;
794 }
795
796 /*
797 * Special mid-R17 for middle distance
798 */
799 if (rssi >= -74) {
800 if (r17 != (low_bound + 0x10))
801 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
802 return;
803 }
804
805 /*
806 * Special case: Change up_bound based on the rssi.
807 * Lower up_bound when rssi is weaker then -74 dBm.
808 */
809 up_bound -= 2 * (-74 - rssi);
810 if (low_bound > up_bound)
811 up_bound = low_bound;
812
813 if (r17 > up_bound) {
814 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
815 return;
816 }
817
6bb40dd1
ID		 818dynamic_cca_tune:
819
95ea3627
ID		 820 /*
821 * r17 does not yet exceed upper limit, continue and base
822 * the r17 tuning on the false CCA count.
823 */
ebcf26da 824 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 825 r17 += 4;
826 if (r17 > up_bound)
827 r17 = up_bound;
828 rt73usb_bbp_write(rt2x00dev, 17, r17);
ebcf26da 829 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 830 r17 -= 4;
831 if (r17 < low_bound)
832 r17 = low_bound;
833 rt73usb_bbp_write(rt2x00dev, 17, r17);
834 }
835}
836
837/*
a7f3a06c 838 * Firmware functions
95ea3627
ID		 839 */
840static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
841{
842 return FIRMWARE_RT2571;
843}
844
a7f3a06c
ID		 845static u16 rt73usb_get_firmware_crc(void *data, const size_t len)
846{
847 u16 crc;
848
849 /*
850 * Use the crc itu-t algorithm.
851 * The last 2 bytes in the firmware array are the crc checksum itself,
852 * this means that we should never pass those 2 bytes to the crc
853 * algorithm.
854 */
855 crc = crc_itu_t(0, data, len - 2);
856 crc = crc_itu_t_byte(crc, 0);
857 crc = crc_itu_t_byte(crc, 0);
858
859 return crc;
860}
861
95ea3627
ID		 862static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
863 const size_t len)
864{
865 unsigned int i;
866 int status;
867 u32 reg;
868 char *ptr = data;
869 char *cache;
870 int buflen;
871 int timeout;
872
873 /*
874 * Wait for stable hardware.
875 */
876 for (i = 0; i < 100; i++) {
877 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
878 if (reg)
879 break;
880 msleep(1);
881 }
882
883 if (!reg) {
884 ERROR(rt2x00dev, "Unstable hardware.\n");
885 return -EBUSY;
886 }
887
888 /*
889 * Write firmware to device.
890 * We setup a seperate cache for this action,
891 * since we are going to write larger chunks of data
892 * then normally used cache size.
893 */
894 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
895 if (!cache) {
896 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
897 return -ENOMEM;
898 }
899
900 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
901 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
902 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
903
904 memcpy(cache, ptr, buflen);
905
906 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
907 USB_VENDOR_REQUEST_OUT,
3b640f21 908 FIRMWARE_IMAGE_BASE + i, 0,
95ea3627
ID		 909 cache, buflen, timeout);
910
911 ptr += buflen;
912 }
913
914 kfree(cache);
915
916 /*
917 * Send firmware request to device to load firmware,
918 * we need to specify a long timeout time.
919 */
920 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 921 0, USB_MODE_FIRMWARE,
95ea3627
ID		 922 REGISTER_TIMEOUT_FIRMWARE);
923 if (status < 0) {
924 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
925 return status;
926 }
927
95ea3627
ID		 928 return 0;
929}
930
a7f3a06c
ID		 931/*
932 * Initialization functions.
933 */
95ea3627
ID		 934static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
935{
936 u32 reg;
937
938 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
939 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
940 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
941 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
942 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
943
944 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
945 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
946 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
947 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
948 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
949 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
950 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
951 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
952 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
953 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
954
955 /*
956 * CCK TXD BBP registers
957 */
958 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
959 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
960 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
961 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
962 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
963 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
964 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
965 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
966 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
967 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
968
969 /*
970 * OFDM TXD BBP registers
971 */
972 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
973 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
974 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
975 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
976 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
977 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
978 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
979 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
980
981 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
982 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
983 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
984 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
985 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
986 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
987
988 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
989 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
990 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
991 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
992 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
993 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
994
995 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
996
997 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
998 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
999 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
1000
1001 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1002
1003 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1004 return -EBUSY;
1005
1006 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1007
a9450b70
ID		 1008 rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg);
1009 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
1010 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
1011 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
1012
95ea3627
ID		 1013 /*
1014 * Invalidate all Shared Keys (SEC_CSR0),
1015 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1016 */
1017 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1018 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1019 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1020
1021 reg = 0x000023b0;
1022 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1023 rt2x00_rf(&rt2x00dev->chip, RF2527))
1024 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1025 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1026
1027 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1028 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1029 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1030
1031 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1032 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1033 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1034 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1035
1036 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1037 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1038 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1039 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1040
1041 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1042 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1043 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1044
6bb40dd1
ID		 1045 /*
1046 * Clear all beacons
1047 * For the Beacon base registers we only need to clear
1048 * the first byte since that byte contains the VALID and OWNER
1049 * bits which (when set to 0) will invalidate the entire beacon.
1050 */
1051 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1052 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1053 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1054 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1055
95ea3627
ID		 1056 /*
1057 * We must clear the error counters.
1058 * These registers are cleared on read,
1059 * so we may pass a useless variable to store the value.
1060 */
1061 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1062 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1063 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1064
1065 /*
1066 * Reset MAC and BBP registers.
1067 */
1068 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1069 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1070 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1071 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1072
1073 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1074 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1075 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1076 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1077
1078 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1079 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1080 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1081
1082 return 0;
1083}
1084
1085static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1086{
1087 unsigned int i;
1088 u16 eeprom;
1089 u8 reg_id;
1090 u8 value;
1091
1092 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1093 rt73usb_bbp_read(rt2x00dev, 0, &value);
1094 if ((value != 0xff) && (value != 0x00))
1095 goto continue_csr_init;
1096 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1097 udelay(REGISTER_BUSY_DELAY);
1098 }
1099
1100 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1101 return -EACCES;
1102
1103continue_csr_init:
1104 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1105 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1106 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1107 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1108 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1109 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1110 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1111 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1112 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1113 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1114 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1115 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1116 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1117 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1118 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1119 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1120 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1121 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1122 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1123 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1124 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1125 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1126 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1127 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1128 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1129
95ea3627
ID		 1130 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1131 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1132
1133 if (eeprom != 0xffff && eeprom != 0x0000) {
1134 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1135 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1136 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1137 }
1138 }
95ea3627
ID		 1139
1140 return 0;
1141}
1142
1143/*
1144 * Device state switch handlers.
1145 */
1146static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1147 enum dev_state state)
1148{
1149 u32 reg;
1150
1151 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1152 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1153 state == STATE_RADIO_RX_OFF);
1154 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1155}
1156
1157static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1158{
1159 /*
1160 * Initialize all registers.
1161 */
1162 if (rt73usb_init_registers(rt2x00dev) ||
1163 rt73usb_init_bbp(rt2x00dev)) {
1164 ERROR(rt2x00dev, "Register initialization failed.\n");
1165 return -EIO;
1166 }
1167
95ea3627
ID		 1168 return 0;
1169}
1170
1171static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1172{
95ea3627
ID		 1173 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1174
1175 /*
1176 * Disable synchronisation.
1177 */
1178 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1179
1180 rt2x00usb_disable_radio(rt2x00dev);
1181}
1182
1183static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1184{
1185 u32 reg;
1186 unsigned int i;
1187 char put_to_sleep;
1188 char current_state;
1189
1190 put_to_sleep = (state != STATE_AWAKE);
1191
1192 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1193 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1194 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1195 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1196
1197 /*
1198 * Device is not guaranteed to be in the requested state yet.
1199 * We must wait until the register indicates that the
1200 * device has entered the correct state.
1201 */
1202 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1203 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1204 current_state =
1205 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1206 if (current_state == !put_to_sleep)
1207 return 0;
1208 msleep(10);
1209 }
1210
1211 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1212 "current device state %d.\n", !put_to_sleep, current_state);
1213
1214 return -EBUSY;
1215}
1216
1217static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1218 enum dev_state state)
1219{
1220 int retval = 0;
1221
1222 switch (state) {
1223 case STATE_RADIO_ON:
1224 retval = rt73usb_enable_radio(rt2x00dev);
1225 break;
1226 case STATE_RADIO_OFF:
1227 rt73usb_disable_radio(rt2x00dev);
1228 break;
1229 case STATE_RADIO_RX_ON:
61667d8d
ID		 1230 case STATE_RADIO_RX_ON_LINK:
1231 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1232 break;
95ea3627 1233 case STATE_RADIO_RX_OFF:
61667d8d
ID		 1234 case STATE_RADIO_RX_OFF_LINK:
1235 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 1236 break;
1237 case STATE_DEEP_SLEEP:
1238 case STATE_SLEEP:
1239 case STATE_STANDBY:
1240 case STATE_AWAKE:
1241 retval = rt73usb_set_state(rt2x00dev, state);
1242 break;
1243 default:
1244 retval = -ENOTSUPP;
1245 break;
1246 }
1247
1248 return retval;
1249}
1250
1251/*
1252 * TX descriptor initialization
1253 */
1254static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1255 struct sk_buff *skb,
181d6902 1256 struct txentry_desc *txdesc,
dd3193e1 1257 struct ieee80211_tx_control *control)
95ea3627 1258{
181d6902 1259 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1260 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1261 u32 word;
1262
1263 /*
1264 * Start writing the descriptor words.
1265 */
1266 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1267 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1268 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1269 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1270 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1271 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1272 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1273 rt2x00_desc_write(txd, 1, word);
1274
1275 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1276 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1277 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1278 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1279 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1280 rt2x00_desc_write(txd, 2, word);
1281
1282 rt2x00_desc_read(txd, 5, &word);
1283 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1284 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1285 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1286 rt2x00_desc_write(txd, 5, word);
1287
1288 rt2x00_desc_read(txd, 0, &word);
1289 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1290 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1291 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1292 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1293 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1294 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1295 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1296 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1297 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1298 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1299 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1300 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1301 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1302 !!(control->flags &
1303 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1304 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
dd3193e1 1305 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627 1306 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1307 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1308 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1309 rt2x00_desc_write(txd, 0, word);
1310}
1311
dd9fa2d2 1312static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
b242e891 1313 struct sk_buff *skb)
dd9fa2d2
ID		 1314{
1315 int length;
1316
1317 /*
1318 * The length _must_ be a multiple of 4,
1319 * but it must _not_ be a multiple of the USB packet size.
1320 */
1321 length = roundup(skb->len, 4);
b242e891 1322 length += (4 * !(length % rt2x00dev->usb_maxpacket));
dd9fa2d2
ID		 1323
1324 return length;
1325}
1326
95ea3627
ID		 1327/*
1328 * TX data initialization
1329 */
1330static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1331 const unsigned int queue)
95ea3627
ID		 1332{
1333 u32 reg;
1334
5957da4c 1335 if (queue != RT2X00_BCN_QUEUE_BEACON)
95ea3627
ID		 1336 return;
1337
1338 /*
1339 * For Wi-Fi faily generated beacons between participating stations.
1340 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1341 */
1342 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1343
1344 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1345 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1346 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1347 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1348 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1349 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1350 }
1351}
1352
1353/*
1354 * RX control handlers
1355 */
1356static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1357{
1358 u16 eeprom;
1359 u8 offset;
1360 u8 lna;
1361
1362 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1363 switch (lna) {
1364 case 3:
1365 offset = 90;
1366 break;
1367 case 2:
1368 offset = 74;
1369 break;
1370 case 1:
1371 offset = 64;
1372 break;
1373 default:
1374 return 0;
1375 }
1376
8318d78a 1377 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1378 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1379 if (lna == 3 || lna == 2)
1380 offset += 10;
1381 } else {
1382 if (lna == 3)
1383 offset += 6;
1384 else if (lna == 2)
1385 offset += 8;
1386 }
1387
1388 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1389 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1390 } else {
1391 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1392 offset += 14;
1393
1394 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1395 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1396 }
1397
1398 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1399}
1400
181d6902
ID		 1401static void rt73usb_fill_rxdone(struct queue_entry *entry,
1402 struct rxdone_entry_desc *rxdesc)
95ea3627 1403{
181d6902 1404 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1405 __le32 *rxd = (__le32 *)entry->skb->data;
f855c10b 1406 unsigned int offset = entry->queue->desc_size + 2;
95ea3627
ID		 1407 u32 word0;
1408 u32 word1;
1409
f855c10b
ID		 1410 /*
1411 * Copy descriptor to the available headroom inside the skbuffer.
f855c10b
ID		 1412 */
1413 skb_push(entry->skb, offset);
1414 memcpy(entry->skb->data, rxd, entry->queue->desc_size);
1415 rxd = (__le32 *)entry->skb->data;
f855c10b
ID		 1416
1417 /*
1418 * The descriptor is now aligned to 4 bytes and thus it is
1419 * now safe to read it on all architectures.
1420 */
95ea3627
ID		 1421 rt2x00_desc_read(rxd, 0, &word0);
1422 rt2x00_desc_read(rxd, 1, &word1);
1423
181d6902 1424 rxdesc->flags = 0;
4150c572 1425 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1426 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1427
1428 /*
1429 * Obtain the status about this packet.
89993890
ID		 1430 * When frame was received with an OFDM bitrate,
1431 * the signal is the PLCP value. If it was received with
1432 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1433 */
181d6902
ID		 1434 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1435 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
181d6902 1436 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02
ID		 1437
1438 rxdesc->dev_flags = 0;
1439 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1440 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1441 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1442 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1443
2ae23854
MN		 1444 /*
1445 * Adjust the skb memory window to the frame boundaries.
1446 */
1447 skb_pull(entry->skb, offset + entry->queue->desc_size);
1448 skb_trim(entry->skb, rxdesc->size);
1449
7d1de806
ID		 1450 /*
1451 * Set descriptor and data pointer.
1452 */
f855c10b 1453 skbdesc->data = entry->skb->data;
647d0ca9 1454 skbdesc->data_len = rxdesc->size;
2ae23854 1455 skbdesc->desc = rxd;
181d6902 1456 skbdesc->desc_len = entry->queue->desc_size;
95ea3627
ID		 1457}
1458
1459/*
1460 * Device probe functions.
1461 */
1462static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1463{
1464 u16 word;
1465 u8 *mac;
1466 s8 value;
1467
1468 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1469
1470 /*
1471 * Start validation of the data that has been read.
1472 */
1473 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1474 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1475 DECLARE_MAC_BUF(macbuf);
1476
95ea3627 1477 random_ether_addr(mac);
0795af57 1478 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1479 }
1480
1481 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1482 if (word == 0xffff) {
1483 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1484 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1485 ANTENNA_B);
1486 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1487 ANTENNA_B);
95ea3627
ID		 1488 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1489 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1490 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1491 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1492 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1493 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1494 }
1495
1496 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1497 if (word == 0xffff) {
1498 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1499 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1500 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1501 }
1502
1503 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1504 if (word == 0xffff) {
1505 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1506 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1507 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1508 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1509 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1510 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1511 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1512 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1513 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1514 LED_MODE_DEFAULT);
1515 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1516 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1517 }
1518
1519 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1520 if (word == 0xffff) {
1521 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1522 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1523 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1524 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1525 }
1526
1527 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1528 if (word == 0xffff) {
1529 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1530 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1531 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1532 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1533 } else {
1534 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1535 if (value < -10 || value > 10)
1536 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1537 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1538 if (value < -10 || value > 10)
1539 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1540 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1541 }
1542
1543 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1544 if (word == 0xffff) {
1545 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1546 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1547 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1548 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1549 } else {
1550 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1551 if (value < -10 || value > 10)
1552 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1553 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1554 if (value < -10 || value > 10)
1555 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1556 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1557 }
1558
1559 return 0;
1560}
1561
1562static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1563{
1564 u32 reg;
1565 u16 value;
1566 u16 eeprom;
1567
1568 /*
1569 * Read EEPROM word for configuration.
1570 */
1571 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1572
1573 /*
1574 * Identify RF chipset.
1575 */
1576 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1577 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1578 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1579
755a957d 1580 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
95ea3627
ID		 1581 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1582 return -ENODEV;
1583 }
1584
1585 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1586 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1587 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1588 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1589 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1590 return -ENODEV;
1591 }
1592
1593 /*
1594 * Identify default antenna configuration.
1595 */
addc81bd 1596 rt2x00dev->default_ant.tx =
95ea3627 1597 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1598 rt2x00dev->default_ant.rx =
95ea3627
ID		 1599 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1600
1601 /*
1602 * Read the Frame type.
1603 */
1604 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1605 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1606
1607 /*
1608 * Read frequency offset.
1609 */
1610 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1611 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1612
1613 /*
1614 * Read external LNA informations.
1615 */
1616 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1617
1618 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1619 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1620 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1621 }
1622
1623 /*
1624 * Store led settings, for correct led behaviour.
1625 */
a9450b70 1626#ifdef CONFIG_RT73USB_LEDS
95ea3627
ID		 1627 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1628
a9450b70
ID		 1629 switch (value) {
1630 case LED_MODE_TXRX_ACTIVITY:
1631 case LED_MODE_ASUS:
1632 case LED_MODE_ALPHA:
1633 case LED_MODE_DEFAULT:
1634 rt2x00dev->led_flags =
1635 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
1636 break;
1637 case LED_MODE_SIGNAL_STRENGTH:
1638 rt2x00dev->led_flags =
1639 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
1640 LED_SUPPORT_QUALITY;
1641 break;
1642 }
1643
1644 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1645 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1646 rt2x00_get_field16(eeprom,
1647 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1648 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1649 rt2x00_get_field16(eeprom,
1650 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1651 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1652 rt2x00_get_field16(eeprom,
1653 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1654 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1655 rt2x00_get_field16(eeprom,
1656 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1657 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1658 rt2x00_get_field16(eeprom,
1659 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1660 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1661 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1662 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1663 rt2x00_get_field16(eeprom,
1664 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1665 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1666 rt2x00_get_field16(eeprom,
1667 EEPROM_LED_POLARITY_RDY_A));
a9450b70 1668#endif /* CONFIG_RT73USB_LEDS */
95ea3627
ID		 1669
1670 return 0;
1671}
1672
1673/*
1674 * RF value list for RF2528
1675 * Supports: 2.4 GHz
1676 */
1677static const struct rf_channel rf_vals_bg_2528[] = {
1678 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1679 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1680 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1681 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1682 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1683 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1684 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1685 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1686 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1687 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1688 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1689 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1690 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1691 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1692};
1693
1694/*
1695 * RF value list for RF5226
1696 * Supports: 2.4 GHz & 5.2 GHz
1697 */
1698static const struct rf_channel rf_vals_5226[] = {
1699 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1700 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1701 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1702 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1703 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1704 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1705 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1706 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1707 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1708 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1709 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1710 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1711 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1712 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1713
1714 /* 802.11 UNI / HyperLan 2 */
1715 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1716 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1717 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1718 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1719 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1720 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1721 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1722 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1723
1724 /* 802.11 HyperLan 2 */
1725 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1726 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1727 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1728 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1729 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1730 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1731 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1732 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1733 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1734 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1735
1736 /* 802.11 UNII */
1737 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1738 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1739 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1740 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1741 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1742 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1743
1744 /* MMAC(Japan)J52 ch 34,38,42,46 */
1745 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1746 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1747 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1748 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1749};
1750
1751/*
1752 * RF value list for RF5225 & RF2527
1753 * Supports: 2.4 GHz & 5.2 GHz
1754 */
1755static const struct rf_channel rf_vals_5225_2527[] = {
1756 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1757 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1758 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1759 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1760 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1761 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1762 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1763 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1764 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1765 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1766 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1767 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1768 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1769 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1770
1771 /* 802.11 UNI / HyperLan 2 */
1772 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1773 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1774 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1775 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1776 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1777 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1778 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1779 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1780
1781 /* 802.11 HyperLan 2 */
1782 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1783 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1784 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1785 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1786 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1787 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1788 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1789 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1790 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1791 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1792
1793 /* 802.11 UNII */
1794 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1795 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1796 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1797 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1798 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1799 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1800
1801 /* MMAC(Japan)J52 ch 34,38,42,46 */
1802 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1803 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1804 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1805 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1806};
1807
1808
1809static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1810{
1811 struct hw_mode_spec *spec = &rt2x00dev->spec;
1812 u8 *txpower;
1813 unsigned int i;
1814
1815 /*
1816 * Initialize all hw fields.
1817 */
1818 rt2x00dev->hw->flags =
1819 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 1820 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1821 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1822 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1823 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
871ff6ed 1824 rt2x00dev->hw->queues = 4;
95ea3627
ID		 1825
1826 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1827 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1828 rt2x00_eeprom_addr(rt2x00dev,
1829 EEPROM_MAC_ADDR_0));
1830
1831 /*
1832 * Convert tx_power array in eeprom.
1833 */
1834 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1835 for (i = 0; i < 14; i++)
1836 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1837
1838 /*
1839 * Initialize hw_mode information.
1840 */
31562e80
ID		 1841 spec->supported_bands = SUPPORT_BAND_2GHZ;
1842 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 1843 spec->tx_power_a = NULL;
1844 spec->tx_power_bg = txpower;
1845 spec->tx_power_default = DEFAULT_TXPOWER;
1846
1847 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1848 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1849 spec->channels = rf_vals_bg_2528;
1850 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
31562e80 1851 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1852 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1853 spec->channels = rf_vals_5226;
1854 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1855 spec->num_channels = 14;
1856 spec->channels = rf_vals_5225_2527;
1857 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
31562e80 1858 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1859 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1860 spec->channels = rf_vals_5225_2527;
1861 }
1862
1863 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1864 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
95ea3627
ID		 1865 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1866 for (i = 0; i < 14; i++)
1867 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1868
1869 spec->tx_power_a = txpower;
1870 }
1871}
1872
1873static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1874{
1875 int retval;
1876
1877 /*
1878 * Allocate eeprom data.
1879 */
1880 retval = rt73usb_validate_eeprom(rt2x00dev);
1881 if (retval)
1882 return retval;
1883
1884 retval = rt73usb_init_eeprom(rt2x00dev);
1885 if (retval)
1886 return retval;
1887
1888 /*
1889 * Initialize hw specifications.
1890 */
1891 rt73usb_probe_hw_mode(rt2x00dev);
1892
1893 /*
9404ef34 1894 * This device requires firmware.
95ea3627 1895 */
066cb637 1896 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
3a643d24 1897 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
95ea3627
ID		 1898
1899 /*
1900 * Set the rssi offset.
1901 */
1902 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1903
1904 return 0;
1905}
1906
1907/*
1908 * IEEE80211 stack callback functions.
1909 */
1910static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1911 u32 short_retry, u32 long_retry)
1912{
1913 struct rt2x00_dev *rt2x00dev = hw->priv;
1914 u32 reg;
1915
1916 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1917 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1918 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1919 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1920
1921 return 0;
1922}
1923
1924#if 0
1925/*
1926 * Mac80211 demands get_tsf must be atomic.
1927 * This is not possible for rt73usb since all register access
1928 * functions require sleeping. Untill mac80211 no longer needs
1929 * get_tsf to be atomic, this function should be disabled.
1930 */
1931static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1932{
1933 struct rt2x00_dev *rt2x00dev = hw->priv;
1934 u64 tsf;
1935 u32 reg;
1936
1937 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1938 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1939 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1940 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1941
1942 return tsf;
1943}
37894473
ID		 1944#else
1945#define rt73usb_get_tsf NULL
95ea3627
ID		 1946#endif
1947
24845910 1948static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
6bb40dd1 1949 struct ieee80211_tx_control *control)
95ea3627
ID		 1950{
1951 struct rt2x00_dev *rt2x00dev = hw->priv;
6bb40dd1 1952 struct rt2x00_intf *intf = vif_to_intf(control->vif);
181d6902 1953 struct skb_frame_desc *skbdesc;
6bb40dd1
ID		 1954 unsigned int beacon_base;
1955 unsigned int timeout;
8af244cc 1956 u32 reg;
95ea3627 1957
6bb40dd1
ID		 1958 if (unlikely(!intf->beacon))
1959 return -ENOBUFS;
95ea3627
ID		 1960
1961 /*
08992f7f 1962 * Add the descriptor in front of the skb.
95ea3627 1963 */
6bb40dd1
ID		 1964 skb_push(skb, intf->beacon->queue->desc_size);
1965 memset(skb->data, 0, intf->beacon->queue->desc_size);
c22eb87b 1966
08992f7f
ID		 1967 /*
1968 * Fill in skb descriptor
1969 */
181d6902
ID		 1970 skbdesc = get_skb_frame_desc(skb);
1971 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 1972 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
6bb40dd1
ID		 1973 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
1974 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
181d6902 1975 skbdesc->desc = skb->data;
6bb40dd1
ID		 1976 skbdesc->desc_len = intf->beacon->queue->desc_size;
1977 skbdesc->entry = intf->beacon;
08992f7f 1978
8af244cc
ID		 1979 /*
1980 * Disable beaconing while we are reloading the beacon data,
1981 * otherwise we might be sending out invalid data.
1982 */
1983 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1984 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1985 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1986 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1987 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1988
6bb40dd1 1989 /*
5957da4c
ID		 1990 * mac80211 doesn't provide the control->queue variable
1991 * for beacons. Set our own queue identification so
1992 * it can be used during descriptor initialization.
6bb40dd1 1993 */
5957da4c 1994 control->queue = RT2X00_BCN_QUEUE_BEACON;
08992f7f 1995 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
95ea3627
ID		 1996
1997 /*
1998 * Write entire beacon with descriptor to register,
1999 * and kick the beacon generator.
2000 */
6bb40dd1 2001 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
95ea3627
ID		 2002 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
2003 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
6bb40dd1 2004 USB_VENDOR_REQUEST_OUT, beacon_base, 0,
95ea3627 2005 skb->data, skb->len, timeout);
6bb40dd1 2006 rt73usb_kick_tx_queue(rt2x00dev, control->queue);
95ea3627
ID		 2007
2008 return 0;
2009}
2010
2011static const struct ieee80211_ops rt73usb_mac80211_ops = {
2012 .tx = rt2x00mac_tx,
4150c572
JB		 2013 .start = rt2x00mac_start,
2014 .stop = rt2x00mac_stop,
95ea3627
ID		 2015 .add_interface = rt2x00mac_add_interface,
2016 .remove_interface = rt2x00mac_remove_interface,
2017 .config = rt2x00mac_config,
2018 .config_interface = rt2x00mac_config_interface,
3a643d24 2019 .configure_filter = rt2x00mac_configure_filter,
95ea3627
ID		 2020 .get_stats = rt2x00mac_get_stats,
2021 .set_retry_limit = rt73usb_set_retry_limit,
471b3efd 2022 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2023 .conf_tx = rt2x00mac_conf_tx,
2024 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2025 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2026 .beacon_update = rt73usb_beacon_update,
2027};
2028
2029static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2030 .probe_hw = rt73usb_probe_hw,
2031 .get_firmware_name = rt73usb_get_firmware_name,
a7f3a06c 2032 .get_firmware_crc = rt73usb_get_firmware_crc,
95ea3627
ID		 2033 .load_firmware = rt73usb_load_firmware,
2034 .initialize = rt2x00usb_initialize,
2035 .uninitialize = rt2x00usb_uninitialize,
837e7f24
ID		 2036 .init_rxentry = rt2x00usb_init_rxentry,
2037 .init_txentry = rt2x00usb_init_txentry,
95ea3627
ID		 2038 .set_device_state = rt73usb_set_device_state,
2039 .link_stats = rt73usb_link_stats,
2040 .reset_tuner = rt73usb_reset_tuner,
2041 .link_tuner = rt73usb_link_tuner,
a9450b70 2042 .led_brightness = rt73usb_led_brightness,
95ea3627
ID		 2043 .write_tx_desc = rt73usb_write_tx_desc,
2044 .write_tx_data = rt2x00usb_write_tx_data,
dd9fa2d2 2045 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627
ID		 2046 .kick_tx_queue = rt73usb_kick_tx_queue,
2047 .fill_rxdone = rt73usb_fill_rxdone,
3a643d24 2048 .config_filter = rt73usb_config_filter,
6bb40dd1 2049 .config_intf = rt73usb_config_intf,
72810379 2050 .config_erp = rt73usb_config_erp,
95ea3627
ID		 2051 .config = rt73usb_config,
2052};
2053
181d6902
ID		 2054static const struct data_queue_desc rt73usb_queue_rx = {
2055 .entry_num = RX_ENTRIES,
2056 .data_size = DATA_FRAME_SIZE,
2057 .desc_size = RXD_DESC_SIZE,
2058 .priv_size = sizeof(struct queue_entry_priv_usb_rx),
2059};
2060
2061static const struct data_queue_desc rt73usb_queue_tx = {
2062 .entry_num = TX_ENTRIES,
2063 .data_size = DATA_FRAME_SIZE,
2064 .desc_size = TXD_DESC_SIZE,
2065 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2066};
2067
2068static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2069 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2070 .data_size = MGMT_FRAME_SIZE,
2071 .desc_size = TXINFO_SIZE,
2072 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2073};
2074
95ea3627 2075static const struct rt2x00_ops rt73usb_ops = {
2360157c 2076 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2077 .max_sta_intf = 1,
2078 .max_ap_intf = 4,
95ea3627
ID		 2079 .eeprom_size = EEPROM_SIZE,
2080 .rf_size = RF_SIZE,
181d6902
ID		 2081 .rx = &rt73usb_queue_rx,
2082 .tx = &rt73usb_queue_tx,
2083 .bcn = &rt73usb_queue_bcn,
95ea3627
ID		 2084 .lib = &rt73usb_rt2x00_ops,
2085 .hw = &rt73usb_mac80211_ops,
2086#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2087 .debugfs = &rt73usb_rt2x00debug,
2088#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2089};
2090
2091/*
2092 * rt73usb module information.
2093 */
2094static struct usb_device_id rt73usb_device_table[] = {
2095 /* AboCom */
2096 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2097 /* Askey */
2098 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2099 /* ASUS */
2100 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2101 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2102 /* Belkin */
2103 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2104 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2105 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2106 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2107 /* Billionton */
2108 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2109 /* Buffalo */
2110 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2111 /* CNet */
2112 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2113 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2114 /* Conceptronic */
2115 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2116 /* D-Link */
2117 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2118 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
445815d7 2119 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2120 /* Gemtek */
2121 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2122 /* Gigabyte */
2123 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2124 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2125 /* Huawei-3Com */
2126 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2127 /* Hercules */
2128 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2129 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2130 /* Linksys */
2131 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2132 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2133 /* MSI */
2134 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2135 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2136 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2137 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2138 /* Ralink */
2139 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2140 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2141 /* Qcom */
2142 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2143 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2144 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2145 /* Senao */
2146 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2147 /* Sitecom */
2148 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2149 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2150 /* Surecom */
2151 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2152 /* Planex */
2153 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2154 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2155 { 0, }
2156};
2157
2158MODULE_AUTHOR(DRV_PROJECT);
2159MODULE_VERSION(DRV_VERSION);
2160MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2161MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2162MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2163MODULE_FIRMWARE(FIRMWARE_RT2571);
2164MODULE_LICENSE("GPL");
2165
2166static struct usb_driver rt73usb_driver = {
2360157c 2167 .name = KBUILD_MODNAME,
95ea3627
ID		 2168 .id_table = rt73usb_device_table,
2169 .probe = rt2x00usb_probe,
2170 .disconnect = rt2x00usb_disconnect,
2171 .suspend = rt2x00usb_suspend,
2172 .resume = rt2x00usb_resume,
2173};
2174
2175static int __init rt73usb_init(void)
2176{
2177 return usb_register(&rt73usb_driver);
2178}
2179
2180static void __exit rt73usb_exit(void)
2181{
2182 usb_deregister(&rt73usb_driver);
2183}
2184
2185module_init(rt73usb_init);
2186module_exit(rt73usb_exit);
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