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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / rt2x00 / rt73usb.c
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95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
95ea3627
ID		 34#include <linux/usb.h>
35
36#include "rt2x00.h"
37#include "rt2x00usb.h"
38#include "rt73usb.h"
39
008c4482
ID		 40/*
41 * Allow hardware encryption to be disabled.
42 */
43static int modparam_nohwcrypt = 0;
44module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46
95ea3627
ID		 47/*
48 * Register access.
49 * All access to the CSR registers will go through the methods
0f829b1d 50 * rt2x00usb_register_read and rt2x00usb_register_write.
95ea3627
ID		 51 * BBP and RF register require indirect register access,
52 * and use the CSR registers BBPCSR and RFCSR to achieve this.
53 * These indirect registers work with busy bits,
54 * and we will try maximal REGISTER_BUSY_COUNT times to access
55 * the register while taking a REGISTER_BUSY_DELAY us delay
56 * between each attampt. When the busy bit is still set at that time,
57 * the access attempt is considered to have failed,
58 * and we will print an error.
8ff48a8b 59 * The _lock versions must be used if you already hold the csr_mutex
95ea3627 60 */
c9c3b1a5 61#define WAIT_FOR_BBP(__dev, __reg) \
0f829b1d 62 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
c9c3b1a5 63#define WAIT_FOR_RF(__dev, __reg) \
0f829b1d 64 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
c9c3b1a5 65
0e14f6d3 66static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 67 const unsigned int word, const u8 value)
68{
69 u32 reg;
70
8ff48a8b 71 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 72
95ea3627 73 /*
c9c3b1a5
ID		 74 * Wait until the BBP becomes available, afterwards we
75 * can safely write the new data into the register.
95ea3627 76 */
c9c3b1a5
ID		 77 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
78 reg = 0;
79 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
80 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
81 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
82 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
83
0f829b1d 84 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
c9c3b1a5 85 }
99ade259 86
8ff48a8b 87 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 88}
89
0e14f6d3 90static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 91 const unsigned int word, u8 *value)
92{
93 u32 reg;
94
8ff48a8b 95 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 96
95ea3627 97 /*
c9c3b1a5
ID		 98 * Wait until the BBP becomes available, afterwards we
99 * can safely write the read request into the register.
100 * After the data has been written, we wait until hardware
101 * returns the correct value, if at any time the register
102 * doesn't become available in time, reg will be 0xffffffff
103 * which means we return 0xff to the caller.
95ea3627 104 */
c9c3b1a5
ID		 105 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
106 reg = 0;
107 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
108 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
109 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 110
0f829b1d 111 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627 112
c9c3b1a5
ID		 113 WAIT_FOR_BBP(rt2x00dev, &reg);
114 }
95ea3627
ID		 115
116 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
99ade259 117
8ff48a8b 118 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 119}
120
0e14f6d3 121static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 122 const unsigned int word, const u32 value)
123{
124 u32 reg;
95ea3627 125
8ff48a8b 126 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 127
4f5af6eb 128 /*
c9c3b1a5
ID		 129 * Wait until the RF becomes available, afterwards we
130 * can safely write the new data into the register.
4f5af6eb 131 */
c9c3b1a5
ID		 132 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
133 reg = 0;
134 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
135 /*
136 * RF5225 and RF2527 contain 21 bits per RF register value,
137 * all others contain 20 bits.
138 */
139 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
5122d898
GW		 140 20 + (rt2x00_rf(rt2x00dev, RF5225) ||
141 rt2x00_rf(rt2x00dev, RF2527)));
c9c3b1a5
ID		 142 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
143 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
144
0f829b1d 145 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
c9c3b1a5
ID		 146 rt2x00_rf_write(rt2x00dev, word, value);
147 }
8ff48a8b
ID		 148
149 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 150}
151
152#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 153static const struct rt2x00debug rt73usb_rt2x00debug = {
154 .owner = THIS_MODULE,
155 .csr = {
0f829b1d
ID		 156 .read = rt2x00usb_register_read,
157 .write = rt2x00usb_register_write,
743b97ca
ID		 158 .flags = RT2X00DEBUGFS_OFFSET,
159 .word_base = CSR_REG_BASE,
95ea3627
ID		 160 .word_size = sizeof(u32),
161 .word_count = CSR_REG_SIZE / sizeof(u32),
162 },
163 .eeprom = {
164 .read = rt2x00_eeprom_read,
165 .write = rt2x00_eeprom_write,
743b97ca 166 .word_base = EEPROM_BASE,
95ea3627
ID		 167 .word_size = sizeof(u16),
168 .word_count = EEPROM_SIZE / sizeof(u16),
169 },
170 .bbp = {
171 .read = rt73usb_bbp_read,
172 .write = rt73usb_bbp_write,
743b97ca 173 .word_base = BBP_BASE,
95ea3627
ID		 174 .word_size = sizeof(u8),
175 .word_count = BBP_SIZE / sizeof(u8),
176 },
177 .rf = {
178 .read = rt2x00_rf_read,
179 .write = rt73usb_rf_write,
743b97ca 180 .word_base = RF_BASE,
95ea3627
ID		 181 .word_size = sizeof(u32),
182 .word_count = RF_SIZE / sizeof(u32),
183 },
184};
185#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
186
7396faf4
ID		 187static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
188{
189 u32 reg;
190
191 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
192 return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
193}
7396faf4 194
771fd565 195#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 196static void rt73usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 197 enum led_brightness brightness)
198{
199 struct rt2x00_led *led =
200 container_of(led_cdev, struct rt2x00_led, led_dev);
201 unsigned int enabled = brightness != LED_OFF;
202 unsigned int a_mode =
203 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
204 unsigned int bg_mode =
205 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
206
207 if (led->type == LED_TYPE_RADIO) {
208 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
209 MCU_LEDCS_RADIO_STATUS, enabled);
210
47b10cd1
ID		 211 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
212 0, led->rt2x00dev->led_mcu_reg,
213 REGISTER_TIMEOUT);
a9450b70
ID		 214 } else if (led->type == LED_TYPE_ASSOC) {
215 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
216 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
217 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
218 MCU_LEDCS_LINK_A_STATUS, a_mode);
219
47b10cd1
ID		 220 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
221 0, led->rt2x00dev->led_mcu_reg,
222 REGISTER_TIMEOUT);
a9450b70
ID		 223 } else if (led->type == LED_TYPE_QUALITY) {
224 /*
225 * The brightness is divided into 6 levels (0 - 5),
226 * this means we need to convert the brightness
227 * argument into the matching level within that range.
228 */
47b10cd1
ID		 229 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
230 brightness / (LED_FULL / 6),
231 led->rt2x00dev->led_mcu_reg,
232 REGISTER_TIMEOUT);
a9450b70
ID		 233 }
234}
a2e1d52a
ID		 235
236static int rt73usb_blink_set(struct led_classdev *led_cdev,
237 unsigned long *delay_on,
238 unsigned long *delay_off)
239{
240 struct rt2x00_led *led =
241 container_of(led_cdev, struct rt2x00_led, led_dev);
242 u32 reg;
243
0f829b1d 244 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
a2e1d52a
ID		 245 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
246 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
0f829b1d 247 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
a2e1d52a
ID		 248
249 return 0;
250}
475433be
ID		 251
252static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
253 struct rt2x00_led *led,
254 enum led_type type)
255{
256 led->rt2x00dev = rt2x00dev;
257 led->type = type;
258 led->led_dev.brightness_set = rt73usb_brightness_set;
259 led->led_dev.blink_set = rt73usb_blink_set;
260 led->flags = LED_INITIALIZED;
261}
771fd565 262#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 263
95ea3627
ID		 264/*
265 * Configuration handlers.
266 */
906c110f
ID		 267static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
268 struct rt2x00lib_crypto *crypto,
269 struct ieee80211_key_conf *key)
270{
271 struct hw_key_entry key_entry;
272 struct rt2x00_field32 field;
273 int timeout;
274 u32 mask;
275 u32 reg;
276
277 if (crypto->cmd == SET_KEY) {
278 /*
279 * rt2x00lib can't determine the correct free
280 * key_idx for shared keys. We have 1 register
281 * with key valid bits. The goal is simple, read
282 * the register, if that is full we have no slots
283 * left.
284 * Note that each BSS is allowed to have up to 4
285 * shared keys, so put a mask over the allowed
286 * entries.
287 */
288 mask = (0xf << crypto->bssidx);
289
0f829b1d 290 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 291 reg &= mask;
292
293 if (reg && reg == mask)
294 return -ENOSPC;
295
acaf908d 296 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 297
298 /*
299 * Upload key to hardware
300 */
301 memcpy(key_entry.key, crypto->key,
302 sizeof(key_entry.key));
303 memcpy(key_entry.tx_mic, crypto->tx_mic,
304 sizeof(key_entry.tx_mic));
305 memcpy(key_entry.rx_mic, crypto->rx_mic,
306 sizeof(key_entry.rx_mic));
307
308 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
309 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
310 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
311 USB_VENDOR_REQUEST_OUT, reg,
312 &key_entry,
313 sizeof(key_entry),
314 timeout);
315
316 /*
317 * The cipher types are stored over 2 registers.
318 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
319 * bssidx 1 and 2 keys are stored in SEC_CSR5.
320 * Using the correct defines correctly will cause overhead,
321 * so just calculate the correct offset.
322 */
323 if (key->hw_key_idx < 8) {
324 field.bit_offset = (3 * key->hw_key_idx);
325 field.bit_mask = 0x7 << field.bit_offset;
326
0f829b1d 327 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
906c110f 328 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 329 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
906c110f
ID		 330 } else {
331 field.bit_offset = (3 * (key->hw_key_idx - 8));
332 field.bit_mask = 0x7 << field.bit_offset;
333
0f829b1d 334 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
906c110f 335 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 336 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
906c110f
ID		 337 }
338
339 /*
340 * The driver does not support the IV/EIV generation
341 * in hardware. However it doesn't support the IV/EIV
342 * inside the ieee80211 frame either, but requires it
3ad2f3fb 343 * to be provided separately for the descriptor.
906c110f
ID		 344 * rt2x00lib will cut the IV/EIV data out of all frames
345 * given to us by mac80211, but we must tell mac80211
346 * to generate the IV/EIV data.
347 */
348 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
349 }
350
351 /*
352 * SEC_CSR0 contains only single-bit fields to indicate
353 * a particular key is valid. Because using the FIELD32()
354 * defines directly will cause a lot of overhead we use
355 * a calculation to determine the correct bit directly.
356 */
357 mask = 1 << key->hw_key_idx;
358
0f829b1d 359 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 360 if (crypto->cmd == SET_KEY)
361 reg |= mask;
362 else if (crypto->cmd == DISABLE_KEY)
363 reg &= ~mask;
0f829b1d 364 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
906c110f
ID		 365
366 return 0;
367}
368
369static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
370 struct rt2x00lib_crypto *crypto,
371 struct ieee80211_key_conf *key)
372{
373 struct hw_pairwise_ta_entry addr_entry;
374 struct hw_key_entry key_entry;
375 int timeout;
376 u32 mask;
377 u32 reg;
378
379 if (crypto->cmd == SET_KEY) {
380 /*
381 * rt2x00lib can't determine the correct free
382 * key_idx for pairwise keys. We have 2 registers
383 * with key valid bits. The goal is simple, read
384 * the first register, if that is full move to
385 * the next register.
386 * When both registers are full, we drop the key,
387 * otherwise we use the first invalid entry.
388 */
0f829b1d 389 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 390 if (reg && reg == ~0) {
391 key->hw_key_idx = 32;
0f829b1d 392 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 393 if (reg && reg == ~0)
394 return -ENOSPC;
395 }
396
acaf908d 397 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 398
399 /*
400 * Upload key to hardware
401 */
402 memcpy(key_entry.key, crypto->key,
403 sizeof(key_entry.key));
404 memcpy(key_entry.tx_mic, crypto->tx_mic,
405 sizeof(key_entry.tx_mic));
406 memcpy(key_entry.rx_mic, crypto->rx_mic,
407 sizeof(key_entry.rx_mic));
408
409 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
410 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
411 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
412 USB_VENDOR_REQUEST_OUT, reg,
413 &key_entry,
414 sizeof(key_entry),
415 timeout);
416
417 /*
418 * Send the address and cipher type to the hardware register.
419 * This data fits within the CSR cache size, so we can use
0f829b1d 420 * rt2x00usb_register_multiwrite() directly.
906c110f
ID		 421 */
422 memset(&addr_entry, 0, sizeof(addr_entry));
423 memcpy(&addr_entry, crypto->address, ETH_ALEN);
424 addr_entry.cipher = crypto->cipher;
425
426 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
0f829b1d 427 rt2x00usb_register_multiwrite(rt2x00dev, reg,
906c110f
ID		 428 &addr_entry, sizeof(addr_entry));
429
430 /*
431 * Enable pairwise lookup table for given BSS idx,
432 * without this received frames will not be decrypted
433 * by the hardware.
434 */
0f829b1d 435 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
906c110f 436 reg |= (1 << crypto->bssidx);
0f829b1d 437 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
906c110f
ID		 438
439 /*
440 * The driver does not support the IV/EIV generation
441 * in hardware. However it doesn't support the IV/EIV
442 * inside the ieee80211 frame either, but requires it
3ad2f3fb 443 * to be provided separately for the descriptor.
906c110f
ID		 444 * rt2x00lib will cut the IV/EIV data out of all frames
445 * given to us by mac80211, but we must tell mac80211
446 * to generate the IV/EIV data.
447 */
448 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
449 }
450
451 /*
452 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
453 * a particular key is valid. Because using the FIELD32()
454 * defines directly will cause a lot of overhead we use
455 * a calculation to determine the correct bit directly.
456 */
457 if (key->hw_key_idx < 32) {
458 mask = 1 << key->hw_key_idx;
459
0f829b1d 460 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 461 if (crypto->cmd == SET_KEY)
462 reg |= mask;
463 else if (crypto->cmd == DISABLE_KEY)
464 reg &= ~mask;
0f829b1d 465 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
906c110f
ID		 466 } else {
467 mask = 1 << (key->hw_key_idx - 32);
468
0f829b1d 469 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 470 if (crypto->cmd == SET_KEY)
471 reg |= mask;
472 else if (crypto->cmd == DISABLE_KEY)
473 reg &= ~mask;
0f829b1d 474 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
906c110f
ID		 475 }
476
477 return 0;
478}
479
3a643d24
ID		 480static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
481 const unsigned int filter_flags)
482{
483 u32 reg;
484
485 /*
486 * Start configuration steps.
487 * Note that the version error will always be dropped
488 * and broadcast frames will always be accepted since
489 * there is no filter for it at this time.
490 */
0f829b1d 491 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
3a643d24
ID		 492 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
493 !(filter_flags & FIF_FCSFAIL));
494 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
495 !(filter_flags & FIF_PLCPFAIL));
496 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1afcfd54 497 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
3a643d24
ID		 498 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
499 !(filter_flags & FIF_PROMISC_IN_BSS));
500 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 501 !(filter_flags & FIF_PROMISC_IN_BSS) &&
502 !rt2x00dev->intf_ap_count);
3a643d24
ID		 503 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
504 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
505 !(filter_flags & FIF_ALLMULTI));
506 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
507 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
508 !(filter_flags & FIF_CONTROL));
0f829b1d 509 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
3a643d24
ID		 510}
511
6bb40dd1
ID		 512static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
513 struct rt2x00_intf *intf,
514 struct rt2x00intf_conf *conf,
515 const unsigned int flags)
95ea3627 516{
6bb40dd1
ID		 517 unsigned int beacon_base;
518 u32 reg;
95ea3627 519
6bb40dd1
ID		 520 if (flags & CONFIG_UPDATE_TYPE) {
521 /*
522 * Clear current synchronisation setup.
523 * For the Beacon base registers we only need to clear
524 * the first byte since that byte contains the VALID and OWNER
525 * bits which (when set to 0) will invalidate the entire beacon.
526 */
527 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
0f829b1d 528 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 529
6bb40dd1
ID		 530 /*
531 * Enable synchronisation.
532 */
0f829b1d 533 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 534 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 535 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 536 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
0f829b1d 537 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
6bb40dd1 538 }
95ea3627 539
6bb40dd1
ID		 540 if (flags & CONFIG_UPDATE_MAC) {
541 reg = le32_to_cpu(conf->mac[1]);
542 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
543 conf->mac[1] = cpu_to_le32(reg);
95ea3627 544
0f829b1d 545 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
6bb40dd1
ID		 546 conf->mac, sizeof(conf->mac));
547 }
95ea3627 548
6bb40dd1
ID		 549 if (flags & CONFIG_UPDATE_BSSID) {
550 reg = le32_to_cpu(conf->bssid[1]);
551 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
552 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 553
0f829b1d 554 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
6bb40dd1
ID		 555 conf->bssid, sizeof(conf->bssid));
556 }
95ea3627
ID		 557}
558
3a643d24
ID		 559static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
560 struct rt2x00lib_erp *erp)
95ea3627 561{
95ea3627 562 u32 reg;
95ea3627 563
0f829b1d 564 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
4789666e 565 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
8a566afe 566 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
0f829b1d 567 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 568
0f829b1d 569 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
8a566afe 570 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
4f5af6eb 571 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 572 !!erp->short_preamble);
0f829b1d 573 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 574
0f829b1d 575 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 576
8a566afe
ID		 577 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
578 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
579 erp->beacon_int * 16);
580 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
581
0f829b1d 582 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
e4ea1c40 583 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
0f829b1d 584 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 585
0f829b1d 586 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
e4ea1c40
ID		 587 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
588 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
589 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
0f829b1d 590 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 591}
592
593static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 594 struct antenna_setup *ant)
95ea3627
ID		 595{
596 u8 r3;
597 u8 r4;
598 u8 r77;
2676c94d 599 u8 temp;
95ea3627
ID		 600
601 rt73usb_bbp_read(rt2x00dev, 3, &r3);
602 rt73usb_bbp_read(rt2x00dev, 4, &r4);
603 rt73usb_bbp_read(rt2x00dev, 77, &r77);
604
605 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
606
e4cd2ff8
ID		 607 /*
608 * Configure the RX antenna.
609 */
addc81bd 610 switch (ant->rx) {
95ea3627 611 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 612 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
613 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 614 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 615 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 616 break;
617 case ANTENNA_A:
2676c94d 618 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 619 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 620 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 621 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
622 else
623 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 624 break;
625 case ANTENNA_B:
a4fe07d9 626 default:
2676c94d 627 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 628 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 629 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 630 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
631 else
632 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 633 break;
634 }
635
636 rt73usb_bbp_write(rt2x00dev, 77, r77);
637 rt73usb_bbp_write(rt2x00dev, 3, r3);
638 rt73usb_bbp_write(rt2x00dev, 4, r4);
639}
640
641static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 642 struct antenna_setup *ant)
95ea3627
ID		 643{
644 u8 r3;
645 u8 r4;
646 u8 r77;
647
648 rt73usb_bbp_read(rt2x00dev, 3, &r3);
649 rt73usb_bbp_read(rt2x00dev, 4, &r4);
650 rt73usb_bbp_read(rt2x00dev, 77, &r77);
651
652 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
653 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
654 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
655
e4cd2ff8
ID		 656 /*
657 * Configure the RX antenna.
658 */
addc81bd 659 switch (ant->rx) {
95ea3627 660 case ANTENNA_HW_DIVERSITY:
2676c94d 661 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 662 break;
663 case ANTENNA_A:
2676c94d
MN		 664 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
665 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 666 break;
667 case ANTENNA_B:
a4fe07d9 668 default:
2676c94d
MN		 669 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
670 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 671 break;
672 }
673
674 rt73usb_bbp_write(rt2x00dev, 77, r77);
675 rt73usb_bbp_write(rt2x00dev, 3, r3);
676 rt73usb_bbp_write(rt2x00dev, 4, r4);
677}
678
679struct antenna_sel {
680 u8 word;
681 /*
682 * value[0] -> non-LNA
683 * value[1] -> LNA
684 */
685 u8 value[2];
686};
687
688static const struct antenna_sel antenna_sel_a[] = {
689 { 96, { 0x58, 0x78 } },
690 { 104, { 0x38, 0x48 } },
691 { 75, { 0xfe, 0x80 } },
692 { 86, { 0xfe, 0x80 } },
693 { 88, { 0xfe, 0x80 } },
694 { 35, { 0x60, 0x60 } },
695 { 97, { 0x58, 0x58 } },
696 { 98, { 0x58, 0x58 } },
697};
698
699static const struct antenna_sel antenna_sel_bg[] = {
700 { 96, { 0x48, 0x68 } },
701 { 104, { 0x2c, 0x3c } },
702 { 75, { 0xfe, 0x80 } },
703 { 86, { 0xfe, 0x80 } },
704 { 88, { 0xfe, 0x80 } },
705 { 35, { 0x50, 0x50 } },
706 { 97, { 0x48, 0x48 } },
707 { 98, { 0x48, 0x48 } },
708};
709
e4ea1c40
ID		 710static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
711 struct antenna_setup *ant)
95ea3627
ID		 712{
713 const struct antenna_sel *sel;
714 unsigned int lna;
715 unsigned int i;
716 u32 reg;
717
a4fe07d9
ID		 718 /*
719 * We should never come here because rt2x00lib is supposed
720 * to catch this and send us the correct antenna explicitely.
721 */
722 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
723 ant->tx == ANTENNA_SW_DIVERSITY);
724
8318d78a 725 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 726 sel = antenna_sel_a;
727 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 728 } else {
729 sel = antenna_sel_bg;
730 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 731 }
732
2676c94d
MN		 733 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
734 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
735
0f829b1d 736 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
2676c94d 737
ddc827f9 738 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 739 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 740 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 741 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 742
0f829b1d 743 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
95ea3627 744
5122d898 745 if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
addc81bd 746 rt73usb_config_antenna_5x(rt2x00dev, ant);
5122d898 747 else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
addc81bd 748 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 749}
750
e4ea1c40 751static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
5c58ee51 752 struct rt2x00lib_conf *libconf)
e4ea1c40
ID		 753{
754 u16 eeprom;
755 short lna_gain = 0;
756
757 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
758 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
759 lna_gain += 14;
760
761 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
762 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
763 } else {
764 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
765 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
766 }
767
768 rt2x00dev->lna_gain = lna_gain;
769}
770
771static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
772 struct rf_channel *rf, const int txpower)
773{
774 u8 r3;
775 u8 r94;
776 u8 smart;
777
778 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
779 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
780
5122d898 781 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
e4ea1c40
ID		 782
783 rt73usb_bbp_read(rt2x00dev, 3, &r3);
784 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
785 rt73usb_bbp_write(rt2x00dev, 3, r3);
786
787 r94 = 6;
788 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
789 r94 += txpower - MAX_TXPOWER;
790 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
791 r94 += txpower;
792 rt73usb_bbp_write(rt2x00dev, 94, r94);
793
794 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
795 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
796 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
797 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
798
799 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
800 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
801 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
802 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
803
804 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
805 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
806 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
807 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
808
809 udelay(10);
810}
811
812static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
813 const int txpower)
814{
815 struct rf_channel rf;
816
817 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
818 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
819 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
820 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
821
822 rt73usb_config_channel(rt2x00dev, &rf, txpower);
823}
824
825static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
826 struct rt2x00lib_conf *libconf)
95ea3627
ID		 827{
828 u32 reg;
829
0f829b1d 830 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
e4ea1c40
ID		 831 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
832 libconf->conf->long_frame_max_tx_count);
833 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
834 libconf->conf->short_frame_max_tx_count);
0f829b1d 835 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
e4ea1c40 836}
95ea3627 837
7d7f19cc
ID		 838static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
839 struct rt2x00lib_conf *libconf)
840{
841 enum dev_state state =
842 (libconf->conf->flags & IEEE80211_CONF_PS) ?
843 STATE_SLEEP : STATE_AWAKE;
844 u32 reg;
845
846 if (state == STATE_SLEEP) {
847 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
848 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 849 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 850 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
851 libconf->conf->listen_interval - 1);
852 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
853
854 /* We must first disable autowake before it can be enabled */
855 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
856 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
857
858 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
859 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
860
861 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
862 USB_MODE_SLEEP, REGISTER_TIMEOUT);
863 } else {
864 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
865 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
866
867 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
868 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
869 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
870 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
871 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
872 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
873 }
874}
875
95ea3627 876static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 877 struct rt2x00lib_conf *libconf,
878 const unsigned int flags)
95ea3627 879{
ba2ab471
ID		 880 /* Always recalculate LNA gain before changing configuration */
881 rt73usb_config_lna_gain(rt2x00dev, libconf);
882
e4ea1c40 883 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 884 rt73usb_config_channel(rt2x00dev, &libconf->rf,
885 libconf->conf->power_level);
e4ea1c40
ID		 886 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
887 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 888 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 889 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
890 rt73usb_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 891 if (flags & IEEE80211_CONF_CHANGE_PS)
892 rt73usb_config_ps(rt2x00dev, libconf);
95ea3627
ID		 893}
894
95ea3627
ID		 895/*
896 * Link tuning
897 */
ebcf26da
ID		 898static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
899 struct link_qual *qual)
95ea3627
ID		 900{
901 u32 reg;
902
903 /*
904 * Update FCS error count from register.
905 */
0f829b1d 906 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 907 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 908
909 /*
910 * Update False CCA count from register.
911 */
0f829b1d 912 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 913 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 914}
915
5352ff65
ID		 916static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
917 struct link_qual *qual, u8 vgc_level)
eb20b4e8 918{
5352ff65 919 if (qual->vgc_level != vgc_level) {
eb20b4e8 920 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 921 qual->vgc_level = vgc_level;
922 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 923 }
924}
925
5352ff65
ID		 926static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
927 struct link_qual *qual)
95ea3627 928{
5352ff65 929 rt73usb_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 930}
931
5352ff65
ID		 932static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
933 struct link_qual *qual, const u32 count)
95ea3627 934{
95ea3627
ID		 935 u8 up_bound;
936 u8 low_bound;
937
95ea3627
ID		 938 /*
939 * Determine r17 bounds.
940 */
8318d78a 941 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 942 low_bound = 0x28;
943 up_bound = 0x48;
944
945 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
946 low_bound += 0x10;
947 up_bound += 0x10;
948 }
949 } else {
5352ff65 950 if (qual->rssi > -82) {
95ea3627
ID		 951 low_bound = 0x1c;
952 up_bound = 0x40;
5352ff65 953 } else if (qual->rssi > -84) {
95ea3627
ID		 954 low_bound = 0x1c;
955 up_bound = 0x20;
956 } else {
957 low_bound = 0x1c;
958 up_bound = 0x1c;
959 }
960
961 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
962 low_bound += 0x14;
963 up_bound += 0x10;
964 }
965 }
966
6bb40dd1
ID		 967 /*
968 * If we are not associated, we should go straight to the
969 * dynamic CCA tuning.
970 */
971 if (!rt2x00dev->intf_associated)
972 goto dynamic_cca_tune;
973
95ea3627
ID		 974 /*
975 * Special big-R17 for very short distance
976 */
5352ff65
ID		 977 if (qual->rssi > -35) {
978 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 979 return;
980 }
981
982 /*
983 * Special big-R17 for short distance
984 */
5352ff65
ID		 985 if (qual->rssi >= -58) {
986 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 987 return;
988 }
989
990 /*
991 * Special big-R17 for middle-short distance
992 */
5352ff65
ID		 993 if (qual->rssi >= -66) {
994 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 995 return;
996 }
997
998 /*
999 * Special mid-R17 for middle distance
1000 */
5352ff65
ID		 1001 if (qual->rssi >= -74) {
1002 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 1003 return;
1004 }
1005
1006 /*
1007 * Special case: Change up_bound based on the rssi.
1008 * Lower up_bound when rssi is weaker then -74 dBm.
1009 */
5352ff65 1010 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1011 if (low_bound > up_bound)
1012 up_bound = low_bound;
1013
5352ff65
ID		 1014 if (qual->vgc_level > up_bound) {
1015 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1016 return;
1017 }
1018
6bb40dd1
ID		 1019dynamic_cca_tune:
1020
95ea3627
ID		 1021 /*
1022 * r17 does not yet exceed upper limit, continue and base
1023 * the r17 tuning on the false CCA count.
1024 */
5352ff65
ID		 1025 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1026 rt73usb_set_vgc(rt2x00dev, qual,
1027 min_t(u8, qual->vgc_level + 4, up_bound));
1028 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1029 rt73usb_set_vgc(rt2x00dev, qual,
1030 max_t(u8, qual->vgc_level - 4, low_bound));
95ea3627
ID		 1031}
1032
1033/*
a7f3a06c 1034 * Firmware functions
95ea3627
ID		 1035 */
1036static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1037{
1038 return FIRMWARE_RT2571;
1039}
1040
0cbe0064
ID		 1041static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1042 const u8 *data, const size_t len)
a7f3a06c 1043{
0cbe0064 1044 u16 fw_crc;
a7f3a06c
ID		 1045 u16 crc;
1046
1047 /*
0cbe0064
ID		 1048 * Only support 2kb firmware files.
1049 */
1050 if (len != 2048)
1051 return FW_BAD_LENGTH;
1052
1053 /*
a7f3a06c
ID		 1054 * The last 2 bytes in the firmware array are the crc checksum itself,
1055 * this means that we should never pass those 2 bytes to the crc
1056 * algorithm.
1057 */
0cbe0064
ID		 1058 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1059
1060 /*
1061 * Use the crc itu-t algorithm.
1062 */
a7f3a06c
ID		 1063 crc = crc_itu_t(0, data, len - 2);
1064 crc = crc_itu_t_byte(crc, 0);
1065 crc = crc_itu_t_byte(crc, 0);
1066
0cbe0064 1067 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1068}
1069
0cbe0064
ID		 1070static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1071 const u8 *data, const size_t len)
95ea3627
ID		 1072{
1073 unsigned int i;
1074 int status;
1075 u32 reg;
95ea3627
ID		 1076
1077 /*
1078 * Wait for stable hardware.
1079 */
1080 for (i = 0; i < 100; i++) {
0f829b1d 1081 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1082 if (reg)
1083 break;
1084 msleep(1);
1085 }
1086
1087 if (!reg) {
1088 ERROR(rt2x00dev, "Unstable hardware.\n");
1089 return -EBUSY;
1090 }
1091
1092 /*
1093 * Write firmware to device.
95ea3627 1094 */
3e0c1abe
IM		 1095 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1096 USB_VENDOR_REQUEST_OUT,
1097 FIRMWARE_IMAGE_BASE,
1098 data, len,
1099 REGISTER_TIMEOUT32(len));
95ea3627
ID		 1100
1101 /*
1102 * Send firmware request to device to load firmware,
1103 * we need to specify a long timeout time.
1104 */
1105 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 1106 0, USB_MODE_FIRMWARE,
95ea3627
ID		 1107 REGISTER_TIMEOUT_FIRMWARE);
1108 if (status < 0) {
1109 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1110 return status;
1111 }
1112
95ea3627
ID		 1113 return 0;
1114}
1115
a7f3a06c
ID		 1116/*
1117 * Initialization functions.
1118 */
95ea3627
ID		 1119static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1120{
1121 u32 reg;
1122
0f829b1d 1123 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627
ID		 1124 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1125 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1126 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
0f829b1d 1127 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 1128
0f829b1d 1129 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
95ea3627
ID		 1130 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1131 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1132 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1133 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1134 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1135 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1136 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1137 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
0f829b1d 1138 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
95ea3627
ID		 1139
1140 /*
1141 * CCK TXD BBP registers
1142 */
0f829b1d 1143 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
95ea3627
ID		 1144 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1145 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1146 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1147 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1148 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1149 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1150 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1151 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
0f829b1d 1152 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
95ea3627
ID		 1153
1154 /*
1155 * OFDM TXD BBP registers
1156 */
0f829b1d 1157 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
95ea3627
ID		 1158 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1159 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1160 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1161 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1162 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1163 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
0f829b1d 1164 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
95ea3627 1165
0f829b1d 1166 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
95ea3627
ID		 1167 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1168 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1169 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1170 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
0f829b1d 1171 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
95ea3627 1172
0f829b1d 1173 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
95ea3627
ID		 1174 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1175 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1176 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1177 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
0f829b1d 1178 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
95ea3627 1179
0f829b1d 1180 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1f909162
ID		 1181 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1182 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1183 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1184 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1185 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1186 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
0f829b1d 1187 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1f909162 1188
0f829b1d 1189 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
95ea3627 1190
0f829b1d 1191 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
95ea3627 1192 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
0f829b1d 1193 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
95ea3627 1194
0f829b1d 1195 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
95ea3627
ID		 1196
1197 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1198 return -EBUSY;
1199
0f829b1d 1200 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
95ea3627
ID		 1201
1202 /*
1203 * Invalidate all Shared Keys (SEC_CSR0),
1204 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1205 */
0f829b1d
ID		 1206 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1207 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1208 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
95ea3627
ID		 1209
1210 reg = 0x000023b0;
5122d898 1211 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
95ea3627 1212 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
0f829b1d 1213 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
95ea3627 1214
0f829b1d
ID		 1215 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1216 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1217 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
95ea3627 1218
0f829b1d 1219 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
95ea3627 1220 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
0f829b1d 1221 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 1222
6bb40dd1
ID		 1223 /*
1224 * Clear all beacons
1225 * For the Beacon base registers we only need to clear
1226 * the first byte since that byte contains the VALID and OWNER
1227 * bits which (when set to 0) will invalidate the entire beacon.
1228 */
0f829b1d
ID		 1229 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1230 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1231 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1232 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
6bb40dd1 1233
95ea3627
ID		 1234 /*
1235 * We must clear the error counters.
1236 * These registers are cleared on read,
1237 * so we may pass a useless variable to store the value.
1238 */
0f829b1d
ID		 1239 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1240 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1241 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
95ea3627
ID		 1242
1243 /*
1244 * Reset MAC and BBP registers.
1245 */
0f829b1d 1246 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1247 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1248 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
0f829b1d 1249 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1250
0f829b1d 1251 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1252 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1253 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
0f829b1d 1254 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1255
0f829b1d 1256 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627 1257 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
0f829b1d 1258 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627
ID		 1259
1260 return 0;
1261}
1262
2b08da3f 1263static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1264{
1265 unsigned int i;
95ea3627
ID		 1266 u8 value;
1267
1268 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1269 rt73usb_bbp_read(rt2x00dev, 0, &value);
1270 if ((value != 0xff) && (value != 0x00))
2b08da3f 1271 return 0;
95ea3627
ID		 1272 udelay(REGISTER_BUSY_DELAY);
1273 }
1274
1275 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1276 return -EACCES;
2b08da3f
ID		 1277}
1278
1279static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1280{
1281 unsigned int i;
1282 u16 eeprom;
1283 u8 reg_id;
1284 u8 value;
1285
1286 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1287 return -EACCES;
95ea3627 1288
95ea3627
ID		 1289 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1290 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1291 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1292 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1293 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1294 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1295 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1296 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1297 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1298 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1299 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1300 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1301 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1302 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1303 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1304 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1305 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1306 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1307 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1308 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1309 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1310 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1311 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1312 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1313 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1314
95ea3627
ID		 1315 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1316 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1317
1318 if (eeprom != 0xffff && eeprom != 0x0000) {
1319 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1320 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1321 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1322 }
1323 }
95ea3627
ID		 1324
1325 return 0;
1326}
1327
1328/*
1329 * Device state switch handlers.
1330 */
1331static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1332 enum dev_state state)
1333{
1334 u32 reg;
1335
0f829b1d 1336 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627 1337 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1338 (state == STATE_RADIO_RX_OFF) ||
1339 (state == STATE_RADIO_RX_OFF_LINK));
0f829b1d 1340 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627
ID		 1341}
1342
1343static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1344{
1345 /*
1346 * Initialize all registers.
1347 */
2b08da3f
ID		 1348 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1349 rt73usb_init_bbp(rt2x00dev)))
95ea3627 1350 return -EIO;
95ea3627 1351
95ea3627
ID		 1352 return 0;
1353}
1354
1355static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1356{
0f829b1d 1357 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1358
1359 /*
1360 * Disable synchronisation.
1361 */
0f829b1d 1362 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
95ea3627
ID		 1363
1364 rt2x00usb_disable_radio(rt2x00dev);
1365}
1366
1367static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1368{
1369 u32 reg;
1370 unsigned int i;
1371 char put_to_sleep;
95ea3627
ID		 1372
1373 put_to_sleep = (state != STATE_AWAKE);
1374
0f829b1d 1375 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
95ea3627
ID		 1376 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1377 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
0f829b1d 1378 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1379
1380 /*
1381 * Device is not guaranteed to be in the requested state yet.
1382 * We must wait until the register indicates that the
1383 * device has entered the correct state.
1384 */
1385 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
0f829b1d 1386 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1387 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1388 if (state == !put_to_sleep)
95ea3627
ID		 1389 return 0;
1390 msleep(10);
1391 }
1392
95ea3627
ID		 1393 return -EBUSY;
1394}
1395
1396static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1397 enum dev_state state)
1398{
1399 int retval = 0;
1400
1401 switch (state) {
1402 case STATE_RADIO_ON:
1403 retval = rt73usb_enable_radio(rt2x00dev);
1404 break;
1405 case STATE_RADIO_OFF:
1406 rt73usb_disable_radio(rt2x00dev);
1407 break;
1408 case STATE_RADIO_RX_ON:
61667d8d 1409 case STATE_RADIO_RX_ON_LINK:
95ea3627 1410 case STATE_RADIO_RX_OFF:
61667d8d 1411 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1412 rt73usb_toggle_rx(rt2x00dev, state);
1413 break;
1414 case STATE_RADIO_IRQ_ON:
1415 case STATE_RADIO_IRQ_OFF:
1416 /* No support, but no error either */
95ea3627
ID		 1417 break;
1418 case STATE_DEEP_SLEEP:
1419 case STATE_SLEEP:
1420 case STATE_STANDBY:
1421 case STATE_AWAKE:
1422 retval = rt73usb_set_state(rt2x00dev, state);
1423 break;
1424 default:
1425 retval = -ENOTSUPP;
1426 break;
1427 }
1428
2b08da3f
ID		 1429 if (unlikely(retval))
1430 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1431 state, retval);
1432
95ea3627
ID		 1433 return retval;
1434}
1435
1436/*
1437 * TX descriptor initialization
1438 */
1439static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
906c110f
ID		 1440 struct sk_buff *skb,
1441 struct txentry_desc *txdesc)
95ea3627 1442{
181d6902 1443 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1444 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1445 u32 word;
1446
1447 /*
1448 * Start writing the descriptor words.
1449 */
1450 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1451 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1452 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1453 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1454 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
906c110f 1455 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1456 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1457 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
95ea3627
ID		 1458 rt2x00_desc_write(txd, 1, word);
1459
1460 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1461 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1462 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1463 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1464 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1465 rt2x00_desc_write(txd, 2, word);
1466
906c110f 1467 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1468 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1469 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
906c110f
ID		 1470 }
1471
95ea3627
ID		 1472 rt2x00_desc_read(txd, 5, &word);
1473 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1474 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1475 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1476 rt2x00_desc_write(txd, 5, word);
1477
1478 rt2x00_desc_read(txd, 0, &word);
1479 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1480 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1481 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1482 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1483 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1484 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1485 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1486 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1487 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1488 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1489 (txdesc->rate_mode == RATE_MODE_OFDM));
181d6902 1490 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1491 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1492 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
906c110f
ID		 1493 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1494 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1495 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1496 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1497 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1abc3656 1498 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627 1499 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1500 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
906c110f 1501 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627
ID		 1502 rt2x00_desc_write(txd, 0, word);
1503}
1504
bd88a781
ID		 1505/*
1506 * TX data initialization
1507 */
1508static void rt73usb_write_beacon(struct queue_entry *entry)
1509{
1510 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1511 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1512 unsigned int beacon_base;
1513 u32 reg;
1514
1515 /*
1516 * Add the descriptor in front of the skb.
1517 */
1518 skb_push(entry->skb, entry->queue->desc_size);
1519 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1520 skbdesc->desc = entry->skb->data;
1521
1522 /*
1523 * Disable beaconing while we are reloading the beacon data,
1524 * otherwise we might be sending out invalid data.
1525 */
0f829b1d 1526 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781 1527 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
0f829b1d 1528 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
bd88a781
ID		 1529
1530 /*
1531 * Write entire beacon with descriptor to register.
1532 */
1533 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
3e0c1abe
IM		 1534 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1535 USB_VENDOR_REQUEST_OUT, beacon_base,
1536 entry->skb->data, entry->skb->len,
1537 REGISTER_TIMEOUT32(entry->skb->len));
bd88a781
ID		 1538
1539 /*
1540 * Clean up the beacon skb.
1541 */
1542 dev_kfree_skb(entry->skb);
1543 entry->skb = NULL;
1544}
1545
f1ca2167 1546static int rt73usb_get_tx_data_len(struct queue_entry *entry)
dd9fa2d2
ID		 1547{
1548 int length;
1549
1550 /*
1551 * The length _must_ be a multiple of 4,
1552 * but it must _not_ be a multiple of the USB packet size.
1553 */
f1ca2167
ID		 1554 length = roundup(entry->skb->len, 4);
1555 length += (4 * !(length % entry->queue->usb_maxpacket));
dd9fa2d2
ID		 1556
1557 return length;
1558}
1559
95ea3627 1560static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1561 const enum data_queue_qid queue)
95ea3627
ID		 1562{
1563 u32 reg;
1564
f019d514
ID		 1565 if (queue != QID_BEACON) {
1566 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
95ea3627 1567 return;
f019d514 1568 }
95ea3627
ID		 1569
1570 /*
1571 * For Wi-Fi faily generated beacons between participating stations.
1572 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1573 */
0f829b1d 1574 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
95ea3627 1575
0f829b1d 1576 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
95ea3627 1577 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1578 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1579 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627 1580 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
0f829b1d 1581 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
95ea3627
ID		 1582 }
1583}
1584
1585/*
1586 * RX control handlers
1587 */
1588static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1589{
ba2ab471 1590 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1591 u8 lna;
1592
1593 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1594 switch (lna) {
1595 case 3:
ba2ab471 1596 offset += 90;
95ea3627
ID		 1597 break;
1598 case 2:
ba2ab471 1599 offset += 74;
95ea3627
ID		 1600 break;
1601 case 1:
ba2ab471 1602 offset += 64;
95ea3627
ID		 1603 break;
1604 default:
1605 return 0;
1606 }
1607
8318d78a 1608 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1609 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1610 if (lna == 3 || lna == 2)
1611 offset += 10;
1612 } else {
1613 if (lna == 3)
1614 offset += 6;
1615 else if (lna == 2)
1616 offset += 8;
1617 }
95ea3627
ID		 1618 }
1619
1620 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1621}
1622
181d6902 1623static void rt73usb_fill_rxdone(struct queue_entry *entry,
55887511 1624 struct rxdone_entry_desc *rxdesc)
95ea3627 1625{
906c110f 1626 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
181d6902 1627 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1628 __le32 *rxd = (__le32 *)entry->skb->data;
95ea3627
ID		 1629 u32 word0;
1630 u32 word1;
1631
f855c10b 1632 /*
a26cbc65
GW		 1633 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1634 * frame data in rt2x00usb.
f855c10b 1635 */
a26cbc65 1636 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1637 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1638
1639 /*
70a96109 1640 * It is now safe to read the descriptor on all architectures.
f855c10b 1641 */
95ea3627
ID		 1642 rt2x00_desc_read(rxd, 0, &word0);
1643 rt2x00_desc_read(rxd, 1, &word1);
1644
4150c572 1645 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1646 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1647
906c110f
ID		 1648 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1649 rxdesc->cipher =
1650 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1651 rxdesc->cipher_status =
1652 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1653 }
1654
1655 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 1656 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1657 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
74415edb
ID		 1658 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1659
906c110f 1660 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
74415edb 1661 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
906c110f
ID		 1662
1663 /*
1664 * Hardware has stripped IV/EIV data from 802.11 frame during
3ad2f3fb 1665 * decryption. It has provided the data separately but rt2x00lib
906c110f
ID		 1666 * should decide if it should be reinserted.
1667 */
1668 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1669
1670 /*
1671 * FIXME: Legacy driver indicates that the frame does
1672 * contain the Michael Mic. Unfortunately, in rt2x00
1673 * the MIC seems to be missing completely...
1674 */
1675 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1676
1677 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1678 rxdesc->flags |= RX_FLAG_DECRYPTED;
1679 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1680 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1681 }
1682
95ea3627
ID		 1683 /*
1684 * Obtain the status about this packet.
89993890
ID		 1685 * When frame was received with an OFDM bitrate,
1686 * the signal is the PLCP value. If it was received with
1687 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1688 */
181d6902 1689 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
906c110f 1690 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
181d6902 1691 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1692
19d30e02
ID		 1693 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1694 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1695 else
1696 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1697 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1698 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1699
2ae23854 1700 /*
70a96109 1701 * Set skb pointers, and update frame information.
2ae23854 1702 */
70a96109 1703 skb_pull(entry->skb, entry->queue->desc_size);
2ae23854 1704 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1705}
1706
1707/*
1708 * Device probe functions.
1709 */
1710static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1711{
1712 u16 word;
1713 u8 *mac;
1714 s8 value;
1715
1716 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1717
1718 /*
1719 * Start validation of the data that has been read.
1720 */
1721 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1722 if (!is_valid_ether_addr(mac)) {
1723 random_ether_addr(mac);
e174961c 1724 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1725 }
1726
1727 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1728 if (word == 0xffff) {
1729 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1730 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1731 ANTENNA_B);
1732 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1733 ANTENNA_B);
95ea3627
ID		 1734 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1735 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1736 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1737 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1738 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1739 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1740 }
1741
1742 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1743 if (word == 0xffff) {
1744 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1745 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1746 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1747 }
1748
1749 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1750 if (word == 0xffff) {
1751 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1752 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1753 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1754 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1755 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1756 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1757 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1758 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1759 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1760 LED_MODE_DEFAULT);
1761 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1762 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1763 }
1764
1765 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1766 if (word == 0xffff) {
1767 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1768 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1769 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1770 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1771 }
1772
1773 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1774 if (word == 0xffff) {
1775 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1776 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1777 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1778 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1779 } else {
1780 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1781 if (value < -10 || value > 10)
1782 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1783 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1784 if (value < -10 || value > 10)
1785 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1786 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1787 }
1788
1789 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1790 if (word == 0xffff) {
1791 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1792 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1793 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1794 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1795 } else {
1796 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1797 if (value < -10 || value > 10)
1798 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1799 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1800 if (value < -10 || value > 10)
1801 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1802 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1803 }
1804
1805 return 0;
1806}
1807
1808static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1809{
1810 u32 reg;
1811 u16 value;
1812 u16 eeprom;
1813
1814 /*
1815 * Read EEPROM word for configuration.
1816 */
1817 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1818
1819 /*
1820 * Identify RF chipset.
1821 */
1822 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
0f829b1d 1823 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
49e721ec
GW		 1824 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1825 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
95ea3627 1826
49e721ec 1827 if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
95ea3627
ID		 1828 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1829 return -ENODEV;
1830 }
1831
5122d898
GW		 1832 if (!rt2x00_rf(rt2x00dev, RF5226) &&
1833 !rt2x00_rf(rt2x00dev, RF2528) &&
1834 !rt2x00_rf(rt2x00dev, RF5225) &&
1835 !rt2x00_rf(rt2x00dev, RF2527)) {
95ea3627
ID		 1836 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1837 return -ENODEV;
1838 }
1839
1840 /*
1841 * Identify default antenna configuration.
1842 */
addc81bd 1843 rt2x00dev->default_ant.tx =
95ea3627 1844 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1845 rt2x00dev->default_ant.rx =
95ea3627
ID		 1846 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1847
1848 /*
1849 * Read the Frame type.
1850 */
1851 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1852 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1853
7396faf4
ID		 1854 /*
1855 * Detect if this device has an hardware controlled radio.
1856 */
7396faf4
ID		 1857 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1858 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
7396faf4 1859
95ea3627
ID		 1860 /*
1861 * Read frequency offset.
1862 */
1863 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1864 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1865
1866 /*
1867 * Read external LNA informations.
1868 */
1869 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1870
1871 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1872 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1873 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1874 }
1875
1876 /*
1877 * Store led settings, for correct led behaviour.
1878 */
771fd565 1879#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627
ID		 1880 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1881
475433be
ID		 1882 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1883 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1884 if (value == LED_MODE_SIGNAL_STRENGTH)
1885 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1886 LED_TYPE_QUALITY);
a9450b70
ID		 1887
1888 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1889 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1890 rt2x00_get_field16(eeprom,
1891 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1892 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1893 rt2x00_get_field16(eeprom,
1894 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1895 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1896 rt2x00_get_field16(eeprom,
1897 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1898 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1899 rt2x00_get_field16(eeprom,
1900 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1901 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1902 rt2x00_get_field16(eeprom,
1903 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1904 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1905 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1906 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1907 rt2x00_get_field16(eeprom,
1908 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1909 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1910 rt2x00_get_field16(eeprom,
1911 EEPROM_LED_POLARITY_RDY_A));
771fd565 1912#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1913
1914 return 0;
1915}
1916
1917/*
1918 * RF value list for RF2528
1919 * Supports: 2.4 GHz
1920 */
1921static const struct rf_channel rf_vals_bg_2528[] = {
1922 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1923 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1924 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1925 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1926 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1927 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1928 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1929 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1930 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1931 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1932 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1933 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1934 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1935 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1936};
1937
1938/*
1939 * RF value list for RF5226
1940 * Supports: 2.4 GHz & 5.2 GHz
1941 */
1942static const struct rf_channel rf_vals_5226[] = {
1943 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1944 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1945 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1946 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1947 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1948 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1949 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1950 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1951 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1952 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1953 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1954 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1955 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1956 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1957
1958 /* 802.11 UNI / HyperLan 2 */
1959 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1960 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1961 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1962 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1963 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1964 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1965 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1966 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1967
1968 /* 802.11 HyperLan 2 */
1969 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1970 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1971 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1972 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1973 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1974 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1975 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1976 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1977 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1978 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1979
1980 /* 802.11 UNII */
1981 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1982 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1983 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1984 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1985 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1986 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1987
1988 /* MMAC(Japan)J52 ch 34,38,42,46 */
1989 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1990 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1991 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1992 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1993};
1994
1995/*
1996 * RF value list for RF5225 & RF2527
1997 * Supports: 2.4 GHz & 5.2 GHz
1998 */
1999static const struct rf_channel rf_vals_5225_2527[] = {
2000 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2001 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2002 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2003 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2004 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2005 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2006 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2007 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2008 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2009 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2010 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2011 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2012 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2013 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2014
2015 /* 802.11 UNI / HyperLan 2 */
2016 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2017 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2018 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2019 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2020 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2021 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2022 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2023 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2024
2025 /* 802.11 HyperLan 2 */
2026 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2027 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2028 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2029 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2030 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2031 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2032 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2033 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2034 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2035 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2036
2037 /* 802.11 UNII */
2038 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2039 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2040 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2041 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2042 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2043 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2044
2045 /* MMAC(Japan)J52 ch 34,38,42,46 */
2046 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2047 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2048 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2049 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2050};
2051
2052
8c5e7a5f 2053static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2054{
2055 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2056 struct channel_info *info;
2057 char *tx_power;
95ea3627
ID		 2058 unsigned int i;
2059
2060 /*
2061 * Initialize all hw fields.
2062 */
2063 rt2x00dev->hw->flags =
566bfe5a 2064 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2065 IEEE80211_HW_SIGNAL_DBM |
2066 IEEE80211_HW_SUPPORTS_PS |
2067 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2068
14a3bf89 2069 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2070 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2071 rt2x00_eeprom_addr(rt2x00dev,
2072 EEPROM_MAC_ADDR_0));
2073
95ea3627
ID		 2074 /*
2075 * Initialize hw_mode information.
2076 */
31562e80
ID		 2077 spec->supported_bands = SUPPORT_BAND_2GHZ;
2078 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627 2079
5122d898 2080 if (rt2x00_rf(rt2x00dev, RF2528)) {
95ea3627
ID		 2081 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2082 spec->channels = rf_vals_bg_2528;
5122d898 2083 } else if (rt2x00_rf(rt2x00dev, RF5226)) {
31562e80 2084 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2085 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2086 spec->channels = rf_vals_5226;
5122d898 2087 } else if (rt2x00_rf(rt2x00dev, RF2527)) {
95ea3627
ID		 2088 spec->num_channels = 14;
2089 spec->channels = rf_vals_5225_2527;
5122d898 2090 } else if (rt2x00_rf(rt2x00dev, RF5225)) {
31562e80 2091 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2092 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2093 spec->channels = rf_vals_5225_2527;
2094 }
2095
8c5e7a5f
ID		 2096 /*
2097 * Create channel information array
2098 */
2099 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2100 if (!info)
2101 return -ENOMEM;
95ea3627 2102
8c5e7a5f
ID		 2103 spec->channels_info = info;
2104
2105 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2106 for (i = 0; i < 14; i++)
2107 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2108
2109 if (spec->num_channels > 14) {
2110 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2111 for (i = 14; i < spec->num_channels; i++)
2112 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2113 }
8c5e7a5f
ID		 2114
2115 return 0;
95ea3627
ID		 2116}
2117
2118static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2119{
2120 int retval;
2121
2122 /*
2123 * Allocate eeprom data.
2124 */
2125 retval = rt73usb_validate_eeprom(rt2x00dev);
2126 if (retval)
2127 return retval;
2128
2129 retval = rt73usb_init_eeprom(rt2x00dev);
2130 if (retval)
2131 return retval;
2132
2133 /*
2134 * Initialize hw specifications.
2135 */
8c5e7a5f
ID		 2136 retval = rt73usb_probe_hw_mode(rt2x00dev);
2137 if (retval)
2138 return retval;
95ea3627 2139
1afcfd54
IP		 2140 /*
2141 * This device has multiple filters for control frames,
2142 * but has no a separate filter for PS Poll frames.
2143 */
2144 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2145
95ea3627 2146 /*
9404ef34 2147 * This device requires firmware.
95ea3627 2148 */
066cb637 2149 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
008c4482
ID		 2150 if (!modparam_nohwcrypt)
2151 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
95ea3627
ID		 2152
2153 /*
2154 * Set the rssi offset.
2155 */
2156 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2157
2158 return 0;
2159}
2160
2161/*
2162 * IEEE80211 stack callback functions.
2163 */
2af0a570
ID		 2164static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2165 const struct ieee80211_tx_queue_params *params)
2166{
2167 struct rt2x00_dev *rt2x00dev = hw->priv;
2168 struct data_queue *queue;
2169 struct rt2x00_field32 field;
2170 int retval;
2171 u32 reg;
5e790023 2172 u32 offset;
2af0a570
ID		 2173
2174 /*
2175 * First pass the configuration through rt2x00lib, that will
2176 * update the queue settings and validate the input. After that
2177 * we are free to update the registers based on the value
2178 * in the queue parameter.
2179 */
2180 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2181 if (retval)
2182 return retval;
2183
5e790023
ID		 2184 /*
2185 * We only need to perform additional register initialization
2186 * for WMM queues/
2187 */
2188 if (queue_idx >= 4)
2189 return 0;
2190
2af0a570
ID		 2191 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2192
2193 /* Update WMM TXOP register */
5e790023
ID		 2194 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2195 field.bit_offset = (queue_idx & 1) * 16;
2196 field.bit_mask = 0xffff << field.bit_offset;
2197
2198 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2199 rt2x00_set_field32(&reg, field, queue->txop);
2200 rt2x00usb_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2201
2202 /* Update WMM registers */
2203 field.bit_offset = queue_idx * 4;
2204 field.bit_mask = 0xf << field.bit_offset;
2205
0f829b1d 2206 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2af0a570 2207 rt2x00_set_field32(&reg, field, queue->aifs);
0f829b1d 2208 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2af0a570 2209
0f829b1d 2210 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2af0a570 2211 rt2x00_set_field32(&reg, field, queue->cw_min);
0f829b1d 2212 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2af0a570 2213
0f829b1d 2214 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2af0a570 2215 rt2x00_set_field32(&reg, field, queue->cw_max);
0f829b1d 2216 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2af0a570
ID		 2217
2218 return 0;
2219}
2220
95ea3627
ID		 2221static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2222{
2223 struct rt2x00_dev *rt2x00dev = hw->priv;
2224 u64 tsf;
2225 u32 reg;
2226
0f829b1d 2227 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
95ea3627 2228 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
0f829b1d 2229 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
95ea3627
ID		 2230 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2231
2232 return tsf;
2233}
95ea3627 2234
95ea3627
ID		 2235static const struct ieee80211_ops rt73usb_mac80211_ops = {
2236 .tx = rt2x00mac_tx,
4150c572
JB		 2237 .start = rt2x00mac_start,
2238 .stop = rt2x00mac_stop,
95ea3627
ID		 2239 .add_interface = rt2x00mac_add_interface,
2240 .remove_interface = rt2x00mac_remove_interface,
2241 .config = rt2x00mac_config,
3a643d24 2242 .configure_filter = rt2x00mac_configure_filter,
930c06f2 2243 .set_tim = rt2x00mac_set_tim,
906c110f 2244 .set_key = rt2x00mac_set_key,
95ea3627 2245 .get_stats = rt2x00mac_get_stats,
471b3efd 2246 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2247 .conf_tx = rt73usb_conf_tx,
95ea3627 2248 .get_tsf = rt73usb_get_tsf,
e47a5cdd 2249 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 2250};
2251
2252static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2253 .probe_hw = rt73usb_probe_hw,
2254 .get_firmware_name = rt73usb_get_firmware_name,
0cbe0064 2255 .check_firmware = rt73usb_check_firmware,
95ea3627
ID		 2256 .load_firmware = rt73usb_load_firmware,
2257 .initialize = rt2x00usb_initialize,
2258 .uninitialize = rt2x00usb_uninitialize,
798b7adb 2259 .clear_entry = rt2x00usb_clear_entry,
95ea3627 2260 .set_device_state = rt73usb_set_device_state,
7396faf4 2261 .rfkill_poll = rt73usb_rfkill_poll,
95ea3627
ID		 2262 .link_stats = rt73usb_link_stats,
2263 .reset_tuner = rt73usb_reset_tuner,
2264 .link_tuner = rt73usb_link_tuner,
2265 .write_tx_desc = rt73usb_write_tx_desc,
2266 .write_tx_data = rt2x00usb_write_tx_data,
bd88a781 2267 .write_beacon = rt73usb_write_beacon,
dd9fa2d2 2268 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627 2269 .kick_tx_queue = rt73usb_kick_tx_queue,
a2c9b652 2270 .kill_tx_queue = rt2x00usb_kill_tx_queue,
95ea3627 2271 .fill_rxdone = rt73usb_fill_rxdone,
906c110f
ID		 2272 .config_shared_key = rt73usb_config_shared_key,
2273 .config_pairwise_key = rt73usb_config_pairwise_key,
3a643d24 2274 .config_filter = rt73usb_config_filter,
6bb40dd1 2275 .config_intf = rt73usb_config_intf,
72810379 2276 .config_erp = rt73usb_config_erp,
e4ea1c40 2277 .config_ant = rt73usb_config_ant,
95ea3627
ID		 2278 .config = rt73usb_config,
2279};
2280
181d6902
ID		 2281static const struct data_queue_desc rt73usb_queue_rx = {
2282 .entry_num = RX_ENTRIES,
2283 .data_size = DATA_FRAME_SIZE,
2284 .desc_size = RXD_DESC_SIZE,
b8be63ff 2285 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2286};
2287
2288static const struct data_queue_desc rt73usb_queue_tx = {
2289 .entry_num = TX_ENTRIES,
2290 .data_size = DATA_FRAME_SIZE,
2291 .desc_size = TXD_DESC_SIZE,
b8be63ff 2292 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2293};
2294
2295static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2296 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2297 .data_size = MGMT_FRAME_SIZE,
2298 .desc_size = TXINFO_SIZE,
b8be63ff 2299 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2300};
2301
95ea3627 2302static const struct rt2x00_ops rt73usb_ops = {
04d0362e
GW		 2303 .name = KBUILD_MODNAME,
2304 .max_sta_intf = 1,
2305 .max_ap_intf = 4,
2306 .eeprom_size = EEPROM_SIZE,
2307 .rf_size = RF_SIZE,
2308 .tx_queues = NUM_TX_QUEUES,
e6218cc4 2309 .extra_tx_headroom = TXD_DESC_SIZE,
04d0362e
GW		 2310 .rx = &rt73usb_queue_rx,
2311 .tx = &rt73usb_queue_tx,
2312 .bcn = &rt73usb_queue_bcn,
2313 .lib = &rt73usb_rt2x00_ops,
2314 .hw = &rt73usb_mac80211_ops,
95ea3627 2315#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 2316 .debugfs = &rt73usb_rt2x00debug,
95ea3627
ID		 2317#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2318};
2319
2320/*
2321 * rt73usb module information.
2322 */
2323static struct usb_device_id rt73usb_device_table[] = {
2324 /* AboCom */
ef4bb70d
XVP		 2325 { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) },
2326 { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2327 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2328 { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) },
2329 { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) },
2330 /* AL */
2331 { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) },
144d9ad9
ID		 2332 /* Amigo */
2333 { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2334 { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2335 /* AMIT */
2336 { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2337 /* Askey */
2338 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2339 /* ASUS */
2340 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2341 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2342 /* Belkin */
2343 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2344 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2345 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2346 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2347 /* Billionton */
2348 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d 2349 { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2350 /* Buffalo */
964d6ad9 2351 { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
050e8a47 2352 { USB_DEVICE(0x0411, 0x00d9), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2353 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
6aabd4c4
ID		 2354 { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) },
2355 { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) },
51b2853f
BP		 2356 /* CEIVA */
2357 { USB_DEVICE(0x178d, 0x02be), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2358 /* CNet */
2359 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2360 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2361 /* Conceptronic */
2362 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
0a74892b
MM		 2363 /* Corega */
2364 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2365 /* D-Link */
2366 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2367 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
cb62eccd 2368 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
445815d7 2369 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2370 /* Edimax */
2371 { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2372 { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) },
2373 /* EnGenius */
2374 { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2375 /* Gemtek */
2376 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2377 /* Gigabyte */
2378 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2379 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2380 /* Huawei-3Com */
2381 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2382 /* Hercules */
78bd6bbf 2383 { USB_DEVICE(0x06f8, 0xe002), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2384 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2385 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2386 /* Linksys */
2387 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2388 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
3be36ae2 2389 { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2390 /* MSI */
22720645 2391 { USB_DEVICE(0x0db0, 0x4600), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2392 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2393 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2394 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2395 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
22720645
XVP		 2396 /* Ovislink */
2397 { USB_DEVICE(0x1b75, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2398 /* Ralink */
144d9ad9 2399 { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2400 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2401 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2402 /* Qcom */
2403 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2404 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2405 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2406 /* Samsung */
2407 { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2408 /* Senao */
2409 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2410 /* Sitecom */
ef4bb70d
XVP		 2411 { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) },
2412 { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) },
2413 { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2414 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d 2415 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2416 /* Surecom */
2417 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
14344b81
ID		 2418 /* Tilgin */
2419 { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2420 /* Philips */
2421 { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2422 /* Planex */
2423 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2424 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
22720645
XVP		 2425 /* WideTell */
2426 { USB_DEVICE(0x7167, 0x3840), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2427 /* Zcom */
2428 { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) },
144d9ad9
ID		 2429 /* ZyXEL */
2430 { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2431 { 0, }
2432};
2433
2434MODULE_AUTHOR(DRV_PROJECT);
2435MODULE_VERSION(DRV_VERSION);
2436MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2437MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2438MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2439MODULE_FIRMWARE(FIRMWARE_RT2571);
2440MODULE_LICENSE("GPL");
2441
2442static struct usb_driver rt73usb_driver = {
2360157c 2443 .name = KBUILD_MODNAME,
95ea3627
ID		 2444 .id_table = rt73usb_device_table,
2445 .probe = rt2x00usb_probe,
2446 .disconnect = rt2x00usb_disconnect,
2447 .suspend = rt2x00usb_suspend,
2448 .resume = rt2x00usb_resume,
2449};
2450
2451static int __init rt73usb_init(void)
2452{
2453 return usb_register(&rt73usb_driver);
2454}
2455
2456static void __exit rt73usb_exit(void)
2457{
2458 usb_deregister(&rt73usb_driver);
2459}
2460
2461module_init(rt73usb_init);
2462module_exit(rt73usb_exit);
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