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[PATCH] rt2x00: Reorganize configuration handler
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627
ID		 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
27/*
28 * Set enviroment defines for rt2x00.h
29 */
30#define DRV_NAME "rt73usb"
31
32#include <linux/delay.h>
33#include <linux/etherdevice.h>
34#include <linux/init.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/usb.h>
38
39#include "rt2x00.h"
40#include "rt2x00usb.h"
41#include "rt73usb.h"
42
43/*
44 * Register access.
45 * All access to the CSR registers will go through the methods
46 * rt73usb_register_read and rt73usb_register_write.
47 * BBP and RF register require indirect register access,
48 * and use the CSR registers BBPCSR and RFCSR to achieve this.
49 * These indirect registers work with busy bits,
50 * and we will try maximal REGISTER_BUSY_COUNT times to access
51 * the register while taking a REGISTER_BUSY_DELAY us delay
52 * between each attampt. When the busy bit is still set at that time,
53 * the access attempt is considered to have failed,
54 * and we will print an error.
55 */
56static inline void rt73usb_register_read(const struct rt2x00_dev *rt2x00dev,
57 const unsigned int offset, u32 *value)
58{
59 __le32 reg;
60 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
61 USB_VENDOR_REQUEST_IN, offset,
62 &reg, sizeof(u32), REGISTER_TIMEOUT);
63 *value = le32_to_cpu(reg);
64}
65
66static inline void rt73usb_register_multiread(const struct rt2x00_dev
67 *rt2x00dev,
68 const unsigned int offset,
69 void *value, const u32 length)
70{
71 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
72 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
73 USB_VENDOR_REQUEST_IN, offset,
74 value, length, timeout);
75}
76
77static inline void rt73usb_register_write(const struct rt2x00_dev *rt2x00dev,
78 const unsigned int offset, u32 value)
79{
80 __le32 reg = cpu_to_le32(value);
81 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
82 USB_VENDOR_REQUEST_OUT, offset,
83 &reg, sizeof(u32), REGISTER_TIMEOUT);
84}
85
86static inline void rt73usb_register_multiwrite(const struct rt2x00_dev
87 *rt2x00dev,
88 const unsigned int offset,
89 void *value, const u32 length)
90{
91 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
92 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
93 USB_VENDOR_REQUEST_OUT, offset,
94 value, length, timeout);
95}
96
97static u32 rt73usb_bbp_check(const struct rt2x00_dev *rt2x00dev)
98{
99 u32 reg;
100 unsigned int i;
101
102 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
103 rt73usb_register_read(rt2x00dev, PHY_CSR3, &reg);
104 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
105 break;
106 udelay(REGISTER_BUSY_DELAY);
107 }
108
109 return reg;
110}
111
112static void rt73usb_bbp_write(const struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, const u8 value)
114{
115 u32 reg;
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt73usb_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
122 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
123 return;
124 }
125
126 /*
127 * Write the data into the BBP.
128 */
129 reg = 0;
130 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
131 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
132 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
133 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
134
135 rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
136}
137
138static void rt73usb_bbp_read(const struct rt2x00_dev *rt2x00dev,
139 const unsigned int word, u8 *value)
140{
141 u32 reg;
142
143 /*
144 * Wait until the BBP becomes ready.
145 */
146 reg = rt73usb_bbp_check(rt2x00dev);
147 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
148 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
149 return;
150 }
151
152 /*
153 * Write the request into the BBP.
154 */
155 reg = 0;
156 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
157 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
158 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
159
160 rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
161
162 /*
163 * Wait until the BBP becomes ready.
164 */
165 reg = rt73usb_bbp_check(rt2x00dev);
166 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
167 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
168 *value = 0xff;
169 return;
170 }
171
172 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
173}
174
175static void rt73usb_rf_write(const struct rt2x00_dev *rt2x00dev,
176 const unsigned int word, const u32 value)
177{
178 u32 reg;
179 unsigned int i;
180
181 if (!word)
182 return;
183
184 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
185 rt73usb_register_read(rt2x00dev, PHY_CSR4, &reg);
186 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
187 goto rf_write;
188 udelay(REGISTER_BUSY_DELAY);
189 }
190
191 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
192 return;
193
194rf_write:
195 reg = 0;
196 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
197
4f5af6eb
ID		 198 /*
199 * RF5225 and RF2527 contain 21 bits per RF register value,
200 * all others contain 20 bits.
201 */
202 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
203 20 + !!(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
204 rt2x00_rf(&rt2x00dev->chip, RF2527)));
95ea3627
ID		 205 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
206 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
207
208 rt73usb_register_write(rt2x00dev, PHY_CSR4, reg);
209 rt2x00_rf_write(rt2x00dev, word, value);
210}
211
212#ifdef CONFIG_RT2X00_LIB_DEBUGFS
213#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
214
215static void rt73usb_read_csr(const struct rt2x00_dev *rt2x00dev,
216 const unsigned int word, u32 *data)
217{
218 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
219}
220
221static void rt73usb_write_csr(const struct rt2x00_dev *rt2x00dev,
222 const unsigned int word, u32 data)
223{
224 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
225}
226
227static const struct rt2x00debug rt73usb_rt2x00debug = {
228 .owner = THIS_MODULE,
229 .csr = {
230 .read = rt73usb_read_csr,
231 .write = rt73usb_write_csr,
232 .word_size = sizeof(u32),
233 .word_count = CSR_REG_SIZE / sizeof(u32),
234 },
235 .eeprom = {
236 .read = rt2x00_eeprom_read,
237 .write = rt2x00_eeprom_write,
238 .word_size = sizeof(u16),
239 .word_count = EEPROM_SIZE / sizeof(u16),
240 },
241 .bbp = {
242 .read = rt73usb_bbp_read,
243 .write = rt73usb_bbp_write,
244 .word_size = sizeof(u8),
245 .word_count = BBP_SIZE / sizeof(u8),
246 },
247 .rf = {
248 .read = rt2x00_rf_read,
249 .write = rt73usb_rf_write,
250 .word_size = sizeof(u32),
251 .word_count = RF_SIZE / sizeof(u32),
252 },
253};
254#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
255
256/*
257 * Configuration handlers.
258 */
4abee4bb 259static void rt73usb_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
95ea3627 260{
95ea3627
ID		 261 u32 tmp;
262
4abee4bb 263 tmp = le32_to_cpu(mac[1]);
95ea3627 264 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
4abee4bb 265 mac[1] = cpu_to_le32(tmp);
95ea3627 266
4abee4bb
ID		 267 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
268 (2 * sizeof(__le32)));
95ea3627
ID		 269}
270
4abee4bb 271static void rt73usb_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
95ea3627 272{
95ea3627
ID		 273 u32 tmp;
274
4abee4bb 275 tmp = le32_to_cpu(bssid[1]);
95ea3627 276 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
4abee4bb 277 bssid[1] = cpu_to_le32(tmp);
95ea3627 278
4abee4bb
ID		 279 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
280 (2 * sizeof(__le32)));
95ea3627
ID		 281}
282
feb24691
ID		 283static void rt73usb_config_type(struct rt2x00_dev *rt2x00dev, const int type,
284 const int tsf_sync)
95ea3627
ID		 285{
286 u32 reg;
287
288 /*
289 * Clear current synchronisation setup.
290 * For the Beacon base registers we only need to clear
291 * the first byte since that byte contains the VALID and OWNER
292 * bits which (when set to 0) will invalidate the entire beacon.
293 */
294 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
295 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
296 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
297 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
298 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
299
95ea3627
ID		 300 /*
301 * Enable synchronisation.
302 */
303 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
4150c572
JB		 304 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
305 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627 306 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
feb24691 307 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
95ea3627
ID		 308 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
309}
310
5c58ee51
ID		 311static void rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
312 const int short_preamble,
313 const int ack_timeout,
314 const int ack_consume_time)
95ea3627 315{
95ea3627 316 u32 reg;
95ea3627 317
5c58ee51
ID		 318 /*
319 * When in atomic context, reschedule and let rt2x00lib
320 * call this function again.
321 */
322 if (in_atomic()) {
323 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->config_work);
324 return;
325 }
95ea3627
ID		 326
327 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
5c58ee51 328 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
95ea3627
ID		 329 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
330
331 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 332 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
5c58ee51 333 !!short_preamble);
95ea3627
ID		 334 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
335}
336
337static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 338 const int basic_rate_mask)
95ea3627 339{
5c58ee51 340 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 341}
342
5c58ee51
ID		 343static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
344 struct rf_channel *rf, const int txpower)
95ea3627
ID		 345{
346 u8 r3;
347 u8 r94;
348 u8 smart;
349
350 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
351 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
352
353 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
354 rt2x00_rf(&rt2x00dev->chip, RF2527));
355
356 rt73usb_bbp_read(rt2x00dev, 3, &r3);
357 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
358 rt73usb_bbp_write(rt2x00dev, 3, r3);
359
360 r94 = 6;
361 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
362 r94 += txpower - MAX_TXPOWER;
363 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
364 r94 += txpower;
365 rt73usb_bbp_write(rt2x00dev, 94, r94);
366
367 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
368 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
369 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
370 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
371
372 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
373 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
374 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
375 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
376
377 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
378 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
379 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
380 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
381
382 udelay(10);
383}
384
95ea3627
ID		 385static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
386 const int txpower)
387{
388 struct rf_channel rf;
389
390 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
391 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
392 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
393 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
394
5c58ee51 395 rt73usb_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 396}
397
398static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
399 const int antenna_tx,
400 const int antenna_rx)
401{
402 u8 r3;
403 u8 r4;
404 u8 r77;
405
406 rt73usb_bbp_read(rt2x00dev, 3, &r3);
407 rt73usb_bbp_read(rt2x00dev, 4, &r4);
408 rt73usb_bbp_read(rt2x00dev, 77, &r77);
409
410 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
411
412 switch (antenna_rx) {
413 case ANTENNA_SW_DIVERSITY:
414 case ANTENNA_HW_DIVERSITY:
415 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
416 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
417 !!(rt2x00dev->curr_hwmode != HWMODE_A));
418 break;
419 case ANTENNA_A:
420 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
421 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
422
423 if (rt2x00dev->curr_hwmode == HWMODE_A)
424 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
425 else
426 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
427 break;
428 case ANTENNA_B:
429 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
430 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
431
432 if (rt2x00dev->curr_hwmode == HWMODE_A)
433 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
434 else
435 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
436 break;
437 }
438
439 rt73usb_bbp_write(rt2x00dev, 77, r77);
440 rt73usb_bbp_write(rt2x00dev, 3, r3);
441 rt73usb_bbp_write(rt2x00dev, 4, r4);
442}
443
444static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
445 const int antenna_tx,
446 const int antenna_rx)
447{
448 u8 r3;
449 u8 r4;
450 u8 r77;
451
452 rt73usb_bbp_read(rt2x00dev, 3, &r3);
453 rt73usb_bbp_read(rt2x00dev, 4, &r4);
454 rt73usb_bbp_read(rt2x00dev, 77, &r77);
455
456 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
457 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
458 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
459
460 switch (antenna_rx) {
461 case ANTENNA_SW_DIVERSITY:
462 case ANTENNA_HW_DIVERSITY:
463 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
464 break;
465 case ANTENNA_A:
466 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
467 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
468 break;
469 case ANTENNA_B:
470 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
471 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
472 break;
473 }
474
475 rt73usb_bbp_write(rt2x00dev, 77, r77);
476 rt73usb_bbp_write(rt2x00dev, 3, r3);
477 rt73usb_bbp_write(rt2x00dev, 4, r4);
478}
479
480struct antenna_sel {
481 u8 word;
482 /*
483 * value[0] -> non-LNA
484 * value[1] -> LNA
485 */
486 u8 value[2];
487};
488
489static const struct antenna_sel antenna_sel_a[] = {
490 { 96, { 0x58, 0x78 } },
491 { 104, { 0x38, 0x48 } },
492 { 75, { 0xfe, 0x80 } },
493 { 86, { 0xfe, 0x80 } },
494 { 88, { 0xfe, 0x80 } },
495 { 35, { 0x60, 0x60 } },
496 { 97, { 0x58, 0x58 } },
497 { 98, { 0x58, 0x58 } },
498};
499
500static const struct antenna_sel antenna_sel_bg[] = {
501 { 96, { 0x48, 0x68 } },
502 { 104, { 0x2c, 0x3c } },
503 { 75, { 0xfe, 0x80 } },
504 { 86, { 0xfe, 0x80 } },
505 { 88, { 0xfe, 0x80 } },
506 { 35, { 0x50, 0x50 } },
507 { 97, { 0x48, 0x48 } },
508 { 98, { 0x48, 0x48 } },
509};
510
511static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
512 const int antenna_tx, const int antenna_rx)
513{
514 const struct antenna_sel *sel;
515 unsigned int lna;
516 unsigned int i;
517 u32 reg;
518
519 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
520
521 if (rt2x00dev->curr_hwmode == HWMODE_A) {
522 sel = antenna_sel_a;
523 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
524
525 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 0);
526 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 1);
527 } else {
528 sel = antenna_sel_bg;
529 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
530
531 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 1);
532 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 0);
533 }
534
535 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
536 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
537
538 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
539
540 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
541 rt2x00_rf(&rt2x00dev->chip, RF5225))
542 rt73usb_config_antenna_5x(rt2x00dev, antenna_tx, antenna_rx);
543 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
544 rt2x00_rf(&rt2x00dev->chip, RF2527))
545 rt73usb_config_antenna_2x(rt2x00dev, antenna_tx, antenna_rx);
546}
547
548static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 549 struct rt2x00lib_conf *libconf)
95ea3627
ID		 550{
551 u32 reg;
552
553 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 554 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 555 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
556
557 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 558 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 559 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 560 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 561 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
562
563 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
564 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
565 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
566
567 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
568 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
569 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
570
571 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 572 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
573 libconf->conf->beacon_int * 16);
95ea3627
ID		 574 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
575}
576
577static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
578 const unsigned int flags,
5c58ee51 579 struct rt2x00lib_conf *libconf)
95ea3627 580{
95ea3627 581 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 582 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 583 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 584 rt73usb_config_channel(rt2x00dev, &libconf->rf,
585 libconf->conf->power_level);
95ea3627 586 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 587 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 588 if (flags & CONFIG_UPDATE_ANTENNA)
5c58ee51
ID		 589 rt73usb_config_antenna(rt2x00dev, libconf->conf->antenna_sel_tx,
590 libconf->conf->antenna_sel_rx);
95ea3627 591 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 592 rt73usb_config_duration(rt2x00dev, libconf);
95ea3627
ID		 593}
594
595/*
596 * LED functions.
597 */
598static void rt73usb_enable_led(struct rt2x00_dev *rt2x00dev)
599{
600 u32 reg;
601
602 rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg);
603 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
604 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
605 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
606
607 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
608 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
609 rt2x00_set_field16(&rt2x00dev->led_reg,
610 MCU_LEDCS_LINK_A_STATUS, 1);
611 else
612 rt2x00_set_field16(&rt2x00dev->led_reg,
613 MCU_LEDCS_LINK_BG_STATUS, 1);
614
615 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
616 rt2x00dev->led_reg, REGISTER_TIMEOUT);
617}
618
619static void rt73usb_disable_led(struct rt2x00_dev *rt2x00dev)
620{
621 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 0);
622 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
623 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
624
625 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
626 rt2x00dev->led_reg, REGISTER_TIMEOUT);
627}
628
629static void rt73usb_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
630{
631 u32 led;
632
633 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
634 return;
635
636 /*
637 * Led handling requires a positive value for the rssi,
638 * to do that correctly we need to add the correction.
639 */
640 rssi += rt2x00dev->rssi_offset;
641
642 if (rssi <= 30)
643 led = 0;
644 else if (rssi <= 39)
645 led = 1;
646 else if (rssi <= 49)
647 led = 2;
648 else if (rssi <= 53)
649 led = 3;
650 else if (rssi <= 63)
651 led = 4;
652 else
653 led = 5;
654
655 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, led,
656 rt2x00dev->led_reg, REGISTER_TIMEOUT);
657}
658
659/*
660 * Link tuning
661 */
662static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev)
663{
664 u32 reg;
665
666 /*
667 * Update FCS error count from register.
668 */
669 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
670 rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
671
672 /*
673 * Update False CCA count from register.
674 */
675 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
676 reg = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
677 rt2x00dev->link.false_cca =
678 rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
679}
680
681static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
682{
683 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
684 rt2x00dev->link.vgc_level = 0x20;
685}
686
687static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
688{
689 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
690 u8 r17;
691 u8 up_bound;
692 u8 low_bound;
693
694 /*
695 * Update Led strength
696 */
697 rt73usb_activity_led(rt2x00dev, rssi);
698
699 rt73usb_bbp_read(rt2x00dev, 17, &r17);
700
701 /*
702 * Determine r17 bounds.
703 */
704 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
705 low_bound = 0x28;
706 up_bound = 0x48;
707
708 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
709 low_bound += 0x10;
710 up_bound += 0x10;
711 }
712 } else {
713 if (rssi > -82) {
714 low_bound = 0x1c;
715 up_bound = 0x40;
716 } else if (rssi > -84) {
717 low_bound = 0x1c;
718 up_bound = 0x20;
719 } else {
720 low_bound = 0x1c;
721 up_bound = 0x1c;
722 }
723
724 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
725 low_bound += 0x14;
726 up_bound += 0x10;
727 }
728 }
729
730 /*
731 * Special big-R17 for very short distance
732 */
733 if (rssi > -35) {
734 if (r17 != 0x60)
735 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
736 return;
737 }
738
739 /*
740 * Special big-R17 for short distance
741 */
742 if (rssi >= -58) {
743 if (r17 != up_bound)
744 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
745 return;
746 }
747
748 /*
749 * Special big-R17 for middle-short distance
750 */
751 if (rssi >= -66) {
752 low_bound += 0x10;
753 if (r17 != low_bound)
754 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
755 return;
756 }
757
758 /*
759 * Special mid-R17 for middle distance
760 */
761 if (rssi >= -74) {
762 if (r17 != (low_bound + 0x10))
763 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
764 return;
765 }
766
767 /*
768 * Special case: Change up_bound based on the rssi.
769 * Lower up_bound when rssi is weaker then -74 dBm.
770 */
771 up_bound -= 2 * (-74 - rssi);
772 if (low_bound > up_bound)
773 up_bound = low_bound;
774
775 if (r17 > up_bound) {
776 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
777 return;
778 }
779
780 /*
781 * r17 does not yet exceed upper limit, continue and base
782 * the r17 tuning on the false CCA count.
783 */
784 if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
785 r17 += 4;
786 if (r17 > up_bound)
787 r17 = up_bound;
788 rt73usb_bbp_write(rt2x00dev, 17, r17);
789 } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
790 r17 -= 4;
791 if (r17 < low_bound)
792 r17 = low_bound;
793 rt73usb_bbp_write(rt2x00dev, 17, r17);
794 }
795}
796
797/*
798 * Firmware name function.
799 */
800static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
801{
802 return FIRMWARE_RT2571;
803}
804
805/*
806 * Initialization functions.
807 */
808static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
809 const size_t len)
810{
811 unsigned int i;
812 int status;
813 u32 reg;
814 char *ptr = data;
815 char *cache;
816 int buflen;
817 int timeout;
818
819 /*
820 * Wait for stable hardware.
821 */
822 for (i = 0; i < 100; i++) {
823 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
824 if (reg)
825 break;
826 msleep(1);
827 }
828
829 if (!reg) {
830 ERROR(rt2x00dev, "Unstable hardware.\n");
831 return -EBUSY;
832 }
833
834 /*
835 * Write firmware to device.
836 * We setup a seperate cache for this action,
837 * since we are going to write larger chunks of data
838 * then normally used cache size.
839 */
840 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
841 if (!cache) {
842 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
843 return -ENOMEM;
844 }
845
846 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
847 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
848 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
849
850 memcpy(cache, ptr, buflen);
851
852 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
853 USB_VENDOR_REQUEST_OUT,
854 FIRMWARE_IMAGE_BASE + i, 0x0000,
855 cache, buflen, timeout);
856
857 ptr += buflen;
858 }
859
860 kfree(cache);
861
862 /*
863 * Send firmware request to device to load firmware,
864 * we need to specify a long timeout time.
865 */
866 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
867 0x0000, USB_MODE_FIRMWARE,
868 REGISTER_TIMEOUT_FIRMWARE);
869 if (status < 0) {
870 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
871 return status;
872 }
873
874 rt73usb_disable_led(rt2x00dev);
875
876 return 0;
877}
878
879static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
880{
881 u32 reg;
882
883 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
884 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
885 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
886 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
887 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
888
889 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
890 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
891 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
892 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
893 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
894 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
895 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
896 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
897 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
898 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
899
900 /*
901 * CCK TXD BBP registers
902 */
903 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
904 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
905 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
906 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
907 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
908 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
909 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
910 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
911 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
912 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
913
914 /*
915 * OFDM TXD BBP registers
916 */
917 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
918 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
919 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
920 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
921 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
922 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
923 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
924 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
925
926 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
927 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
928 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
929 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
930 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
931 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
932
933 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
934 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
935 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
936 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
937 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
938 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
939
940 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
941
942 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
943 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
944 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
945
946 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
947
948 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
949 return -EBUSY;
950
951 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
952
953 /*
954 * Invalidate all Shared Keys (SEC_CSR0),
955 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
956 */
957 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
958 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
959 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
960
961 reg = 0x000023b0;
962 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
963 rt2x00_rf(&rt2x00dev->chip, RF2527))
964 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
965 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
966
967 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
968 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
969 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
970
971 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
972 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
973 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
974 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
975
976 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
977 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
978 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
979 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
980
981 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
982 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
983 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
984
985 /*
986 * We must clear the error counters.
987 * These registers are cleared on read,
988 * so we may pass a useless variable to store the value.
989 */
990 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
991 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
992 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
993
994 /*
995 * Reset MAC and BBP registers.
996 */
997 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
998 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
999 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1000 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1001
1002 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1003 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1004 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1005 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1006
1007 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1008 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1009 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1010
1011 return 0;
1012}
1013
1014static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1015{
1016 unsigned int i;
1017 u16 eeprom;
1018 u8 reg_id;
1019 u8 value;
1020
1021 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1022 rt73usb_bbp_read(rt2x00dev, 0, &value);
1023 if ((value != 0xff) && (value != 0x00))
1024 goto continue_csr_init;
1025 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1026 udelay(REGISTER_BUSY_DELAY);
1027 }
1028
1029 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1030 return -EACCES;
1031
1032continue_csr_init:
1033 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1034 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1035 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1036 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1037 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1038 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1039 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1040 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1041 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1042 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1043 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1044 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1045 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1046 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1047 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1048 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1049 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1050 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1051 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1052 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1053 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1054 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1055 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1056 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1057 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1058
1059 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1060 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1061 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1062
1063 if (eeprom != 0xffff && eeprom != 0x0000) {
1064 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1065 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1066 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1067 reg_id, value);
1068 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1069 }
1070 }
1071 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1072
1073 return 0;
1074}
1075
1076/*
1077 * Device state switch handlers.
1078 */
1079static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1080 enum dev_state state)
1081{
1082 u32 reg;
1083
1084 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1085 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1086 state == STATE_RADIO_RX_OFF);
1087 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1088}
1089
1090static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1091{
1092 /*
1093 * Initialize all registers.
1094 */
1095 if (rt73usb_init_registers(rt2x00dev) ||
1096 rt73usb_init_bbp(rt2x00dev)) {
1097 ERROR(rt2x00dev, "Register initialization failed.\n");
1098 return -EIO;
1099 }
1100
1101 rt2x00usb_enable_radio(rt2x00dev);
1102
1103 /*
1104 * Enable LED
1105 */
1106 rt73usb_enable_led(rt2x00dev);
1107
1108 return 0;
1109}
1110
1111static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1112{
1113 /*
1114 * Disable LED
1115 */
1116 rt73usb_disable_led(rt2x00dev);
1117
1118 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1119
1120 /*
1121 * Disable synchronisation.
1122 */
1123 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1124
1125 rt2x00usb_disable_radio(rt2x00dev);
1126}
1127
1128static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1129{
1130 u32 reg;
1131 unsigned int i;
1132 char put_to_sleep;
1133 char current_state;
1134
1135 put_to_sleep = (state != STATE_AWAKE);
1136
1137 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1138 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1139 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1140 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1141
1142 /*
1143 * Device is not guaranteed to be in the requested state yet.
1144 * We must wait until the register indicates that the
1145 * device has entered the correct state.
1146 */
1147 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1148 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1149 current_state =
1150 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1151 if (current_state == !put_to_sleep)
1152 return 0;
1153 msleep(10);
1154 }
1155
1156 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1157 "current device state %d.\n", !put_to_sleep, current_state);
1158
1159 return -EBUSY;
1160}
1161
1162static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1163 enum dev_state state)
1164{
1165 int retval = 0;
1166
1167 switch (state) {
1168 case STATE_RADIO_ON:
1169 retval = rt73usb_enable_radio(rt2x00dev);
1170 break;
1171 case STATE_RADIO_OFF:
1172 rt73usb_disable_radio(rt2x00dev);
1173 break;
1174 case STATE_RADIO_RX_ON:
1175 case STATE_RADIO_RX_OFF:
1176 rt73usb_toggle_rx(rt2x00dev, state);
1177 break;
1178 case STATE_DEEP_SLEEP:
1179 case STATE_SLEEP:
1180 case STATE_STANDBY:
1181 case STATE_AWAKE:
1182 retval = rt73usb_set_state(rt2x00dev, state);
1183 break;
1184 default:
1185 retval = -ENOTSUPP;
1186 break;
1187 }
1188
1189 return retval;
1190}
1191
1192/*
1193 * TX descriptor initialization
1194 */
1195static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1196 struct data_desc *txd,
4150c572 1197 struct txdata_entry_desc *desc,
95ea3627
ID		 1198 struct ieee80211_hdr *ieee80211hdr,
1199 unsigned int length,
1200 struct ieee80211_tx_control *control)
1201{
1202 u32 word;
1203
1204 /*
1205 * Start writing the descriptor words.
1206 */
1207 rt2x00_desc_read(txd, 1, &word);
1208 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1209 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1210 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1211 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1212 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1213 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1214 rt2x00_desc_write(txd, 1, word);
1215
1216 rt2x00_desc_read(txd, 2, &word);
1217 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1218 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1219 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1220 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1221 rt2x00_desc_write(txd, 2, word);
1222
1223 rt2x00_desc_read(txd, 5, &word);
1224 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1225 TXPOWER_TO_DEV(control->power_level));
1226 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1227 rt2x00_desc_write(txd, 5, word);
1228
1229 rt2x00_desc_read(txd, 0, &word);
1230 rt2x00_set_field32(&word, TXD_W0_BURST,
1231 test_bit(ENTRY_TXD_BURST, &desc->flags));
1232 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1233 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1234 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1235 rt2x00_set_field32(&word, TXD_W0_ACK,
1236 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1237 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1238 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1239 rt2x00_set_field32(&word, TXD_W0_OFDM,
1240 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1241 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1242 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1243 !!(control->flags &
1244 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1245 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1246 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1247 rt2x00_set_field32(&word, TXD_W0_BURST2,
1248 test_bit(ENTRY_TXD_BURST, &desc->flags));
1249 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1250 rt2x00_desc_write(txd, 0, word);
1251}
1252
dd9fa2d2
ID		 1253static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1254 int maxpacket, struct sk_buff *skb)
1255{
1256 int length;
1257
1258 /*
1259 * The length _must_ be a multiple of 4,
1260 * but it must _not_ be a multiple of the USB packet size.
1261 */
1262 length = roundup(skb->len, 4);
1263 length += (4 * !(length % maxpacket));
1264
1265 return length;
1266}
1267
95ea3627
ID		 1268/*
1269 * TX data initialization
1270 */
1271static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1272 unsigned int queue)
1273{
1274 u32 reg;
1275
1276 if (queue != IEEE80211_TX_QUEUE_BEACON)
1277 return;
1278
1279 /*
1280 * For Wi-Fi faily generated beacons between participating stations.
1281 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1282 */
1283 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1284
1285 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1286 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1287 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1288 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1289 }
1290}
1291
1292/*
1293 * RX control handlers
1294 */
1295static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1296{
1297 u16 eeprom;
1298 u8 offset;
1299 u8 lna;
1300
1301 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1302 switch (lna) {
1303 case 3:
1304 offset = 90;
1305 break;
1306 case 2:
1307 offset = 74;
1308 break;
1309 case 1:
1310 offset = 64;
1311 break;
1312 default:
1313 return 0;
1314 }
1315
1316 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1317 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1318 if (lna == 3 || lna == 2)
1319 offset += 10;
1320 } else {
1321 if (lna == 3)
1322 offset += 6;
1323 else if (lna == 2)
1324 offset += 8;
1325 }
1326
1327 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1328 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1329 } else {
1330 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1331 offset += 14;
1332
1333 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1334 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1335 }
1336
1337 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1338}
1339
4150c572
JB		 1340static void rt73usb_fill_rxdone(struct data_entry *entry,
1341 struct rxdata_entry_desc *desc)
95ea3627
ID		 1342{
1343 struct data_desc *rxd = (struct data_desc *)entry->skb->data;
1344 u32 word0;
1345 u32 word1;
1346
1347 rt2x00_desc_read(rxd, 0, &word0);
1348 rt2x00_desc_read(rxd, 1, &word1);
1349
4150c572
JB		 1350 desc->flags = 0;
1351 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1352 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1353
1354 /*
1355 * Obtain the status about this packet.
1356 */
4150c572
JB		 1357 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1358 desc->rssi = rt73usb_agc_to_rssi(entry->ring->rt2x00dev, word1);
1359 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1360 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
95ea3627
ID		 1361
1362 /*
1363 * Pull the skb to clear the descriptor area.
1364 */
1365 skb_pull(entry->skb, entry->ring->desc_size);
1366
4150c572 1367 return;
95ea3627
ID		 1368}
1369
1370/*
1371 * Device probe functions.
1372 */
1373static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1374{
1375 u16 word;
1376 u8 *mac;
1377 s8 value;
1378
1379 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1380
1381 /*
1382 * Start validation of the data that has been read.
1383 */
1384 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1385 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1386 DECLARE_MAC_BUF(macbuf);
1387
95ea3627 1388 random_ether_addr(mac);
0795af57 1389 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1390 }
1391
1392 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1393 if (word == 0xffff) {
1394 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1395 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2);
1396 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2);
1397 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1398 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1399 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1400 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1401 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1402 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1403 }
1404
1405 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1406 if (word == 0xffff) {
1407 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1408 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1409 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1410 }
1411
1412 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1413 if (word == 0xffff) {
1414 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1415 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1416 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1417 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1418 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1419 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1420 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1421 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1422 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1423 LED_MODE_DEFAULT);
1424 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1425 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1426 }
1427
1428 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1429 if (word == 0xffff) {
1430 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1431 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1432 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1433 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1434 }
1435
1436 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1437 if (word == 0xffff) {
1438 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1439 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1440 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1441 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1442 } else {
1443 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1444 if (value < -10 || value > 10)
1445 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1446 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1447 if (value < -10 || value > 10)
1448 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1449 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1450 }
1451
1452 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1453 if (word == 0xffff) {
1454 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1455 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1456 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1457 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1458 } else {
1459 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1460 if (value < -10 || value > 10)
1461 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1462 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1463 if (value < -10 || value > 10)
1464 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1465 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1466 }
1467
1468 return 0;
1469}
1470
1471static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1472{
1473 u32 reg;
1474 u16 value;
1475 u16 eeprom;
1476
1477 /*
1478 * Read EEPROM word for configuration.
1479 */
1480 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1481
1482 /*
1483 * Identify RF chipset.
1484 */
1485 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1486 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1487 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1488
1489 if (!rt2x00_rev(&rt2x00dev->chip, 0x25730)) {
1490 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1491 return -ENODEV;
1492 }
1493
1494 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1495 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1496 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1497 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1498 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1499 return -ENODEV;
1500 }
1501
1502 /*
1503 * Identify default antenna configuration.
1504 */
1505 rt2x00dev->hw->conf.antenna_sel_tx =
1506 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1507 rt2x00dev->hw->conf.antenna_sel_rx =
1508 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1509
1510 /*
1511 * Read the Frame type.
1512 */
1513 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1514 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1515
1516 /*
1517 * Read frequency offset.
1518 */
1519 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1520 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1521
1522 /*
1523 * Read external LNA informations.
1524 */
1525 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1526
1527 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1528 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1529 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1530 }
1531
1532 /*
1533 * Store led settings, for correct led behaviour.
1534 */
1535 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1536
1537 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
1538 rt2x00dev->led_mode);
1539 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
1540 rt2x00_get_field16(eeprom,
1541 EEPROM_LED_POLARITY_GPIO_0));
1542 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
1543 rt2x00_get_field16(eeprom,
1544 EEPROM_LED_POLARITY_GPIO_1));
1545 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
1546 rt2x00_get_field16(eeprom,
1547 EEPROM_LED_POLARITY_GPIO_2));
1548 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
1549 rt2x00_get_field16(eeprom,
1550 EEPROM_LED_POLARITY_GPIO_3));
1551 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
1552 rt2x00_get_field16(eeprom,
1553 EEPROM_LED_POLARITY_GPIO_4));
1554 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
1555 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1556 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
1557 rt2x00_get_field16(eeprom,
1558 EEPROM_LED_POLARITY_RDY_G));
1559 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
1560 rt2x00_get_field16(eeprom,
1561 EEPROM_LED_POLARITY_RDY_A));
1562
1563 return 0;
1564}
1565
1566/*
1567 * RF value list for RF2528
1568 * Supports: 2.4 GHz
1569 */
1570static const struct rf_channel rf_vals_bg_2528[] = {
1571 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1572 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1573 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1574 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1575 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1576 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1577 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1578 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1579 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1580 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1581 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1582 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1583 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1584 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1585};
1586
1587/*
1588 * RF value list for RF5226
1589 * Supports: 2.4 GHz & 5.2 GHz
1590 */
1591static const struct rf_channel rf_vals_5226[] = {
1592 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1593 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1594 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1595 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1596 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1597 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1598 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1599 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1600 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1601 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1602 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1603 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1604 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1605 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1606
1607 /* 802.11 UNI / HyperLan 2 */
1608 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1609 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1610 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1611 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1612 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1613 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1614 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1615 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1616
1617 /* 802.11 HyperLan 2 */
1618 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1619 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1620 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1621 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1622 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1623 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1624 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1625 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1626 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1627 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1628
1629 /* 802.11 UNII */
1630 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1631 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1632 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1633 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1634 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1635 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1636
1637 /* MMAC(Japan)J52 ch 34,38,42,46 */
1638 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1639 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1640 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1641 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1642};
1643
1644/*
1645 * RF value list for RF5225 & RF2527
1646 * Supports: 2.4 GHz & 5.2 GHz
1647 */
1648static const struct rf_channel rf_vals_5225_2527[] = {
1649 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1650 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1651 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1652 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1653 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1654 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1655 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1656 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1657 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1658 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1659 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1660 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1661 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1662 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1663
1664 /* 802.11 UNI / HyperLan 2 */
1665 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1666 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1667 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1668 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1669 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1670 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1671 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1672 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1673
1674 /* 802.11 HyperLan 2 */
1675 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1676 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1677 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1678 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1679 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1680 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1681 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1682 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1683 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1684 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1685
1686 /* 802.11 UNII */
1687 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1688 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1689 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1690 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1691 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1692 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1693
1694 /* MMAC(Japan)J52 ch 34,38,42,46 */
1695 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1696 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1697 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1698 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1699};
1700
1701
1702static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1703{
1704 struct hw_mode_spec *spec = &rt2x00dev->spec;
1705 u8 *txpower;
1706 unsigned int i;
1707
1708 /*
1709 * Initialize all hw fields.
1710 */
1711 rt2x00dev->hw->flags =
1712 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 1713 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1714 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1715 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1716 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1717 rt2x00dev->hw->queues = 5;
1718
1719 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1720 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1721 rt2x00_eeprom_addr(rt2x00dev,
1722 EEPROM_MAC_ADDR_0));
1723
1724 /*
1725 * Convert tx_power array in eeprom.
1726 */
1727 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1728 for (i = 0; i < 14; i++)
1729 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1730
1731 /*
1732 * Initialize hw_mode information.
1733 */
1734 spec->num_modes = 2;
1735 spec->num_rates = 12;
1736 spec->tx_power_a = NULL;
1737 spec->tx_power_bg = txpower;
1738 spec->tx_power_default = DEFAULT_TXPOWER;
1739
1740 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1741 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1742 spec->channels = rf_vals_bg_2528;
1743 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1744 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1745 spec->channels = rf_vals_5226;
1746 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1747 spec->num_channels = 14;
1748 spec->channels = rf_vals_5225_2527;
1749 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1750 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1751 spec->channels = rf_vals_5225_2527;
1752 }
1753
1754 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1755 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1756 spec->num_modes = 3;
1757
1758 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1759 for (i = 0; i < 14; i++)
1760 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1761
1762 spec->tx_power_a = txpower;
1763 }
1764}
1765
1766static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1767{
1768 int retval;
1769
1770 /*
1771 * Allocate eeprom data.
1772 */
1773 retval = rt73usb_validate_eeprom(rt2x00dev);
1774 if (retval)
1775 return retval;
1776
1777 retval = rt73usb_init_eeprom(rt2x00dev);
1778 if (retval)
1779 return retval;
1780
1781 /*
1782 * Initialize hw specifications.
1783 */
1784 rt73usb_probe_hw_mode(rt2x00dev);
1785
1786 /*
95ea3627
ID		 1787 * This device requires firmware
1788 */
066cb637 1789 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
95ea3627
ID		 1790
1791 /*
1792 * Set the rssi offset.
1793 */
1794 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1795
1796 return 0;
1797}
1798
1799/*
1800 * IEEE80211 stack callback functions.
1801 */
4150c572
JB		 1802static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1803 unsigned int changed_flags,
1804 unsigned int *total_flags,
1805 int mc_count,
1806 struct dev_addr_list *mc_list)
1807{
1808 struct rt2x00_dev *rt2x00dev = hw->priv;
1809 struct interface *intf = &rt2x00dev->interface;
1810 u32 reg;
1811
1812 /*
1813 * Mask off any flags we are going to ignore from
1814 * the total_flags field.
1815 */
1816 *total_flags &=
1817 FIF_ALLMULTI |
1818 FIF_FCSFAIL |
1819 FIF_PLCPFAIL |
1820 FIF_CONTROL |
1821 FIF_OTHER_BSS |
1822 FIF_PROMISC_IN_BSS;
1823
1824 /*
1825 * Apply some rules to the filters:
1826 * - Some filters imply different filters to be set.
1827 * - Some things we can't filter out at all.
1828 * - Some filters are set based on interface type.
1829 */
1830 if (mc_count)
1831 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1832 if (*total_flags & FIF_OTHER_BSS ||
1833 *total_flags & FIF_PROMISC_IN_BSS)
4150c572
JB		 1834 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1835 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1836 *total_flags |= FIF_PROMISC_IN_BSS;
1837
1838 /*
1839 * Check if there is any work left for us.
1840 */
1841 if (intf->filter == *total_flags)
1842 return;
1843 intf->filter = *total_flags;
1844
1845 /*
1846 * When in atomic context, reschedule and let rt2x00lib
1847 * call this function again.
1848 */
1849 if (in_atomic()) {
1850 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1851 return;
1852 }
1853
1854 /*
1855 * Start configuration steps.
1856 * Note that the version error will always be dropped
1857 * and broadcast frames will always be accepted since
1858 * there is no filter for it at this time.
1859 */
1860 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1861 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
1862 !(*total_flags & FIF_FCSFAIL));
1863 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
1864 !(*total_flags & FIF_PLCPFAIL));
1865 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1866 !(*total_flags & FIF_CONTROL));
1867 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
1868 !(*total_flags & FIF_PROMISC_IN_BSS));
1869 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
1870 !(*total_flags & FIF_PROMISC_IN_BSS));
1871 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1872 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
1873 !(*total_flags & FIF_ALLMULTI));
1874 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
1875 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
1876 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1877}
1878
95ea3627
ID		 1879static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1880 u32 short_retry, u32 long_retry)
1881{
1882 struct rt2x00_dev *rt2x00dev = hw->priv;
1883 u32 reg;
1884
1885 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1886 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1887 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1888 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1889
1890 return 0;
1891}
1892
1893#if 0
1894/*
1895 * Mac80211 demands get_tsf must be atomic.
1896 * This is not possible for rt73usb since all register access
1897 * functions require sleeping. Untill mac80211 no longer needs
1898 * get_tsf to be atomic, this function should be disabled.
1899 */
1900static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1901{
1902 struct rt2x00_dev *rt2x00dev = hw->priv;
1903 u64 tsf;
1904 u32 reg;
1905
1906 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1907 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1908 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1909 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1910
1911 return tsf;
1912}
1913#endif
1914
1915static void rt73usb_reset_tsf(struct ieee80211_hw *hw)
1916{
1917 struct rt2x00_dev *rt2x00dev = hw->priv;
1918
1919 rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0);
1920 rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0);
1921}
1922
24845910 1923static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
95ea3627
ID		 1924 struct ieee80211_tx_control *control)
1925{
1926 struct rt2x00_dev *rt2x00dev = hw->priv;
1927 int timeout;
1928
1929 /*
1930 * Just in case the ieee80211 doesn't set this,
1931 * but we need this queue set for the descriptor
1932 * initialization.
1933 */
1934 control->queue = IEEE80211_TX_QUEUE_BEACON;
1935
1936 /*
1937 * First we create the beacon.
1938 */
1939 skb_push(skb, TXD_DESC_SIZE);
1940 rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
1941 (struct ieee80211_hdr *)(skb->data +
1942 TXD_DESC_SIZE),
1943 skb->len - TXD_DESC_SIZE, control);
1944
1945 /*
1946 * Write entire beacon with descriptor to register,
1947 * and kick the beacon generator.
1948 */
1949 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
1950 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
1951 USB_VENDOR_REQUEST_OUT,
1952 HW_BEACON_BASE0, 0x0000,
1953 skb->data, skb->len, timeout);
1954 rt73usb_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
1955
1956 return 0;
1957}
1958
1959static const struct ieee80211_ops rt73usb_mac80211_ops = {
1960 .tx = rt2x00mac_tx,
4150c572
JB		 1961 .start = rt2x00mac_start,
1962 .stop = rt2x00mac_stop,
95ea3627
ID		 1963 .add_interface = rt2x00mac_add_interface,
1964 .remove_interface = rt2x00mac_remove_interface,
1965 .config = rt2x00mac_config,
1966 .config_interface = rt2x00mac_config_interface,
4150c572 1967 .configure_filter = rt73usb_configure_filter,
95ea3627
ID		 1968 .get_stats = rt2x00mac_get_stats,
1969 .set_retry_limit = rt73usb_set_retry_limit,
5c58ee51 1970 .erp_ie_changed = rt2x00mac_erp_ie_changed,
95ea3627
ID		 1971 .conf_tx = rt2x00mac_conf_tx,
1972 .get_tx_stats = rt2x00mac_get_tx_stats,
1973#if 0
1974/*
1975 * See comment at the rt73usb_get_tsf function.
1976 */
1977 .get_tsf = rt73usb_get_tsf,
1978#endif
1979 .reset_tsf = rt73usb_reset_tsf,
1980 .beacon_update = rt73usb_beacon_update,
1981};
1982
1983static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
1984 .probe_hw = rt73usb_probe_hw,
1985 .get_firmware_name = rt73usb_get_firmware_name,
1986 .load_firmware = rt73usb_load_firmware,
1987 .initialize = rt2x00usb_initialize,
1988 .uninitialize = rt2x00usb_uninitialize,
1989 .set_device_state = rt73usb_set_device_state,
1990 .link_stats = rt73usb_link_stats,
1991 .reset_tuner = rt73usb_reset_tuner,
1992 .link_tuner = rt73usb_link_tuner,
1993 .write_tx_desc = rt73usb_write_tx_desc,
1994 .write_tx_data = rt2x00usb_write_tx_data,
dd9fa2d2 1995 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627
ID		 1996 .kick_tx_queue = rt73usb_kick_tx_queue,
1997 .fill_rxdone = rt73usb_fill_rxdone,
1998 .config_mac_addr = rt73usb_config_mac_addr,
1999 .config_bssid = rt73usb_config_bssid,
95ea3627 2000 .config_type = rt73usb_config_type,
5c58ee51 2001 .config_preamble = rt73usb_config_preamble,
95ea3627
ID		 2002 .config = rt73usb_config,
2003};
2004
2005static const struct rt2x00_ops rt73usb_ops = {
2006 .name = DRV_NAME,
2007 .rxd_size = RXD_DESC_SIZE,
2008 .txd_size = TXD_DESC_SIZE,
2009 .eeprom_size = EEPROM_SIZE,
2010 .rf_size = RF_SIZE,
2011 .lib = &rt73usb_rt2x00_ops,
2012 .hw = &rt73usb_mac80211_ops,
2013#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2014 .debugfs = &rt73usb_rt2x00debug,
2015#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2016};
2017
2018/*
2019 * rt73usb module information.
2020 */
2021static struct usb_device_id rt73usb_device_table[] = {
2022 /* AboCom */
2023 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2024 /* Askey */
2025 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2026 /* ASUS */
2027 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2028 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2029 /* Belkin */
2030 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2031 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2032 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2033 /* Billionton */
2034 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2035 /* Buffalo */
2036 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2037 /* CNet */
2038 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2039 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2040 /* Conceptronic */
2041 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2042 /* D-Link */
2043 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2044 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2045 /* Gemtek */
2046 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2047 /* Gigabyte */
2048 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2049 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2050 /* Huawei-3Com */
2051 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2052 /* Hercules */
2053 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2054 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2055 /* Linksys */
2056 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2057 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2058 /* MSI */
2059 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2060 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2061 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2062 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2063 /* Ralink */
2064 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2065 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2066 /* Qcom */
2067 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2068 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2069 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2070 /* Senao */
2071 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2072 /* Sitecom */
2073 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2074 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2075 /* Surecom */
2076 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2077 /* Planex */
2078 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2079 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2080 { 0, }
2081};
2082
2083MODULE_AUTHOR(DRV_PROJECT);
2084MODULE_VERSION(DRV_VERSION);
2085MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2086MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2087MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2088MODULE_FIRMWARE(FIRMWARE_RT2571);
2089MODULE_LICENSE("GPL");
2090
2091static struct usb_driver rt73usb_driver = {
2092 .name = DRV_NAME,
2093 .id_table = rt73usb_device_table,
2094 .probe = rt2x00usb_probe,
2095 .disconnect = rt2x00usb_disconnect,
2096 .suspend = rt2x00usb_suspend,
2097 .resume = rt2x00usb_resume,
2098};
2099
2100static int __init rt73usb_init(void)
2101{
2102 return usb_register(&rt73usb_driver);
2103}
2104
2105static void __exit rt73usb_exit(void)
2106{
2107 usb_deregister(&rt73usb_driver);
2108}
2109
2110module_init(rt73usb_init);
2111module_exit(rt73usb_exit);
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