]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/net/wireless/rtl8180_dev.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mac80211: dont use interface indices in drivers
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / rtl8180_dev.c
CommitLineData
f6532111
MW		 1
2/*
3 * Linux device driver for RTL8180 / RTL8185
4 *
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
7 *
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
10 *
11 * Thanks to Realtek for their support!
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/pci.h>
20#include <linux/delay.h>
21#include <linux/etherdevice.h>
22#include <linux/eeprom_93cx6.h>
23#include <net/mac80211.h>
24
25#include "rtl8180.h"
26#include "rtl8180_rtl8225.h"
27#include "rtl8180_sa2400.h"
28#include "rtl8180_max2820.h"
29#include "rtl8180_grf5101.h"
30
31MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
32MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
33MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
34MODULE_LICENSE("GPL");
35
36static struct pci_device_id rtl8180_table[] __devinitdata = {
37 /* rtl8185 */
38 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
39 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
40
41 /* rtl8180 */
42 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
43 { PCI_DEVICE(0x1799, 0x6001) },
44 { PCI_DEVICE(0x1799, 0x6020) },
45 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
46 { }
47};
48
49MODULE_DEVICE_TABLE(pci, rtl8180_table);
50
51void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
52{
53 struct rtl8180_priv *priv = dev->priv;
54 int i = 10;
55 u32 buf;
56
57 buf = (data << 8) | addr;
58
59 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
60 while (i--) {
61 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
62 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
63 return;
64 }
65}
66
67static void rtl8180_handle_rx(struct ieee80211_hw *dev)
68{
69 struct rtl8180_priv *priv = dev->priv;
70 unsigned int count = 32;
71
72 while (count--) {
73 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
74 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
75 u32 flags = le32_to_cpu(entry->flags);
76
77 if (flags & RTL8180_RX_DESC_FLAG_OWN)
78 return;
79
80 if (unlikely(flags & (RTL8180_RX_DESC_FLAG_DMA_FAIL |
81 RTL8180_RX_DESC_FLAG_FOF |
82 RTL8180_RX_DESC_FLAG_RX_ERR)))
83 goto done;
84 else {
85 u32 flags2 = le32_to_cpu(entry->flags2);
86 struct ieee80211_rx_status rx_status = {0};
87 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
88
89 if (unlikely(!new_skb))
90 goto done;
91
92 pci_unmap_single(priv->pdev,
93 *((dma_addr_t *)skb->cb),
94 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
95 skb_put(skb, flags & 0xFFF);
96
97 rx_status.antenna = (flags2 >> 15) & 1;
98 /* TODO: improve signal/rssi reporting */
99 rx_status.signal = flags2 & 0xFF;
100 rx_status.ssi = (flags2 >> 8) & 0x7F;
101 rx_status.rate = (flags >> 20) & 0xF;
102 rx_status.freq = dev->conf.freq;
103 rx_status.channel = dev->conf.channel;
104 rx_status.phymode = dev->conf.phymode;
105 rx_status.mactime = le64_to_cpu(entry->tsft);
106 rx_status.flag |= RX_FLAG_TSFT;
107 if (flags & RTL8180_RX_DESC_FLAG_CRC32_ERR)
108 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
109
110 ieee80211_rx_irqsafe(dev, skb, &rx_status);
111
112 skb = new_skb;
113 priv->rx_buf[priv->rx_idx] = skb;
114 *((dma_addr_t *) skb->cb) =
115 pci_map_single(priv->pdev, skb_tail_pointer(skb),
116 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
117 }
118
119 done:
120 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
121 entry->flags = cpu_to_le32(RTL8180_RX_DESC_FLAG_OWN |
122 MAX_RX_SIZE);
123 if (priv->rx_idx == 31)
124 entry->flags |= cpu_to_le32(RTL8180_RX_DESC_FLAG_EOR);
125 priv->rx_idx = (priv->rx_idx + 1) % 32;
126 }
127}
128
129static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
130{
131 struct rtl8180_priv *priv = dev->priv;
132 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
133
134 while (skb_queue_len(&ring->queue)) {
135 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
136 struct sk_buff *skb;
137 struct ieee80211_tx_status status = { {0} };
138 struct ieee80211_tx_control *control;
139 u32 flags = le32_to_cpu(entry->flags);
140
141 if (flags & RTL8180_TX_DESC_FLAG_OWN)
142 return;
143
144 ring->idx = (ring->idx + 1) % ring->entries;
145 skb = __skb_dequeue(&ring->queue);
146 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
147 skb->len, PCI_DMA_TODEVICE);
148
149 control = *((struct ieee80211_tx_control **)skb->cb);
150 if (control)
151 memcpy(&status.control, control, sizeof(*control));
152 kfree(control);
153
154 if (!(status.control.flags & IEEE80211_TXCTL_NO_ACK)) {
155 if (flags & RTL8180_TX_DESC_FLAG_TX_OK)
156 status.flags = IEEE80211_TX_STATUS_ACK;
157 else
158 status.excessive_retries = 1;
159 }
160 status.retry_count = flags & 0xFF;
161
162 ieee80211_tx_status_irqsafe(dev, skb, &status);
163 if (ring->entries - skb_queue_len(&ring->queue) == 2)
164 ieee80211_wake_queue(dev, prio);
165 }
166}
167
168static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
169{
170 struct ieee80211_hw *dev = dev_id;
171 struct rtl8180_priv *priv = dev->priv;
172 u16 reg;
173
174 spin_lock(&priv->lock);
175 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
176 if (unlikely(reg == 0xFFFF)) {
177 spin_unlock(&priv->lock);
178 return IRQ_HANDLED;
179 }
180
181 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
182
183 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
184 rtl8180_handle_tx(dev, 3);
185
186 if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR))
187 rtl8180_handle_tx(dev, 2);
188
189 if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
190 rtl8180_handle_tx(dev, 1);
191
192 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
193 rtl8180_handle_tx(dev, 0);
194
195 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
196 rtl8180_handle_rx(dev);
197
198 spin_unlock(&priv->lock);
199
200 return IRQ_HANDLED;
201}
202
203static int rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
204 struct ieee80211_tx_control *control)
205{
206 struct rtl8180_priv *priv = dev->priv;
207 struct rtl8180_tx_ring *ring;
208 struct rtl8180_tx_desc *entry;
209 unsigned long flags;
210 unsigned int idx, prio;
211 dma_addr_t mapping;
212 u32 tx_flags;
213 u16 plcp_len = 0;
214 __le16 rts_duration = 0;
215
216 prio = control->queue;
217 ring = &priv->tx_ring[prio];
218
219 mapping = pci_map_single(priv->pdev, skb->data,
220 skb->len, PCI_DMA_TODEVICE);
221
222 tx_flags = RTL8180_TX_DESC_FLAG_OWN | RTL8180_TX_DESC_FLAG_FS |
223 RTL8180_TX_DESC_FLAG_LS | (control->tx_rate << 24) |
224 (control->rts_cts_rate << 19) | skb->len;
225
226 if (priv->r8185)
227 tx_flags |= RTL8180_TX_DESC_FLAG_DMA |
228 RTL8180_TX_DESC_FLAG_NO_ENC;
229
230 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
231 tx_flags |= RTL8180_TX_DESC_FLAG_RTS;
232 else if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)
233 tx_flags |= RTL8180_TX_DESC_FLAG_CTS;
234
235 *((struct ieee80211_tx_control **) skb->cb) =
236 kmemdup(control, sizeof(*control), GFP_ATOMIC);
237
238 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
32bfd35d
JB		 239 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
240 control);
f6532111
MW		 241
242 if (!priv->r8185) {
243 unsigned int remainder;
244
245 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
246 (control->rate->rate * 2) / 10);
247 remainder = (16 * (skb->len + 4)) %
248 ((control->rate->rate * 2) / 10);
249 if (remainder > 0 && remainder <= 6)
250 plcp_len |= 1 << 15;
251 }
252
253 spin_lock_irqsave(&priv->lock, flags);
254 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
255 entry = &ring->desc[idx];
256
257 entry->rts_duration = rts_duration;
258 entry->plcp_len = cpu_to_le16(plcp_len);
259 entry->tx_buf = cpu_to_le32(mapping);
260 entry->frame_len = cpu_to_le32(skb->len);
261 entry->flags2 = control->alt_retry_rate != -1 ?
262 control->alt_retry_rate << 4 : 0;
263 entry->retry_limit = control->retry_limit;
264 entry->flags = cpu_to_le32(tx_flags);
265 __skb_queue_tail(&ring->queue, skb);
266 if (ring->entries - skb_queue_len(&ring->queue) < 2)
267 ieee80211_stop_queue(dev, control->queue);
268 spin_unlock_irqrestore(&priv->lock, flags);
269
270 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
271
272 return 0;
273}
274
275void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
276{
277 u8 reg;
278
279 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
280 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
281 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
282 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
283 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
284 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
285 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
286 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
287}
288
289static int rtl8180_init_hw(struct ieee80211_hw *dev)
290{
291 struct rtl8180_priv *priv = dev->priv;
292 u16 reg;
293
294 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
295 rtl818x_ioread8(priv, &priv->map->CMD);
296 msleep(10);
297
298 /* reset */
299 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
300 rtl818x_ioread8(priv, &priv->map->CMD);
301
302 reg = rtl818x_ioread8(priv, &priv->map->CMD);
303 reg &= (1 << 1);
304 reg |= RTL818X_CMD_RESET;
305 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
306 rtl818x_ioread8(priv, &priv->map->CMD);
307 msleep(200);
308
309 /* check success of reset */
310 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
311 printk(KERN_ERR "%s: reset timeout!\n", wiphy_name(dev->wiphy));
312 return -ETIMEDOUT;
313 }
314
315 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
316 rtl818x_ioread8(priv, &priv->map->CMD);
317 msleep(200);
318
319 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
320 /* For cardbus */
321 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
322 reg |= 1 << 1;
323 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
324 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
325 reg |= (1 << 15) | (1 << 14) | (1 << 4);
326 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
327 }
328
329 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
330
331 if (!priv->r8185)
332 rtl8180_set_anaparam(priv, priv->anaparam);
333
334 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
335 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
336 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
337 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
338 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
339
340 /* TODO: necessary? specs indicate not */
341 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
342 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
343 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
344 if (priv->r8185) {
345 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
346 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
347 }
348 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
349
350 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
351
352 /* TODO: turn off hw wep on rtl8180 */
353
354 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
355
356 if (priv->r8185) {
357 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
358 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
359 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
360
361 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
362
363 /* TODO: set ClkRun enable? necessary? */
364 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
365 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
366 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
367 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
368 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
369 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
370 } else {
371 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
372 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
373
374 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
375 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
376 }
377
378 priv->rf->init(dev);
379 if (priv->r8185)
380 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
381 return 0;
382}
383
384static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
385{
386 struct rtl8180_priv *priv = dev->priv;
387 struct rtl8180_rx_desc *entry;
388 int i;
389
390 priv->rx_ring = pci_alloc_consistent(priv->pdev,
391 sizeof(*priv->rx_ring) * 32,
392 &priv->rx_ring_dma);
393
394 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
395 printk(KERN_ERR "%s: Cannot allocate RX ring\n",
396 wiphy_name(dev->wiphy));
397 return -ENOMEM;
398 }
399
400 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
401 priv->rx_idx = 0;
402
403 for (i = 0; i < 32; i++) {
404 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
405 dma_addr_t *mapping;
406 entry = &priv->rx_ring[i];
407 if (!skb)
408 return 0;
409
410 priv->rx_buf[i] = skb;
411 mapping = (dma_addr_t *)skb->cb;
412 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
413 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
414 entry->rx_buf = cpu_to_le32(*mapping);
415 entry->flags = cpu_to_le32(RTL8180_RX_DESC_FLAG_OWN |
416 MAX_RX_SIZE);
417 }
418 entry->flags |= cpu_to_le32(RTL8180_RX_DESC_FLAG_EOR);
419 return 0;
420}
421
422static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
423{
424 struct rtl8180_priv *priv = dev->priv;
425 int i;
426
427 for (i = 0; i < 32; i++) {
428 struct sk_buff *skb = priv->rx_buf[i];
429 if (!skb)
430 continue;
431
432 pci_unmap_single(priv->pdev,
433 *((dma_addr_t *)skb->cb),
434 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
435 kfree_skb(skb);
436 }
437
438 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
439 priv->rx_ring, priv->rx_ring_dma);
440 priv->rx_ring = NULL;
441}
442
443static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
444 unsigned int prio, unsigned int entries)
445{
446 struct rtl8180_priv *priv = dev->priv;
447 struct rtl8180_tx_desc *ring;
448 dma_addr_t dma;
449 int i;
450
451 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
452 if (!ring || (unsigned long)ring & 0xFF) {
453 printk(KERN_ERR "%s: Cannot allocate TX ring (prio = %d)\n",
454 wiphy_name(dev->wiphy), prio);
455 return -ENOMEM;
456 }
457
458 memset(ring, 0, sizeof(*ring)*entries);
459 priv->tx_ring[prio].desc = ring;
460 priv->tx_ring[prio].dma = dma;
461 priv->tx_ring[prio].idx = 0;
462 priv->tx_ring[prio].entries = entries;
463 skb_queue_head_init(&priv->tx_ring[prio].queue);
464
465 for (i = 0; i < entries; i++)
466 ring[i].next_tx_desc =
467 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
468
469 return 0;
470}
471
472static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
473{
474 struct rtl8180_priv *priv = dev->priv;
475 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
476
477 while (skb_queue_len(&ring->queue)) {
478 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
479 struct sk_buff *skb = __skb_dequeue(&ring->queue);
480
481 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
482 skb->len, PCI_DMA_TODEVICE);
483 kfree(*((struct ieee80211_tx_control **) skb->cb));
484 kfree_skb(skb);
485 ring->idx = (ring->idx + 1) % ring->entries;
486 }
487
488 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
489 ring->desc, ring->dma);
490 ring->desc = NULL;
491}
492
493static int rtl8180_start(struct ieee80211_hw *dev)
494{
495 struct rtl8180_priv *priv = dev->priv;
496 int ret, i;
497 u32 reg;
498
499 ret = rtl8180_init_rx_ring(dev);
500 if (ret)
501 return ret;
502
503 for (i = 0; i < 4; i++)
504 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
505 goto err_free_rings;
506
507 ret = rtl8180_init_hw(dev);
508 if (ret)
509 goto err_free_rings;
510
511 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
512 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
513 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
514 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
515 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
516
517 ret = request_irq(priv->pdev->irq, &rtl8180_interrupt,
518 IRQF_SHARED, KBUILD_MODNAME, dev);
519 if (ret) {
520 printk(KERN_ERR "%s: failed to register IRQ handler\n",
521 wiphy_name(dev->wiphy));
522 goto err_free_rings;
523 }
524
525 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
526
527 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
528 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
529
530 reg = RTL818X_RX_CONF_ONLYERLPKT |
531 RTL818X_RX_CONF_RX_AUTORESETPHY |
532 RTL818X_RX_CONF_MGMT |
533 RTL818X_RX_CONF_DATA |
534 (7 << 8 /* MAX RX DMA */) |
535 RTL818X_RX_CONF_BROADCAST |
536 RTL818X_RX_CONF_NICMAC;
537
538 if (priv->r8185)
539 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
540 else {
541 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
542 ? RTL818X_RX_CONF_CSDM1 : 0;
543 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
544 ? RTL818X_RX_CONF_CSDM2 : 0;
545 }
546
547 priv->rx_conf = reg;
548 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
549
550 if (priv->r8185) {
551 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
552 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
553 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
554 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
555
556 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
557 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
558 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
559 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
560 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
561
562 /* disable early TX */
563 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
564 }
565
566 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
567 reg |= (6 << 21 /* MAX TX DMA */) |
568 RTL818X_TX_CONF_NO_ICV;
569
570 if (priv->r8185)
571 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
572 else
573 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
574
575 /* different meaning, same value on both rtl8185 and rtl8180 */
576 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
577
578 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
579
580 reg = rtl818x_ioread8(priv, &priv->map->CMD);
581 reg |= RTL818X_CMD_RX_ENABLE;
582 reg |= RTL818X_CMD_TX_ENABLE;
583 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
584
585 priv->mode = IEEE80211_IF_TYPE_MNTR;
586 return 0;
587
588 err_free_rings:
589 rtl8180_free_rx_ring(dev);
590 for (i = 0; i < 4; i++)
591 if (priv->tx_ring[i].desc)
592 rtl8180_free_tx_ring(dev, i);
593
594 return ret;
595}
596
597static void rtl8180_stop(struct ieee80211_hw *dev)
598{
599 struct rtl8180_priv *priv = dev->priv;
600 u8 reg;
601 int i;
602
603 priv->mode = IEEE80211_IF_TYPE_INVALID;
604
605 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
606
607 reg = rtl818x_ioread8(priv, &priv->map->CMD);
608 reg &= ~RTL818X_CMD_TX_ENABLE;
609 reg &= ~RTL818X_CMD_RX_ENABLE;
610 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
611
612 priv->rf->stop(dev);
613
614 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
615 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
616 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
617 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
618
619 free_irq(priv->pdev->irq, dev);
620
621 rtl8180_free_rx_ring(dev);
622 for (i = 0; i < 4; i++)
623 rtl8180_free_tx_ring(dev, i);
624}
625
626static int rtl8180_add_interface(struct ieee80211_hw *dev,
627 struct ieee80211_if_init_conf *conf)
628{
629 struct rtl8180_priv *priv = dev->priv;
630
631 if (priv->mode != IEEE80211_IF_TYPE_MNTR)
632 return -EOPNOTSUPP;
633
634 switch (conf->type) {
635 case IEEE80211_IF_TYPE_STA:
636 priv->mode = conf->type;
637 break;
638 default:
639 return -EOPNOTSUPP;
640 }
641
32bfd35d
JB		 642 priv->vif = conf->vif;
643
f6532111
MW		 644 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
645 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
646 cpu_to_le32(*(u32 *)conf->mac_addr));
647 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
648 cpu_to_le16(*(u16 *)(conf->mac_addr + 4)));
649 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
650
651 return 0;
652}
653
654static void rtl8180_remove_interface(struct ieee80211_hw *dev,
655 struct ieee80211_if_init_conf *conf)
656{
657 struct rtl8180_priv *priv = dev->priv;
658 priv->mode = IEEE80211_IF_TYPE_MNTR;
32bfd35d 659 priv->vif = NULL;
f6532111
MW		 660}
661
662static int rtl8180_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
663{
664 struct rtl8180_priv *priv = dev->priv;
665
666 priv->rf->set_chan(dev, conf);
667
668 return 0;
669}
670
32bfd35d
JB		 671static int rtl8180_config_interface(struct ieee80211_hw *dev,
672 struct ieee80211_vif *vif,
f6532111
MW		 673 struct ieee80211_if_conf *conf)
674{
675 struct rtl8180_priv *priv = dev->priv;
676 int i;
677
f6532111
MW		 678 for (i = 0; i < ETH_ALEN; i++)
679 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
680
681 if (is_valid_ether_addr(conf->bssid))
682 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_INFRA);
683 else
684 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_NO_LINK);
685
686 return 0;
687}
688
689static void rtl8180_configure_filter(struct ieee80211_hw *dev,
690 unsigned int changed_flags,
691 unsigned int *total_flags,
692 int mc_count, struct dev_addr_list *mclist)
693{
694 struct rtl8180_priv *priv = dev->priv;
695
696 if (changed_flags & FIF_FCSFAIL)
697 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
698 if (changed_flags & FIF_CONTROL)
699 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
700 if (changed_flags & FIF_OTHER_BSS)
701 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
702 if (*total_flags & FIF_ALLMULTI || mc_count > 0)
703 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
704 else
705 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
706
707 *total_flags = 0;
708
709 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
710 *total_flags |= FIF_FCSFAIL;
711 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
712 *total_flags |= FIF_CONTROL;
713 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
714 *total_flags |= FIF_OTHER_BSS;
715 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
716 *total_flags |= FIF_ALLMULTI;
717
718 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
719}
720
721static const struct ieee80211_ops rtl8180_ops = {
722 .tx = rtl8180_tx,
723 .start = rtl8180_start,
724 .stop = rtl8180_stop,
725 .add_interface = rtl8180_add_interface,
726 .remove_interface = rtl8180_remove_interface,
727 .config = rtl8180_config,
728 .config_interface = rtl8180_config_interface,
729 .configure_filter = rtl8180_configure_filter,
730};
731
732static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
733{
734 struct ieee80211_hw *dev = eeprom->data;
735 struct rtl8180_priv *priv = dev->priv;
736 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
737
738 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
739 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
740 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
741 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
742}
743
744static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
745{
746 struct ieee80211_hw *dev = eeprom->data;
747 struct rtl8180_priv *priv = dev->priv;
748 u8 reg = 2 << 6;
749
750 if (eeprom->reg_data_in)
751 reg |= RTL818X_EEPROM_CMD_WRITE;
752 if (eeprom->reg_data_out)
753 reg |= RTL818X_EEPROM_CMD_READ;
754 if (eeprom->reg_data_clock)
755 reg |= RTL818X_EEPROM_CMD_CK;
756 if (eeprom->reg_chip_select)
757 reg |= RTL818X_EEPROM_CMD_CS;
758
759 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
760 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
761 udelay(10);
762}
763
764static int __devinit rtl8180_probe(struct pci_dev *pdev,
765 const struct pci_device_id *id)
766{
767 struct ieee80211_hw *dev;
768 struct rtl8180_priv *priv;
769 unsigned long mem_addr, mem_len;
770 unsigned int io_addr, io_len;
771 int err, i;
772 struct eeprom_93cx6 eeprom;
773 const char *chip_name, *rf_name = NULL;
774 u32 reg;
775 u16 eeprom_val;
776 DECLARE_MAC_BUF(mac);
777
778 err = pci_enable_device(pdev);
779 if (err) {
780 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
781 pci_name(pdev));
782 return err;
783 }
784
785 err = pci_request_regions(pdev, KBUILD_MODNAME);
786 if (err) {
787 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
788 pci_name(pdev));
789 return err;
790 }
791
792 io_addr = pci_resource_start(pdev, 0);
793 io_len = pci_resource_len(pdev, 0);
794 mem_addr = pci_resource_start(pdev, 1);
795 mem_len = pci_resource_len(pdev, 1);
796
797 if (mem_len < sizeof(struct rtl818x_csr) ||
798 io_len < sizeof(struct rtl818x_csr)) {
799 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
800 pci_name(pdev));
801 err = -ENOMEM;
802 goto err_free_reg;
803 }
804
805 if ((err = pci_set_dma_mask(pdev, 0xFFFFFF00ULL)) ||
806 (err = pci_set_consistent_dma_mask(pdev, 0xFFFFFF00ULL))) {
807 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
808 pci_name(pdev));
809 goto err_free_reg;
810 }
811
812 pci_set_master(pdev);
813
814 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
815 if (!dev) {
816 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
817 pci_name(pdev));
818 err = -ENOMEM;
819 goto err_free_reg;
820 }
821
822 priv = dev->priv;
823 priv->pdev = pdev;
824
825 SET_IEEE80211_DEV(dev, &pdev->dev);
826 pci_set_drvdata(pdev, dev);
827
828 priv->map = pci_iomap(pdev, 1, mem_len);
829 if (!priv->map)
830 priv->map = pci_iomap(pdev, 0, io_len);
831
832 if (!priv->map) {
833 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
834 pci_name(pdev));
835 goto err_free_dev;
836 }
837
838 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
839 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
840 priv->modes[0].mode = MODE_IEEE80211G;
841 priv->modes[0].num_rates = ARRAY_SIZE(rtl818x_rates);
842 priv->modes[0].rates = priv->rates;
843 priv->modes[0].num_channels = ARRAY_SIZE(rtl818x_channels);
844 priv->modes[0].channels = priv->channels;
845 priv->modes[1].mode = MODE_IEEE80211B;
846 priv->modes[1].num_rates = 4;
847 priv->modes[1].rates = priv->rates;
848 priv->modes[1].num_channels = ARRAY_SIZE(rtl818x_channels);
849 priv->modes[1].channels = priv->channels;
850 priv->mode = IEEE80211_IF_TYPE_INVALID;
851 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
852 IEEE80211_HW_RX_INCLUDES_FCS;
853 dev->queues = 1;
854 dev->max_rssi = 65;
855
856 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
857 reg &= RTL818X_TX_CONF_HWVER_MASK;
858 switch (reg) {
859 case RTL818X_TX_CONF_R8180_ABCD:
860 chip_name = "RTL8180";
861 break;
862 case RTL818X_TX_CONF_R8180_F:
863 chip_name = "RTL8180vF";
864 break;
865 case RTL818X_TX_CONF_R8185_ABC:
866 chip_name = "RTL8185";
867 break;
868 case RTL818X_TX_CONF_R8185_D:
869 chip_name = "RTL8185vD";
870 break;
871 default:
872 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
873 pci_name(pdev), reg >> 25);
874 goto err_iounmap;
875 }
876
877 priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
878 if (priv->r8185) {
879 if ((err = ieee80211_register_hwmode(dev, &priv->modes[0])))
880 goto err_iounmap;
881
882 pci_try_set_mwi(pdev);
883 }
884
885 if ((err = ieee80211_register_hwmode(dev, &priv->modes[1])))
886 goto err_iounmap;
887
888 eeprom.data = dev;
889 eeprom.register_read = rtl8180_eeprom_register_read;
890 eeprom.register_write = rtl8180_eeprom_register_write;
891 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
892 eeprom.width = PCI_EEPROM_WIDTH_93C66;
893 else
894 eeprom.width = PCI_EEPROM_WIDTH_93C46;
895
896 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
897 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
898 udelay(10);
899
900 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
901 eeprom_val &= 0xFF;
902 switch (eeprom_val) {
903 case 1: rf_name = "Intersil";
904 break;
905 case 2: rf_name = "RFMD";
906 break;
907 case 3: priv->rf = &sa2400_rf_ops;
908 break;
909 case 4: priv->rf = &max2820_rf_ops;
910 break;
911 case 5: priv->rf = &grf5101_rf_ops;
912 break;
913 case 9: priv->rf = rtl8180_detect_rf(dev);
914 break;
915 case 10:
916 rf_name = "RTL8255";
917 break;
918 default:
919 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
920 pci_name(pdev), eeprom_val);
921 goto err_iounmap;
922 }
923
924 if (!priv->rf) {
925 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
926 pci_name(pdev), rf_name);
927 goto err_iounmap;
928 }
929
930 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
931 priv->csthreshold = eeprom_val >> 8;
932 if (!priv->r8185) {
933 __le32 anaparam;
934 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
935 priv->anaparam = le32_to_cpu(anaparam);
936 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
937 }
938
939 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)dev->wiphy->perm_addr, 3);
940 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
941 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
942 " randomly generated MAC addr\n", pci_name(pdev));
943 random_ether_addr(dev->wiphy->perm_addr);
944 }
945
946 /* CCK TX power */
947 for (i = 0; i < 14; i += 2) {
948 u16 txpwr;
949 eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
950 priv->channels[i].val = txpwr & 0xFF;
951 priv->channels[i + 1].val = txpwr >> 8;
952 }
953
954 /* OFDM TX power */
955 if (priv->r8185) {
956 for (i = 0; i < 14; i += 2) {
957 u16 txpwr;
958 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
959 priv->channels[i].val |= (txpwr & 0xFF) << 8;
960 priv->channels[i + 1].val |= txpwr & 0xFF00;
961 }
962 }
963
964 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
965
966 spin_lock_init(&priv->lock);
967
968 err = ieee80211_register_hw(dev);
969 if (err) {
970 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
971 pci_name(pdev));
972 goto err_iounmap;
973 }
974
975 printk(KERN_INFO "%s: hwaddr %s, %s + %s\n",
976 wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
977 chip_name, priv->rf->name);
978
979 return 0;
980
981 err_iounmap:
982 iounmap(priv->map);
983
984 err_free_dev:
985 pci_set_drvdata(pdev, NULL);
986 ieee80211_free_hw(dev);
987
988 err_free_reg:
989 pci_release_regions(pdev);
990 pci_disable_device(pdev);
991 return err;
992}
993
994static void __devexit rtl8180_remove(struct pci_dev *pdev)
995{
996 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
997 struct rtl8180_priv *priv;
998
999 if (!dev)
1000 return;
1001
1002 ieee80211_unregister_hw(dev);
1003
1004 priv = dev->priv;
1005
1006 pci_iounmap(pdev, priv->map);
1007 pci_release_regions(pdev);
1008 pci_disable_device(pdev);
1009 ieee80211_free_hw(dev);
1010}
1011
1012#ifdef CONFIG_PM
1013static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1014{
1015 pci_save_state(pdev);
1016 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1017 return 0;
1018}
1019
1020static int rtl8180_resume(struct pci_dev *pdev)
1021{
1022 pci_set_power_state(pdev, PCI_D0);
1023 pci_restore_state(pdev);
1024 return 0;
1025}
1026
1027#endif /* CONFIG_PM */
1028
1029static struct pci_driver rtl8180_driver = {
1030 .name = KBUILD_MODNAME,
1031 .id_table = rtl8180_table,
1032 .probe = rtl8180_probe,
1033 .remove = __devexit_p(rtl8180_remove),
1034#ifdef CONFIG_PM
1035 .suspend = rtl8180_suspend,
1036 .resume = rtl8180_resume,
1037#endif /* CONFIG_PM */
1038};
1039
1040static int __init rtl8180_init(void)
1041{
1042 return pci_register_driver(&rtl8180_driver);
1043}
1044
1045static void __exit rtl8180_exit(void)
1046{
1047 pci_unregister_driver(&rtl8180_driver);
1048}
1049
1050module_init(rtl8180_init);
1051module_exit(rtl8180_exit);
ubuntu-zesty-kernel mirror