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f6532111 MW |
1 | |
2 | /* | |
3 | * Linux device driver for RTL8180 / RTL8185 | |
4 | * | |
5 | * Copyright 2007 Michael Wu <flamingice@sourmilk.net> | |
6 | * Copyright 2007 Andrea Merello <andreamrl@tiscali.it> | |
7 | * | |
8 | * Based on the r8180 driver, which is: | |
9 | * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. | |
10 | * | |
11 | * Thanks to Realtek for their support! | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/etherdevice.h> | |
22 | #include <linux/eeprom_93cx6.h> | |
23 | #include <net/mac80211.h> | |
24 | ||
25 | #include "rtl8180.h" | |
26 | #include "rtl8180_rtl8225.h" | |
27 | #include "rtl8180_sa2400.h" | |
28 | #include "rtl8180_max2820.h" | |
29 | #include "rtl8180_grf5101.h" | |
30 | ||
31 | MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>"); | |
32 | MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>"); | |
33 | MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver"); | |
34 | MODULE_LICENSE("GPL"); | |
35 | ||
a3aa1884 | 36 | static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = { |
f6532111 MW |
37 | /* rtl8185 */ |
38 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) }, | |
4fcc5470 | 39 | { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) }, |
f6532111 MW |
40 | { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) }, |
41 | ||
42 | /* rtl8180 */ | |
43 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) }, | |
44 | { PCI_DEVICE(0x1799, 0x6001) }, | |
45 | { PCI_DEVICE(0x1799, 0x6020) }, | |
46 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) }, | |
47 | { } | |
48 | }; | |
49 | ||
50 | MODULE_DEVICE_TABLE(pci, rtl8180_table); | |
51 | ||
8318d78a JB |
52 | static const struct ieee80211_rate rtl818x_rates[] = { |
53 | { .bitrate = 10, .hw_value = 0, }, | |
54 | { .bitrate = 20, .hw_value = 1, }, | |
55 | { .bitrate = 55, .hw_value = 2, }, | |
56 | { .bitrate = 110, .hw_value = 3, }, | |
57 | { .bitrate = 60, .hw_value = 4, }, | |
58 | { .bitrate = 90, .hw_value = 5, }, | |
59 | { .bitrate = 120, .hw_value = 6, }, | |
60 | { .bitrate = 180, .hw_value = 7, }, | |
61 | { .bitrate = 240, .hw_value = 8, }, | |
62 | { .bitrate = 360, .hw_value = 9, }, | |
63 | { .bitrate = 480, .hw_value = 10, }, | |
64 | { .bitrate = 540, .hw_value = 11, }, | |
65 | }; | |
66 | ||
67 | static const struct ieee80211_channel rtl818x_channels[] = { | |
68 | { .center_freq = 2412 }, | |
69 | { .center_freq = 2417 }, | |
70 | { .center_freq = 2422 }, | |
71 | { .center_freq = 2427 }, | |
72 | { .center_freq = 2432 }, | |
73 | { .center_freq = 2437 }, | |
74 | { .center_freq = 2442 }, | |
75 | { .center_freq = 2447 }, | |
76 | { .center_freq = 2452 }, | |
77 | { .center_freq = 2457 }, | |
78 | { .center_freq = 2462 }, | |
79 | { .center_freq = 2467 }, | |
80 | { .center_freq = 2472 }, | |
81 | { .center_freq = 2484 }, | |
82 | }; | |
83 | ||
84 | ||
f6532111 MW |
85 | void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data) |
86 | { | |
87 | struct rtl8180_priv *priv = dev->priv; | |
88 | int i = 10; | |
89 | u32 buf; | |
90 | ||
91 | buf = (data << 8) | addr; | |
92 | ||
93 | rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80); | |
94 | while (i--) { | |
95 | rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf); | |
96 | if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF)) | |
97 | return; | |
98 | } | |
99 | } | |
100 | ||
101 | static void rtl8180_handle_rx(struct ieee80211_hw *dev) | |
102 | { | |
103 | struct rtl8180_priv *priv = dev->priv; | |
104 | unsigned int count = 32; | |
105 | ||
106 | while (count--) { | |
107 | struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx]; | |
108 | struct sk_buff *skb = priv->rx_buf[priv->rx_idx]; | |
109 | u32 flags = le32_to_cpu(entry->flags); | |
110 | ||
38e3b0d8 | 111 | if (flags & RTL818X_RX_DESC_FLAG_OWN) |
f6532111 MW |
112 | return; |
113 | ||
38e3b0d8 HRK |
114 | if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL | |
115 | RTL818X_RX_DESC_FLAG_FOF | | |
116 | RTL818X_RX_DESC_FLAG_RX_ERR))) | |
f6532111 MW |
117 | goto done; |
118 | else { | |
119 | u32 flags2 = le32_to_cpu(entry->flags2); | |
120 | struct ieee80211_rx_status rx_status = {0}; | |
121 | struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE); | |
122 | ||
123 | if (unlikely(!new_skb)) | |
124 | goto done; | |
125 | ||
126 | pci_unmap_single(priv->pdev, | |
127 | *((dma_addr_t *)skb->cb), | |
128 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
129 | skb_put(skb, flags & 0xFFF); | |
130 | ||
131 | rx_status.antenna = (flags2 >> 15) & 1; | |
132 | /* TODO: improve signal/rssi reporting */ | |
566bfe5a | 133 | rx_status.signal = (flags2 >> 8) & 0x7F; |
8318d78a JB |
134 | /* XXX: is this correct? */ |
135 | rx_status.rate_idx = (flags >> 20) & 0xF; | |
136 | rx_status.freq = dev->conf.channel->center_freq; | |
137 | rx_status.band = dev->conf.channel->band; | |
f6532111 MW |
138 | rx_status.mactime = le64_to_cpu(entry->tsft); |
139 | rx_status.flag |= RX_FLAG_TSFT; | |
38e3b0d8 | 140 | if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR) |
f6532111 MW |
141 | rx_status.flag |= RX_FLAG_FAILED_FCS_CRC; |
142 | ||
f1d58c25 JB |
143 | memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status)); |
144 | ieee80211_rx_irqsafe(dev, skb); | |
f6532111 MW |
145 | |
146 | skb = new_skb; | |
147 | priv->rx_buf[priv->rx_idx] = skb; | |
148 | *((dma_addr_t *) skb->cb) = | |
149 | pci_map_single(priv->pdev, skb_tail_pointer(skb), | |
150 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
151 | } | |
152 | ||
153 | done: | |
154 | entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb)); | |
38e3b0d8 | 155 | entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN | |
f6532111 MW |
156 | MAX_RX_SIZE); |
157 | if (priv->rx_idx == 31) | |
38e3b0d8 | 158 | entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR); |
f6532111 MW |
159 | priv->rx_idx = (priv->rx_idx + 1) % 32; |
160 | } | |
161 | } | |
162 | ||
163 | static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio) | |
164 | { | |
165 | struct rtl8180_priv *priv = dev->priv; | |
166 | struct rtl8180_tx_ring *ring = &priv->tx_ring[prio]; | |
167 | ||
168 | while (skb_queue_len(&ring->queue)) { | |
169 | struct rtl8180_tx_desc *entry = &ring->desc[ring->idx]; | |
170 | struct sk_buff *skb; | |
e039fa4a | 171 | struct ieee80211_tx_info *info; |
f6532111 MW |
172 | u32 flags = le32_to_cpu(entry->flags); |
173 | ||
38e3b0d8 | 174 | if (flags & RTL818X_TX_DESC_FLAG_OWN) |
f6532111 MW |
175 | return; |
176 | ||
177 | ring->idx = (ring->idx + 1) % ring->entries; | |
178 | skb = __skb_dequeue(&ring->queue); | |
179 | pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf), | |
180 | skb->len, PCI_DMA_TODEVICE); | |
181 | ||
e039fa4a | 182 | info = IEEE80211_SKB_CB(skb); |
e6a9854b | 183 | ieee80211_tx_info_clear_status(info); |
f6532111 | 184 | |
e6a9854b JB |
185 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) && |
186 | (flags & RTL818X_TX_DESC_FLAG_TX_OK)) | |
187 | info->flags |= IEEE80211_TX_STAT_ACK; | |
188 | ||
189 | info->status.rates[0].count = (flags & 0xFF) + 1; | |
f6532111 | 190 | |
e039fa4a | 191 | ieee80211_tx_status_irqsafe(dev, skb); |
f6532111 MW |
192 | if (ring->entries - skb_queue_len(&ring->queue) == 2) |
193 | ieee80211_wake_queue(dev, prio); | |
194 | } | |
195 | } | |
196 | ||
197 | static irqreturn_t rtl8180_interrupt(int irq, void *dev_id) | |
198 | { | |
199 | struct ieee80211_hw *dev = dev_id; | |
200 | struct rtl8180_priv *priv = dev->priv; | |
201 | u16 reg; | |
202 | ||
203 | spin_lock(&priv->lock); | |
204 | reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS); | |
205 | if (unlikely(reg == 0xFFFF)) { | |
206 | spin_unlock(&priv->lock); | |
207 | return IRQ_HANDLED; | |
208 | } | |
209 | ||
210 | rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg); | |
211 | ||
212 | if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR)) | |
213 | rtl8180_handle_tx(dev, 3); | |
214 | ||
215 | if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR)) | |
216 | rtl8180_handle_tx(dev, 2); | |
217 | ||
218 | if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR)) | |
219 | rtl8180_handle_tx(dev, 1); | |
220 | ||
221 | if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR)) | |
222 | rtl8180_handle_tx(dev, 0); | |
223 | ||
224 | if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR)) | |
225 | rtl8180_handle_rx(dev); | |
226 | ||
227 | spin_unlock(&priv->lock); | |
228 | ||
229 | return IRQ_HANDLED; | |
230 | } | |
231 | ||
e039fa4a | 232 | static int rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb) |
f6532111 | 233 | { |
e039fa4a | 234 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
f6532111 MW |
235 | struct rtl8180_priv *priv = dev->priv; |
236 | struct rtl8180_tx_ring *ring; | |
237 | struct rtl8180_tx_desc *entry; | |
238 | unsigned long flags; | |
239 | unsigned int idx, prio; | |
240 | dma_addr_t mapping; | |
241 | u32 tx_flags; | |
e6a9854b | 242 | u8 rc_flags; |
f6532111 MW |
243 | u16 plcp_len = 0; |
244 | __le16 rts_duration = 0; | |
245 | ||
e2530083 | 246 | prio = skb_get_queue_mapping(skb); |
f6532111 MW |
247 | ring = &priv->tx_ring[prio]; |
248 | ||
249 | mapping = pci_map_single(priv->pdev, skb->data, | |
250 | skb->len, PCI_DMA_TODEVICE); | |
251 | ||
38e3b0d8 HRK |
252 | tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS | |
253 | RTL818X_TX_DESC_FLAG_LS | | |
e039fa4a | 254 | (ieee80211_get_tx_rate(dev, info)->hw_value << 24) | |
2e92e6f2 | 255 | skb->len; |
f6532111 MW |
256 | |
257 | if (priv->r8185) | |
38e3b0d8 HRK |
258 | tx_flags |= RTL818X_TX_DESC_FLAG_DMA | |
259 | RTL818X_TX_DESC_FLAG_NO_ENC; | |
f6532111 | 260 | |
e6a9854b JB |
261 | rc_flags = info->control.rates[0].flags; |
262 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { | |
38e3b0d8 | 263 | tx_flags |= RTL818X_TX_DESC_FLAG_RTS; |
e039fa4a | 264 | tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19; |
e6a9854b | 265 | } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
38e3b0d8 | 266 | tx_flags |= RTL818X_TX_DESC_FLAG_CTS; |
e039fa4a | 267 | tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19; |
aa68cbfb | 268 | } |
f6532111 | 269 | |
e6a9854b | 270 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) |
32bfd35d | 271 | rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len, |
e039fa4a | 272 | info); |
f6532111 MW |
273 | |
274 | if (!priv->r8185) { | |
275 | unsigned int remainder; | |
276 | ||
277 | plcp_len = DIV_ROUND_UP(16 * (skb->len + 4), | |
e039fa4a | 278 | (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10); |
f6532111 | 279 | remainder = (16 * (skb->len + 4)) % |
e039fa4a | 280 | ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10); |
35a0ace7 | 281 | if (remainder <= 6) |
f6532111 MW |
282 | plcp_len |= 1 << 15; |
283 | } | |
284 | ||
285 | spin_lock_irqsave(&priv->lock, flags); | |
286 | idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries; | |
287 | entry = &ring->desc[idx]; | |
288 | ||
289 | entry->rts_duration = rts_duration; | |
290 | entry->plcp_len = cpu_to_le16(plcp_len); | |
291 | entry->tx_buf = cpu_to_le32(mapping); | |
292 | entry->frame_len = cpu_to_le32(skb->len); | |
e6a9854b | 293 | entry->flags2 = info->control.rates[1].idx >= 0 ? |
870abdf6 | 294 | ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0; |
e6a9854b | 295 | entry->retry_limit = info->control.rates[0].count; |
f6532111 MW |
296 | entry->flags = cpu_to_le32(tx_flags); |
297 | __skb_queue_tail(&ring->queue, skb); | |
298 | if (ring->entries - skb_queue_len(&ring->queue) < 2) | |
e2530083 | 299 | ieee80211_stop_queue(dev, skb_get_queue_mapping(skb)); |
f6532111 MW |
300 | spin_unlock_irqrestore(&priv->lock, flags); |
301 | ||
302 | rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4))); | |
303 | ||
304 | return 0; | |
305 | } | |
306 | ||
307 | void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam) | |
308 | { | |
309 | u8 reg; | |
310 | ||
311 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
312 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
313 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, | |
314 | reg | RTL818X_CONFIG3_ANAPARAM_WRITE); | |
315 | rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam); | |
316 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, | |
317 | reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); | |
318 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
319 | } | |
320 | ||
321 | static int rtl8180_init_hw(struct ieee80211_hw *dev) | |
322 | { | |
323 | struct rtl8180_priv *priv = dev->priv; | |
324 | u16 reg; | |
325 | ||
326 | rtl818x_iowrite8(priv, &priv->map->CMD, 0); | |
327 | rtl818x_ioread8(priv, &priv->map->CMD); | |
328 | msleep(10); | |
329 | ||
330 | /* reset */ | |
331 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); | |
332 | rtl818x_ioread8(priv, &priv->map->CMD); | |
333 | ||
334 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
335 | reg &= (1 << 1); | |
336 | reg |= RTL818X_CMD_RESET; | |
337 | rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET); | |
338 | rtl818x_ioread8(priv, &priv->map->CMD); | |
339 | msleep(200); | |
340 | ||
341 | /* check success of reset */ | |
342 | if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) { | |
343 | printk(KERN_ERR "%s: reset timeout!\n", wiphy_name(dev->wiphy)); | |
344 | return -ETIMEDOUT; | |
345 | } | |
346 | ||
347 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD); | |
348 | rtl818x_ioread8(priv, &priv->map->CMD); | |
349 | msleep(200); | |
350 | ||
351 | if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) { | |
352 | /* For cardbus */ | |
353 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
354 | reg |= 1 << 1; | |
355 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg); | |
356 | reg = rtl818x_ioread16(priv, &priv->map->FEMR); | |
357 | reg |= (1 << 15) | (1 << 14) | (1 << 4); | |
358 | rtl818x_iowrite16(priv, &priv->map->FEMR, reg); | |
359 | } | |
360 | ||
361 | rtl818x_iowrite8(priv, &priv->map->MSR, 0); | |
362 | ||
363 | if (!priv->r8185) | |
364 | rtl8180_set_anaparam(priv, priv->anaparam); | |
365 | ||
366 | rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma); | |
367 | rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma); | |
368 | rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma); | |
369 | rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma); | |
370 | rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma); | |
371 | ||
372 | /* TODO: necessary? specs indicate not */ | |
373 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
374 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG2); | |
375 | rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3)); | |
376 | if (priv->r8185) { | |
377 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG2); | |
378 | rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4)); | |
379 | } | |
380 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
381 | ||
382 | /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */ | |
383 | ||
384 | /* TODO: turn off hw wep on rtl8180 */ | |
385 | ||
386 | rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0); | |
387 | ||
388 | if (priv->r8185) { | |
389 | rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0); | |
390 | rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81); | |
391 | rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0); | |
392 | ||
393 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3); | |
394 | ||
395 | /* TODO: set ClkRun enable? necessary? */ | |
396 | reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE); | |
397 | rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6)); | |
398 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
399 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
400 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2)); | |
401 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
402 | } else { | |
403 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1); | |
404 | rtl818x_iowrite8(priv, &priv->map->SECURITY, 0); | |
405 | ||
406 | rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6); | |
407 | rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C); | |
408 | } | |
409 | ||
410 | priv->rf->init(dev); | |
411 | if (priv->r8185) | |
412 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3); | |
413 | return 0; | |
414 | } | |
415 | ||
416 | static int rtl8180_init_rx_ring(struct ieee80211_hw *dev) | |
417 | { | |
418 | struct rtl8180_priv *priv = dev->priv; | |
419 | struct rtl8180_rx_desc *entry; | |
420 | int i; | |
421 | ||
422 | priv->rx_ring = pci_alloc_consistent(priv->pdev, | |
423 | sizeof(*priv->rx_ring) * 32, | |
424 | &priv->rx_ring_dma); | |
425 | ||
426 | if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) { | |
427 | printk(KERN_ERR "%s: Cannot allocate RX ring\n", | |
428 | wiphy_name(dev->wiphy)); | |
429 | return -ENOMEM; | |
430 | } | |
431 | ||
432 | memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32); | |
433 | priv->rx_idx = 0; | |
434 | ||
435 | for (i = 0; i < 32; i++) { | |
436 | struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE); | |
437 | dma_addr_t *mapping; | |
438 | entry = &priv->rx_ring[i]; | |
439 | if (!skb) | |
440 | return 0; | |
441 | ||
442 | priv->rx_buf[i] = skb; | |
443 | mapping = (dma_addr_t *)skb->cb; | |
444 | *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb), | |
445 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
446 | entry->rx_buf = cpu_to_le32(*mapping); | |
38e3b0d8 | 447 | entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN | |
f6532111 MW |
448 | MAX_RX_SIZE); |
449 | } | |
38e3b0d8 | 450 | entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR); |
f6532111 MW |
451 | return 0; |
452 | } | |
453 | ||
454 | static void rtl8180_free_rx_ring(struct ieee80211_hw *dev) | |
455 | { | |
456 | struct rtl8180_priv *priv = dev->priv; | |
457 | int i; | |
458 | ||
459 | for (i = 0; i < 32; i++) { | |
460 | struct sk_buff *skb = priv->rx_buf[i]; | |
461 | if (!skb) | |
462 | continue; | |
463 | ||
464 | pci_unmap_single(priv->pdev, | |
465 | *((dma_addr_t *)skb->cb), | |
466 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
467 | kfree_skb(skb); | |
468 | } | |
469 | ||
470 | pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32, | |
471 | priv->rx_ring, priv->rx_ring_dma); | |
472 | priv->rx_ring = NULL; | |
473 | } | |
474 | ||
475 | static int rtl8180_init_tx_ring(struct ieee80211_hw *dev, | |
476 | unsigned int prio, unsigned int entries) | |
477 | { | |
478 | struct rtl8180_priv *priv = dev->priv; | |
479 | struct rtl8180_tx_desc *ring; | |
480 | dma_addr_t dma; | |
481 | int i; | |
482 | ||
483 | ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma); | |
484 | if (!ring || (unsigned long)ring & 0xFF) { | |
485 | printk(KERN_ERR "%s: Cannot allocate TX ring (prio = %d)\n", | |
486 | wiphy_name(dev->wiphy), prio); | |
487 | return -ENOMEM; | |
488 | } | |
489 | ||
490 | memset(ring, 0, sizeof(*ring)*entries); | |
491 | priv->tx_ring[prio].desc = ring; | |
492 | priv->tx_ring[prio].dma = dma; | |
493 | priv->tx_ring[prio].idx = 0; | |
494 | priv->tx_ring[prio].entries = entries; | |
495 | skb_queue_head_init(&priv->tx_ring[prio].queue); | |
496 | ||
497 | for (i = 0; i < entries; i++) | |
498 | ring[i].next_tx_desc = | |
499 | cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring)); | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
504 | static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio) | |
505 | { | |
506 | struct rtl8180_priv *priv = dev->priv; | |
507 | struct rtl8180_tx_ring *ring = &priv->tx_ring[prio]; | |
508 | ||
509 | while (skb_queue_len(&ring->queue)) { | |
510 | struct rtl8180_tx_desc *entry = &ring->desc[ring->idx]; | |
511 | struct sk_buff *skb = __skb_dequeue(&ring->queue); | |
512 | ||
513 | pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf), | |
514 | skb->len, PCI_DMA_TODEVICE); | |
f6532111 MW |
515 | kfree_skb(skb); |
516 | ring->idx = (ring->idx + 1) % ring->entries; | |
517 | } | |
518 | ||
519 | pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries, | |
520 | ring->desc, ring->dma); | |
521 | ring->desc = NULL; | |
522 | } | |
523 | ||
524 | static int rtl8180_start(struct ieee80211_hw *dev) | |
525 | { | |
526 | struct rtl8180_priv *priv = dev->priv; | |
527 | int ret, i; | |
528 | u32 reg; | |
529 | ||
530 | ret = rtl8180_init_rx_ring(dev); | |
531 | if (ret) | |
532 | return ret; | |
533 | ||
534 | for (i = 0; i < 4; i++) | |
535 | if ((ret = rtl8180_init_tx_ring(dev, i, 16))) | |
536 | goto err_free_rings; | |
537 | ||
538 | ret = rtl8180_init_hw(dev); | |
539 | if (ret) | |
540 | goto err_free_rings; | |
541 | ||
542 | rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma); | |
543 | rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma); | |
544 | rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma); | |
545 | rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma); | |
546 | rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma); | |
547 | ||
ea31ba35 | 548 | ret = request_irq(priv->pdev->irq, rtl8180_interrupt, |
f6532111 MW |
549 | IRQF_SHARED, KBUILD_MODNAME, dev); |
550 | if (ret) { | |
551 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
552 | wiphy_name(dev->wiphy)); | |
553 | goto err_free_rings; | |
554 | } | |
555 | ||
556 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF); | |
557 | ||
558 | rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0); | |
559 | rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0); | |
560 | ||
561 | reg = RTL818X_RX_CONF_ONLYERLPKT | | |
562 | RTL818X_RX_CONF_RX_AUTORESETPHY | | |
563 | RTL818X_RX_CONF_MGMT | | |
564 | RTL818X_RX_CONF_DATA | | |
565 | (7 << 8 /* MAX RX DMA */) | | |
566 | RTL818X_RX_CONF_BROADCAST | | |
567 | RTL818X_RX_CONF_NICMAC; | |
568 | ||
569 | if (priv->r8185) | |
570 | reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2; | |
571 | else { | |
572 | reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1) | |
573 | ? RTL818X_RX_CONF_CSDM1 : 0; | |
574 | reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2) | |
575 | ? RTL818X_RX_CONF_CSDM2 : 0; | |
576 | } | |
577 | ||
578 | priv->rx_conf = reg; | |
579 | rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg); | |
580 | ||
581 | if (priv->r8185) { | |
582 | reg = rtl818x_ioread8(priv, &priv->map->CW_CONF); | |
583 | reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT; | |
584 | reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT; | |
585 | rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg); | |
586 | ||
587 | reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL); | |
588 | reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT; | |
589 | reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT; | |
590 | reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT; | |
591 | rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg); | |
592 | ||
593 | /* disable early TX */ | |
594 | rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f); | |
595 | } | |
596 | ||
597 | reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); | |
598 | reg |= (6 << 21 /* MAX TX DMA */) | | |
599 | RTL818X_TX_CONF_NO_ICV; | |
600 | ||
601 | if (priv->r8185) | |
602 | reg &= ~RTL818X_TX_CONF_PROBE_DTS; | |
603 | else | |
604 | reg &= ~RTL818X_TX_CONF_HW_SEQNUM; | |
605 | ||
606 | /* different meaning, same value on both rtl8185 and rtl8180 */ | |
607 | reg &= ~RTL818X_TX_CONF_SAT_HWPLCP; | |
608 | ||
609 | rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg); | |
610 | ||
611 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
612 | reg |= RTL818X_CMD_RX_ENABLE; | |
613 | reg |= RTL818X_CMD_TX_ENABLE; | |
614 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); | |
615 | ||
f6532111 MW |
616 | return 0; |
617 | ||
618 | err_free_rings: | |
619 | rtl8180_free_rx_ring(dev); | |
620 | for (i = 0; i < 4; i++) | |
621 | if (priv->tx_ring[i].desc) | |
622 | rtl8180_free_tx_ring(dev, i); | |
623 | ||
624 | return ret; | |
625 | } | |
626 | ||
627 | static void rtl8180_stop(struct ieee80211_hw *dev) | |
628 | { | |
629 | struct rtl8180_priv *priv = dev->priv; | |
630 | u8 reg; | |
631 | int i; | |
632 | ||
f6532111 MW |
633 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); |
634 | ||
635 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
636 | reg &= ~RTL818X_CMD_TX_ENABLE; | |
637 | reg &= ~RTL818X_CMD_RX_ENABLE; | |
638 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); | |
639 | ||
640 | priv->rf->stop(dev); | |
641 | ||
642 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
643 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG4); | |
644 | rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF); | |
645 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
646 | ||
647 | free_irq(priv->pdev->irq, dev); | |
648 | ||
649 | rtl8180_free_rx_ring(dev); | |
650 | for (i = 0; i < 4; i++) | |
651 | rtl8180_free_tx_ring(dev, i); | |
652 | } | |
653 | ||
654 | static int rtl8180_add_interface(struct ieee80211_hw *dev, | |
1ed32e4f | 655 | struct ieee80211_vif *vif) |
f6532111 MW |
656 | { |
657 | struct rtl8180_priv *priv = dev->priv; | |
658 | ||
643aab67 JL |
659 | /* |
660 | * We only support one active interface at a time. | |
661 | */ | |
662 | if (priv->vif) | |
663 | return -EBUSY; | |
f6532111 | 664 | |
1ed32e4f | 665 | switch (vif->type) { |
05c914fe | 666 | case NL80211_IFTYPE_STATION: |
f6532111 MW |
667 | break; |
668 | default: | |
669 | return -EOPNOTSUPP; | |
670 | } | |
671 | ||
1ed32e4f | 672 | priv->vif = vif; |
32bfd35d | 673 | |
f6532111 MW |
674 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); |
675 | rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0], | |
1ed32e4f | 676 | le32_to_cpu(*(__le32 *)vif->addr)); |
f6532111 | 677 | rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4], |
1ed32e4f | 678 | le16_to_cpu(*(__le16 *)(vif->addr + 4))); |
f6532111 MW |
679 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
684 | static void rtl8180_remove_interface(struct ieee80211_hw *dev, | |
1ed32e4f | 685 | struct ieee80211_vif *vif) |
f6532111 MW |
686 | { |
687 | struct rtl8180_priv *priv = dev->priv; | |
32bfd35d | 688 | priv->vif = NULL; |
f6532111 MW |
689 | } |
690 | ||
e8975581 | 691 | static int rtl8180_config(struct ieee80211_hw *dev, u32 changed) |
f6532111 MW |
692 | { |
693 | struct rtl8180_priv *priv = dev->priv; | |
e8975581 | 694 | struct ieee80211_conf *conf = &dev->conf; |
f6532111 MW |
695 | |
696 | priv->rf->set_chan(dev, conf); | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
da81dede JL |
701 | static void rtl8180_bss_info_changed(struct ieee80211_hw *dev, |
702 | struct ieee80211_vif *vif, | |
703 | struct ieee80211_bss_conf *info, | |
704 | u32 changed) | |
705 | { | |
706 | struct rtl8180_priv *priv = dev->priv; | |
2d0ddec5 JB |
707 | int i; |
708 | ||
709 | if (changed & BSS_CHANGED_BSSID) { | |
710 | for (i = 0; i < ETH_ALEN; i++) | |
711 | rtl818x_iowrite8(priv, &priv->map->BSSID[i], | |
712 | info->bssid[i]); | |
713 | ||
714 | if (is_valid_ether_addr(info->bssid)) | |
715 | rtl818x_iowrite8(priv, &priv->map->MSR, | |
716 | RTL818X_MSR_INFRA); | |
717 | else | |
718 | rtl818x_iowrite8(priv, &priv->map->MSR, | |
719 | RTL818X_MSR_NO_LINK); | |
720 | } | |
da81dede JL |
721 | |
722 | if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp) | |
723 | priv->rf->conf_erp(dev, info); | |
724 | } | |
725 | ||
3ac64bee JB |
726 | static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev, int mc_count, |
727 | struct dev_addr_list *mc_list) | |
728 | { | |
729 | return mc_count; | |
730 | } | |
731 | ||
f6532111 MW |
732 | static void rtl8180_configure_filter(struct ieee80211_hw *dev, |
733 | unsigned int changed_flags, | |
734 | unsigned int *total_flags, | |
3ac64bee | 735 | u64 multicast) |
f6532111 MW |
736 | { |
737 | struct rtl8180_priv *priv = dev->priv; | |
738 | ||
739 | if (changed_flags & FIF_FCSFAIL) | |
740 | priv->rx_conf ^= RTL818X_RX_CONF_FCS; | |
741 | if (changed_flags & FIF_CONTROL) | |
742 | priv->rx_conf ^= RTL818X_RX_CONF_CTRL; | |
743 | if (changed_flags & FIF_OTHER_BSS) | |
744 | priv->rx_conf ^= RTL818X_RX_CONF_MONITOR; | |
3ac64bee | 745 | if (*total_flags & FIF_ALLMULTI || multicast > 0) |
f6532111 MW |
746 | priv->rx_conf |= RTL818X_RX_CONF_MULTICAST; |
747 | else | |
748 | priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST; | |
749 | ||
750 | *total_flags = 0; | |
751 | ||
752 | if (priv->rx_conf & RTL818X_RX_CONF_FCS) | |
753 | *total_flags |= FIF_FCSFAIL; | |
754 | if (priv->rx_conf & RTL818X_RX_CONF_CTRL) | |
755 | *total_flags |= FIF_CONTROL; | |
756 | if (priv->rx_conf & RTL818X_RX_CONF_MONITOR) | |
757 | *total_flags |= FIF_OTHER_BSS; | |
758 | if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST) | |
759 | *total_flags |= FIF_ALLMULTI; | |
760 | ||
761 | rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf); | |
762 | } | |
763 | ||
764 | static const struct ieee80211_ops rtl8180_ops = { | |
765 | .tx = rtl8180_tx, | |
766 | .start = rtl8180_start, | |
767 | .stop = rtl8180_stop, | |
768 | .add_interface = rtl8180_add_interface, | |
769 | .remove_interface = rtl8180_remove_interface, | |
770 | .config = rtl8180_config, | |
da81dede | 771 | .bss_info_changed = rtl8180_bss_info_changed, |
3ac64bee | 772 | .prepare_multicast = rtl8180_prepare_multicast, |
f6532111 MW |
773 | .configure_filter = rtl8180_configure_filter, |
774 | }; | |
775 | ||
776 | static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom) | |
777 | { | |
778 | struct ieee80211_hw *dev = eeprom->data; | |
779 | struct rtl8180_priv *priv = dev->priv; | |
780 | u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); | |
781 | ||
782 | eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE; | |
783 | eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ; | |
784 | eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK; | |
785 | eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS; | |
786 | } | |
787 | ||
788 | static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom) | |
789 | { | |
790 | struct ieee80211_hw *dev = eeprom->data; | |
791 | struct rtl8180_priv *priv = dev->priv; | |
792 | u8 reg = 2 << 6; | |
793 | ||
794 | if (eeprom->reg_data_in) | |
795 | reg |= RTL818X_EEPROM_CMD_WRITE; | |
796 | if (eeprom->reg_data_out) | |
797 | reg |= RTL818X_EEPROM_CMD_READ; | |
798 | if (eeprom->reg_data_clock) | |
799 | reg |= RTL818X_EEPROM_CMD_CK; | |
800 | if (eeprom->reg_chip_select) | |
801 | reg |= RTL818X_EEPROM_CMD_CS; | |
802 | ||
803 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg); | |
804 | rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); | |
805 | udelay(10); | |
806 | } | |
807 | ||
808 | static int __devinit rtl8180_probe(struct pci_dev *pdev, | |
809 | const struct pci_device_id *id) | |
810 | { | |
811 | struct ieee80211_hw *dev; | |
812 | struct rtl8180_priv *priv; | |
813 | unsigned long mem_addr, mem_len; | |
814 | unsigned int io_addr, io_len; | |
815 | int err, i; | |
816 | struct eeprom_93cx6 eeprom; | |
817 | const char *chip_name, *rf_name = NULL; | |
818 | u32 reg; | |
819 | u16 eeprom_val; | |
f6532111 MW |
820 | |
821 | err = pci_enable_device(pdev); | |
822 | if (err) { | |
823 | printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n", | |
824 | pci_name(pdev)); | |
825 | return err; | |
826 | } | |
827 | ||
828 | err = pci_request_regions(pdev, KBUILD_MODNAME); | |
829 | if (err) { | |
830 | printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n", | |
831 | pci_name(pdev)); | |
832 | return err; | |
833 | } | |
834 | ||
835 | io_addr = pci_resource_start(pdev, 0); | |
836 | io_len = pci_resource_len(pdev, 0); | |
837 | mem_addr = pci_resource_start(pdev, 1); | |
838 | mem_len = pci_resource_len(pdev, 1); | |
839 | ||
840 | if (mem_len < sizeof(struct rtl818x_csr) || | |
841 | io_len < sizeof(struct rtl818x_csr)) { | |
842 | printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n", | |
843 | pci_name(pdev)); | |
844 | err = -ENOMEM; | |
845 | goto err_free_reg; | |
846 | } | |
847 | ||
848 | if ((err = pci_set_dma_mask(pdev, 0xFFFFFF00ULL)) || | |
849 | (err = pci_set_consistent_dma_mask(pdev, 0xFFFFFF00ULL))) { | |
850 | printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n", | |
851 | pci_name(pdev)); | |
852 | goto err_free_reg; | |
853 | } | |
854 | ||
855 | pci_set_master(pdev); | |
856 | ||
857 | dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops); | |
858 | if (!dev) { | |
859 | printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n", | |
860 | pci_name(pdev)); | |
861 | err = -ENOMEM; | |
862 | goto err_free_reg; | |
863 | } | |
864 | ||
865 | priv = dev->priv; | |
866 | priv->pdev = pdev; | |
867 | ||
e6a9854b | 868 | dev->max_rates = 2; |
f6532111 MW |
869 | SET_IEEE80211_DEV(dev, &pdev->dev); |
870 | pci_set_drvdata(pdev, dev); | |
871 | ||
872 | priv->map = pci_iomap(pdev, 1, mem_len); | |
873 | if (!priv->map) | |
874 | priv->map = pci_iomap(pdev, 0, io_len); | |
875 | ||
876 | if (!priv->map) { | |
877 | printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n", | |
878 | pci_name(pdev)); | |
879 | goto err_free_dev; | |
880 | } | |
881 | ||
8318d78a JB |
882 | BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels)); |
883 | BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates)); | |
884 | ||
f6532111 MW |
885 | memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels)); |
886 | memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates)); | |
8318d78a JB |
887 | |
888 | priv->band.band = IEEE80211_BAND_2GHZ; | |
889 | priv->band.channels = priv->channels; | |
890 | priv->band.n_channels = ARRAY_SIZE(rtl818x_channels); | |
891 | priv->band.bitrates = priv->rates; | |
892 | priv->band.n_bitrates = 4; | |
893 | dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; | |
894 | ||
f6532111 | 895 | dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
566bfe5a BR |
896 | IEEE80211_HW_RX_INCLUDES_FCS | |
897 | IEEE80211_HW_SIGNAL_UNSPEC; | |
b55eae33 | 898 | dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); |
f6532111 | 899 | dev->queues = 1; |
566bfe5a | 900 | dev->max_signal = 65; |
f6532111 MW |
901 | |
902 | reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); | |
903 | reg &= RTL818X_TX_CONF_HWVER_MASK; | |
904 | switch (reg) { | |
905 | case RTL818X_TX_CONF_R8180_ABCD: | |
906 | chip_name = "RTL8180"; | |
907 | break; | |
908 | case RTL818X_TX_CONF_R8180_F: | |
909 | chip_name = "RTL8180vF"; | |
910 | break; | |
911 | case RTL818X_TX_CONF_R8185_ABC: | |
912 | chip_name = "RTL8185"; | |
913 | break; | |
914 | case RTL818X_TX_CONF_R8185_D: | |
915 | chip_name = "RTL8185vD"; | |
916 | break; | |
917 | default: | |
918 | printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n", | |
919 | pci_name(pdev), reg >> 25); | |
920 | goto err_iounmap; | |
921 | } | |
922 | ||
923 | priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC; | |
924 | if (priv->r8185) { | |
8318d78a | 925 | priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates); |
f6532111 MW |
926 | pci_try_set_mwi(pdev); |
927 | } | |
928 | ||
f6532111 MW |
929 | eeprom.data = dev; |
930 | eeprom.register_read = rtl8180_eeprom_register_read; | |
931 | eeprom.register_write = rtl8180_eeprom_register_write; | |
932 | if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6)) | |
933 | eeprom.width = PCI_EEPROM_WIDTH_93C66; | |
934 | else | |
935 | eeprom.width = PCI_EEPROM_WIDTH_93C46; | |
936 | ||
937 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM); | |
938 | rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); | |
939 | udelay(10); | |
940 | ||
941 | eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val); | |
942 | eeprom_val &= 0xFF; | |
943 | switch (eeprom_val) { | |
944 | case 1: rf_name = "Intersil"; | |
945 | break; | |
946 | case 2: rf_name = "RFMD"; | |
947 | break; | |
948 | case 3: priv->rf = &sa2400_rf_ops; | |
949 | break; | |
950 | case 4: priv->rf = &max2820_rf_ops; | |
951 | break; | |
952 | case 5: priv->rf = &grf5101_rf_ops; | |
953 | break; | |
954 | case 9: priv->rf = rtl8180_detect_rf(dev); | |
955 | break; | |
956 | case 10: | |
957 | rf_name = "RTL8255"; | |
958 | break; | |
959 | default: | |
960 | printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n", | |
961 | pci_name(pdev), eeprom_val); | |
962 | goto err_iounmap; | |
963 | } | |
964 | ||
965 | if (!priv->rf) { | |
966 | printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n", | |
967 | pci_name(pdev), rf_name); | |
968 | goto err_iounmap; | |
969 | } | |
970 | ||
971 | eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val); | |
972 | priv->csthreshold = eeprom_val >> 8; | |
973 | if (!priv->r8185) { | |
974 | __le32 anaparam; | |
975 | eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2); | |
976 | priv->anaparam = le32_to_cpu(anaparam); | |
977 | eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam); | |
978 | } | |
979 | ||
980 | eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)dev->wiphy->perm_addr, 3); | |
981 | if (!is_valid_ether_addr(dev->wiphy->perm_addr)) { | |
982 | printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using" | |
983 | " randomly generated MAC addr\n", pci_name(pdev)); | |
984 | random_ether_addr(dev->wiphy->perm_addr); | |
985 | } | |
986 | ||
987 | /* CCK TX power */ | |
988 | for (i = 0; i < 14; i += 2) { | |
989 | u16 txpwr; | |
990 | eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr); | |
8318d78a JB |
991 | priv->channels[i].hw_value = txpwr & 0xFF; |
992 | priv->channels[i + 1].hw_value = txpwr >> 8; | |
f6532111 MW |
993 | } |
994 | ||
995 | /* OFDM TX power */ | |
996 | if (priv->r8185) { | |
997 | for (i = 0; i < 14; i += 2) { | |
998 | u16 txpwr; | |
999 | eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr); | |
8318d78a JB |
1000 | priv->channels[i].hw_value |= (txpwr & 0xFF) << 8; |
1001 | priv->channels[i + 1].hw_value |= txpwr & 0xFF00; | |
f6532111 MW |
1002 | } |
1003 | } | |
1004 | ||
1005 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
1006 | ||
1007 | spin_lock_init(&priv->lock); | |
1008 | ||
1009 | err = ieee80211_register_hw(dev); | |
1010 | if (err) { | |
1011 | printk(KERN_ERR "%s (rtl8180): Cannot register device\n", | |
1012 | pci_name(pdev)); | |
1013 | goto err_iounmap; | |
1014 | } | |
1015 | ||
e174961c JB |
1016 | printk(KERN_INFO "%s: hwaddr %pM, %s + %s\n", |
1017 | wiphy_name(dev->wiphy), dev->wiphy->perm_addr, | |
f6532111 MW |
1018 | chip_name, priv->rf->name); |
1019 | ||
1020 | return 0; | |
1021 | ||
1022 | err_iounmap: | |
1023 | iounmap(priv->map); | |
1024 | ||
1025 | err_free_dev: | |
1026 | pci_set_drvdata(pdev, NULL); | |
1027 | ieee80211_free_hw(dev); | |
1028 | ||
1029 | err_free_reg: | |
1030 | pci_release_regions(pdev); | |
1031 | pci_disable_device(pdev); | |
1032 | return err; | |
1033 | } | |
1034 | ||
1035 | static void __devexit rtl8180_remove(struct pci_dev *pdev) | |
1036 | { | |
1037 | struct ieee80211_hw *dev = pci_get_drvdata(pdev); | |
1038 | struct rtl8180_priv *priv; | |
1039 | ||
1040 | if (!dev) | |
1041 | return; | |
1042 | ||
1043 | ieee80211_unregister_hw(dev); | |
1044 | ||
1045 | priv = dev->priv; | |
1046 | ||
1047 | pci_iounmap(pdev, priv->map); | |
1048 | pci_release_regions(pdev); | |
1049 | pci_disable_device(pdev); | |
1050 | ieee80211_free_hw(dev); | |
1051 | } | |
1052 | ||
1053 | #ifdef CONFIG_PM | |
1054 | static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state) | |
1055 | { | |
1056 | pci_save_state(pdev); | |
1057 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1058 | return 0; | |
1059 | } | |
1060 | ||
1061 | static int rtl8180_resume(struct pci_dev *pdev) | |
1062 | { | |
1063 | pci_set_power_state(pdev, PCI_D0); | |
1064 | pci_restore_state(pdev); | |
1065 | return 0; | |
1066 | } | |
1067 | ||
1068 | #endif /* CONFIG_PM */ | |
1069 | ||
1070 | static struct pci_driver rtl8180_driver = { | |
1071 | .name = KBUILD_MODNAME, | |
1072 | .id_table = rtl8180_table, | |
1073 | .probe = rtl8180_probe, | |
1074 | .remove = __devexit_p(rtl8180_remove), | |
1075 | #ifdef CONFIG_PM | |
1076 | .suspend = rtl8180_suspend, | |
1077 | .resume = rtl8180_resume, | |
1078 | #endif /* CONFIG_PM */ | |
1079 | }; | |
1080 | ||
1081 | static int __init rtl8180_init(void) | |
1082 | { | |
1083 | return pci_register_driver(&rtl8180_driver); | |
1084 | } | |
1085 | ||
1086 | static void __exit rtl8180_exit(void) | |
1087 | { | |
1088 | pci_unregister_driver(&rtl8180_driver); | |
1089 | } | |
1090 | ||
1091 | module_init(rtl8180_init); | |
1092 | module_exit(rtl8180_exit); |