]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/net/wireless/rtlwifi/pci.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rtlwifi: rtl8192c: rtl8192ce: Update to vendor driver of 2013.02.07
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rtlwifi / pci.c
CommitLineData
0c817338
LF		 1/******************************************************************************
2 *
a8d76066 3 * Copyright(c) 2009-2012 Realtek Corporation.
0c817338
LF		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
0c817338 30#include "wifi.h"
d273bb20 31#include "core.h"
0c817338
LF		 32#include "pci.h"
33#include "base.h"
34#include "ps.h"
c7cfe38e 35#include "efuse.h"
d273bb20 36#include <linux/export.h>
f11bbfd8 37#include <linux/kmemleak.h>
0c817338
LF		 38
39static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
f01dce94
JM		 40 PCI_VENDOR_ID_INTEL,
41 PCI_VENDOR_ID_ATI,
42 PCI_VENDOR_ID_AMD,
43 PCI_VENDOR_ID_SI
0c817338
LF		 44};
45
c7cfe38e
C		 46static const u8 ac_to_hwq[] = {
47 VO_QUEUE,
48 VI_QUEUE,
49 BE_QUEUE,
50 BK_QUEUE
51};
52
d3bb1429 53static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
c7cfe38e
C		 54 struct sk_buff *skb)
55{
56 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
d3bb1429 57 __le16 fc = rtl_get_fc(skb);
c7cfe38e
C		 58 u8 queue_index = skb_get_queue_mapping(skb);
59
60 if (unlikely(ieee80211_is_beacon(fc)))
61 return BEACON_QUEUE;
26634c4b 62 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
c7cfe38e
C		 63 return MGNT_QUEUE;
64 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
65 if (ieee80211_is_nullfunc(fc))
66 return HIGH_QUEUE;
67
68 return ac_to_hwq[queue_index];
69}
70
0c817338
LF		 71/* Update PCI dependent default settings*/
72static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
73{
74 struct rtl_priv *rtlpriv = rtl_priv(hw);
75 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
76 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
77 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
78 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
c7cfe38e 79 u8 init_aspm;
0c817338
LF		 80
81 ppsc->reg_rfps_level = 0;
3db1cd5c 82 ppsc->support_aspm = false;
0c817338
LF		 83
84 /*Update PCI ASPM setting */
85 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
86 switch (rtlpci->const_pci_aspm) {
87 case 0:
88 /*No ASPM */
89 break;
90
91 case 1:
92 /*ASPM dynamically enabled/disable. */
93 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
94 break;
95
96 case 2:
97 /*ASPM with Clock Req dynamically enabled/disable. */
98 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
99 RT_RF_OFF_LEVL_CLK_REQ);
100 break;
101
102 case 3:
103 /*
104 * Always enable ASPM and Clock Req
105 * from initialization to halt.
106 * */
107 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
108 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
109 RT_RF_OFF_LEVL_CLK_REQ);
110 break;
111
112 case 4:
113 /*
114 * Always enable ASPM without Clock Req
115 * from initialization to halt.
116 * */
117 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
118 RT_RF_OFF_LEVL_CLK_REQ);
119 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
120 break;
121 }
122
123 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
124
125 /*Update Radio OFF setting */
126 switch (rtlpci->const_hwsw_rfoff_d3) {
127 case 1:
128 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
129 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
130 break;
131
132 case 2:
133 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
134 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
135 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
136 break;
137
138 case 3:
139 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
140 break;
141 }
142
143 /*Set HW definition to determine if it supports ASPM. */
144 switch (rtlpci->const_support_pciaspm) {
c7cfe38e
C		 145 case 0:{
146 /*Not support ASPM. */
147 bool support_aspm = false;
148 ppsc->support_aspm = support_aspm;
149 break;
150 }
151 case 1:{
152 /*Support ASPM. */
153 bool support_aspm = true;
154 bool support_backdoor = true;
155 ppsc->support_aspm = support_aspm;
156
157 /*if (priv->oem_id == RT_CID_TOSHIBA &&
158 !priv->ndis_adapter.amd_l1_patch)
159 support_backdoor = false; */
160
161 ppsc->support_backdoor = support_backdoor;
162
163 break;
164 }
0c817338
LF		 165 case 2:
166 /*ASPM value set by chipset. */
c7cfe38e
C		 167 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
168 bool support_aspm = true;
169 ppsc->support_aspm = support_aspm;
170 }
0c817338
LF		 171 break;
172 default:
173 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 174 "switch case not processed\n");
0c817338
LF		 175 break;
176 }
c7cfe38e
C		 177
178 /* toshiba aspm issue, toshiba will set aspm selfly
179 * so we should not set aspm in driver */
180 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
181 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
182 init_aspm == 0x43)
183 ppsc->support_aspm = false;
184}
185
0c817338
LF		 186static bool _rtl_pci_platform_switch_device_pci_aspm(
187 struct ieee80211_hw *hw,
188 u8 value)
189{
190 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e
C		 191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
192
193 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
194 value |= 0x40;
0c817338 195
0c817338
LF		 196 pci_write_config_byte(rtlpci->pdev, 0x80, value);
197
32473284 198 return false;
0c817338
LF		 199}
200
201/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
1d73c51a 202static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
0c817338
LF		 203{
204 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e 205 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338 206
0c817338 207 pci_write_config_byte(rtlpci->pdev, 0x81, value);
0c817338 208
c7cfe38e
C		 209 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
210 udelay(100);
0c817338
LF		 211}
212
213/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
214static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
215{
216 struct rtl_priv *rtlpriv = rtl_priv(hw);
217 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
218 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
219 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
220 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 221 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
222 /*Retrieve original configuration settings. */
223 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
224 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
225 pcibridge_linkctrlreg;
226 u16 aspmlevel = 0;
32473284 227 u8 tmp_u1b = 0;
0c817338 228
c7cfe38e
C		 229 if (!ppsc->support_aspm)
230 return;
231
0c817338
LF		 232 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
233 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
f30d7507 234 "PCI(Bridge) UNKNOWN\n");
0c817338
LF		 235
236 return;
237 }
238
239 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
240 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
241 _rtl_pci_switch_clk_req(hw, 0x0);
242 }
243
32473284
LF		 244 /*for promising device will in L0 state after an I/O. */
245 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
0c817338
LF		 246
247 /*Set corresponding value. */
248 aspmlevel |= BIT(0) | BIT(1);
249 linkctrl_reg &= ~aspmlevel;
250 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
251
252 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
253 udelay(50);
254
255 /*4 Disable Pci Bridge ASPM */
886e14b6
LF		 256 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
257 pcibridge_linkctrlreg);
0c817338
LF		 258
259 udelay(50);
0c817338
LF		 260}
261
262/*
263 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
264 *power saving We should follow the sequence to enable
265 *RTL8192SE first then enable Pci Bridge ASPM
266 *or the system will show bluescreen.
267 */
268static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
269{
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
272 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
273 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338 274 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 275 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
276 u16 aspmlevel;
277 u8 u_pcibridge_aspmsetting;
278 u8 u_device_aspmsetting;
279
c7cfe38e
C		 280 if (!ppsc->support_aspm)
281 return;
282
0c817338
LF		 283 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
284 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
f30d7507 285 "PCI(Bridge) UNKNOWN\n");
0c817338
LF		 286 return;
287 }
288
289 /*4 Enable Pci Bridge ASPM */
0c817338
LF		 290
291 u_pcibridge_aspmsetting =
292 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
293 rtlpci->const_hostpci_aspm_setting;
294
295 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
296 u_pcibridge_aspmsetting &= ~BIT(0);
297
886e14b6
LF		 298 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
299 u_pcibridge_aspmsetting);
0c817338
LF		 300
301 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
26634c4b 302 "PlatformEnableASPM(): Write reg[%x] = %x\n",
f30d7507
JP		 303 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
304 u_pcibridge_aspmsetting);
0c817338
LF		 305
306 udelay(50);
307
308 /*Get ASPM level (with/without Clock Req) */
309 aspmlevel = rtlpci->const_devicepci_aspm_setting;
310 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
311
312 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
313 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
314
315 u_device_aspmsetting |= aspmlevel;
316
317 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
318
319 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
320 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
321 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
322 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
323 }
c7cfe38e 324 udelay(100);
0c817338
LF		 325}
326
327static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
328{
886e14b6 329 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338
LF		 330
331 bool status = false;
332 u8 offset_e0;
333 unsigned offset_e4;
334
886e14b6 335 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
0c817338 336
886e14b6 337 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
0c817338
LF		 338
339 if (offset_e0 == 0xA0) {
886e14b6 340 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
0c817338
LF		 341 if (offset_e4 & BIT(23))
342 status = true;
343 }
344
345 return status;
346}
347
26634c4b
LF		 348static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
349 struct rtl_priv **buddy_priv)
350{
351 struct rtl_priv *rtlpriv = rtl_priv(hw);
352 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
353 bool find_buddy_priv = false;
354 struct rtl_priv *tpriv = NULL;
355 struct rtl_pci_priv *tpcipriv = NULL;
356
357 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
358 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
359 list) {
360 if (tpriv) {
361 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
362 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
363 "pcipriv->ndis_adapter.funcnumber %x\n",
364 pcipriv->ndis_adapter.funcnumber);
365 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
366 "tpcipriv->ndis_adapter.funcnumber %x\n",
367 tpcipriv->ndis_adapter.funcnumber);
368
369 if ((pcipriv->ndis_adapter.busnumber ==
370 tpcipriv->ndis_adapter.busnumber) &&
371 (pcipriv->ndis_adapter.devnumber ==
372 tpcipriv->ndis_adapter.devnumber) &&
373 (pcipriv->ndis_adapter.funcnumber !=
374 tpcipriv->ndis_adapter.funcnumber)) {
375 find_buddy_priv = true;
376 break;
377 }
378 }
379 }
380 }
381
382 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
383 "find_buddy_priv %d\n", find_buddy_priv);
384
385 if (find_buddy_priv)
386 *buddy_priv = tpriv;
387
388 return find_buddy_priv;
389}
390
d3bb1429 391static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
0c817338
LF		 392{
393 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
886e14b6 394 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
0c817338 395 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
0c817338 396 u8 linkctrl_reg;
c7cfe38e 397 u8 num4bbytes;
0c817338 398
c7cfe38e 399 num4bbytes = (capabilityoffset + 0x10) / 4;
0c817338
LF		 400
401 /*Read Link Control Register */
886e14b6 402 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
0c817338
LF		 403
404 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
405}
406
407static void rtl_pci_parse_configuration(struct pci_dev *pdev,
408 struct ieee80211_hw *hw)
409{
410 struct rtl_priv *rtlpriv = rtl_priv(hw);
411 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
412
413 u8 tmp;
332badc3 414 u16 linkctrl_reg;
0c817338
LF		 415
416 /*Link Control Register */
332badc3
JL		 417 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
418 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
0c817338 419
f30d7507
JP		 420 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
421 pcipriv->ndis_adapter.linkctrl_reg);
0c817338
LF		 422
423 pci_read_config_byte(pdev, 0x98, &tmp);
424 tmp |= BIT(4);
425 pci_write_config_byte(pdev, 0x98, tmp);
426
427 tmp = 0x17;
428 pci_write_config_byte(pdev, 0x70f, tmp);
429}
430
c7cfe38e 431static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
0c817338
LF		 432{
433 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
434
435 _rtl_pci_update_default_setting(hw);
436
437 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
438 /*Always enable ASPM & Clock Req. */
439 rtl_pci_enable_aspm(hw);
440 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
441 }
442
443}
444
0c817338
LF		 445static void _rtl_pci_io_handler_init(struct device *dev,
446 struct ieee80211_hw *hw)
447{
448 struct rtl_priv *rtlpriv = rtl_priv(hw);
449
450 rtlpriv->io.dev = dev;
451
452 rtlpriv->io.write8_async = pci_write8_async;
453 rtlpriv->io.write16_async = pci_write16_async;
454 rtlpriv->io.write32_async = pci_write32_async;
455
456 rtlpriv->io.read8_sync = pci_read8_sync;
457 rtlpriv->io.read16_sync = pci_read16_sync;
458 rtlpriv->io.read32_sync = pci_read32_sync;
459
460}
461
c7cfe38e
C		 462static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
463 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
464{
465 struct rtl_priv *rtlpriv = rtl_priv(hw);
466 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
26634c4b 467 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
c7cfe38e 468 struct sk_buff *next_skb;
26634c4b 469 u8 additionlen = FCS_LEN;
c7cfe38e
C		 470
471 /* here open is 4, wep/tkip is 8, aes is 12*/
472 if (info->control.hw_key)
473 additionlen += info->control.hw_key->icv_len;
474
475 /* The most skb num is 6 */
476 tcb_desc->empkt_num = 0;
477 spin_lock_bh(&rtlpriv->locks.waitq_lock);
478 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
479 struct ieee80211_tx_info *next_info;
480
481 next_info = IEEE80211_SKB_CB(next_skb);
482 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
483 tcb_desc->empkt_len[tcb_desc->empkt_num] =
484 next_skb->len + additionlen;
485 tcb_desc->empkt_num++;
486 } else {
487 break;
488 }
489
490 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
491 next_skb))
492 break;
493
26634c4b 494 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
c7cfe38e
C		 495 break;
496 }
497 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
498
499 return true;
500}
501
502/* just for early mode now */
503static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
504{
505 struct rtl_priv *rtlpriv = rtl_priv(hw);
506 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
507 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
508 struct sk_buff *skb = NULL;
509 struct ieee80211_tx_info *info = NULL;
26634c4b 510 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
fb914ebf 511 int tid;
c7cfe38e
C		 512
513 if (!rtlpriv->rtlhal.earlymode_enable)
514 return;
515
26634c4b
LF		 516 if (rtlpriv->dm.supp_phymode_switch &&
517 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
518 (rtlpriv->buddy_priv &&
519 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
520 return;
c7cfe38e
C		 521 /* we juse use em for BE/BK/VI/VO */
522 for (tid = 7; tid >= 0; tid--) {
2a00def4 523 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
c7cfe38e
C		 524 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
525 while (!mac->act_scanning &&
526 rtlpriv->psc.rfpwr_state == ERFON) {
527 struct rtl_tcb_desc tcb_desc;
528 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
529
530 spin_lock_bh(&rtlpriv->locks.waitq_lock);
531 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
26634c4b
LF		 532 (ring->entries - skb_queue_len(&ring->queue) >
533 rtlhal->max_earlymode_num)) {
c7cfe38e
C		 534 skb = skb_dequeue(&mac->skb_waitq[tid]);
535 } else {
536 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
537 break;
538 }
539 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
540
541 /* Some macaddr can't do early mode. like
542 * multicast/broadcast/no_qos data */
543 info = IEEE80211_SKB_CB(skb);
544 if (info->flags & IEEE80211_TX_CTL_AMPDU)
545 _rtl_update_earlymode_info(hw, skb,
546 &tcb_desc, tid);
547
36323f81 548 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
c7cfe38e
C		 549 }
550 }
551}
552
553
0c817338
LF		 554static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
555{
556 struct rtl_priv *rtlpriv = rtl_priv(hw);
557 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
558
559 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
560
561 while (skb_queue_len(&ring->queue)) {
562 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
563 struct sk_buff *skb;
564 struct ieee80211_tx_info *info;
c7cfe38e
C		 565 __le16 fc;
566 u8 tid;
0c817338
LF		 567
568 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
569 HW_DESC_OWN);
570
26634c4b
LF		 571 /*beacon packet will only use the first
572 *descriptor by defaut, and the own may not
0c817338
LF		 573 *be cleared by the hardware
574 */
575 if (own)
576 return;
577 ring->idx = (ring->idx + 1) % ring->entries;
578
579 skb = __skb_dequeue(&ring->queue);
580 pci_unmap_single(rtlpci->pdev,
d3bb1429 581 rtlpriv->cfg->ops->
0c817338 582 get_desc((u8 *) entry, true,
d3bb1429 583 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 584 skb->len, PCI_DMA_TODEVICE);
585
c7cfe38e
C		 586 /* remove early mode header */
587 if (rtlpriv->rtlhal.earlymode_enable)
588 skb_pull(skb, EM_HDR_LEN);
589
0c817338 590 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
f30d7507
JP		 591 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
592 ring->idx,
593 skb_queue_len(&ring->queue),
594 *(u16 *) (skb->data + 22));
0c817338 595
c7cfe38e
C		 596 if (prio == TXCMD_QUEUE) {
597 dev_kfree_skb(skb);
598 goto tx_status_ok;
599
600 }
601
602 /* for sw LPS, just after NULL skb send out, we can
26634c4b
LF		 603 * sure AP knows we are sleeping, we should not let
604 * rf sleep
605 */
c7cfe38e
C		 606 fc = rtl_get_fc(skb);
607 if (ieee80211_is_nullfunc(fc)) {
608 if (ieee80211_has_pm(fc)) {
9c050440 609 rtlpriv->mac80211.offchan_delay = true;
3db1cd5c 610 rtlpriv->psc.state_inap = true;
c7cfe38e 611 } else {
3db1cd5c 612 rtlpriv->psc.state_inap = false;
c7cfe38e
C		 613 }
614 }
26634c4b
LF		 615 if (ieee80211_is_action(fc)) {
616 struct ieee80211_mgmt *action_frame =
617 (struct ieee80211_mgmt *)skb->data;
618 if (action_frame->u.action.u.ht_smps.action ==
619 WLAN_HT_ACTION_SMPS) {
620 dev_kfree_skb(skb);
621 goto tx_status_ok;
622 }
623 }
c7cfe38e
C		 624
625 /* update tid tx pkt num */
626 tid = rtl_get_tid(skb);
627 if (tid <= 7)
628 rtlpriv->link_info.tidtx_inperiod[tid]++;
629
0c817338
LF		 630 info = IEEE80211_SKB_CB(skb);
631 ieee80211_tx_info_clear_status(info);
632
633 info->flags |= IEEE80211_TX_STAT_ACK;
634 /*info->status.rates[0].count = 1; */
635
636 ieee80211_tx_status_irqsafe(hw, skb);
637
638 if ((ring->entries - skb_queue_len(&ring->queue))
639 == 2) {
640
641 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
f30d7507
JP		 642 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%d\n",
643 prio, ring->idx,
644 skb_queue_len(&ring->queue));
0c817338
LF		 645
646 ieee80211_wake_queue(hw,
647 skb_get_queue_mapping
648 (skb));
649 }
c7cfe38e 650tx_status_ok:
0c817338
LF		 651 skb = NULL;
652 }
653
654 if (((rtlpriv->link_info.num_rx_inperiod +
655 rtlpriv->link_info.num_tx_inperiod) > 8) ||
656 (rtlpriv->link_info.num_rx_inperiod > 2)) {
41affd52 657 schedule_work(&rtlpriv->works.lps_leave_work);
0c817338
LF		 658 }
659}
660
fd854772
MM		 661static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
662 struct ieee80211_rx_status rx_status)
663{
664 struct rtl_priv *rtlpriv = rtl_priv(hw);
665 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
666 __le16 fc = rtl_get_fc(skb);
667 bool unicast = false;
668 struct sk_buff *uskb = NULL;
669 u8 *pdata;
670
671
672 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
673
674 if (is_broadcast_ether_addr(hdr->addr1)) {
675 ;/*TODO*/
676 } else if (is_multicast_ether_addr(hdr->addr1)) {
677 ;/*TODO*/
678 } else {
679 unicast = true;
680 rtlpriv->stats.rxbytesunicast += skb->len;
681 }
682
683 rtl_is_special_data(hw, skb, false);
684
685 if (ieee80211_is_data(fc)) {
686 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
687
688 if (unicast)
689 rtlpriv->link_info.num_rx_inperiod++;
690 }
691
26634c4b
LF		 692 /* static bcn for roaming */
693 rtl_beacon_statistic(hw, skb);
694 rtl_p2p_info(hw, (void *)skb->data, skb->len);
695
fd854772
MM		 696 /* for sw lps */
697 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
698 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
699 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
700 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
701 (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
702 return;
703
704 if (unlikely(!rtl_action_proc(hw, skb, false)))
705 return;
706
707 uskb = dev_alloc_skb(skb->len + 128);
76a92be5
LF		 708 if (!uskb)
709 return; /* exit if allocation failed */
fd854772
MM		 710 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
711 pdata = (u8 *)skb_put(uskb, skb->len);
712 memcpy(pdata, skb->data, skb->len);
713
714 ieee80211_rx_irqsafe(hw, uskb);
715}
716
0c817338
LF		 717static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
718{
719 struct rtl_priv *rtlpriv = rtl_priv(hw);
720 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
721 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
722
723 struct ieee80211_rx_status rx_status = { 0 };
724 unsigned int count = rtlpci->rxringcount;
725 u8 own;
726 u8 tmp_one;
727 u32 bufferaddress;
0c817338
LF		 728
729 struct rtl_stats stats = {
730 .signal = 0,
731 .noise = -98,
732 .rate = 0,
733 };
34ddb207 734 int index = rtlpci->rx_ring[rx_queue_idx].idx;
0c817338
LF		 735
736 /*RX NORMAL PKT */
737 while (count--) {
738 /*rx descriptor */
739 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
34ddb207 740 index];
0c817338
LF		 741 /*rx pkt */
742 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
34ddb207 743 index];
2c333366 744 struct sk_buff *new_skb = NULL;
0c817338
LF		 745
746 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
747 false, HW_DESC_OWN);
748
2c333366
MM		 749 /*wait data to be filled by hardware */
750 if (own)
34ddb207 751 break;
6633d649 752
2c333366
MM		 753 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
754 &rx_status,
755 (u8 *) pdesc, skb);
756
8db8ddf1
MM		 757 if (stats.crc || stats.hwerror)
758 goto done;
759
2c333366
MM		 760 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
761 if (unlikely(!new_skb)) {
f30d7507
JP		 762 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV), DBG_DMESG,
763 "can't alloc skb for rx\n");
2c333366
MM		 764 goto done;
765 }
766
767 pci_unmap_single(rtlpci->pdev,
768 *((dma_addr_t *) skb->cb),
769 rtlpci->rxbuffersize,
770 PCI_DMA_FROMDEVICE);
771
772 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
773 HW_DESC_RXPKT_LEN));
774 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
775
776 /*
777 * NOTICE This can not be use for mac80211,
778 * this is done in mac80211 code,
779 * if you done here sec DHCP will fail
780 * skb_trim(skb, skb->len - 4);
781 */
782
fd854772 783 _rtl_receive_one(hw, skb, rx_status);
0c817338 784
2c333366
MM		 785 if (((rtlpriv->link_info.num_rx_inperiod +
786 rtlpriv->link_info.num_tx_inperiod) > 8) ||
787 (rtlpriv->link_info.num_rx_inperiod > 2)) {
41affd52 788 schedule_work(&rtlpriv->works.lps_leave_work);
2c333366 789 }
0c817338 790
14058add 791 dev_kfree_skb_any(skb);
2c333366 792 skb = new_skb;
0c817338 793
2c333366
MM		 794 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
795 *((dma_addr_t *) skb->cb) =
0c817338
LF		 796 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
797 rtlpci->rxbuffersize,
798 PCI_DMA_FROMDEVICE);
799
0c817338 800done:
d3bb1429 801 bufferaddress = (*((dma_addr_t *)skb->cb));
86bfec8d
LF		 802 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
803 return;
0c817338
LF		 804 tmp_one = 1;
805 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
806 HW_DESC_RXBUFF_ADDR,
807 (u8 *)&bufferaddress);
0c817338
LF		 808 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
809 HW_DESC_RXPKT_LEN,
810 (u8 *)&rtlpci->rxbuffersize);
811
34ddb207 812 if (index == rtlpci->rxringcount - 1)
0c817338
LF		 813 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
814 HW_DESC_RXERO,
2c208890 815 &tmp_one);
0c817338 816
febc9fe5 817 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
2c208890 818 &tmp_one);
febc9fe5 819
34ddb207 820 index = (index + 1) % rtlpci->rxringcount;
0c817338
LF		 821 }
822
34ddb207 823 rtlpci->rx_ring[rx_queue_idx].idx = index;
0c817338
LF		 824}
825
0c817338
LF		 826static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
827{
828 struct ieee80211_hw *hw = dev_id;
829 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 830 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 831 unsigned long flags;
832 u32 inta = 0;
833 u32 intb = 0;
de2e56ce 834 irqreturn_t ret = IRQ_HANDLED;
0c817338 835
0c817338
LF		 836 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
837
838 /*read ISR: 4/8bytes */
839 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
840
841 /*Shared IRQ or HW disappared */
de2e56ce
LF		 842 if (!inta || inta == 0xffff) {
843 ret = IRQ_NONE;
0c817338 844 goto done;
de2e56ce 845 }
0c817338
LF		 846
847 /*<1> beacon related */
848 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
849 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 850 "beacon ok interrupt!\n");
0c817338
LF		 851 }
852
853 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
854 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 855 "beacon err interrupt!\n");
0c817338
LF		 856 }
857
858 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
f30d7507 859 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
0c817338
LF		 860 }
861
862 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
863 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 864 "prepare beacon for interrupt!\n");
0c817338
LF		 865 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
866 }
867
868 /*<3> Tx related */
869 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
f30d7507 870 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
0c817338
LF		 871
872 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
873 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 874 "Manage ok interrupt!\n");
0c817338
LF		 875 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
876 }
877
878 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
879 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 880 "HIGH_QUEUE ok interrupt!\n");
0c817338
LF		 881 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
882 }
883
884 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
885 rtlpriv->link_info.num_tx_inperiod++;
886
887 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 888 "BK Tx OK interrupt!\n");
0c817338
LF		 889 _rtl_pci_tx_isr(hw, BK_QUEUE);
890 }
891
892 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
893 rtlpriv->link_info.num_tx_inperiod++;
894
895 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 896 "BE TX OK interrupt!\n");
0c817338
LF		 897 _rtl_pci_tx_isr(hw, BE_QUEUE);
898 }
899
900 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
901 rtlpriv->link_info.num_tx_inperiod++;
902
903 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 904 "VI TX OK interrupt!\n");
0c817338
LF		 905 _rtl_pci_tx_isr(hw, VI_QUEUE);
906 }
907
908 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
909 rtlpriv->link_info.num_tx_inperiod++;
910
911 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 912 "Vo TX OK interrupt!\n");
0c817338
LF		 913 _rtl_pci_tx_isr(hw, VO_QUEUE);
914 }
915
c7cfe38e
C		 916 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
917 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
918 rtlpriv->link_info.num_tx_inperiod++;
919
920 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 921 "CMD TX OK interrupt!\n");
c7cfe38e
C		 922 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
923 }
924 }
925
0c817338
LF		 926 /*<2> Rx related */
927 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
f30d7507 928 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
c7cfe38e 929 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 930 }
931
932 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
933 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 934 "rx descriptor unavailable!\n");
c7cfe38e 935 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 936 }
937
938 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
f30d7507 939 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
c7cfe38e 940 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 941 }
942
26634c4b
LF		 943 /*fw related*/
944 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
945 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
946 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
947 "firmware interrupt!\n");
948 queue_delayed_work(rtlpriv->works.rtl_wq,
949 &rtlpriv->works.fwevt_wq, 0);
950 }
951 }
952
c7cfe38e
C		 953 if (rtlpriv->rtlhal.earlymode_enable)
954 tasklet_schedule(&rtlpriv->works.irq_tasklet);
955
0c817338
LF		 956done:
957 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
de2e56ce 958 return ret;
0c817338
LF		 959}
960
961static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
962{
c7cfe38e 963 _rtl_pci_tx_chk_waitq(hw);
0c817338
LF		 964}
965
966static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
967{
968 struct rtl_priv *rtlpriv = rtl_priv(hw);
969 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
970 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e 971 struct rtl8192_tx_ring *ring = NULL;
0c817338
LF		 972 struct ieee80211_hdr *hdr = NULL;
973 struct ieee80211_tx_info *info = NULL;
974 struct sk_buff *pskb = NULL;
975 struct rtl_tx_desc *pdesc = NULL;
c7cfe38e 976 struct rtl_tcb_desc tcb_desc;
0c817338
LF		 977 u8 temp_one = 1;
978
c7cfe38e 979 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
0c817338
LF		 980 ring = &rtlpci->tx_ring[BEACON_QUEUE];
981 pskb = __skb_dequeue(&ring->queue);
a75e2ad7
LF		 982 if (pskb) {
983 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
984 pci_unmap_single(rtlpci->pdev, rtlpriv->cfg->ops->get_desc(
985 (u8 *) entry, true, HW_DESC_TXBUFF_ADDR),
986 pskb->len, PCI_DMA_TODEVICE);
0c817338 987 kfree_skb(pskb);
a75e2ad7 988 }
0c817338
LF		 989
990 /*NB: the beacon data buffer must be 32-bit aligned. */
991 pskb = ieee80211_beacon_get(hw, mac->vif);
992 if (pskb == NULL)
993 return;
c7cfe38e 994 hdr = rtl_get_hdr(pskb);
0c817338 995 info = IEEE80211_SKB_CB(pskb);
0c817338
LF		 996 pdesc = &ring->desc[0];
997 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
36323f81 998 info, NULL, pskb, BEACON_QUEUE, &tcb_desc);
0c817338
LF		 999
1000 __skb_queue_tail(&ring->queue, pskb);
1001
1002 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
2c208890 1003 &temp_one);
0c817338
LF		 1004
1005 return;
1006}
1007
41affd52
SG		 1008static void rtl_lps_leave_work_callback(struct work_struct *work)
1009{
1010 struct rtl_works *rtlworks =
1011 container_of(work, struct rtl_works, lps_leave_work);
1012 struct ieee80211_hw *hw = rtlworks->hw;
1013
1014 rtl_lps_leave(hw);
1015}
1016
0c817338
LF		 1017static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1018{
1019 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1020 u8 i;
1021
1022 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1023 rtlpci->txringcount[i] = RT_TXDESC_NUM;
1024
1025 /*
1026 *we just alloc 2 desc for beacon queue,
1027 *because we just need first desc in hw beacon.
1028 */
1029 rtlpci->txringcount[BEACON_QUEUE] = 2;
1030
1031 /*
1032 *BE queue need more descriptor for performance
1033 *consideration or, No more tx desc will happen,
1034 *and may cause mac80211 mem leakage.
1035 */
1036 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1037
1038 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1039 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1040}
1041
1042static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1043 struct pci_dev *pdev)
1044{
1045 struct rtl_priv *rtlpriv = rtl_priv(hw);
1046 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1047 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1048 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 1049
1050 rtlpci->up_first_time = true;
1051 rtlpci->being_init_adapter = false;
1052
1053 rtlhal->hw = hw;
1054 rtlpci->pdev = pdev;
1055
0c817338
LF		 1056 /*Tx/Rx related var */
1057 _rtl_pci_init_trx_var(hw);
1058
c7cfe38e 1059 /*IBSS*/ mac->beacon_interval = 100;
0c817338 1060
c7cfe38e
C		 1061 /*AMPDU*/
1062 mac->min_space_cfg = 0;
0c817338
LF		 1063 mac->max_mss_density = 0;
1064 /*set sane AMPDU defaults */
1065 mac->current_ampdu_density = 7;
1066 mac->current_ampdu_factor = 3;
1067
c7cfe38e
C		 1068 /*QOS*/
1069 rtlpci->acm_method = eAcmWay2_SW;
0c817338
LF		 1070
1071 /*task */
1072 tasklet_init(&rtlpriv->works.irq_tasklet,
1073 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1074 (unsigned long)hw);
1075 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1076 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1077 (unsigned long)hw);
41affd52 1078 INIT_WORK(&rtlpriv->works.lps_leave_work, rtl_lps_leave_work_callback);
0c817338
LF		 1079}
1080
1081static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1082 unsigned int prio, unsigned int entries)
1083{
1084 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1085 struct rtl_priv *rtlpriv = rtl_priv(hw);
1086 struct rtl_tx_desc *ring;
1087 dma_addr_t dma;
1088 u32 nextdescaddress;
1089 int i;
1090
1091 ring = pci_alloc_consistent(rtlpci->pdev,
1092 sizeof(*ring) * entries, &dma);
1093
1094 if (!ring || (unsigned long)ring & 0xFF) {
1095 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1096 "Cannot allocate TX ring (prio = %d)\n", prio);
0c817338
LF		 1097 return -ENOMEM;
1098 }
1099
1100 memset(ring, 0, sizeof(*ring) * entries);
1101 rtlpci->tx_ring[prio].desc = ring;
1102 rtlpci->tx_ring[prio].dma = dma;
1103 rtlpci->tx_ring[prio].idx = 0;
1104 rtlpci->tx_ring[prio].entries = entries;
1105 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1106
f30d7507
JP		 1107 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1108 prio, ring);
0c817338
LF		 1109
1110 for (i = 0; i < entries; i++) {
d3bb1429 1111 nextdescaddress = (u32) dma +
982d96bb 1112 ((i + 1) % entries) *
d3bb1429 1113 sizeof(*ring);
0c817338
LF		 1114
1115 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1116 true, HW_DESC_TX_NEXTDESC_ADDR,
1117 (u8 *)&nextdescaddress);
1118 }
1119
1120 return 0;
1121}
1122
1123static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1124{
1125 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1126 struct rtl_priv *rtlpriv = rtl_priv(hw);
1127 struct rtl_rx_desc *entry = NULL;
1128 int i, rx_queue_idx;
1129 u8 tmp_one = 1;
1130
1131 /*
1132 *rx_queue_idx 0:RX_MPDU_QUEUE
1133 *rx_queue_idx 1:RX_CMD_QUEUE
1134 */
1135 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1136 rx_queue_idx++) {
1137 rtlpci->rx_ring[rx_queue_idx].desc =
1138 pci_alloc_consistent(rtlpci->pdev,
1139 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1140 desc) * rtlpci->rxringcount,
1141 &rtlpci->rx_ring[rx_queue_idx].dma);
1142
1143 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1144 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1145 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1146 "Cannot allocate RX ring\n");
0c817338
LF		 1147 return -ENOMEM;
1148 }
1149
1150 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1151 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1152 rtlpci->rxringcount);
1153
1154 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1155
0019a2c9
LF		 1156 /* If amsdu_8k is disabled, set buffersize to 4096. This
1157 * change will reduce memory fragmentation.
1158 */
1159 if (rtlpci->rxbuffersize > 4096 &&
1160 rtlpriv->rtlhal.disable_amsdu_8k)
1161 rtlpci->rxbuffersize = 4096;
1162
0c817338
LF		 1163 for (i = 0; i < rtlpci->rxringcount; i++) {
1164 struct sk_buff *skb =
1165 dev_alloc_skb(rtlpci->rxbuffersize);
1166 u32 bufferaddress;
0c817338
LF		 1167 if (!skb)
1168 return 0;
f11bbfd8 1169 kmemleak_not_leak(skb);
bdc4bf65 1170 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
0c817338
LF		 1171
1172 /*skb->dev = dev; */
1173
1174 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1175
1176 /*
1177 *just set skb->cb to mapping addr
1178 *for pci_unmap_single use
1179 */
1180 *((dma_addr_t *) skb->cb) =
1181 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1182 rtlpci->rxbuffersize,
1183 PCI_DMA_FROMDEVICE);
1184
d3bb1429 1185 bufferaddress = (*((dma_addr_t *)skb->cb));
86bfec8d
LF		 1186 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) {
1187 dev_kfree_skb_any(skb);
1188 return 1;
1189 }
0c817338
LF		 1190 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1191 HW_DESC_RXBUFF_ADDR,
1192 (u8 *)&bufferaddress);
1193 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1194 HW_DESC_RXPKT_LEN,
1195 (u8 *)&rtlpci->
1196 rxbuffersize);
1197 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1198 HW_DESC_RXOWN,
2c208890 1199 &tmp_one);
0c817338
LF		 1200 }
1201
1202 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
2c208890 1203 HW_DESC_RXERO, &tmp_one);
0c817338
LF		 1204 }
1205 return 0;
1206}
1207
1208static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1209 unsigned int prio)
1210{
1211 struct rtl_priv *rtlpriv = rtl_priv(hw);
1212 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1213 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1214
1215 while (skb_queue_len(&ring->queue)) {
1216 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1217 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1218
1219 pci_unmap_single(rtlpci->pdev,
d3bb1429 1220 rtlpriv->cfg->
0c817338 1221 ops->get_desc((u8 *) entry, true,
d3bb1429 1222 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 1223 skb->len, PCI_DMA_TODEVICE);
1224 kfree_skb(skb);
1225 ring->idx = (ring->idx + 1) % ring->entries;
1226 }
1227
7f66c2f9
SG		 1228 if (ring->desc) {
1229 pci_free_consistent(rtlpci->pdev,
1230 sizeof(*ring->desc) * ring->entries,
1231 ring->desc, ring->dma);
1232 ring->desc = NULL;
1233 }
0c817338
LF		 1234}
1235
1236static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1237{
1238 int i, rx_queue_idx;
1239
1240 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1241 /*rx_queue_idx 1:RX_CMD_QUEUE */
1242 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1243 rx_queue_idx++) {
1244 for (i = 0; i < rtlpci->rxringcount; i++) {
1245 struct sk_buff *skb =
1246 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1247 if (!skb)
1248 continue;
1249
1250 pci_unmap_single(rtlpci->pdev,
1251 *((dma_addr_t *) skb->cb),
1252 rtlpci->rxbuffersize,
1253 PCI_DMA_FROMDEVICE);
1254 kfree_skb(skb);
1255 }
1256
7f66c2f9
SG		 1257 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1258 pci_free_consistent(rtlpci->pdev,
0c817338
LF		 1259 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1260 desc) * rtlpci->rxringcount,
1261 rtlpci->rx_ring[rx_queue_idx].desc,
1262 rtlpci->rx_ring[rx_queue_idx].dma);
7f66c2f9
SG		 1263 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1264 }
0c817338
LF		 1265 }
1266}
1267
1268static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1269{
1270 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1271 int ret;
1272 int i;
1273
1274 ret = _rtl_pci_init_rx_ring(hw);
1275 if (ret)
1276 return ret;
1277
1278 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1279 ret = _rtl_pci_init_tx_ring(hw, i,
1280 rtlpci->txringcount[i]);
1281 if (ret)
1282 goto err_free_rings;
1283 }
1284
1285 return 0;
1286
1287err_free_rings:
1288 _rtl_pci_free_rx_ring(rtlpci);
1289
1290 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1291 if (rtlpci->tx_ring[i].desc)
1292 _rtl_pci_free_tx_ring(hw, i);
1293
1294 return 1;
1295}
1296
1297static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1298{
1299 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1300 u32 i;
1301
1302 /*free rx rings */
1303 _rtl_pci_free_rx_ring(rtlpci);
1304
1305 /*free tx rings */
1306 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1307 _rtl_pci_free_tx_ring(hw, i);
1308
1309 return 0;
1310}
1311
1312int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1313{
1314 struct rtl_priv *rtlpriv = rtl_priv(hw);
1315 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1316 int i, rx_queue_idx;
1317 unsigned long flags;
1318 u8 tmp_one = 1;
1319
1320 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1321 /*rx_queue_idx 1:RX_CMD_QUEUE */
1322 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1323 rx_queue_idx++) {
1324 /*
1325 *force the rx_ring[RX_MPDU_QUEUE/
1326 *RX_CMD_QUEUE].idx to the first one
1327 */
1328 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1329 struct rtl_rx_desc *entry = NULL;
1330
1331 for (i = 0; i < rtlpci->rxringcount; i++) {
1332 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1333 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1334 false,
1335 HW_DESC_RXOWN,
2c208890 1336 &tmp_one);
0c817338
LF		 1337 }
1338 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1339 }
1340 }
1341
1342 /*
1343 *after reset, release previous pending packet,
1344 *and force the tx idx to the first one
1345 */
0c817338
LF		 1346 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1347 if (rtlpci->tx_ring[i].desc) {
1348 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1349
1350 while (skb_queue_len(&ring->queue)) {
5a2766ab
LF		 1351 struct rtl_tx_desc *entry;
1352 struct sk_buff *skb;
0c817338 1353
5a2766ab
LF		 1354 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock,
1355 flags);
1356 entry = &ring->desc[ring->idx];
1357 skb = __skb_dequeue(&ring->queue);
0c817338 1358 pci_unmap_single(rtlpci->pdev,
d3bb1429 1359 rtlpriv->cfg->ops->
0c817338
LF		 1360 get_desc((u8 *)
1361 entry,
1362 true,
d3bb1429 1363 HW_DESC_TXBUFF_ADDR),
0c817338 1364 skb->len, PCI_DMA_TODEVICE);
0c817338 1365 ring->idx = (ring->idx + 1) % ring->entries;
5a2766ab
LF		 1366 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1367 flags);
1368 kfree_skb(skb);
0c817338
LF		 1369 }
1370 ring->idx = 0;
1371 }
1372 }
1373
0c817338
LF		 1374 return 0;
1375}
1376
c7cfe38e 1377static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
36323f81 1378 struct ieee80211_sta *sta,
c7cfe38e 1379 struct sk_buff *skb)
0c817338 1380{
c7cfe38e 1381 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e
C		 1382 struct rtl_sta_info *sta_entry = NULL;
1383 u8 tid = rtl_get_tid(skb);
0f015453 1384 __le16 fc = rtl_get_fc(skb);
c7cfe38e
C		 1385
1386 if (!sta)
1387 return false;
1388 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1389
1390 if (!rtlpriv->rtlhal.earlymode_enable)
1391 return false;
0f015453
LF		 1392 if (ieee80211_is_nullfunc(fc))
1393 return false;
1394 if (ieee80211_is_qos_nullfunc(fc))
1395 return false;
1396 if (ieee80211_is_pspoll(fc))
1397 return false;
c7cfe38e
C		 1398 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1399 return false;
1400 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1401 return false;
1402 if (tid > 7)
1403 return false;
1404
1405 /* maybe every tid should be checked */
1406 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1407 return false;
1408
1409 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1410 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1411 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
0c817338 1412
c7cfe38e 1413 return true;
0c817338
LF		 1414}
1415
36323f81
TH		 1416static int rtl_pci_tx(struct ieee80211_hw *hw,
1417 struct ieee80211_sta *sta,
1418 struct sk_buff *skb,
1419 struct rtl_tcb_desc *ptcb_desc)
0c817338
LF		 1420{
1421 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 1422 struct rtl_sta_info *sta_entry = NULL;
0c817338
LF		 1423 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1424 struct rtl8192_tx_ring *ring;
1425 struct rtl_tx_desc *pdesc;
1426 u8 idx;
c7cfe38e 1427 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
0c817338 1428 unsigned long flags;
c7cfe38e
C		 1429 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1430 __le16 fc = rtl_get_fc(skb);
0c817338
LF		 1431 u8 *pda_addr = hdr->addr1;
1432 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1433 /*ssn */
0c817338
LF		 1434 u8 tid = 0;
1435 u16 seq_number = 0;
1436 u8 own;
1437 u8 temp_one = 1;
1438
0f015453
LF		 1439 if (ieee80211_is_mgmt(fc))
1440 rtl_tx_mgmt_proc(hw, skb);
c7cfe38e
C		 1441
1442 if (rtlpriv->psc.sw_ps_enabled) {
1443 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1444 !ieee80211_has_pm(fc))
1445 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1446 }
0c817338 1447
c7cfe38e 1448 rtl_action_proc(hw, skb, true);
0c817338
LF		 1449
1450 if (is_multicast_ether_addr(pda_addr))
1451 rtlpriv->stats.txbytesmulticast += skb->len;
1452 else if (is_broadcast_ether_addr(pda_addr))
1453 rtlpriv->stats.txbytesbroadcast += skb->len;
1454 else
1455 rtlpriv->stats.txbytesunicast += skb->len;
1456
1457 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0c817338
LF		 1458 ring = &rtlpci->tx_ring[hw_queue];
1459 if (hw_queue != BEACON_QUEUE)
1460 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1461 ring->entries;
1462 else
1463 idx = 0;
1464
1465 pdesc = &ring->desc[idx];
1466 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1467 true, HW_DESC_OWN);
1468
1469 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1470 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 1471 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1472 hw_queue, ring->idx, idx,
1473 skb_queue_len(&ring->queue));
0c817338
LF		 1474
1475 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1476 return skb->len;
1477 }
1478
0c817338 1479 if (ieee80211_is_data_qos(fc)) {
c7cfe38e
C		 1480 tid = rtl_get_tid(skb);
1481 if (sta) {
1482 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1483 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1484 IEEE80211_SCTL_SEQ) >> 4;
1485 seq_number += 1;
1486
1487 if (!ieee80211_has_morefrags(hdr->frame_control))
1488 sta_entry->tids[tid].seq_number = seq_number;
1489 }
0c817338
LF		 1490 }
1491
1492 if (ieee80211_is_data(fc))
1493 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1494
c7cfe38e 1495 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
36323f81 1496 info, sta, skb, hw_queue, ptcb_desc);
0c817338
LF		 1497
1498 __skb_queue_tail(&ring->queue, skb);
1499
c7cfe38e 1500 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
2c208890 1501 HW_DESC_OWN, &temp_one);
0c817338 1502
0c817338
LF		 1503
1504 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1505 hw_queue != BEACON_QUEUE) {
1506
1507 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
f30d7507
JP		 1508 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1509 hw_queue, ring->idx, idx,
1510 skb_queue_len(&ring->queue));
0c817338
LF		 1511
1512 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1513 }
1514
1515 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1516
1517 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1518
1519 return 0;
1520}
1521
c7cfe38e
C		 1522static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1523{
1524 struct rtl_priv *rtlpriv = rtl_priv(hw);
1525 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1526 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
26634c4b 1527 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e
C		 1528 u16 i = 0;
1529 int queue_id;
1530 struct rtl8192_tx_ring *ring;
1531
26634c4b
LF		 1532 if (mac->skip_scan)
1533 return;
1534
c7cfe38e
C		 1535 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1536 u32 queue_len;
1537 ring = &pcipriv->dev.tx_ring[queue_id];
1538 queue_len = skb_queue_len(&ring->queue);
1539 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1540 queue_id == TXCMD_QUEUE) {
1541 queue_id--;
1542 continue;
1543 } else {
1544 msleep(20);
1545 i++;
1546 }
1547
1548 /* we just wait 1s for all queues */
1549 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1550 is_hal_stop(rtlhal) || i >= 200)
1551 return;
1552 }
1553}
1554
d3bb1429 1555static void rtl_pci_deinit(struct ieee80211_hw *hw)
0c817338
LF		 1556{
1557 struct rtl_priv *rtlpriv = rtl_priv(hw);
1558 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1559
1560 _rtl_pci_deinit_trx_ring(hw);
1561
1562 synchronize_irq(rtlpci->pdev->irq);
1563 tasklet_kill(&rtlpriv->works.irq_tasklet);
41affd52 1564 cancel_work_sync(&rtlpriv->works.lps_leave_work);
0c817338
LF		 1565
1566 flush_workqueue(rtlpriv->works.rtl_wq);
1567 destroy_workqueue(rtlpriv->works.rtl_wq);
1568
1569}
1570
d3bb1429 1571static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
0c817338
LF		 1572{
1573 struct rtl_priv *rtlpriv = rtl_priv(hw);
1574 int err;
1575
1576 _rtl_pci_init_struct(hw, pdev);
1577
1578 err = _rtl_pci_init_trx_ring(hw);
1579 if (err) {
1580 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1581 "tx ring initialization failed\n");
12325280 1582 return err;
0c817338
LF		 1583 }
1584
12325280 1585 return 0;
0c817338
LF		 1586}
1587
d3bb1429 1588static int rtl_pci_start(struct ieee80211_hw *hw)
0c817338
LF		 1589{
1590 struct rtl_priv *rtlpriv = rtl_priv(hw);
1591 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1592 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1593 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1594
1595 int err;
1596
1597 rtl_pci_reset_trx_ring(hw);
1598
1599 rtlpci->driver_is_goingto_unload = false;
1600 err = rtlpriv->cfg->ops->hw_init(hw);
1601 if (err) {
1602 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507 1603 "Failed to config hardware!\n");
0c817338
LF		 1604 return err;
1605 }
1606
1607 rtlpriv->cfg->ops->enable_interrupt(hw);
f30d7507 1608 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
0c817338
LF		 1609
1610 rtl_init_rx_config(hw);
1611
fb914ebf 1612 /*should be after adapter start and interrupt enable. */
0c817338
LF		 1613 set_hal_start(rtlhal);
1614
1615 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1616
1617 rtlpci->up_first_time = false;
1618
f30d7507 1619 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
0c817338
LF		 1620 return 0;
1621}
1622
d3bb1429 1623static void rtl_pci_stop(struct ieee80211_hw *hw)
0c817338
LF		 1624{
1625 struct rtl_priv *rtlpriv = rtl_priv(hw);
1626 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1627 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1628 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1629 unsigned long flags;
1630 u8 RFInProgressTimeOut = 0;
1631
1632 /*
fb914ebf 1633 *should be before disable interrupt&adapter
0c817338
LF		 1634 *and will do it immediately.
1635 */
1636 set_hal_stop(rtlhal);
1637
1638 rtlpriv->cfg->ops->disable_interrupt(hw);
41affd52 1639 cancel_work_sync(&rtlpriv->works.lps_leave_work);
0c817338
LF		 1640
1641 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1642 while (ppsc->rfchange_inprogress) {
1643 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1644 if (RFInProgressTimeOut > 100) {
1645 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1646 break;
1647 }
1648 mdelay(1);
1649 RFInProgressTimeOut++;
1650 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1651 }
1652 ppsc->rfchange_inprogress = true;
1653 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1654
1655 rtlpci->driver_is_goingto_unload = true;
1656 rtlpriv->cfg->ops->hw_disable(hw);
b0302aba
LF		 1657 /* some things are not needed if firmware not available */
1658 if (!rtlpriv->max_fw_size)
1659 return;
0c817338
LF		 1660 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1661
1662 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1663 ppsc->rfchange_inprogress = false;
1664 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1665
1666 rtl_pci_enable_aspm(hw);
1667}
1668
1669static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1670 struct ieee80211_hw *hw)
1671{
1672 struct rtl_priv *rtlpriv = rtl_priv(hw);
1673 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1674 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1675 struct pci_dev *bridge_pdev = pdev->bus->self;
1676 u16 venderid;
1677 u16 deviceid;
c7cfe38e 1678 u8 revisionid;
0c817338
LF		 1679 u16 irqline;
1680 u8 tmp;
1681
fc7707a4 1682 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
0c817338
LF		 1683 venderid = pdev->vendor;
1684 deviceid = pdev->device;
c7cfe38e 1685 pci_read_config_byte(pdev, 0x8, &revisionid);
0c817338
LF		 1686 pci_read_config_word(pdev, 0x3C, &irqline);
1687
fa7ccfb1
LF		 1688 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1689 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1690 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1691 * the correct driver is r8192e_pci, thus this routine should
1692 * return false.
1693 */
1694 if (deviceid == RTL_PCI_8192SE_DID &&
1695 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1696 return false;
1697
0c817338
LF		 1698 if (deviceid == RTL_PCI_8192_DID ||
1699 deviceid == RTL_PCI_0044_DID ||
1700 deviceid == RTL_PCI_0047_DID ||
1701 deviceid == RTL_PCI_8192SE_DID ||
1702 deviceid == RTL_PCI_8174_DID ||
1703 deviceid == RTL_PCI_8173_DID ||
1704 deviceid == RTL_PCI_8172_DID ||
1705 deviceid == RTL_PCI_8171_DID) {
c7cfe38e 1706 switch (revisionid) {
0c817338
LF		 1707 case RTL_PCI_REVISION_ID_8192PCIE:
1708 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1709 "8192 PCI-E is found - vid/did=%x/%x\n",
1710 venderid, deviceid);
0c817338 1711 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
0f015453 1712 return false;
0c817338
LF		 1713 case RTL_PCI_REVISION_ID_8192SE:
1714 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1715 "8192SE is found - vid/did=%x/%x\n",
1716 venderid, deviceid);
0c817338
LF		 1717 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1718 break;
1719 default:
1720 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 1721 "Err: Unknown device - vid/did=%x/%x\n",
1722 venderid, deviceid);
0c817338
LF		 1723 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1724 break;
1725
1726 }
0f015453
LF		 1727 } else if (deviceid == RTL_PCI_8723AE_DID) {
1728 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1729 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1730 "8723AE PCI-E is found - "
1731 "vid/did=%x/%x\n", venderid, deviceid);
0c817338
LF		 1732 } else if (deviceid == RTL_PCI_8192CET_DID ||
1733 deviceid == RTL_PCI_8192CE_DID ||
1734 deviceid == RTL_PCI_8191CE_DID ||
1735 deviceid == RTL_PCI_8188CE_DID) {
1736 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1737 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1738 "8192C PCI-E is found - vid/did=%x/%x\n",
1739 venderid, deviceid);
c7cfe38e
C		 1740 } else if (deviceid == RTL_PCI_8192DE_DID ||
1741 deviceid == RTL_PCI_8192DE_DID2) {
1742 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1743 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1744 "8192D PCI-E is found - vid/did=%x/%x\n",
1745 venderid, deviceid);
0c817338
LF		 1746 } else {
1747 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 1748 "Err: Unknown device - vid/did=%x/%x\n",
1749 venderid, deviceid);
0c817338
LF		 1750
1751 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1752 }
1753
c7cfe38e
C		 1754 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1755 if (revisionid == 0 || revisionid == 1) {
1756 if (revisionid == 0) {
f30d7507
JP		 1757 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1758 "Find 92DE MAC0\n");
c7cfe38e
C		 1759 rtlhal->interfaceindex = 0;
1760 } else if (revisionid == 1) {
1761 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1762 "Find 92DE MAC1\n");
c7cfe38e
C		 1763 rtlhal->interfaceindex = 1;
1764 }
1765 } else {
1766 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507
JP		 1767 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1768 venderid, deviceid, revisionid);
c7cfe38e
C		 1769 rtlhal->interfaceindex = 0;
1770 }
1771 }
0c817338
LF		 1772 /*find bus info */
1773 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1774 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1775 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1776
26634c4b
LF		 1777 /* some ARM have no bridge_pdev and will crash here
1778 * so we should check if bridge_pdev is NULL
1779 */
b6b67df3
LF		 1780 if (bridge_pdev) {
1781 /*find bridge info if available */
1782 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1783 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1784 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1785 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1786 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1787 "Pci Bridge Vendor is found index: %d\n",
1788 tmp);
b6b67df3
LF		 1789 break;
1790 }
0c817338
LF		 1791 }
1792 }
1793
1794 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1795 PCI_BRIDGE_VENDOR_UNKNOWN) {
1796 pcipriv->ndis_adapter.pcibridge_busnum =
1797 bridge_pdev->bus->number;
1798 pcipriv->ndis_adapter.pcibridge_devnum =
1799 PCI_SLOT(bridge_pdev->devfn);
1800 pcipriv->ndis_adapter.pcibridge_funcnum =
1801 PCI_FUNC(bridge_pdev->devfn);
c7cfe38e
C		 1802 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1803 pci_pcie_cap(bridge_pdev);
0c817338
LF		 1804 pcipriv->ndis_adapter.num4bytes =
1805 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1806
1807 rtl_pci_get_linkcontrol_field(hw);
1808
1809 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1810 PCI_BRIDGE_VENDOR_AMD) {
1811 pcipriv->ndis_adapter.amd_l1_patch =
1812 rtl_pci_get_amd_l1_patch(hw);
1813 }
1814 }
1815
1816 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1817 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
1818 pcipriv->ndis_adapter.busnumber,
1819 pcipriv->ndis_adapter.devnumber,
1820 pcipriv->ndis_adapter.funcnumber,
1821 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
0c817338
LF		 1822
1823 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1824 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1825 pcipriv->ndis_adapter.pcibridge_busnum,
1826 pcipriv->ndis_adapter.pcibridge_devnum,
1827 pcipriv->ndis_adapter.pcibridge_funcnum,
1828 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1829 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1830 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1831 pcipriv->ndis_adapter.amd_l1_patch);
0c817338
LF		 1832
1833 rtl_pci_parse_configuration(pdev, hw);
26634c4b 1834 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
0c817338
LF		 1835
1836 return true;
1837}
1838
9e2ff36b 1839int rtl_pci_probe(struct pci_dev *pdev,
0c817338
LF		 1840 const struct pci_device_id *id)
1841{
1842 struct ieee80211_hw *hw = NULL;
1843
1844 struct rtl_priv *rtlpriv = NULL;
1845 struct rtl_pci_priv *pcipriv = NULL;
1846 struct rtl_pci *rtlpci;
1847 unsigned long pmem_start, pmem_len, pmem_flags;
1848 int err;
1849
1850 err = pci_enable_device(pdev);
1851 if (err) {
9d833ed7
JP		 1852 RT_ASSERT(false, "%s : Cannot enable new PCI device\n",
1853 pci_name(pdev));
0c817338
LF		 1854 return err;
1855 }
1856
1857 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1858 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
9d833ed7
JP		 1859 RT_ASSERT(false,
1860 "Unable to obtain 32bit DMA for consistent allocations\n");
3d86b930
TG		 1861 err = -ENOMEM;
1862 goto fail1;
0c817338
LF		 1863 }
1864 }
1865
1866 pci_set_master(pdev);
1867
1868 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1869 sizeof(struct rtl_priv), &rtl_ops);
1870 if (!hw) {
1871 RT_ASSERT(false,
9d833ed7 1872 "%s : ieee80211 alloc failed\n", pci_name(pdev));
0c817338
LF		 1873 err = -ENOMEM;
1874 goto fail1;
1875 }
1876
1877 SET_IEEE80211_DEV(hw, &pdev->dev);
1878 pci_set_drvdata(pdev, hw);
1879
1880 rtlpriv = hw->priv;
26634c4b 1881 rtlpriv->hw = hw;
0c817338
LF		 1882 pcipriv = (void *)rtlpriv->priv;
1883 pcipriv->dev.pdev = pdev;
b0302aba 1884 init_completion(&rtlpriv->firmware_loading_complete);
0c817338 1885
c7cfe38e
C		 1886 /* init cfg & intf_ops */
1887 rtlpriv->rtlhal.interface = INTF_PCI;
1888 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1889 rtlpriv->intf_ops = &rtl_pci_ops;
26634c4b 1890 rtlpriv->glb_var = &global_var;
c7cfe38e 1891
0c817338
LF		 1892 /*
1893 *init dbgp flags before all
1894 *other functions, because we will
1895 *use it in other funtions like
1896 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1897 *you can not use these macro
1898 *before this
1899 */
1900 rtl_dbgp_flag_init(hw);
1901
1902 /* MEM map */
1903 err = pci_request_regions(pdev, KBUILD_MODNAME);
1904 if (err) {
9d833ed7 1905 RT_ASSERT(false, "Can't obtain PCI resources\n");
3d86b930 1906 goto fail1;
0c817338
LF		 1907 }
1908
c7cfe38e
C		 1909 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1910 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1911 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
0c817338
LF		 1912
1913 /*shared mem start */
1914 rtlpriv->io.pci_mem_start =
c7cfe38e
C		 1915 (unsigned long)pci_iomap(pdev,
1916 rtlpriv->cfg->bar_id, pmem_len);
0c817338 1917 if (rtlpriv->io.pci_mem_start == 0) {
9d833ed7 1918 RT_ASSERT(false, "Can't map PCI mem\n");
3d86b930 1919 err = -ENOMEM;
0c817338
LF		 1920 goto fail2;
1921 }
1922
1923 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1924 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
1925 pmem_start, pmem_len, pmem_flags,
1926 rtlpriv->io.pci_mem_start);
0c817338
LF		 1927
1928 /* Disable Clk Request */
1929 pci_write_config_byte(pdev, 0x81, 0);
1930 /* leave D3 mode */
1931 pci_write_config_byte(pdev, 0x44, 0);
1932 pci_write_config_byte(pdev, 0x04, 0x06);
1933 pci_write_config_byte(pdev, 0x04, 0x07);
1934
0c817338 1935 /* find adapter */
3d86b930
TG		 1936 if (!_rtl_pci_find_adapter(pdev, hw)) {
1937 err = -ENODEV;
fa7ccfb1 1938 goto fail3;
3d86b930 1939 }
0c817338
LF		 1940
1941 /* Init IO handler */
1942 _rtl_pci_io_handler_init(&pdev->dev, hw);
1943
1944 /*like read eeprom and so on */
1945 rtlpriv->cfg->ops->read_eeprom_info(hw);
1946
0c817338
LF		 1947 /*aspm */
1948 rtl_pci_init_aspm(hw);
1949
1950 /* Init mac80211 sw */
1951 err = rtl_init_core(hw);
1952 if (err) {
1953 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1954 "Can't allocate sw for mac80211\n");
0c817338
LF		 1955 goto fail3;
1956 }
1957
1958 /* Init PCI sw */
12325280 1959 err = rtl_pci_init(hw, pdev);
0c817338 1960 if (err) {
f30d7507 1961 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n");
0c817338
LF		 1962 goto fail3;
1963 }
1964
574e02ab
LF		 1965 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1966 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n");
1967 err = -ENODEV;
1968 goto fail3;
1969 }
1970
1971 rtlpriv->cfg->ops->init_sw_leds(hw);
1972
0c817338
LF		 1973 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1974 if (err) {
1975 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1976 "failed to create sysfs device attributes\n");
0c817338
LF		 1977 goto fail3;
1978 }
1979
0c817338
LF		 1980 rtlpci = rtl_pcidev(pcipriv);
1981 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1982 IRQF_SHARED, KBUILD_MODNAME, hw);
1983 if (err) {
1984 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1985 "%s: failed to register IRQ handler\n",
1986 wiphy_name(hw->wiphy));
0c817338 1987 goto fail3;
0c817338 1988 }
b0302aba 1989 rtlpci->irq_alloc = 1;
0c817338 1990
0c817338
LF		 1991 return 0;
1992
1993fail3:
0c817338 1994 rtl_deinit_core(hw);
0c817338
LF		 1995
1996 if (rtlpriv->io.pci_mem_start != 0)
62e63975 1997 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 1998
1999fail2:
2000 pci_release_regions(pdev);
b0302aba 2001 complete(&rtlpriv->firmware_loading_complete);
0c817338
LF		 2002
2003fail1:
3d86b930
TG		 2004 if (hw)
2005 ieee80211_free_hw(hw);
2006 pci_set_drvdata(pdev, NULL);
0c817338
LF		 2007 pci_disable_device(pdev);
2008
3d86b930 2009 return err;
0c817338
LF		 2010
2011}
2012EXPORT_SYMBOL(rtl_pci_probe);
2013
2014void rtl_pci_disconnect(struct pci_dev *pdev)
2015{
2016 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2017 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2018 struct rtl_priv *rtlpriv = rtl_priv(hw);
2019 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2020 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2021
b0302aba
LF		 2022 /* just in case driver is removed before firmware callback */
2023 wait_for_completion(&rtlpriv->firmware_loading_complete);
0c817338
LF		 2024 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2025
2026 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
2027
2028 /*ieee80211_unregister_hw will call ops_stop */
2029 if (rtlmac->mac80211_registered == 1) {
2030 ieee80211_unregister_hw(hw);
2031 rtlmac->mac80211_registered = 0;
2032 } else {
2033 rtl_deinit_deferred_work(hw);
2034 rtlpriv->intf_ops->adapter_stop(hw);
2035 }
44eb65cf 2036 rtlpriv->cfg->ops->disable_interrupt(hw);
0c817338
LF		 2037
2038 /*deinit rfkill */
2039 rtl_deinit_rfkill(hw);
2040
2041 rtl_pci_deinit(hw);
2042 rtl_deinit_core(hw);
0c817338
LF		 2043 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2044
2045 if (rtlpci->irq_alloc) {
26634c4b 2046 synchronize_irq(rtlpci->pdev->irq);
0c817338
LF		 2047 free_irq(rtlpci->pdev->irq, hw);
2048 rtlpci->irq_alloc = 0;
2049 }
2050
26634c4b 2051 list_del(&rtlpriv->list);
0c817338 2052 if (rtlpriv->io.pci_mem_start != 0) {
62e63975 2053 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 2054 pci_release_regions(pdev);
2055 }
2056
2057 pci_disable_device(pdev);
c7cfe38e
C		 2058
2059 rtl_pci_disable_aspm(hw);
2060
0c817338
LF		 2061 pci_set_drvdata(pdev, NULL);
2062
2063 ieee80211_free_hw(hw);
2064}
2065EXPORT_SYMBOL(rtl_pci_disconnect);
2066
244a77e9 2067#ifdef CONFIG_PM_SLEEP
0c817338
LF		 2068/***************************************
2069kernel pci power state define:
2070PCI_D0 ((pci_power_t __force) 0)
2071PCI_D1 ((pci_power_t __force) 1)
2072PCI_D2 ((pci_power_t __force) 2)
2073PCI_D3hot ((pci_power_t __force) 3)
2074PCI_D3cold ((pci_power_t __force) 4)
2075PCI_UNKNOWN ((pci_power_t __force) 5)
2076
2077This function is called when system
2078goes into suspend state mac80211 will
2079call rtl_mac_stop() from the mac80211
2080suspend function first, So there is
2081no need to call hw_disable here.
2082****************************************/
603be388 2083int rtl_pci_suspend(struct device *dev)
0c817338 2084{
603be388 2085 struct pci_dev *pdev = to_pci_dev(dev);
c7cfe38e
C		 2086 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2087 struct rtl_priv *rtlpriv = rtl_priv(hw);
2088
2089 rtlpriv->cfg->ops->hw_suspend(hw);
2090 rtl_deinit_rfkill(hw);
2091
0c817338
LF		 2092 return 0;
2093}
2094EXPORT_SYMBOL(rtl_pci_suspend);
2095
603be388 2096int rtl_pci_resume(struct device *dev)
0c817338 2097{
603be388 2098 struct pci_dev *pdev = to_pci_dev(dev);
c7cfe38e
C		 2099 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2100 struct rtl_priv *rtlpriv = rtl_priv(hw);
0c817338 2101
c7cfe38e
C		 2102 rtlpriv->cfg->ops->hw_resume(hw);
2103 rtl_init_rfkill(hw);
0c817338
LF		 2104 return 0;
2105}
2106EXPORT_SYMBOL(rtl_pci_resume);
244a77e9 2107#endif /* CONFIG_PM_SLEEP */
0c817338
LF		 2108
2109struct rtl_intf_ops rtl_pci_ops = {
c7cfe38e 2110 .read_efuse_byte = read_efuse_byte,
0c817338
LF		 2111 .adapter_start = rtl_pci_start,
2112 .adapter_stop = rtl_pci_stop,
26634c4b 2113 .check_buddy_priv = rtl_pci_check_buddy_priv,
0c817338 2114 .adapter_tx = rtl_pci_tx,
c7cfe38e 2115 .flush = rtl_pci_flush,
0c817338 2116 .reset_trx_ring = rtl_pci_reset_trx_ring,
c7cfe38e 2117 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
0c817338
LF		 2118
2119 .disable_aspm = rtl_pci_disable_aspm,
2120 .enable_aspm = rtl_pci_enable_aspm,
2121};
Ubuntu Hirsute Linux kernel mirror