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wlcore/wl18xx/wl12xx: remove __dev* attributes
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rtlwifi / pci.c
CommitLineData
0c817338
LF		 1/******************************************************************************
2 *
a8d76066 3 * Copyright(c) 2009-2012 Realtek Corporation.
0c817338
LF		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
0c817338 30#include "wifi.h"
d273bb20 31#include "core.h"
0c817338
LF		 32#include "pci.h"
33#include "base.h"
34#include "ps.h"
c7cfe38e 35#include "efuse.h"
d273bb20 36#include <linux/export.h>
f11bbfd8 37#include <linux/kmemleak.h>
0c817338
LF		 38
39static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
f01dce94
JM		 40 PCI_VENDOR_ID_INTEL,
41 PCI_VENDOR_ID_ATI,
42 PCI_VENDOR_ID_AMD,
43 PCI_VENDOR_ID_SI
0c817338
LF		 44};
45
c7cfe38e
C		 46static const u8 ac_to_hwq[] = {
47 VO_QUEUE,
48 VI_QUEUE,
49 BE_QUEUE,
50 BK_QUEUE
51};
52
d3bb1429 53static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
c7cfe38e
C		 54 struct sk_buff *skb)
55{
56 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
d3bb1429 57 __le16 fc = rtl_get_fc(skb);
c7cfe38e
C		 58 u8 queue_index = skb_get_queue_mapping(skb);
59
60 if (unlikely(ieee80211_is_beacon(fc)))
61 return BEACON_QUEUE;
62 if (ieee80211_is_mgmt(fc))
63 return MGNT_QUEUE;
64 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
65 if (ieee80211_is_nullfunc(fc))
66 return HIGH_QUEUE;
67
68 return ac_to_hwq[queue_index];
69}
70
0c817338
LF		 71/* Update PCI dependent default settings*/
72static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
73{
74 struct rtl_priv *rtlpriv = rtl_priv(hw);
75 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
76 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
77 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
78 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
c7cfe38e 79 u8 init_aspm;
0c817338
LF		 80
81 ppsc->reg_rfps_level = 0;
3db1cd5c 82 ppsc->support_aspm = false;
0c817338
LF		 83
84 /*Update PCI ASPM setting */
85 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
86 switch (rtlpci->const_pci_aspm) {
87 case 0:
88 /*No ASPM */
89 break;
90
91 case 1:
92 /*ASPM dynamically enabled/disable. */
93 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
94 break;
95
96 case 2:
97 /*ASPM with Clock Req dynamically enabled/disable. */
98 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
99 RT_RF_OFF_LEVL_CLK_REQ);
100 break;
101
102 case 3:
103 /*
104 * Always enable ASPM and Clock Req
105 * from initialization to halt.
106 * */
107 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
108 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
109 RT_RF_OFF_LEVL_CLK_REQ);
110 break;
111
112 case 4:
113 /*
114 * Always enable ASPM without Clock Req
115 * from initialization to halt.
116 * */
117 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
118 RT_RF_OFF_LEVL_CLK_REQ);
119 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
120 break;
121 }
122
123 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
124
125 /*Update Radio OFF setting */
126 switch (rtlpci->const_hwsw_rfoff_d3) {
127 case 1:
128 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
129 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
130 break;
131
132 case 2:
133 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
134 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
135 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
136 break;
137
138 case 3:
139 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
140 break;
141 }
142
143 /*Set HW definition to determine if it supports ASPM. */
144 switch (rtlpci->const_support_pciaspm) {
c7cfe38e
C		 145 case 0:{
146 /*Not support ASPM. */
147 bool support_aspm = false;
148 ppsc->support_aspm = support_aspm;
149 break;
150 }
151 case 1:{
152 /*Support ASPM. */
153 bool support_aspm = true;
154 bool support_backdoor = true;
155 ppsc->support_aspm = support_aspm;
156
157 /*if (priv->oem_id == RT_CID_TOSHIBA &&
158 !priv->ndis_adapter.amd_l1_patch)
159 support_backdoor = false; */
160
161 ppsc->support_backdoor = support_backdoor;
162
163 break;
164 }
0c817338
LF		 165 case 2:
166 /*ASPM value set by chipset. */
c7cfe38e
C		 167 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
168 bool support_aspm = true;
169 ppsc->support_aspm = support_aspm;
170 }
0c817338
LF		 171 break;
172 default:
173 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 174 "switch case not processed\n");
0c817338
LF		 175 break;
176 }
c7cfe38e
C		 177
178 /* toshiba aspm issue, toshiba will set aspm selfly
179 * so we should not set aspm in driver */
180 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
181 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
182 init_aspm == 0x43)
183 ppsc->support_aspm = false;
184}
185
0c817338
LF		 186static bool _rtl_pci_platform_switch_device_pci_aspm(
187 struct ieee80211_hw *hw,
188 u8 value)
189{
190 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e
C		 191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
192
193 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
194 value |= 0x40;
0c817338 195
0c817338
LF		 196 pci_write_config_byte(rtlpci->pdev, 0x80, value);
197
32473284 198 return false;
0c817338
LF		 199}
200
201/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
1d73c51a 202static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
0c817338
LF		 203{
204 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e 205 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338 206
0c817338 207 pci_write_config_byte(rtlpci->pdev, 0x81, value);
0c817338 208
c7cfe38e
C		 209 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
210 udelay(100);
0c817338
LF		 211}
212
213/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
214static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
215{
216 struct rtl_priv *rtlpriv = rtl_priv(hw);
217 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
218 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
219 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
220 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 221 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
222 /*Retrieve original configuration settings. */
223 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
224 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
225 pcibridge_linkctrlreg;
226 u16 aspmlevel = 0;
32473284 227 u8 tmp_u1b = 0;
0c817338 228
c7cfe38e
C		 229 if (!ppsc->support_aspm)
230 return;
231
0c817338
LF		 232 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
233 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
f30d7507 234 "PCI(Bridge) UNKNOWN\n");
0c817338
LF		 235
236 return;
237 }
238
239 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
240 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
241 _rtl_pci_switch_clk_req(hw, 0x0);
242 }
243
32473284
LF		 244 /*for promising device will in L0 state after an I/O. */
245 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
0c817338
LF		 246
247 /*Set corresponding value. */
248 aspmlevel |= BIT(0) | BIT(1);
249 linkctrl_reg &= ~aspmlevel;
250 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
251
252 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
253 udelay(50);
254
255 /*4 Disable Pci Bridge ASPM */
886e14b6
LF		 256 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
257 pcibridge_linkctrlreg);
0c817338
LF		 258
259 udelay(50);
0c817338
LF		 260}
261
262/*
263 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
264 *power saving We should follow the sequence to enable
265 *RTL8192SE first then enable Pci Bridge ASPM
266 *or the system will show bluescreen.
267 */
268static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
269{
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
272 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
273 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
274 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
275 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
276 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
277 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 278 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
279 u16 aspmlevel;
280 u8 u_pcibridge_aspmsetting;
281 u8 u_device_aspmsetting;
282
c7cfe38e
C		 283 if (!ppsc->support_aspm)
284 return;
285
0c817338
LF		 286 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
287 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
f30d7507 288 "PCI(Bridge) UNKNOWN\n");
0c817338
LF		 289 return;
290 }
291
292 /*4 Enable Pci Bridge ASPM */
0c817338
LF		 293
294 u_pcibridge_aspmsetting =
295 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
296 rtlpci->const_hostpci_aspm_setting;
297
298 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
299 u_pcibridge_aspmsetting &= ~BIT(0);
300
886e14b6
LF		 301 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
302 u_pcibridge_aspmsetting);
0c817338
LF		 303
304 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507
JP		 305 "PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
306 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
307 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
308 u_pcibridge_aspmsetting);
0c817338
LF		 309
310 udelay(50);
311
312 /*Get ASPM level (with/without Clock Req) */
313 aspmlevel = rtlpci->const_devicepci_aspm_setting;
314 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
315
316 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
317 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
318
319 u_device_aspmsetting |= aspmlevel;
320
321 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
322
323 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
324 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
325 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
326 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
327 }
c7cfe38e 328 udelay(100);
0c817338
LF		 329}
330
331static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
332{
886e14b6 333 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338
LF		 334
335 bool status = false;
336 u8 offset_e0;
337 unsigned offset_e4;
338
886e14b6 339 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
0c817338 340
886e14b6 341 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
0c817338
LF		 342
343 if (offset_e0 == 0xA0) {
886e14b6 344 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
0c817338
LF		 345 if (offset_e4 & BIT(23))
346 status = true;
347 }
348
349 return status;
350}
351
d3bb1429 352static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
0c817338
LF		 353{
354 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
886e14b6 355 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
0c817338 356 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
0c817338 357 u8 linkctrl_reg;
c7cfe38e 358 u8 num4bbytes;
0c817338 359
c7cfe38e 360 num4bbytes = (capabilityoffset + 0x10) / 4;
0c817338
LF		 361
362 /*Read Link Control Register */
886e14b6 363 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
0c817338
LF		 364
365 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
366}
367
368static void rtl_pci_parse_configuration(struct pci_dev *pdev,
369 struct ieee80211_hw *hw)
370{
371 struct rtl_priv *rtlpriv = rtl_priv(hw);
372 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
373
374 u8 tmp;
332badc3 375 u16 linkctrl_reg;
0c817338
LF		 376
377 /*Link Control Register */
332badc3
JL		 378 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
379 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
0c817338 380
f30d7507
JP		 381 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
382 pcipriv->ndis_adapter.linkctrl_reg);
0c817338
LF		 383
384 pci_read_config_byte(pdev, 0x98, &tmp);
385 tmp |= BIT(4);
386 pci_write_config_byte(pdev, 0x98, tmp);
387
388 tmp = 0x17;
389 pci_write_config_byte(pdev, 0x70f, tmp);
390}
391
c7cfe38e 392static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
0c817338
LF		 393{
394 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
395
396 _rtl_pci_update_default_setting(hw);
397
398 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
399 /*Always enable ASPM & Clock Req. */
400 rtl_pci_enable_aspm(hw);
401 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
402 }
403
404}
405
0c817338
LF		 406static void _rtl_pci_io_handler_init(struct device *dev,
407 struct ieee80211_hw *hw)
408{
409 struct rtl_priv *rtlpriv = rtl_priv(hw);
410
411 rtlpriv->io.dev = dev;
412
413 rtlpriv->io.write8_async = pci_write8_async;
414 rtlpriv->io.write16_async = pci_write16_async;
415 rtlpriv->io.write32_async = pci_write32_async;
416
417 rtlpriv->io.read8_sync = pci_read8_sync;
418 rtlpriv->io.read16_sync = pci_read16_sync;
419 rtlpriv->io.read32_sync = pci_read32_sync;
420
421}
422
423static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
424{
425}
426
c7cfe38e
C		 427static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
428 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
429{
430 struct rtl_priv *rtlpriv = rtl_priv(hw);
431 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
432 u8 additionlen = FCS_LEN;
433 struct sk_buff *next_skb;
434
435 /* here open is 4, wep/tkip is 8, aes is 12*/
436 if (info->control.hw_key)
437 additionlen += info->control.hw_key->icv_len;
438
439 /* The most skb num is 6 */
440 tcb_desc->empkt_num = 0;
441 spin_lock_bh(&rtlpriv->locks.waitq_lock);
442 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
443 struct ieee80211_tx_info *next_info;
444
445 next_info = IEEE80211_SKB_CB(next_skb);
446 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
447 tcb_desc->empkt_len[tcb_desc->empkt_num] =
448 next_skb->len + additionlen;
449 tcb_desc->empkt_num++;
450 } else {
451 break;
452 }
453
454 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
455 next_skb))
456 break;
457
458 if (tcb_desc->empkt_num >= 5)
459 break;
460 }
461 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
462
463 return true;
464}
465
466/* just for early mode now */
467static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
468{
469 struct rtl_priv *rtlpriv = rtl_priv(hw);
470 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
471 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
472 struct sk_buff *skb = NULL;
473 struct ieee80211_tx_info *info = NULL;
fb914ebf 474 int tid;
c7cfe38e
C		 475
476 if (!rtlpriv->rtlhal.earlymode_enable)
477 return;
478
479 /* we juse use em for BE/BK/VI/VO */
480 for (tid = 7; tid >= 0; tid--) {
2a00def4 481 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
c7cfe38e
C		 482 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
483 while (!mac->act_scanning &&
484 rtlpriv->psc.rfpwr_state == ERFON) {
485 struct rtl_tcb_desc tcb_desc;
486 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
487
488 spin_lock_bh(&rtlpriv->locks.waitq_lock);
489 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
490 (ring->entries - skb_queue_len(&ring->queue) > 5)) {
491 skb = skb_dequeue(&mac->skb_waitq[tid]);
492 } else {
493 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
494 break;
495 }
496 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
497
498 /* Some macaddr can't do early mode. like
499 * multicast/broadcast/no_qos data */
500 info = IEEE80211_SKB_CB(skb);
501 if (info->flags & IEEE80211_TX_CTL_AMPDU)
502 _rtl_update_earlymode_info(hw, skb,
503 &tcb_desc, tid);
504
36323f81 505 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
c7cfe38e
C		 506 }
507 }
508}
509
510
0c817338
LF		 511static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
512{
513 struct rtl_priv *rtlpriv = rtl_priv(hw);
514 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
515
516 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
517
518 while (skb_queue_len(&ring->queue)) {
519 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
520 struct sk_buff *skb;
521 struct ieee80211_tx_info *info;
c7cfe38e
C		 522 __le16 fc;
523 u8 tid;
0c817338
LF		 524
525 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
526 HW_DESC_OWN);
527
528 /*
529 *beacon packet will only use the first
530 *descriptor defautly,and the own may not
531 *be cleared by the hardware
532 */
533 if (own)
534 return;
535 ring->idx = (ring->idx + 1) % ring->entries;
536
537 skb = __skb_dequeue(&ring->queue);
538 pci_unmap_single(rtlpci->pdev,
d3bb1429 539 rtlpriv->cfg->ops->
0c817338 540 get_desc((u8 *) entry, true,
d3bb1429 541 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 542 skb->len, PCI_DMA_TODEVICE);
543
c7cfe38e
C		 544 /* remove early mode header */
545 if (rtlpriv->rtlhal.earlymode_enable)
546 skb_pull(skb, EM_HDR_LEN);
547
0c817338 548 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
f30d7507
JP		 549 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
550 ring->idx,
551 skb_queue_len(&ring->queue),
552 *(u16 *) (skb->data + 22));
0c817338 553
c7cfe38e
C		 554 if (prio == TXCMD_QUEUE) {
555 dev_kfree_skb(skb);
556 goto tx_status_ok;
557
558 }
559
560 /* for sw LPS, just after NULL skb send out, we can
561 * sure AP kown we are sleeped, our we should not let
562 * rf to sleep*/
563 fc = rtl_get_fc(skb);
564 if (ieee80211_is_nullfunc(fc)) {
565 if (ieee80211_has_pm(fc)) {
9c050440 566 rtlpriv->mac80211.offchan_delay = true;
3db1cd5c 567 rtlpriv->psc.state_inap = true;
c7cfe38e 568 } else {
3db1cd5c 569 rtlpriv->psc.state_inap = false;
c7cfe38e
C		 570 }
571 }
572
573 /* update tid tx pkt num */
574 tid = rtl_get_tid(skb);
575 if (tid <= 7)
576 rtlpriv->link_info.tidtx_inperiod[tid]++;
577
0c817338
LF		 578 info = IEEE80211_SKB_CB(skb);
579 ieee80211_tx_info_clear_status(info);
580
581 info->flags |= IEEE80211_TX_STAT_ACK;
582 /*info->status.rates[0].count = 1; */
583
584 ieee80211_tx_status_irqsafe(hw, skb);
585
586 if ((ring->entries - skb_queue_len(&ring->queue))
587 == 2) {
588
589 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
f30d7507
JP		 590 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%d\n",
591 prio, ring->idx,
592 skb_queue_len(&ring->queue));
0c817338
LF		 593
594 ieee80211_wake_queue(hw,
595 skb_get_queue_mapping
596 (skb));
597 }
c7cfe38e 598tx_status_ok:
0c817338
LF		 599 skb = NULL;
600 }
601
602 if (((rtlpriv->link_info.num_rx_inperiod +
603 rtlpriv->link_info.num_tx_inperiod) > 8) ||
604 (rtlpriv->link_info.num_rx_inperiod > 2)) {
41affd52 605 schedule_work(&rtlpriv->works.lps_leave_work);
0c817338
LF		 606 }
607}
608
fd854772
MM		 609static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
610 struct ieee80211_rx_status rx_status)
611{
612 struct rtl_priv *rtlpriv = rtl_priv(hw);
613 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
614 __le16 fc = rtl_get_fc(skb);
615 bool unicast = false;
616 struct sk_buff *uskb = NULL;
617 u8 *pdata;
618
619
620 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
621
622 if (is_broadcast_ether_addr(hdr->addr1)) {
623 ;/*TODO*/
624 } else if (is_multicast_ether_addr(hdr->addr1)) {
625 ;/*TODO*/
626 } else {
627 unicast = true;
628 rtlpriv->stats.rxbytesunicast += skb->len;
629 }
630
631 rtl_is_special_data(hw, skb, false);
632
633 if (ieee80211_is_data(fc)) {
634 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
635
636 if (unicast)
637 rtlpriv->link_info.num_rx_inperiod++;
638 }
639
640 /* for sw lps */
641 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
642 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
643 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
644 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
645 (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
646 return;
647
648 if (unlikely(!rtl_action_proc(hw, skb, false)))
649 return;
650
651 uskb = dev_alloc_skb(skb->len + 128);
76a92be5
LF		 652 if (!uskb)
653 return; /* exit if allocation failed */
fd854772
MM		 654 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
655 pdata = (u8 *)skb_put(uskb, skb->len);
656 memcpy(pdata, skb->data, skb->len);
657
658 ieee80211_rx_irqsafe(hw, uskb);
659}
660
0c817338
LF		 661static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
662{
663 struct rtl_priv *rtlpriv = rtl_priv(hw);
664 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
665 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
666
667 struct ieee80211_rx_status rx_status = { 0 };
668 unsigned int count = rtlpci->rxringcount;
669 u8 own;
670 u8 tmp_one;
671 u32 bufferaddress;
0c817338
LF		 672
673 struct rtl_stats stats = {
674 .signal = 0,
675 .noise = -98,
676 .rate = 0,
677 };
34ddb207 678 int index = rtlpci->rx_ring[rx_queue_idx].idx;
0c817338
LF		 679
680 /*RX NORMAL PKT */
681 while (count--) {
682 /*rx descriptor */
683 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
34ddb207 684 index];
0c817338
LF		 685 /*rx pkt */
686 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
34ddb207 687 index];
2c333366 688 struct sk_buff *new_skb = NULL;
0c817338
LF		 689
690 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
691 false, HW_DESC_OWN);
692
2c333366
MM		 693 /*wait data to be filled by hardware */
694 if (own)
34ddb207 695 break;
6633d649 696
2c333366
MM		 697 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
698 &rx_status,
699 (u8 *) pdesc, skb);
700
8db8ddf1
MM		 701 if (stats.crc || stats.hwerror)
702 goto done;
703
2c333366
MM		 704 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
705 if (unlikely(!new_skb)) {
f30d7507
JP		 706 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV), DBG_DMESG,
707 "can't alloc skb for rx\n");
2c333366
MM		 708 goto done;
709 }
710
711 pci_unmap_single(rtlpci->pdev,
712 *((dma_addr_t *) skb->cb),
713 rtlpci->rxbuffersize,
714 PCI_DMA_FROMDEVICE);
715
716 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
717 HW_DESC_RXPKT_LEN));
718 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
719
720 /*
721 * NOTICE This can not be use for mac80211,
722 * this is done in mac80211 code,
723 * if you done here sec DHCP will fail
724 * skb_trim(skb, skb->len - 4);
725 */
726
fd854772 727 _rtl_receive_one(hw, skb, rx_status);
0c817338 728
2c333366
MM		 729 if (((rtlpriv->link_info.num_rx_inperiod +
730 rtlpriv->link_info.num_tx_inperiod) > 8) ||
731 (rtlpriv->link_info.num_rx_inperiod > 2)) {
41affd52 732 schedule_work(&rtlpriv->works.lps_leave_work);
2c333366 733 }
0c817338 734
14058add 735 dev_kfree_skb_any(skb);
2c333366 736 skb = new_skb;
0c817338 737
2c333366
MM		 738 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
739 *((dma_addr_t *) skb->cb) =
0c817338
LF		 740 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
741 rtlpci->rxbuffersize,
742 PCI_DMA_FROMDEVICE);
743
0c817338 744done:
d3bb1429 745 bufferaddress = (*((dma_addr_t *)skb->cb));
0c817338
LF		 746 tmp_one = 1;
747 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
748 HW_DESC_RXBUFF_ADDR,
749 (u8 *)&bufferaddress);
0c817338
LF		 750 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
751 HW_DESC_RXPKT_LEN,
752 (u8 *)&rtlpci->rxbuffersize);
753
34ddb207 754 if (index == rtlpci->rxringcount - 1)
0c817338
LF		 755 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
756 HW_DESC_RXERO,
2c208890 757 &tmp_one);
0c817338 758
febc9fe5 759 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
2c208890 760 &tmp_one);
febc9fe5 761
34ddb207 762 index = (index + 1) % rtlpci->rxringcount;
0c817338
LF		 763 }
764
34ddb207 765 rtlpci->rx_ring[rx_queue_idx].idx = index;
0c817338
LF		 766}
767
0c817338
LF		 768static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
769{
770 struct ieee80211_hw *hw = dev_id;
771 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 772 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 773 unsigned long flags;
774 u32 inta = 0;
775 u32 intb = 0;
de2e56ce 776 irqreturn_t ret = IRQ_HANDLED;
0c817338 777
0c817338
LF		 778 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
779
780 /*read ISR: 4/8bytes */
781 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
782
783 /*Shared IRQ or HW disappared */
de2e56ce
LF		 784 if (!inta || inta == 0xffff) {
785 ret = IRQ_NONE;
0c817338 786 goto done;
de2e56ce 787 }
0c817338
LF		 788
789 /*<1> beacon related */
790 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
791 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 792 "beacon ok interrupt!\n");
0c817338
LF		 793 }
794
795 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
796 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 797 "beacon err interrupt!\n");
0c817338
LF		 798 }
799
800 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
f30d7507 801 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
0c817338
LF		 802 }
803
804 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
805 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 806 "prepare beacon for interrupt!\n");
0c817338
LF		 807 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
808 }
809
810 /*<3> Tx related */
811 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
f30d7507 812 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
0c817338
LF		 813
814 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
815 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 816 "Manage ok interrupt!\n");
0c817338
LF		 817 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
818 }
819
820 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
821 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 822 "HIGH_QUEUE ok interrupt!\n");
0c817338
LF		 823 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
824 }
825
826 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
827 rtlpriv->link_info.num_tx_inperiod++;
828
829 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 830 "BK Tx OK interrupt!\n");
0c817338
LF		 831 _rtl_pci_tx_isr(hw, BK_QUEUE);
832 }
833
834 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
835 rtlpriv->link_info.num_tx_inperiod++;
836
837 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 838 "BE TX OK interrupt!\n");
0c817338
LF		 839 _rtl_pci_tx_isr(hw, BE_QUEUE);
840 }
841
842 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
843 rtlpriv->link_info.num_tx_inperiod++;
844
845 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 846 "VI TX OK interrupt!\n");
0c817338
LF		 847 _rtl_pci_tx_isr(hw, VI_QUEUE);
848 }
849
850 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
851 rtlpriv->link_info.num_tx_inperiod++;
852
853 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 854 "Vo TX OK interrupt!\n");
0c817338
LF		 855 _rtl_pci_tx_isr(hw, VO_QUEUE);
856 }
857
c7cfe38e
C		 858 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
859 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
860 rtlpriv->link_info.num_tx_inperiod++;
861
862 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 863 "CMD TX OK interrupt!\n");
c7cfe38e
C		 864 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
865 }
866 }
867
0c817338
LF		 868 /*<2> Rx related */
869 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
f30d7507 870 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
c7cfe38e 871 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 872 }
873
874 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
875 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 876 "rx descriptor unavailable!\n");
c7cfe38e 877 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 878 }
879
880 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
f30d7507 881 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
c7cfe38e 882 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 883 }
884
c7cfe38e
C		 885 if (rtlpriv->rtlhal.earlymode_enable)
886 tasklet_schedule(&rtlpriv->works.irq_tasklet);
887
0c817338
LF		 888done:
889 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
de2e56ce 890 return ret;
0c817338
LF		 891}
892
893static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
894{
c7cfe38e 895 _rtl_pci_tx_chk_waitq(hw);
0c817338
LF		 896}
897
898static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
899{
900 struct rtl_priv *rtlpriv = rtl_priv(hw);
901 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
902 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e 903 struct rtl8192_tx_ring *ring = NULL;
0c817338
LF		 904 struct ieee80211_hdr *hdr = NULL;
905 struct ieee80211_tx_info *info = NULL;
906 struct sk_buff *pskb = NULL;
907 struct rtl_tx_desc *pdesc = NULL;
c7cfe38e 908 struct rtl_tcb_desc tcb_desc;
0c817338
LF		 909 u8 temp_one = 1;
910
c7cfe38e 911 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
0c817338
LF		 912 ring = &rtlpci->tx_ring[BEACON_QUEUE];
913 pskb = __skb_dequeue(&ring->queue);
a75e2ad7
LF		 914 if (pskb) {
915 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
916 pci_unmap_single(rtlpci->pdev, rtlpriv->cfg->ops->get_desc(
917 (u8 *) entry, true, HW_DESC_TXBUFF_ADDR),
918 pskb->len, PCI_DMA_TODEVICE);
0c817338 919 kfree_skb(pskb);
a75e2ad7 920 }
0c817338
LF		 921
922 /*NB: the beacon data buffer must be 32-bit aligned. */
923 pskb = ieee80211_beacon_get(hw, mac->vif);
924 if (pskb == NULL)
925 return;
c7cfe38e 926 hdr = rtl_get_hdr(pskb);
0c817338 927 info = IEEE80211_SKB_CB(pskb);
0c817338
LF		 928 pdesc = &ring->desc[0];
929 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
36323f81 930 info, NULL, pskb, BEACON_QUEUE, &tcb_desc);
0c817338
LF		 931
932 __skb_queue_tail(&ring->queue, pskb);
933
934 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
2c208890 935 &temp_one);
0c817338
LF		 936
937 return;
938}
939
41affd52
SG		 940static void rtl_lps_leave_work_callback(struct work_struct *work)
941{
942 struct rtl_works *rtlworks =
943 container_of(work, struct rtl_works, lps_leave_work);
944 struct ieee80211_hw *hw = rtlworks->hw;
945
946 rtl_lps_leave(hw);
947}
948
0c817338
LF		 949static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
950{
951 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
952 u8 i;
953
954 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
955 rtlpci->txringcount[i] = RT_TXDESC_NUM;
956
957 /*
958 *we just alloc 2 desc for beacon queue,
959 *because we just need first desc in hw beacon.
960 */
961 rtlpci->txringcount[BEACON_QUEUE] = 2;
962
963 /*
964 *BE queue need more descriptor for performance
965 *consideration or, No more tx desc will happen,
966 *and may cause mac80211 mem leakage.
967 */
968 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
969
970 rtlpci->rxbuffersize = 9100; /*2048/1024; */
971 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
972}
973
974static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
975 struct pci_dev *pdev)
976{
977 struct rtl_priv *rtlpriv = rtl_priv(hw);
978 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
979 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
980 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 981
982 rtlpci->up_first_time = true;
983 rtlpci->being_init_adapter = false;
984
985 rtlhal->hw = hw;
986 rtlpci->pdev = pdev;
987
0c817338
LF		 988 /*Tx/Rx related var */
989 _rtl_pci_init_trx_var(hw);
990
c7cfe38e 991 /*IBSS*/ mac->beacon_interval = 100;
0c817338 992
c7cfe38e
C		 993 /*AMPDU*/
994 mac->min_space_cfg = 0;
0c817338
LF		 995 mac->max_mss_density = 0;
996 /*set sane AMPDU defaults */
997 mac->current_ampdu_density = 7;
998 mac->current_ampdu_factor = 3;
999
c7cfe38e
C		 1000 /*QOS*/
1001 rtlpci->acm_method = eAcmWay2_SW;
0c817338
LF		 1002
1003 /*task */
1004 tasklet_init(&rtlpriv->works.irq_tasklet,
1005 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1006 (unsigned long)hw);
1007 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1008 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1009 (unsigned long)hw);
41affd52 1010 INIT_WORK(&rtlpriv->works.lps_leave_work, rtl_lps_leave_work_callback);
0c817338
LF		 1011}
1012
1013static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1014 unsigned int prio, unsigned int entries)
1015{
1016 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1017 struct rtl_priv *rtlpriv = rtl_priv(hw);
1018 struct rtl_tx_desc *ring;
1019 dma_addr_t dma;
1020 u32 nextdescaddress;
1021 int i;
1022
1023 ring = pci_alloc_consistent(rtlpci->pdev,
1024 sizeof(*ring) * entries, &dma);
1025
1026 if (!ring || (unsigned long)ring & 0xFF) {
1027 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1028 "Cannot allocate TX ring (prio = %d)\n", prio);
0c817338
LF		 1029 return -ENOMEM;
1030 }
1031
1032 memset(ring, 0, sizeof(*ring) * entries);
1033 rtlpci->tx_ring[prio].desc = ring;
1034 rtlpci->tx_ring[prio].dma = dma;
1035 rtlpci->tx_ring[prio].idx = 0;
1036 rtlpci->tx_ring[prio].entries = entries;
1037 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1038
f30d7507
JP		 1039 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1040 prio, ring);
0c817338
LF		 1041
1042 for (i = 0; i < entries; i++) {
d3bb1429 1043 nextdescaddress = (u32) dma +
982d96bb 1044 ((i + 1) % entries) *
d3bb1429 1045 sizeof(*ring);
0c817338
LF		 1046
1047 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1048 true, HW_DESC_TX_NEXTDESC_ADDR,
1049 (u8 *)&nextdescaddress);
1050 }
1051
1052 return 0;
1053}
1054
1055static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1056{
1057 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1058 struct rtl_priv *rtlpriv = rtl_priv(hw);
1059 struct rtl_rx_desc *entry = NULL;
1060 int i, rx_queue_idx;
1061 u8 tmp_one = 1;
1062
1063 /*
1064 *rx_queue_idx 0:RX_MPDU_QUEUE
1065 *rx_queue_idx 1:RX_CMD_QUEUE
1066 */
1067 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1068 rx_queue_idx++) {
1069 rtlpci->rx_ring[rx_queue_idx].desc =
1070 pci_alloc_consistent(rtlpci->pdev,
1071 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1072 desc) * rtlpci->rxringcount,
1073 &rtlpci->rx_ring[rx_queue_idx].dma);
1074
1075 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1076 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1077 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1078 "Cannot allocate RX ring\n");
0c817338
LF		 1079 return -ENOMEM;
1080 }
1081
1082 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1083 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1084 rtlpci->rxringcount);
1085
1086 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1087
0019a2c9
LF		 1088 /* If amsdu_8k is disabled, set buffersize to 4096. This
1089 * change will reduce memory fragmentation.
1090 */
1091 if (rtlpci->rxbuffersize > 4096 &&
1092 rtlpriv->rtlhal.disable_amsdu_8k)
1093 rtlpci->rxbuffersize = 4096;
1094
0c817338
LF		 1095 for (i = 0; i < rtlpci->rxringcount; i++) {
1096 struct sk_buff *skb =
1097 dev_alloc_skb(rtlpci->rxbuffersize);
1098 u32 bufferaddress;
0c817338
LF		 1099 if (!skb)
1100 return 0;
f11bbfd8 1101 kmemleak_not_leak(skb);
bdc4bf65 1102 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
0c817338
LF		 1103
1104 /*skb->dev = dev; */
1105
1106 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1107
1108 /*
1109 *just set skb->cb to mapping addr
1110 *for pci_unmap_single use
1111 */
1112 *((dma_addr_t *) skb->cb) =
1113 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1114 rtlpci->rxbuffersize,
1115 PCI_DMA_FROMDEVICE);
1116
d3bb1429 1117 bufferaddress = (*((dma_addr_t *)skb->cb));
0c817338
LF		 1118 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1119 HW_DESC_RXBUFF_ADDR,
1120 (u8 *)&bufferaddress);
1121 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1122 HW_DESC_RXPKT_LEN,
1123 (u8 *)&rtlpci->
1124 rxbuffersize);
1125 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1126 HW_DESC_RXOWN,
2c208890 1127 &tmp_one);
0c817338
LF		 1128 }
1129
1130 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
2c208890 1131 HW_DESC_RXERO, &tmp_one);
0c817338
LF		 1132 }
1133 return 0;
1134}
1135
1136static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1137 unsigned int prio)
1138{
1139 struct rtl_priv *rtlpriv = rtl_priv(hw);
1140 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1141 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1142
1143 while (skb_queue_len(&ring->queue)) {
1144 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1145 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1146
1147 pci_unmap_single(rtlpci->pdev,
d3bb1429 1148 rtlpriv->cfg->
0c817338 1149 ops->get_desc((u8 *) entry, true,
d3bb1429 1150 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 1151 skb->len, PCI_DMA_TODEVICE);
1152 kfree_skb(skb);
1153 ring->idx = (ring->idx + 1) % ring->entries;
1154 }
1155
7f66c2f9
SG		 1156 if (ring->desc) {
1157 pci_free_consistent(rtlpci->pdev,
1158 sizeof(*ring->desc) * ring->entries,
1159 ring->desc, ring->dma);
1160 ring->desc = NULL;
1161 }
0c817338
LF		 1162}
1163
1164static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1165{
1166 int i, rx_queue_idx;
1167
1168 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1169 /*rx_queue_idx 1:RX_CMD_QUEUE */
1170 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1171 rx_queue_idx++) {
1172 for (i = 0; i < rtlpci->rxringcount; i++) {
1173 struct sk_buff *skb =
1174 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1175 if (!skb)
1176 continue;
1177
1178 pci_unmap_single(rtlpci->pdev,
1179 *((dma_addr_t *) skb->cb),
1180 rtlpci->rxbuffersize,
1181 PCI_DMA_FROMDEVICE);
1182 kfree_skb(skb);
1183 }
1184
7f66c2f9
SG		 1185 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1186 pci_free_consistent(rtlpci->pdev,
0c817338
LF		 1187 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1188 desc) * rtlpci->rxringcount,
1189 rtlpci->rx_ring[rx_queue_idx].desc,
1190 rtlpci->rx_ring[rx_queue_idx].dma);
7f66c2f9
SG		 1191 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1192 }
0c817338
LF		 1193 }
1194}
1195
1196static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1197{
1198 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1199 int ret;
1200 int i;
1201
1202 ret = _rtl_pci_init_rx_ring(hw);
1203 if (ret)
1204 return ret;
1205
1206 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1207 ret = _rtl_pci_init_tx_ring(hw, i,
1208 rtlpci->txringcount[i]);
1209 if (ret)
1210 goto err_free_rings;
1211 }
1212
1213 return 0;
1214
1215err_free_rings:
1216 _rtl_pci_free_rx_ring(rtlpci);
1217
1218 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1219 if (rtlpci->tx_ring[i].desc)
1220 _rtl_pci_free_tx_ring(hw, i);
1221
1222 return 1;
1223}
1224
1225static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1226{
1227 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1228 u32 i;
1229
1230 /*free rx rings */
1231 _rtl_pci_free_rx_ring(rtlpci);
1232
1233 /*free tx rings */
1234 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1235 _rtl_pci_free_tx_ring(hw, i);
1236
1237 return 0;
1238}
1239
1240int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1241{
1242 struct rtl_priv *rtlpriv = rtl_priv(hw);
1243 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1244 int i, rx_queue_idx;
1245 unsigned long flags;
1246 u8 tmp_one = 1;
1247
1248 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1249 /*rx_queue_idx 1:RX_CMD_QUEUE */
1250 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1251 rx_queue_idx++) {
1252 /*
1253 *force the rx_ring[RX_MPDU_QUEUE/
1254 *RX_CMD_QUEUE].idx to the first one
1255 */
1256 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1257 struct rtl_rx_desc *entry = NULL;
1258
1259 for (i = 0; i < rtlpci->rxringcount; i++) {
1260 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1261 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1262 false,
1263 HW_DESC_RXOWN,
2c208890 1264 &tmp_one);
0c817338
LF		 1265 }
1266 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1267 }
1268 }
1269
1270 /*
1271 *after reset, release previous pending packet,
1272 *and force the tx idx to the first one
1273 */
0c817338
LF		 1274 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1275 if (rtlpci->tx_ring[i].desc) {
1276 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1277
1278 while (skb_queue_len(&ring->queue)) {
5a2766ab
LF		 1279 struct rtl_tx_desc *entry;
1280 struct sk_buff *skb;
0c817338 1281
5a2766ab
LF		 1282 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock,
1283 flags);
1284 entry = &ring->desc[ring->idx];
1285 skb = __skb_dequeue(&ring->queue);
0c817338 1286 pci_unmap_single(rtlpci->pdev,
d3bb1429 1287 rtlpriv->cfg->ops->
0c817338
LF		 1288 get_desc((u8 *)
1289 entry,
1290 true,
d3bb1429 1291 HW_DESC_TXBUFF_ADDR),
0c817338 1292 skb->len, PCI_DMA_TODEVICE);
0c817338 1293 ring->idx = (ring->idx + 1) % ring->entries;
5a2766ab
LF		 1294 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1295 flags);
1296 kfree_skb(skb);
0c817338
LF		 1297 }
1298 ring->idx = 0;
1299 }
1300 }
1301
0c817338
LF		 1302 return 0;
1303}
1304
c7cfe38e 1305static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
36323f81 1306 struct ieee80211_sta *sta,
c7cfe38e 1307 struct sk_buff *skb)
0c817338 1308{
c7cfe38e 1309 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e
C		 1310 struct rtl_sta_info *sta_entry = NULL;
1311 u8 tid = rtl_get_tid(skb);
0f015453 1312 __le16 fc = rtl_get_fc(skb);
c7cfe38e
C		 1313
1314 if (!sta)
1315 return false;
1316 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1317
1318 if (!rtlpriv->rtlhal.earlymode_enable)
1319 return false;
0f015453
LF		 1320 if (ieee80211_is_nullfunc(fc))
1321 return false;
1322 if (ieee80211_is_qos_nullfunc(fc))
1323 return false;
1324 if (ieee80211_is_pspoll(fc))
1325 return false;
c7cfe38e
C		 1326 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1327 return false;
1328 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1329 return false;
1330 if (tid > 7)
1331 return false;
1332
1333 /* maybe every tid should be checked */
1334 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1335 return false;
1336
1337 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1338 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1339 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
0c817338 1340
c7cfe38e 1341 return true;
0c817338
LF		 1342}
1343
36323f81
TH		 1344static int rtl_pci_tx(struct ieee80211_hw *hw,
1345 struct ieee80211_sta *sta,
1346 struct sk_buff *skb,
1347 struct rtl_tcb_desc *ptcb_desc)
0c817338
LF		 1348{
1349 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 1350 struct rtl_sta_info *sta_entry = NULL;
0c817338
LF		 1351 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1352 struct rtl8192_tx_ring *ring;
1353 struct rtl_tx_desc *pdesc;
1354 u8 idx;
c7cfe38e 1355 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
0c817338 1356 unsigned long flags;
c7cfe38e
C		 1357 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1358 __le16 fc = rtl_get_fc(skb);
0c817338
LF		 1359 u8 *pda_addr = hdr->addr1;
1360 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1361 /*ssn */
0c817338
LF		 1362 u8 tid = 0;
1363 u16 seq_number = 0;
1364 u8 own;
1365 u8 temp_one = 1;
1366
0f015453
LF		 1367 if (ieee80211_is_mgmt(fc))
1368 rtl_tx_mgmt_proc(hw, skb);
c7cfe38e
C		 1369
1370 if (rtlpriv->psc.sw_ps_enabled) {
1371 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1372 !ieee80211_has_pm(fc))
1373 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1374 }
0c817338 1375
c7cfe38e 1376 rtl_action_proc(hw, skb, true);
0c817338
LF		 1377
1378 if (is_multicast_ether_addr(pda_addr))
1379 rtlpriv->stats.txbytesmulticast += skb->len;
1380 else if (is_broadcast_ether_addr(pda_addr))
1381 rtlpriv->stats.txbytesbroadcast += skb->len;
1382 else
1383 rtlpriv->stats.txbytesunicast += skb->len;
1384
1385 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0c817338
LF		 1386 ring = &rtlpci->tx_ring[hw_queue];
1387 if (hw_queue != BEACON_QUEUE)
1388 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1389 ring->entries;
1390 else
1391 idx = 0;
1392
1393 pdesc = &ring->desc[idx];
1394 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1395 true, HW_DESC_OWN);
1396
1397 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1398 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 1399 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1400 hw_queue, ring->idx, idx,
1401 skb_queue_len(&ring->queue));
0c817338
LF		 1402
1403 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1404 return skb->len;
1405 }
1406
0c817338 1407 if (ieee80211_is_data_qos(fc)) {
c7cfe38e
C		 1408 tid = rtl_get_tid(skb);
1409 if (sta) {
1410 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1411 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1412 IEEE80211_SCTL_SEQ) >> 4;
1413 seq_number += 1;
1414
1415 if (!ieee80211_has_morefrags(hdr->frame_control))
1416 sta_entry->tids[tid].seq_number = seq_number;
1417 }
0c817338
LF		 1418 }
1419
1420 if (ieee80211_is_data(fc))
1421 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1422
c7cfe38e 1423 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
36323f81 1424 info, sta, skb, hw_queue, ptcb_desc);
0c817338
LF		 1425
1426 __skb_queue_tail(&ring->queue, skb);
1427
c7cfe38e 1428 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
2c208890 1429 HW_DESC_OWN, &temp_one);
0c817338 1430
0c817338
LF		 1431
1432 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1433 hw_queue != BEACON_QUEUE) {
1434
1435 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
f30d7507
JP		 1436 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1437 hw_queue, ring->idx, idx,
1438 skb_queue_len(&ring->queue));
0c817338
LF		 1439
1440 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1441 }
1442
1443 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1444
1445 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1446
1447 return 0;
1448}
1449
c7cfe38e
C		 1450static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1451{
1452 struct rtl_priv *rtlpriv = rtl_priv(hw);
1453 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1454 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1455 u16 i = 0;
1456 int queue_id;
1457 struct rtl8192_tx_ring *ring;
1458
1459 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1460 u32 queue_len;
1461 ring = &pcipriv->dev.tx_ring[queue_id];
1462 queue_len = skb_queue_len(&ring->queue);
1463 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1464 queue_id == TXCMD_QUEUE) {
1465 queue_id--;
1466 continue;
1467 } else {
1468 msleep(20);
1469 i++;
1470 }
1471
1472 /* we just wait 1s for all queues */
1473 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1474 is_hal_stop(rtlhal) || i >= 200)
1475 return;
1476 }
1477}
1478
d3bb1429 1479static void rtl_pci_deinit(struct ieee80211_hw *hw)
0c817338
LF		 1480{
1481 struct rtl_priv *rtlpriv = rtl_priv(hw);
1482 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1483
1484 _rtl_pci_deinit_trx_ring(hw);
1485
1486 synchronize_irq(rtlpci->pdev->irq);
1487 tasklet_kill(&rtlpriv->works.irq_tasklet);
41affd52 1488 cancel_work_sync(&rtlpriv->works.lps_leave_work);
0c817338
LF		 1489
1490 flush_workqueue(rtlpriv->works.rtl_wq);
1491 destroy_workqueue(rtlpriv->works.rtl_wq);
1492
1493}
1494
d3bb1429 1495static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
0c817338
LF		 1496{
1497 struct rtl_priv *rtlpriv = rtl_priv(hw);
1498 int err;
1499
1500 _rtl_pci_init_struct(hw, pdev);
1501
1502 err = _rtl_pci_init_trx_ring(hw);
1503 if (err) {
1504 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1505 "tx ring initialization failed\n");
12325280 1506 return err;
0c817338
LF		 1507 }
1508
12325280 1509 return 0;
0c817338
LF		 1510}
1511
d3bb1429 1512static int rtl_pci_start(struct ieee80211_hw *hw)
0c817338
LF		 1513{
1514 struct rtl_priv *rtlpriv = rtl_priv(hw);
1515 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1516 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1517 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1518
1519 int err;
1520
1521 rtl_pci_reset_trx_ring(hw);
1522
1523 rtlpci->driver_is_goingto_unload = false;
1524 err = rtlpriv->cfg->ops->hw_init(hw);
1525 if (err) {
1526 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507 1527 "Failed to config hardware!\n");
0c817338
LF		 1528 return err;
1529 }
1530
1531 rtlpriv->cfg->ops->enable_interrupt(hw);
f30d7507 1532 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
0c817338
LF		 1533
1534 rtl_init_rx_config(hw);
1535
fb914ebf 1536 /*should be after adapter start and interrupt enable. */
0c817338
LF		 1537 set_hal_start(rtlhal);
1538
1539 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1540
1541 rtlpci->up_first_time = false;
1542
f30d7507 1543 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
0c817338
LF		 1544 return 0;
1545}
1546
d3bb1429 1547static void rtl_pci_stop(struct ieee80211_hw *hw)
0c817338
LF		 1548{
1549 struct rtl_priv *rtlpriv = rtl_priv(hw);
1550 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1551 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1552 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1553 unsigned long flags;
1554 u8 RFInProgressTimeOut = 0;
1555
1556 /*
fb914ebf 1557 *should be before disable interrupt&adapter
0c817338
LF		 1558 *and will do it immediately.
1559 */
1560 set_hal_stop(rtlhal);
1561
1562 rtlpriv->cfg->ops->disable_interrupt(hw);
41affd52 1563 cancel_work_sync(&rtlpriv->works.lps_leave_work);
0c817338
LF		 1564
1565 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1566 while (ppsc->rfchange_inprogress) {
1567 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1568 if (RFInProgressTimeOut > 100) {
1569 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1570 break;
1571 }
1572 mdelay(1);
1573 RFInProgressTimeOut++;
1574 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1575 }
1576 ppsc->rfchange_inprogress = true;
1577 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1578
1579 rtlpci->driver_is_goingto_unload = true;
1580 rtlpriv->cfg->ops->hw_disable(hw);
b0302aba
LF		 1581 /* some things are not needed if firmware not available */
1582 if (!rtlpriv->max_fw_size)
1583 return;
0c817338
LF		 1584 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1585
1586 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1587 ppsc->rfchange_inprogress = false;
1588 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1589
1590 rtl_pci_enable_aspm(hw);
1591}
1592
1593static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1594 struct ieee80211_hw *hw)
1595{
1596 struct rtl_priv *rtlpriv = rtl_priv(hw);
1597 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1598 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1599 struct pci_dev *bridge_pdev = pdev->bus->self;
1600 u16 venderid;
1601 u16 deviceid;
c7cfe38e 1602 u8 revisionid;
0c817338
LF		 1603 u16 irqline;
1604 u8 tmp;
1605
fc7707a4 1606 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
0c817338
LF		 1607 venderid = pdev->vendor;
1608 deviceid = pdev->device;
c7cfe38e 1609 pci_read_config_byte(pdev, 0x8, &revisionid);
0c817338
LF		 1610 pci_read_config_word(pdev, 0x3C, &irqline);
1611
fa7ccfb1
LF		 1612 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1613 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1614 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1615 * the correct driver is r8192e_pci, thus this routine should
1616 * return false.
1617 */
1618 if (deviceid == RTL_PCI_8192SE_DID &&
1619 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1620 return false;
1621
0c817338
LF		 1622 if (deviceid == RTL_PCI_8192_DID ||
1623 deviceid == RTL_PCI_0044_DID ||
1624 deviceid == RTL_PCI_0047_DID ||
1625 deviceid == RTL_PCI_8192SE_DID ||
1626 deviceid == RTL_PCI_8174_DID ||
1627 deviceid == RTL_PCI_8173_DID ||
1628 deviceid == RTL_PCI_8172_DID ||
1629 deviceid == RTL_PCI_8171_DID) {
c7cfe38e 1630 switch (revisionid) {
0c817338
LF		 1631 case RTL_PCI_REVISION_ID_8192PCIE:
1632 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1633 "8192 PCI-E is found - vid/did=%x/%x\n",
1634 venderid, deviceid);
0c817338 1635 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
0f015453 1636 return false;
0c817338
LF		 1637 case RTL_PCI_REVISION_ID_8192SE:
1638 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1639 "8192SE is found - vid/did=%x/%x\n",
1640 venderid, deviceid);
0c817338
LF		 1641 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1642 break;
1643 default:
1644 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 1645 "Err: Unknown device - vid/did=%x/%x\n",
1646 venderid, deviceid);
0c817338
LF		 1647 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1648 break;
1649
1650 }
0f015453
LF		 1651 } else if (deviceid == RTL_PCI_8723AE_DID) {
1652 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1653 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1654 "8723AE PCI-E is found - "
1655 "vid/did=%x/%x\n", venderid, deviceid);
0c817338
LF		 1656 } else if (deviceid == RTL_PCI_8192CET_DID ||
1657 deviceid == RTL_PCI_8192CE_DID ||
1658 deviceid == RTL_PCI_8191CE_DID ||
1659 deviceid == RTL_PCI_8188CE_DID) {
1660 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1661 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1662 "8192C PCI-E is found - vid/did=%x/%x\n",
1663 venderid, deviceid);
c7cfe38e
C		 1664 } else if (deviceid == RTL_PCI_8192DE_DID ||
1665 deviceid == RTL_PCI_8192DE_DID2) {
1666 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1667 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1668 "8192D PCI-E is found - vid/did=%x/%x\n",
1669 venderid, deviceid);
0c817338
LF		 1670 } else {
1671 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 1672 "Err: Unknown device - vid/did=%x/%x\n",
1673 venderid, deviceid);
0c817338
LF		 1674
1675 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1676 }
1677
c7cfe38e
C		 1678 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1679 if (revisionid == 0 || revisionid == 1) {
1680 if (revisionid == 0) {
f30d7507
JP		 1681 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1682 "Find 92DE MAC0\n");
c7cfe38e
C		 1683 rtlhal->interfaceindex = 0;
1684 } else if (revisionid == 1) {
1685 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1686 "Find 92DE MAC1\n");
c7cfe38e
C		 1687 rtlhal->interfaceindex = 1;
1688 }
1689 } else {
1690 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507
JP		 1691 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1692 venderid, deviceid, revisionid);
c7cfe38e
C		 1693 rtlhal->interfaceindex = 0;
1694 }
1695 }
0c817338
LF		 1696 /*find bus info */
1697 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1698 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1699 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1700
b6b67df3
LF		 1701 if (bridge_pdev) {
1702 /*find bridge info if available */
1703 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1704 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1705 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1706 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1707 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1708 "Pci Bridge Vendor is found index: %d\n",
1709 tmp);
b6b67df3
LF		 1710 break;
1711 }
0c817338
LF		 1712 }
1713 }
1714
1715 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1716 PCI_BRIDGE_VENDOR_UNKNOWN) {
1717 pcipriv->ndis_adapter.pcibridge_busnum =
1718 bridge_pdev->bus->number;
1719 pcipriv->ndis_adapter.pcibridge_devnum =
1720 PCI_SLOT(bridge_pdev->devfn);
1721 pcipriv->ndis_adapter.pcibridge_funcnum =
1722 PCI_FUNC(bridge_pdev->devfn);
c7cfe38e
C		 1723 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1724 pci_pcie_cap(bridge_pdev);
0c817338
LF		 1725 pcipriv->ndis_adapter.num4bytes =
1726 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1727
1728 rtl_pci_get_linkcontrol_field(hw);
1729
1730 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1731 PCI_BRIDGE_VENDOR_AMD) {
1732 pcipriv->ndis_adapter.amd_l1_patch =
1733 rtl_pci_get_amd_l1_patch(hw);
1734 }
1735 }
1736
1737 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1738 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
1739 pcipriv->ndis_adapter.busnumber,
1740 pcipriv->ndis_adapter.devnumber,
1741 pcipriv->ndis_adapter.funcnumber,
1742 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
0c817338
LF		 1743
1744 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1745 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1746 pcipriv->ndis_adapter.pcibridge_busnum,
1747 pcipriv->ndis_adapter.pcibridge_devnum,
1748 pcipriv->ndis_adapter.pcibridge_funcnum,
1749 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1750 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1751 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1752 pcipriv->ndis_adapter.amd_l1_patch);
0c817338
LF		 1753
1754 rtl_pci_parse_configuration(pdev, hw);
1755
1756 return true;
1757}
1758
1759int __devinit rtl_pci_probe(struct pci_dev *pdev,
1760 const struct pci_device_id *id)
1761{
1762 struct ieee80211_hw *hw = NULL;
1763
1764 struct rtl_priv *rtlpriv = NULL;
1765 struct rtl_pci_priv *pcipriv = NULL;
1766 struct rtl_pci *rtlpci;
1767 unsigned long pmem_start, pmem_len, pmem_flags;
1768 int err;
1769
1770 err = pci_enable_device(pdev);
1771 if (err) {
9d833ed7
JP		 1772 RT_ASSERT(false, "%s : Cannot enable new PCI device\n",
1773 pci_name(pdev));
0c817338
LF		 1774 return err;
1775 }
1776
1777 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1778 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
9d833ed7
JP		 1779 RT_ASSERT(false,
1780 "Unable to obtain 32bit DMA for consistent allocations\n");
3d86b930
TG		 1781 err = -ENOMEM;
1782 goto fail1;
0c817338
LF		 1783 }
1784 }
1785
1786 pci_set_master(pdev);
1787
1788 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1789 sizeof(struct rtl_priv), &rtl_ops);
1790 if (!hw) {
1791 RT_ASSERT(false,
9d833ed7 1792 "%s : ieee80211 alloc failed\n", pci_name(pdev));
0c817338
LF		 1793 err = -ENOMEM;
1794 goto fail1;
1795 }
1796
1797 SET_IEEE80211_DEV(hw, &pdev->dev);
1798 pci_set_drvdata(pdev, hw);
1799
1800 rtlpriv = hw->priv;
1801 pcipriv = (void *)rtlpriv->priv;
1802 pcipriv->dev.pdev = pdev;
b0302aba 1803 init_completion(&rtlpriv->firmware_loading_complete);
0c817338 1804
c7cfe38e
C		 1805 /* init cfg & intf_ops */
1806 rtlpriv->rtlhal.interface = INTF_PCI;
1807 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1808 rtlpriv->intf_ops = &rtl_pci_ops;
1809
0c817338
LF		 1810 /*
1811 *init dbgp flags before all
1812 *other functions, because we will
1813 *use it in other funtions like
1814 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1815 *you can not use these macro
1816 *before this
1817 */
1818 rtl_dbgp_flag_init(hw);
1819
1820 /* MEM map */
1821 err = pci_request_regions(pdev, KBUILD_MODNAME);
1822 if (err) {
9d833ed7 1823 RT_ASSERT(false, "Can't obtain PCI resources\n");
3d86b930 1824 goto fail1;
0c817338
LF		 1825 }
1826
c7cfe38e
C		 1827 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1828 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1829 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
0c817338
LF		 1830
1831 /*shared mem start */
1832 rtlpriv->io.pci_mem_start =
c7cfe38e
C		 1833 (unsigned long)pci_iomap(pdev,
1834 rtlpriv->cfg->bar_id, pmem_len);
0c817338 1835 if (rtlpriv->io.pci_mem_start == 0) {
9d833ed7 1836 RT_ASSERT(false, "Can't map PCI mem\n");
3d86b930 1837 err = -ENOMEM;
0c817338
LF		 1838 goto fail2;
1839 }
1840
1841 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1842 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
1843 pmem_start, pmem_len, pmem_flags,
1844 rtlpriv->io.pci_mem_start);
0c817338
LF		 1845
1846 /* Disable Clk Request */
1847 pci_write_config_byte(pdev, 0x81, 0);
1848 /* leave D3 mode */
1849 pci_write_config_byte(pdev, 0x44, 0);
1850 pci_write_config_byte(pdev, 0x04, 0x06);
1851 pci_write_config_byte(pdev, 0x04, 0x07);
1852
0c817338 1853 /* find adapter */
3d86b930
TG		 1854 if (!_rtl_pci_find_adapter(pdev, hw)) {
1855 err = -ENODEV;
fa7ccfb1 1856 goto fail3;
3d86b930 1857 }
0c817338
LF		 1858
1859 /* Init IO handler */
1860 _rtl_pci_io_handler_init(&pdev->dev, hw);
1861
1862 /*like read eeprom and so on */
1863 rtlpriv->cfg->ops->read_eeprom_info(hw);
1864
0c817338
LF		 1865 /*aspm */
1866 rtl_pci_init_aspm(hw);
1867
1868 /* Init mac80211 sw */
1869 err = rtl_init_core(hw);
1870 if (err) {
1871 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1872 "Can't allocate sw for mac80211\n");
0c817338
LF		 1873 goto fail3;
1874 }
1875
1876 /* Init PCI sw */
12325280 1877 err = rtl_pci_init(hw, pdev);
0c817338 1878 if (err) {
f30d7507 1879 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n");
0c817338
LF		 1880 goto fail3;
1881 }
1882
574e02ab
LF		 1883 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1884 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n");
1885 err = -ENODEV;
1886 goto fail3;
1887 }
1888
1889 rtlpriv->cfg->ops->init_sw_leds(hw);
1890
0c817338
LF		 1891 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1892 if (err) {
1893 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1894 "failed to create sysfs device attributes\n");
0c817338
LF		 1895 goto fail3;
1896 }
1897
0c817338
LF		 1898 rtlpci = rtl_pcidev(pcipriv);
1899 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1900 IRQF_SHARED, KBUILD_MODNAME, hw);
1901 if (err) {
1902 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1903 "%s: failed to register IRQ handler\n",
1904 wiphy_name(hw->wiphy));
0c817338 1905 goto fail3;
0c817338 1906 }
b0302aba 1907 rtlpci->irq_alloc = 1;
0c817338 1908
0c817338
LF		 1909 return 0;
1910
1911fail3:
0c817338
LF		 1912 rtl_deinit_core(hw);
1913 _rtl_pci_io_handler_release(hw);
0c817338
LF		 1914
1915 if (rtlpriv->io.pci_mem_start != 0)
62e63975 1916 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 1917
1918fail2:
1919 pci_release_regions(pdev);
b0302aba 1920 complete(&rtlpriv->firmware_loading_complete);
0c817338
LF		 1921
1922fail1:
3d86b930
TG		 1923 if (hw)
1924 ieee80211_free_hw(hw);
1925 pci_set_drvdata(pdev, NULL);
0c817338
LF		 1926 pci_disable_device(pdev);
1927
3d86b930 1928 return err;
0c817338
LF		 1929
1930}
1931EXPORT_SYMBOL(rtl_pci_probe);
1932
1933void rtl_pci_disconnect(struct pci_dev *pdev)
1934{
1935 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1936 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1937 struct rtl_priv *rtlpriv = rtl_priv(hw);
1938 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1939 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1940
b0302aba
LF		 1941 /* just in case driver is removed before firmware callback */
1942 wait_for_completion(&rtlpriv->firmware_loading_complete);
0c817338
LF		 1943 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1944
1945 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1946
1947 /*ieee80211_unregister_hw will call ops_stop */
1948 if (rtlmac->mac80211_registered == 1) {
1949 ieee80211_unregister_hw(hw);
1950 rtlmac->mac80211_registered = 0;
1951 } else {
1952 rtl_deinit_deferred_work(hw);
1953 rtlpriv->intf_ops->adapter_stop(hw);
1954 }
44eb65cf 1955 rtlpriv->cfg->ops->disable_interrupt(hw);
0c817338
LF		 1956
1957 /*deinit rfkill */
1958 rtl_deinit_rfkill(hw);
1959
1960 rtl_pci_deinit(hw);
1961 rtl_deinit_core(hw);
0c817338
LF		 1962 _rtl_pci_io_handler_release(hw);
1963 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1964
1965 if (rtlpci->irq_alloc) {
1966 free_irq(rtlpci->pdev->irq, hw);
1967 rtlpci->irq_alloc = 0;
1968 }
1969
1970 if (rtlpriv->io.pci_mem_start != 0) {
62e63975 1971 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 1972 pci_release_regions(pdev);
1973 }
1974
1975 pci_disable_device(pdev);
c7cfe38e
C		 1976
1977 rtl_pci_disable_aspm(hw);
1978
0c817338
LF		 1979 pci_set_drvdata(pdev, NULL);
1980
1981 ieee80211_free_hw(hw);
1982}
1983EXPORT_SYMBOL(rtl_pci_disconnect);
1984
244a77e9 1985#ifdef CONFIG_PM_SLEEP
0c817338
LF		 1986/***************************************
1987kernel pci power state define:
1988PCI_D0 ((pci_power_t __force) 0)
1989PCI_D1 ((pci_power_t __force) 1)
1990PCI_D2 ((pci_power_t __force) 2)
1991PCI_D3hot ((pci_power_t __force) 3)
1992PCI_D3cold ((pci_power_t __force) 4)
1993PCI_UNKNOWN ((pci_power_t __force) 5)
1994
1995This function is called when system
1996goes into suspend state mac80211 will
1997call rtl_mac_stop() from the mac80211
1998suspend function first, So there is
1999no need to call hw_disable here.
2000****************************************/
603be388 2001int rtl_pci_suspend(struct device *dev)
0c817338 2002{
603be388 2003 struct pci_dev *pdev = to_pci_dev(dev);
c7cfe38e
C		 2004 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2005 struct rtl_priv *rtlpriv = rtl_priv(hw);
2006
2007 rtlpriv->cfg->ops->hw_suspend(hw);
2008 rtl_deinit_rfkill(hw);
2009
0c817338
LF		 2010 return 0;
2011}
2012EXPORT_SYMBOL(rtl_pci_suspend);
2013
603be388 2014int rtl_pci_resume(struct device *dev)
0c817338 2015{
603be388 2016 struct pci_dev *pdev = to_pci_dev(dev);
c7cfe38e
C		 2017 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2018 struct rtl_priv *rtlpriv = rtl_priv(hw);
0c817338 2019
c7cfe38e
C		 2020 rtlpriv->cfg->ops->hw_resume(hw);
2021 rtl_init_rfkill(hw);
0c817338
LF		 2022 return 0;
2023}
2024EXPORT_SYMBOL(rtl_pci_resume);
244a77e9 2025#endif /* CONFIG_PM_SLEEP */
0c817338
LF		 2026
2027struct rtl_intf_ops rtl_pci_ops = {
c7cfe38e 2028 .read_efuse_byte = read_efuse_byte,
0c817338
LF		 2029 .adapter_start = rtl_pci_start,
2030 .adapter_stop = rtl_pci_stop,
2031 .adapter_tx = rtl_pci_tx,
c7cfe38e 2032 .flush = rtl_pci_flush,
0c817338 2033 .reset_trx_ring = rtl_pci_reset_trx_ring,
c7cfe38e 2034 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
0c817338
LF		 2035
2036 .disable_aspm = rtl_pci_disable_aspm,
2037 .enable_aspm = rtl_pci_enable_aspm,
2038};
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