[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rtlwifi / rtl8188ee / pwrseqcmd.c

/******************************************************************************
 *
 * Copyright(c) 2009-2013  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/

#include "pwrseqcmd.h"
#include "pwrseq.h"


/*	Description:
*		This routine deal with the Power Configuration CMDs
*		 parsing for RTL8723/RTL8188E Series IC.
*	Assumption:
*		We should follow specific format which was released from HW SD.
*
*	2011.07.07, added by Roger.
*/
bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
			      u8 fab_version, u8 interface_type,
			      struct wlan_pwr_cfg pwrcfgcmd[])

{
	struct wlan_pwr_cfg pwr_cfg_cmd = {0};
	bool b_polling_bit = false;
	u32 ary_idx = 0;
	u8 value = 0;
	u32 offset = 0;
	u32 polling_count = 0;
	u32 max_polling_cnt = 5000;

	do {
		pwr_cfg_cmd = pwrcfgcmd[ary_idx];
		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
			"rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), fab_msk(%#x), interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
			GET_PWR_CFG_OFFSET(pwr_cfg_cmd),
				GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd),
			GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd),
				GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd),
			GET_PWR_CFG_BASE(pwr_cfg_cmd),
				GET_PWR_CFG_CMD(pwr_cfg_cmd),
			GET_PWR_CFG_MASK(pwr_cfg_cmd),
				GET_PWR_CFG_VALUE(pwr_cfg_cmd));

		if ((GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd)&fab_version) &&
		    (GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd)&cut_version) &&
		    (GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd)&interface_type)) {
			switch (GET_PWR_CFG_CMD(pwr_cfg_cmd)) {
			case PWR_CMD_READ:
				RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
					"rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n");
				break;
			case PWR_CMD_WRITE:
				RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
					"rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
				offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);

				/*Read the value from system register*/
				value = rtl_read_byte(rtlpriv, offset);
				value &= (~(GET_PWR_CFG_MASK(pwr_cfg_cmd)));
				value |= (GET_PWR_CFG_VALUE(pwr_cfg_cmd)
				      & GET_PWR_CFG_MASK(pwr_cfg_cmd));

				/*Write the back to sytem register*/
				rtl_write_byte(rtlpriv, offset, value);
				break;
			case PWR_CMD_POLLING:
				RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
					"rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
				b_polling_bit = false;
				offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);

				do {
					value = rtl_read_byte(rtlpriv, offset);

					value &= GET_PWR_CFG_MASK(pwr_cfg_cmd);
					if (value ==
					    (GET_PWR_CFG_VALUE(pwr_cfg_cmd) &
					     GET_PWR_CFG_MASK(pwr_cfg_cmd)))
						b_polling_bit = true;
					else
						udelay(10);

					if (polling_count++ > max_polling_cnt) {
						RT_TRACE(rtlpriv, COMP_INIT,
							 DBG_LOUD,
							 "polling fail in pwrseqcmd\n");
						return false;
					}
				} while (!b_polling_bit);

				break;
			case PWR_CMD_DELAY:
				RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
					"rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
				if (GET_PWR_CFG_VALUE(pwr_cfg_cmd) ==
				    PWRSEQ_DELAY_US)
					udelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
				else
					mdelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
				break;
			case PWR_CMD_END:
				RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
					"rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n");
				return true;
			default:
				RT_ASSERT(false,
					"rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n");
				break;
			}
		}
		ary_idx++;
	} while (1);

	return true;
}
Commit	Line	Data
f0eb856e LF	1	/******************************************************************************
	2	*
	3	* Copyright(c) 2009-2013 Realtek Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
f0eb856e LF	14	* The full GNU General Public License is included in this distribution in the
	15	* file called LICENSE.
	16	*
	17	* Contact Information:
	18	* wlanfae <wlanfae@realtek.com>
	19	* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
	20	* Hsinchu 300, Taiwan.
	21	*
	22	* Larry Finger <Larry.Finger@lwfinger.net>
	23	*
	24	*****************************************************************************/
	25
d3feae41	26	#include "pwrseqcmd.h"
f0eb856e LF	27	#include "pwrseq.h"
	28
	29
	30	/* Description:
c151aed6 LF	31	* This routine deal with the Power Configuration CMDs
	32	* parsing for RTL8723/RTL8188E Series IC.
	33	* Assumption:
	34	* We should follow specific format which was released from HW SD.
	35	*
	36	* 2011.07.07, added by Roger.
	37	*/
	38	bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
	39	u8 fab_version, u8 interface_type,
	40	struct wlan_pwr_cfg pwrcfgcmd[])
f0eb856e	41
f0eb856e	42	{
c151aed6 LF	43	struct wlan_pwr_cfg pwr_cfg_cmd = {0};
c151aed6 LF	44	bool b_polling_bit = false;
f0eb856e	45	u32 ary_idx = 0;
c151aed6	46	u8 value = 0;
f0eb856e LF	47	u32 offset = 0;
	48	u32 polling_count = 0;
	49	u32 max_polling_cnt = 5000;
	50
	51	do {
c151aed6	52	pwr_cfg_cmd = pwrcfgcmd[ary_idx];
f0eb856e	53	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
c151aed6 LF	54	"rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), fab_msk(%#x), interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
	55	GET_PWR_CFG_OFFSET(pwr_cfg_cmd),
	56	GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd),
	57	GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd),
	58	GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd),
	59	GET_PWR_CFG_BASE(pwr_cfg_cmd),
	60	GET_PWR_CFG_CMD(pwr_cfg_cmd),
	61	GET_PWR_CFG_MASK(pwr_cfg_cmd),
	62	GET_PWR_CFG_VALUE(pwr_cfg_cmd));
f0eb856e	63
c151aed6 LF	64	if ((GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd)&fab_version) &&
	65	(GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd)&cut_version) &&
	66	(GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd)&interface_type)) {
	67	switch (GET_PWR_CFG_CMD(pwr_cfg_cmd)) {
f0eb856e LF	68	case PWR_CMD_READ:
f0eb856e LF	69	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
c151aed6	70	"rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n");
f0eb856e	71	break;
c151aed6	72	case PWR_CMD_WRITE:
f0eb856e	73	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
c151aed6 LF	74	"rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
c151aed6 LF	75	offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
f0eb856e	76
c151aed6 LF	77	/Read the value from system register/
	78	value = rtl_read_byte(rtlpriv, offset);
	79	value &= (~(GET_PWR_CFG_MASK(pwr_cfg_cmd)));
	80	value \|= (GET_PWR_CFG_VALUE(pwr_cfg_cmd)
	81	& GET_PWR_CFG_MASK(pwr_cfg_cmd));
f0eb856e	82
c151aed6 LF	83	/Write the back to sytem register/
c151aed6 LF	84	rtl_write_byte(rtlpriv, offset, value);
f0eb856e LF	85	break;
	86	case PWR_CMD_POLLING:
	87	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
c151aed6 LF	88	"rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
	89	b_polling_bit = false;
	90	offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
f0eb856e LF	91
f0eb856e LF	92	do {
c151aed6	93	value = rtl_read_byte(rtlpriv, offset);
f0eb856e	94
c151aed6 LF	95	value &= GET_PWR_CFG_MASK(pwr_cfg_cmd);
	96	if (value ==
	97	(GET_PWR_CFG_VALUE(pwr_cfg_cmd) &
	98	GET_PWR_CFG_MASK(pwr_cfg_cmd)))
	99	b_polling_bit = true;
f0eb856e LF	100	else
	101	udelay(10);
	102
	103	if (polling_count++ > max_polling_cnt) {
	104	RT_TRACE(rtlpriv, COMP_INIT,
	105	DBG_LOUD,
	106	"polling fail in pwrseqcmd\n");
	107	return false;
	108	}
c151aed6	109	} while (!b_polling_bit);
f0eb856e LF	110
	111	break;
	112	case PWR_CMD_DELAY:
	113	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
c151aed6 LF	114	"rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
	115	if (GET_PWR_CFG_VALUE(pwr_cfg_cmd) ==
	116	PWRSEQ_DELAY_US)
	117	udelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
f0eb856e	118	else
c151aed6	119	mdelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
f0eb856e LF	120	break;
	121	case PWR_CMD_END:
	122	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
c151aed6	123	"rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n");
f0eb856e	124	return true;
f0eb856e LF	125	default:
f0eb856e LF	126	RT_ASSERT(false,
c151aed6	127	"rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n");
f0eb856e LF	128	break;
	129	}
	130	}
f0eb856e LF	131	ary_idx++;
	132	} while (1);
	133
	134	return true;
	135	}