[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / rtlwifi / rtl8188ee / sw.c

/******************************************************************************
 *
 * Copyright(c) 2009-2013  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/

#include "../wifi.h"
#include "../core.h"
#include "../pci.h"
#include "../base.h"
#include "reg.h"
#include "def.h"
#include "phy.h"
#include "dm.h"
#include "hw.h"
#include "sw.h"
#include "trx.h"
#include "led.h"
#include "table.h"

#include <linux/vmalloc.h>
#include <linux/module.h>

static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw)
{
	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));

	/*close ASPM for AMD defaultly */
	rtlpci->const_amdpci_aspm = 0;

	/* ASPM PS mode.
	 * 0 - Disable ASPM,
	 * 1 - Enable ASPM without Clock Req,
	 * 2 - Enable ASPM with Clock Req,
	 * 3 - Alwyas Enable ASPM with Clock Req,
	 * 4 - Always Enable ASPM without Clock Req.
	 * set defult to RTL8192CE:3 RTL8192E:2
	 */
	rtlpci->const_pci_aspm = 3;

	/*Setting for PCI-E device */
	rtlpci->const_devicepci_aspm_setting = 0x03;

	/*Setting for PCI-E bridge */
	rtlpci->const_hostpci_aspm_setting = 0x02;

	/* In Hw/Sw Radio Off situation.
	 * 0 - Default,
	 * 1 - From ASPM setting without low Mac Pwr,
	 * 2 - From ASPM setting with low Mac Pwr,
	 * 3 - Bus D3
	 * set default to RTL8192CE:0 RTL8192SE:2
	 */
	rtlpci->const_hwsw_rfoff_d3 = 0;

	/* This setting works for those device with
	 * backdoor ASPM setting such as EPHY setting.
	 * 0 - Not support ASPM,
	 * 1 - Support ASPM,
	 * 2 - According to chipset.
	 */
	rtlpci->const_support_pciaspm = 1;
}

int rtl88e_init_sw_vars(struct ieee80211_hw *hw)
{
	int err = 0;
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
	u8 tid;

	rtl8188ee_bt_reg_init(hw);
	rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;

	rtlpriv->dm.dm_initialgain_enable = 1;
	rtlpriv->dm.dm_flag = 0;
	rtlpriv->dm.disable_framebursting = 0;
	rtlpriv->dm.thermalvalue = 0;
	rtlpci->transmit_config = CFENDFORM | BIT(15);

	/* compatible 5G band 88ce just 2.4G band & smsp */
	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;

	rtlpci->receive_config = (RCR_APPFCS |
				  RCR_APP_MIC |
				  RCR_APP_ICV |
				  RCR_APP_PHYST_RXFF |
				  RCR_HTC_LOC_CTRL |
				  RCR_AMF |
				  RCR_ACF |
				  RCR_ADF |
				  RCR_AICV |
				  RCR_ACRC32 |
				  RCR_AB |
				  RCR_AM |
				  RCR_APM |
				  0);

	rtlpci->irq_mask[0] =
				(u32) (IMR_PSTIMEOUT	|
				IMR_HSISR_IND_ON_INT	|
				IMR_C2HCMD		|
				IMR_HIGHDOK		|
				IMR_MGNTDOK		|
				IMR_BKDOK		|
				IMR_BEDOK		|
				IMR_VIDOK		|
				IMR_VODOK		|
				IMR_RDU			|
				IMR_ROK			|
				0);
	rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0);
	rtlpci->sys_irq_mask = (u32) (HSIMR_PDN_INT_EN | HSIMR_RON_INT_EN);

	/* for debug level */
	rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
	/* for LPS & IPS */
	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
	if (!rtlpriv->psc.inactiveps)
		pr_info("rtl8188ee: Power Save off (module option)\n");
	if (!rtlpriv->psc.fwctrl_lps)
		pr_info("rtl8188ee: FW Power Save off (module option)\n");
	rtlpriv->psc.reg_fwctrl_lps = 3;
	rtlpriv->psc.reg_max_lps_awakeintvl = 5;
	/* for ASPM, you can close aspm through
	 * set const_support_pciaspm = 0
	 */
	rtl88e_init_aspm_vars(hw);

	if (rtlpriv->psc.reg_fwctrl_lps == 1)
		rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
	else if (rtlpriv->psc.reg_fwctrl_lps == 2)
		rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
	else if (rtlpriv->psc.reg_fwctrl_lps == 3)
		rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;

	/* for firmware buf */
	rtlpriv->rtlhal.pfirmware = vmalloc(0x8000);
	if (!rtlpriv->rtlhal.pfirmware) {
		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
			 "Can't alloc buffer for fw.\n");
		return 1;
	}

	rtlpriv->cfg->fw_name = "rtlwifi/rtl8188efw.bin";
	rtlpriv->max_fw_size = 0x8000;
	pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
	err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
				      rtlpriv->io.dev, GFP_KERNEL, hw,
				      rtl_fw_cb);
	if (err) {
		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
			 "Failed to request firmware!\n");
		return 1;
	}

	/* for early mode */
	rtlpriv->rtlhal.earlymode_enable = false;
	rtlpriv->rtlhal.max_earlymode_num = 10;
	for (tid = 0; tid < 8; tid++)
		skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);

	/*low power */
	rtlpriv->psc.low_power_enable = false;
	if (rtlpriv->psc.low_power_enable) {
		init_timer(&rtlpriv->works.fw_clockoff_timer);
		setup_timer(&rtlpriv->works.fw_clockoff_timer,
			    rtl88ee_fw_clk_off_timer_callback,
			    (unsigned long)hw);
	}

	init_timer(&rtlpriv->works.fast_antenna_training_timer);
	setup_timer(&rtlpriv->works.fast_antenna_training_timer,
		    rtl88e_dm_fast_antenna_training_callback,
		    (unsigned long)hw);
	return err;
}

void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);

	if (rtlpriv->rtlhal.pfirmware) {
		vfree(rtlpriv->rtlhal.pfirmware);
		rtlpriv->rtlhal.pfirmware = NULL;
	}

	if (rtlpriv->psc.low_power_enable)
		del_timer_sync(&rtlpriv->works.fw_clockoff_timer);

	del_timer_sync(&rtlpriv->works.fast_antenna_training_timer);
}

static struct rtl_hal_ops rtl8188ee_hal_ops = {
	.init_sw_vars = rtl88e_init_sw_vars,
	.deinit_sw_vars = rtl88e_deinit_sw_vars,
	.read_eeprom_info = rtl88ee_read_eeprom_info,
	.interrupt_recognized = rtl88ee_interrupt_recognized,/*need check*/
	.hw_init = rtl88ee_hw_init,
	.hw_disable = rtl88ee_card_disable,
	.hw_suspend = rtl88ee_suspend,
	.hw_resume = rtl88ee_resume,
	.enable_interrupt = rtl88ee_enable_interrupt,
	.disable_interrupt = rtl88ee_disable_interrupt,
	.set_network_type = rtl88ee_set_network_type,
	.set_chk_bssid = rtl88ee_set_check_bssid,
	.set_qos = rtl88ee_set_qos,
	.set_bcn_reg = rtl88ee_set_beacon_related_registers,
	.set_bcn_intv = rtl88ee_set_beacon_interval,
	.update_interrupt_mask = rtl88ee_update_interrupt_mask,
	.get_hw_reg = rtl88ee_get_hw_reg,
	.set_hw_reg = rtl88ee_set_hw_reg,
	.update_rate_tbl = rtl88ee_update_hal_rate_tbl,
	.fill_tx_desc = rtl88ee_tx_fill_desc,
	.fill_tx_cmddesc = rtl88ee_tx_fill_cmddesc,
	.query_rx_desc = rtl88ee_rx_query_desc,
	.set_channel_access = rtl88ee_update_channel_access_setting,
	.radio_onoff_checking = rtl88ee_gpio_radio_on_off_checking,
	.set_bw_mode = rtl88e_phy_set_bw_mode,
	.switch_channel = rtl88e_phy_sw_chnl,
	.dm_watchdog = rtl88e_dm_watchdog,
	.scan_operation_backup = rtl_phy_scan_operation_backup,
	.set_rf_power_state = rtl88e_phy_set_rf_power_state,
	.led_control = rtl88ee_led_control,
	.set_desc = rtl88ee_set_desc,
	.get_desc = rtl88ee_get_desc,
	.tx_polling = rtl88ee_tx_polling,
	.enable_hw_sec = rtl88ee_enable_hw_security_config,
	.set_key = rtl88ee_set_key,
	.init_sw_leds = rtl88ee_init_sw_leds,
	.get_bbreg = rtl88e_phy_query_bb_reg,
	.set_bbreg = rtl88e_phy_set_bb_reg,
	.get_rfreg = rtl88e_phy_query_rf_reg,
	.set_rfreg = rtl88e_phy_set_rf_reg,
};

static struct rtl_mod_params rtl88ee_mod_params = {
	.sw_crypto = false,
	.inactiveps = true,
	.swctrl_lps = false,
	.fwctrl_lps = true,
	.msi_support = false,
	.debug = DBG_EMERG,
};

static struct rtl_hal_cfg rtl88ee_hal_cfg = {
	.bar_id = 2,
	.write_readback = true,
	.name = "rtl88e_pci",
	.ops = &rtl8188ee_hal_ops,
	.mod_params = &rtl88ee_mod_params,

	.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
	.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
	.maps[SYS_CLK] = REG_SYS_CLKR,
	.maps[MAC_RCR_AM] = AM,
	.maps[MAC_RCR_AB] = AB,
	.maps[MAC_RCR_ACRC32] = ACRC32,
	.maps[MAC_RCR_ACF] = ACF,
	.maps[MAC_RCR_AAP] = AAP,

	.maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,

	.maps[EFUSE_TEST] = REG_EFUSE_TEST,
	.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
	.maps[EFUSE_CLK] = 0,
	.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
	.maps[EFUSE_PWC_EV12V] = PWC_EV12V,
	.maps[EFUSE_FEN_ELDR] = FEN_ELDR,
	.maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
	.maps[EFUSE_ANA8M] = ANA8M,
	.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
	.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
	.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
	.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,

	.maps[RWCAM] = REG_CAMCMD,
	.maps[WCAMI] = REG_CAMWRITE,
	.maps[RCAMO] = REG_CAMREAD,
	.maps[CAMDBG] = REG_CAMDBG,
	.maps[SECR] = REG_SECCFG,
	.maps[SEC_CAM_NONE] = CAM_NONE,
	.maps[SEC_CAM_WEP40] = CAM_WEP40,
	.maps[SEC_CAM_TKIP] = CAM_TKIP,
	.maps[SEC_CAM_AES] = CAM_AES,
	.maps[SEC_CAM_WEP104] = CAM_WEP104,

	.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
	.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
	.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
	.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
	.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
	.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
/*	.maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,     */   /*need check*/
	.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
	.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
	.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
	.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
	.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
	.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
	.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
/*	.maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
/*	.maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/

	.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
	.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
	.maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
	.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
	.maps[RTL_IMR_RDU] = IMR_RDU,
	.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
	.maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
	.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
	.maps[RTL_IMR_TBDER] = IMR_TBDER,
	.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
	.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
	.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
	.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
	.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
	.maps[RTL_IMR_VODOK] = IMR_VODOK,
	.maps[RTL_IMR_ROK] = IMR_ROK,
	.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),

	.maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
	.maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
	.maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
	.maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
	.maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
	.maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
	.maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
	.maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
	.maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
	.maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
	.maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
	.maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,

	.maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
	.maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
};

static const struct pci_device_id rtl88ee_pci_ids[] = {
	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)},
	{},
};

MODULE_DEVICE_TABLE(pci, rtl88ee_pci_ids);

MODULE_AUTHOR("zhiyuan_yang	<zhiyuan_yang@realsil.com.cn>");
MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
MODULE_AUTHOR("Larry Finger	<Larry.Finger@lwfinger.net>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Realtek 8188E 802.11n PCI wireless");
MODULE_FIRMWARE("rtlwifi/rtl8188efw.bin");

module_param_named(swenc, rtl88ee_mod_params.sw_crypto, bool, 0444);
module_param_named(debug, rtl88ee_mod_params.debug, int, 0444);
module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444);
module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444);
module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444);
module_param_named(msi, rtl88ee_mod_params.msi_support, bool, 0444);
MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 0)\n");
MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");

static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);

static struct pci_driver rtl88ee_driver = {
	.name = KBUILD_MODNAME,
	.id_table = rtl88ee_pci_ids,
	.probe = rtl_pci_probe,
	.remove = rtl_pci_disconnect,
	.driver.pm = &rtlwifi_pm_ops,
};

module_pci_driver(rtl88ee_driver);
Commit	Line	Data
f0eb856e LF	1	/******************************************************************************
	2	*
	3	* Copyright(c) 2009-2013 Realtek Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called LICENSE.
	20	*
	21	* Contact Information:
	22	* wlanfae <wlanfae@realtek.com>
	23	* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
	24	* Hsinchu 300, Taiwan.
	25	*
	26	* Larry Finger <Larry.Finger@lwfinger.net>
	27	*
	28	*****************************************************************************/
	29
2a2ac756 CCC	30	#include "../wifi.h"
	31	#include "../core.h"
	32	#include "../pci.h"
d41200ad	33	#include "../base.h"
f0eb856e LF	34	#include "reg.h"
	35	#include "def.h"
	36	#include "phy.h"
	37	#include "dm.h"
	38	#include "hw.h"
	39	#include "sw.h"
	40	#include "trx.h"
	41	#include "led.h"
	42	#include "table.h"
	43
	44	#include <linux/vmalloc.h>
	45	#include <linux/module.h>
	46
	47	static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw)
	48	{
	49	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
	50
	51	/close ASPM for AMD defaultly /
	52	rtlpci->const_amdpci_aspm = 0;
	53
	54	/* ASPM PS mode.
	55	* 0 - Disable ASPM,
	56	* 1 - Enable ASPM without Clock Req,
	57	* 2 - Enable ASPM with Clock Req,
	58	* 3 - Alwyas Enable ASPM with Clock Req,
	59	* 4 - Always Enable ASPM without Clock Req.
	60	* set defult to RTL8192CE:3 RTL8192E:2
	61	*/
	62	rtlpci->const_pci_aspm = 3;
	63
	64	/Setting for PCI-E device /
	65	rtlpci->const_devicepci_aspm_setting = 0x03;
	66
	67	/Setting for PCI-E bridge /
	68	rtlpci->const_hostpci_aspm_setting = 0x02;
	69
	70	/* In Hw/Sw Radio Off situation.
	71	* 0 - Default,
	72	* 1 - From ASPM setting without low Mac Pwr,
	73	* 2 - From ASPM setting with low Mac Pwr,
	74	* 3 - Bus D3
	75	* set default to RTL8192CE:0 RTL8192SE:2
	76	*/
	77	rtlpci->const_hwsw_rfoff_d3 = 0;
	78
	79	/* This setting works for those device with
	80	* backdoor ASPM setting such as EPHY setting.
	81	* 0 - Not support ASPM,
	82	* 1 - Support ASPM,
	83	* 2 - According to chipset.
	84	*/
	85	rtlpci->const_support_pciaspm = 1;
	86	}
	87
	88	int rtl88e_init_sw_vars(struct ieee80211_hw *hw)
	89	{
	90	int err = 0;
	91	struct rtl_priv *rtlpriv = rtl_priv(hw);
	92	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
	93	u8 tid;
	94
	95	rtl8188ee_bt_reg_init(hw);
3513d004	96	rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
f0eb856e LF	97
	98	rtlpriv->dm.dm_initialgain_enable = 1;
	99	rtlpriv->dm.dm_flag = 0;
	100	rtlpriv->dm.disable_framebursting = 0;
	101	rtlpriv->dm.thermalvalue = 0;
	102	rtlpci->transmit_config = CFENDFORM \| BIT(15);
	103
	104	/* compatible 5G band 88ce just 2.4G band & smsp */
	105	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
	106	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
	107	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
	108
	109	rtlpci->receive_config = (RCR_APPFCS \|
	110	RCR_APP_MIC \|
	111	RCR_APP_ICV \|
	112	RCR_APP_PHYST_RXFF \|
	113	RCR_HTC_LOC_CTRL \|
	114	RCR_AMF \|
	115	RCR_ACF \|
	116	RCR_ADF \|
	117	RCR_AICV \|
	118	RCR_ACRC32 \|
	119	RCR_AB \|
	120	RCR_AM \|
	121	RCR_APM \|
	122	0);
	123
	124	rtlpci->irq_mask[0] =
	125	(u32) (IMR_PSTIMEOUT \|
	126	IMR_HSISR_IND_ON_INT \|
	127	IMR_C2HCMD \|
	128	IMR_HIGHDOK \|
	129	IMR_MGNTDOK \|
	130	IMR_BKDOK \|
	131	IMR_BEDOK \|
	132	IMR_VIDOK \|
	133	IMR_VODOK \|
	134	IMR_RDU \|
	135	IMR_ROK \|
	136	0);
	137	rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW \| 0);
	138	rtlpci->sys_irq_mask = (u32) (HSIMR_PDN_INT_EN \| HSIMR_RON_INT_EN);
	139
	140	/* for debug level */
	141	rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
	142	/* for LPS & IPS */
	143	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
	144	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
	145	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
	146	if (!rtlpriv->psc.inactiveps)
	147	pr_info("rtl8188ee: Power Save off (module option)\n");
	148	if (!rtlpriv->psc.fwctrl_lps)
	149	pr_info("rtl8188ee: FW Power Save off (module option)\n");
	150	rtlpriv->psc.reg_fwctrl_lps = 3;
	151	rtlpriv->psc.reg_max_lps_awakeintvl = 5;
	152	/* for ASPM, you can close aspm through
	153	* set const_support_pciaspm = 0
	154	*/
	155	rtl88e_init_aspm_vars(hw);
	156
	157	if (rtlpriv->psc.reg_fwctrl_lps == 1)
	158	rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
	159	else if (rtlpriv->psc.reg_fwctrl_lps == 2)
	160	rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
161	else if (rtlpriv->psc.reg_fwctrl_lps == 3)
162	rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
163
164	/* for firmware buf */
165	rtlpriv->rtlhal.pfirmware = vmalloc(0x8000);
166	if (!rtlpriv->rtlhal.pfirmware) {
167	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
168	"Can't alloc buffer for fw.\n");
169	return 1;
170	}
171
172	rtlpriv->cfg->fw_name = "rtlwifi/rtl8188efw.bin";
173	rtlpriv->max_fw_size = 0x8000;
174	pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
175	err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
176	rtlpriv->io.dev, GFP_KERNEL, hw,
177	rtl_fw_cb);
178	if (err) {
179	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
180	"Failed to request firmware!\n");
181	return 1;
182	}
183
184	/* for early mode */
185	rtlpriv->rtlhal.earlymode_enable = false;
186	rtlpriv->rtlhal.max_earlymode_num = 10;
187	for (tid = 0; tid < 8; tid++)
188	skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
189
190	/low power /
191	rtlpriv->psc.low_power_enable = false;
192	if (rtlpriv->psc.low_power_enable) {
193	init_timer(&rtlpriv->works.fw_clockoff_timer);
194	setup_timer(&rtlpriv->works.fw_clockoff_timer,
195	rtl88ee_fw_clk_off_timer_callback,
196	(unsigned long)hw);
197	}
198
199	init_timer(&rtlpriv->works.fast_antenna_training_timer);
200	setup_timer(&rtlpriv->works.fast_antenna_training_timer,
201	rtl88e_dm_fast_antenna_training_callback,
202	(unsigned long)hw);
203	return err;
204	}
205
206	void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw)
207	{
208	struct rtl_priv *rtlpriv = rtl_priv(hw);
209
210	if (rtlpriv->rtlhal.pfirmware) {
211	vfree(rtlpriv->rtlhal.pfirmware);
212	rtlpriv->rtlhal.pfirmware = NULL;
213	}
214
215	if (rtlpriv->psc.low_power_enable)
216	del_timer_sync(&rtlpriv->works.fw_clockoff_timer);
217
218	del_timer_sync(&rtlpriv->works.fast_antenna_training_timer);
219	}
220
221	static struct rtl_hal_ops rtl8188ee_hal_ops = {
222	.init_sw_vars = rtl88e_init_sw_vars,
223	.deinit_sw_vars = rtl88e_deinit_sw_vars,
224	.read_eeprom_info = rtl88ee_read_eeprom_info,
225	.interrupt_recognized = rtl88ee_interrupt_recognized,/need check/
226	.hw_init = rtl88ee_hw_init,
227	.hw_disable = rtl88ee_card_disable,
228	.hw_suspend = rtl88ee_suspend,
229	.hw_resume = rtl88ee_resume,
230	.enable_interrupt = rtl88ee_enable_interrupt,
231	.disable_interrupt = rtl88ee_disable_interrupt,
232	.set_network_type = rtl88ee_set_network_type,
233	.set_chk_bssid = rtl88ee_set_check_bssid,
234	.set_qos = rtl88ee_set_qos,
235	.set_bcn_reg = rtl88ee_set_beacon_related_registers,
236	.set_bcn_intv = rtl88ee_set_beacon_interval,
237	.update_interrupt_mask = rtl88ee_update_interrupt_mask,
238	.get_hw_reg = rtl88ee_get_hw_reg,
239	.set_hw_reg = rtl88ee_set_hw_reg,
240	.update_rate_tbl = rtl88ee_update_hal_rate_tbl,
241	.fill_tx_desc = rtl88ee_tx_fill_desc,
242	.fill_tx_cmddesc = rtl88ee_tx_fill_cmddesc,
243	.query_rx_desc = rtl88ee_rx_query_desc,
244	.set_channel_access = rtl88ee_update_channel_access_setting,
245	.radio_onoff_checking = rtl88ee_gpio_radio_on_off_checking,
246	.set_bw_mode = rtl88e_phy_set_bw_mode,
247	.switch_channel = rtl88e_phy_sw_chnl,
248	.dm_watchdog = rtl88e_dm_watchdog,
d41200ad	249	.scan_operation_backup = rtl_phy_scan_operation_backup,
f0eb856e LF	250	.set_rf_power_state = rtl88e_phy_set_rf_power_state,
	251	.led_control = rtl88ee_led_control,
	252	.set_desc = rtl88ee_set_desc,
	253	.get_desc = rtl88ee_get_desc,
	254	.tx_polling = rtl88ee_tx_polling,
	255	.enable_hw_sec = rtl88ee_enable_hw_security_config,
	256	.set_key = rtl88ee_set_key,
	257	.init_sw_leds = rtl88ee_init_sw_leds,
f0eb856e LF	258	.get_bbreg = rtl88e_phy_query_bb_reg,
	259	.set_bbreg = rtl88e_phy_set_bb_reg,
	260	.get_rfreg = rtl88e_phy_query_rf_reg,
	261	.set_rfreg = rtl88e_phy_set_rf_reg,
	262	};
	263
	264	static struct rtl_mod_params rtl88ee_mod_params = {
	265	.sw_crypto = false,
	266	.inactiveps = true,
	267	.swctrl_lps = false,
	268	.fwctrl_lps = true,
3513d004	269	.msi_support = false,
f0eb856e LF	270	.debug = DBG_EMERG,
	271	};
	272
	273	static struct rtl_hal_cfg rtl88ee_hal_cfg = {
	274	.bar_id = 2,
	275	.write_readback = true,
	276	.name = "rtl88e_pci",
	277	.ops = &rtl8188ee_hal_ops,
	278	.mod_params = &rtl88ee_mod_params,
	279
	280	.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
	281	.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
	282	.maps[SYS_CLK] = REG_SYS_CLKR,
	283	.maps[MAC_RCR_AM] = AM,
	284	.maps[MAC_RCR_AB] = AB,
	285	.maps[MAC_RCR_ACRC32] = ACRC32,
	286	.maps[MAC_RCR_ACF] = ACF,
	287	.maps[MAC_RCR_AAP] = AAP,
	288
	289	.maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
	290
	291	.maps[EFUSE_TEST] = REG_EFUSE_TEST,
	292	.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
	293	.maps[EFUSE_CLK] = 0,
	294	.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
	295	.maps[EFUSE_PWC_EV12V] = PWC_EV12V,
	296	.maps[EFUSE_FEN_ELDR] = FEN_ELDR,
	297	.maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
	298	.maps[EFUSE_ANA8M] = ANA8M,
	299	.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
	300	.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
	301	.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
	302	.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
	303
	304	.maps[RWCAM] = REG_CAMCMD,
	305	.maps[WCAMI] = REG_CAMWRITE,
	306	.maps[RCAMO] = REG_CAMREAD,
	307	.maps[CAMDBG] = REG_CAMDBG,
	308	.maps[SECR] = REG_SECCFG,
	309	.maps[SEC_CAM_NONE] = CAM_NONE,
	310	.maps[SEC_CAM_WEP40] = CAM_WEP40,
	311	.maps[SEC_CAM_TKIP] = CAM_TKIP,
	312	.maps[SEC_CAM_AES] = CAM_AES,
	313	.maps[SEC_CAM_WEP104] = CAM_WEP104,
	314
	315	.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
	316	.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
	317	.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
	318	.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
	319	.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
	320	.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
	321	/* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, / /need check*/
	322	.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
	323	.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
	324	.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
	325	.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
	326	.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
	327	.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
	328	.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
	329	/* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
	330	/* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
	331
	332	.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
	333	.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
334	.maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
335	.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
336	.maps[RTL_IMR_RDU] = IMR_RDU,
337	.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
338	.maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
339	.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
340	.maps[RTL_IMR_TBDER] = IMR_TBDER,
341	.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
342	.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
343	.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
344	.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
345	.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
346	.maps[RTL_IMR_VODOK] = IMR_VODOK,
347	.maps[RTL_IMR_ROK] = IMR_ROK,
348	.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 \| IMR_TBDOK \| IMR_TBDER),
349
350	.maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
351	.maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
352	.maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
353	.maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
354	.maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
355	.maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
356	.maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
357	.maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
358	.maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
359	.maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
360	.maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
361	.maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
362
363	.maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
364	.maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
365	};
366
9baa3c34	367	static const struct pci_device_id rtl88ee_pci_ids[] = {
f0eb856e LF	368	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)},
	369	{},
	370	};
	371
	372	MODULE_DEVICE_TABLE(pci, rtl88ee_pci_ids);
	373
	374	MODULE_AUTHOR("zhiyuan_yang <zhiyuan_yang@realsil.com.cn>");
	375	MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
	376	MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
	377	MODULE_LICENSE("GPL");
	378	MODULE_DESCRIPTION("Realtek 8188E 802.11n PCI wireless");
	379	MODULE_FIRMWARE("rtlwifi/rtl8188efw.bin");
	380
	381	module_param_named(swenc, rtl88ee_mod_params.sw_crypto, bool, 0444);
	382	module_param_named(debug, rtl88ee_mod_params.debug, int, 0444);
	383	module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444);
	384	module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444);
	385	module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444);
3513d004	386	module_param_named(msi, rtl88ee_mod_params.msi_support, bool, 0444);
f0eb856e LF	387	MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
	388	MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
	389	MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
	390	MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
3513d004	391	MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 0)\n");
f0eb856e LF	392	MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
	393
	394	static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
	395
	396	static struct pci_driver rtl88ee_driver = {
	397	.name = KBUILD_MODNAME,
	398	.id_table = rtl88ee_pci_ids,
	399	.probe = rtl_pci_probe,
	400	.remove = rtl_pci_disconnect,
	401	.driver.pm = &rtlwifi_pm_ops,
	402	};
	403
	404	module_pci_driver(rtl88ee_driver);