[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / rtlwifi / rtl8192ce / phy.h

/******************************************************************************
 *
 * Copyright(c) 2009-2012  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/

#ifndef __RTL92C_PHY_H__
#define __RTL92C_PHY_H__

#define MAX_PRECMD_CNT			16
#define MAX_RFDEPENDCMD_CNT		16
#define MAX_POSTCMD_CNT			16

#define MAX_DOZE_WAITING_TIMES_9x	64

#define RT_CANNOT_IO(hw)		false
#define HIGHPOWER_RADIOA_ARRAYLEN	22

#define IQK_ADDA_REG_NUM		16
#define MAX_TOLERANCE			5
#define	IQK_DELAY_TIME			1

#define	APK_BB_REG_NUM			5
#define	APK_AFE_REG_NUM			16
#define	APK_CURVE_REG_NUM		4
#define	PATH_NUM			2

#define LOOP_LIMIT			5
#define MAX_STALL_TIME			50
#define AntennaDiversityValue		0x80
#define MAX_TXPWR_IDX_NMODE_92S		63
#define Reset_Cnt_Limit			3

#define IQK_ADDA_REG_NUM		16
#define IQK_MAC_REG_NUM			4

#define IQK_DELAY_TIME			1

#define RF90_PATH_MAX			2

#define CT_OFFSET_MAC_ADDR		0X16

#define CT_OFFSET_CCK_TX_PWR_IDX	0x5A
#define CT_OFFSET_HT401S_TX_PWR_IDX	0x60
#define CT_OFFSET_HT402S_TX_PWR_IDX_DIF	0x66
#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF	0x69
#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF	0x6C

#define CT_OFFSET_HT40_MAX_PWR_OFFSET	0x6F
#define CT_OFFSET_HT20_MAX_PWR_OFFSET	0x72

#define CT_OFFSET_CHANNEL_PLAH		0x75
#define CT_OFFSET_THERMAL_METER		0x78
#define CT_OFFSET_RF_OPTION		0x79
#define CT_OFFSET_VERSION		0x7E
#define CT_OFFSET_CUSTOMER_ID		0x7F

#define RTL92C_MAX_PATH_NUM		2

enum swchnlcmd_id {
	CMDID_END,
	CMDID_SET_TXPOWEROWER_LEVEL,
	CMDID_BBREGWRITE10,
	CMDID_WRITEPORT_ULONG,
	CMDID_WRITEPORT_USHORT,
	CMDID_WRITEPORT_UCHAR,
	CMDID_RF_WRITEREG,
};

struct swchnlcmd {
	enum swchnlcmd_id cmdid;
	u32 para1;
	u32 para2;
	u32 msdelay;
};

enum hw90_block_e {
	HW90_BLOCK_MAC = 0,
	HW90_BLOCK_PHY0 = 1,
	HW90_BLOCK_PHY1 = 2,
	HW90_BLOCK_RF = 3,
	HW90_BLOCK_MAXIMUM = 4,
};

enum baseband_config_type {
	BASEBAND_CONFIG_PHY_REG = 0,
	BASEBAND_CONFIG_AGC_TAB = 1,
};

enum ra_offset_area {
	RA_OFFSET_LEGACY_OFDM1,
	RA_OFFSET_LEGACY_OFDM2,
	RA_OFFSET_HT_OFDM1,
	RA_OFFSET_HT_OFDM2,
	RA_OFFSET_HT_OFDM3,
	RA_OFFSET_HT_OFDM4,
	RA_OFFSET_HT_CCK,
};

enum antenna_path {
	ANTENNA_NONE,
	ANTENNA_D,
	ANTENNA_C,
	ANTENNA_CD,
	ANTENNA_B,
	ANTENNA_BD,
	ANTENNA_BC,
	ANTENNA_BCD,
	ANTENNA_A,
	ANTENNA_AD,
	ANTENNA_AC,
	ANTENNA_ACD,
	ANTENNA_AB,
	ANTENNA_ABD,
	ANTENNA_ABC,
	ANTENNA_ABCD
};

struct r_antenna_select_ofdm {
	u32 r_tx_antenna:4;
	u32 r_ant_l:4;
	u32 r_ant_non_ht:4;
	u32 r_ant_ht1:4;
	u32 r_ant_ht2:4;
	u32 r_ant_ht_s1:4;
	u32 r_ant_non_ht_s1:4;
	u32 ofdm_txsc:2;
	u32 reserved:2;
};

struct r_antenna_select_cck {
	u8 r_cckrx_enable_2:2;
	u8 r_cckrx_enable:2;
	u8 r_ccktx_enable:4;
};

struct efuse_contents {
	u8 mac_addr[ETH_ALEN];
	u8 cck_tx_power_idx[6];
	u8 ht40_1s_tx_power_idx[6];
	u8 ht40_2s_tx_power_idx_diff[3];
	u8 ht20_tx_power_idx_diff[3];
	u8 ofdm_tx_power_idx_diff[3];
	u8 ht40_max_power_offset[3];
	u8 ht20_max_power_offset[3];
	u8 channel_plan;
	u8 thermal_meter;
	u8 rf_option[5];
	u8 version;
	u8 oem_id;
	u8 regulatory;
};

struct tx_power_struct {
	u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
	u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
	u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
	u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
	u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
	u8 legacy_ht_txpowerdiff;
	u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
	u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
	u8 pwrgroup_cnt;
	u32 mcs_original_offset[4][16];
};

bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw,
				   u32 regaddr, u32 bitmask);
void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
				  u32 regaddr, u32 bitmask, u32 data);
u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
				   enum radio_path rfpath, u32 regaddr,
				   u32 bitmask);
extern void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
				   enum radio_path rfpath, u32 regaddr,
				   u32 bitmask, u32 data);
bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
bool rtl92ce_phy_bb_config(struct ieee80211_hw *hw);
bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
						 enum radio_path rfpath);
void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw,
					 long *powerlevel);
void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
					  long power_indbm);
void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw,
					     u8 operation);
void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
				   enum nl80211_channel_type ch_type);
void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw,
					 u16 beaconinterval);
void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t);
void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
					  enum radio_path rfpath);
bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
					      u32 rfpath);
bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
					  enum rf_pwrstate rfpwr_state);
void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
void rtl92c_phy_set_io(struct ieee80211_hw *hw);
void rtl92c_bb_block_on(struct ieee80211_hw *hw);
u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
				      enum radio_path rfpath, u32 offset);
u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
					 enum radio_path rfpath, u32 offset);
u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
					enum radio_path rfpath, u32 offset,
					u32 data);
void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
					   enum radio_path rfpath, u32 offset,
					   u32 data);
void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
						   u32 regaddr, u32 bitmask,
						   u32 data);
bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw);
bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
				   enum rf_pwrstate rfpwr_state);
bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
					    u8 configtype);
bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
					      u8 configtype);
void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw);

#endif
Commit	Line	Data
0c817338 LF	1	/******************************************************************************
0c817338 LF	2	*
9003a4ab	3	* Copyright(c) 2009-2012 Realtek Corporation.
0c817338 LF	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called LICENSE.
	20	*
	21	* Contact Information:
	22	* wlanfae <wlanfae@realtek.com>
	23	* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
	24	* Hsinchu 300, Taiwan.
	25	*
	26	* Larry Finger <Larry.Finger@lwfinger.net>
	27	*
	28	*****************************************************************************/
	29
	30	#ifndef __RTL92C_PHY_H__
	31	#define __RTL92C_PHY_H__
	32
	33	#define MAX_PRECMD_CNT 16
	34	#define MAX_RFDEPENDCMD_CNT 16
	35	#define MAX_POSTCMD_CNT 16
	36
	37	#define MAX_DOZE_WAITING_TIMES_9x 64
	38
	39	#define RT_CANNOT_IO(hw) false
	40	#define HIGHPOWER_RADIOA_ARRAYLEN 22
	41
e0b5a507	42	#define IQK_ADDA_REG_NUM 16
0c817338 LF	43	#define MAX_TOLERANCE 5
	44	#define IQK_DELAY_TIME 1
	45
	46	#define APK_BB_REG_NUM 5
	47	#define APK_AFE_REG_NUM 16
	48	#define APK_CURVE_REG_NUM 4
	49	#define PATH_NUM 2
	50
	51	#define LOOP_LIMIT 5
	52	#define MAX_STALL_TIME 50
	53	#define AntennaDiversityValue 0x80
	54	#define MAX_TXPWR_IDX_NMODE_92S 63
	55	#define Reset_Cnt_Limit 3
	56
	57	#define IQK_ADDA_REG_NUM 16
	58	#define IQK_MAC_REG_NUM 4
	59
e0b5a507 C	60	#define IQK_DELAY_TIME 1
e0b5a507 C	61
0c817338	62	#define RF90_PATH_MAX 2
0c817338 LF	63
	64	#define CT_OFFSET_MAC_ADDR 0X16
	65
	66	#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
	67	#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
	68	#define CT_OFFSET_HT402S_TX_PWR_IDX_DIF 0x66
	69	#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
	70	#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
	71
	72	#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
	73	#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
	74
	75	#define CT_OFFSET_CHANNEL_PLAH 0x75
	76	#define CT_OFFSET_THERMAL_METER 0x78
	77	#define CT_OFFSET_RF_OPTION 0x79
	78	#define CT_OFFSET_VERSION 0x7E
	79	#define CT_OFFSET_CUSTOMER_ID 0x7F
	80
	81	#define RTL92C_MAX_PATH_NUM 2
e0b5a507	82
0c817338 LF	83	enum swchnlcmd_id {
	84	CMDID_END,
	85	CMDID_SET_TXPOWEROWER_LEVEL,
	86	CMDID_BBREGWRITE10,
	87	CMDID_WRITEPORT_ULONG,
	88	CMDID_WRITEPORT_USHORT,
	89	CMDID_WRITEPORT_UCHAR,
	90	CMDID_RF_WRITEREG,
	91	};
	92
	93	struct swchnlcmd {
	94	enum swchnlcmd_id cmdid;
	95	u32 para1;
	96	u32 para2;
	97	u32 msdelay;
	98	};
	99
	100	enum hw90_block_e {
	101	HW90_BLOCK_MAC = 0,
	102	HW90_BLOCK_PHY0 = 1,
	103	HW90_BLOCK_PHY1 = 2,
	104	HW90_BLOCK_RF = 3,
	105	HW90_BLOCK_MAXIMUM = 4,
	106	};
	107
	108	enum baseband_config_type {
	109	BASEBAND_CONFIG_PHY_REG = 0,
	110	BASEBAND_CONFIG_AGC_TAB = 1,
	111	};
	112
	113	enum ra_offset_area {
	114	RA_OFFSET_LEGACY_OFDM1,
	115	RA_OFFSET_LEGACY_OFDM2,
	116	RA_OFFSET_HT_OFDM1,
	117	RA_OFFSET_HT_OFDM2,
	118	RA_OFFSET_HT_OFDM3,
	119	RA_OFFSET_HT_OFDM4,
	120	RA_OFFSET_HT_CCK,
	121	};
	122
	123	enum antenna_path {
	124	ANTENNA_NONE,
	125	ANTENNA_D,
	126	ANTENNA_C,
	127	ANTENNA_CD,
	128	ANTENNA_B,
	129	ANTENNA_BD,
	130	ANTENNA_BC,
	131	ANTENNA_BCD,
	132	ANTENNA_A,
	133	ANTENNA_AD,
	134	ANTENNA_AC,
	135	ANTENNA_ACD,
	136	ANTENNA_AB,
	137	ANTENNA_ABD,
	138	ANTENNA_ABC,
	139	ANTENNA_ABCD
	140	};
	141
	142	struct r_antenna_select_ofdm {
	143	u32 r_tx_antenna:4;
	144	u32 r_ant_l:4;
	145	u32 r_ant_non_ht:4;
	146	u32 r_ant_ht1:4;
147	u32 r_ant_ht2:4;
148	u32 r_ant_ht_s1:4;
149	u32 r_ant_non_ht_s1:4;
150	u32 ofdm_txsc:2;
151	u32 reserved:2;
152	};
153
154	struct r_antenna_select_cck {
155	u8 r_cckrx_enable_2:2;
156	u8 r_cckrx_enable:2;
157	u8 r_ccktx_enable:4;
158	};
159
160	struct efuse_contents {
161	u8 mac_addr[ETH_ALEN];
162	u8 cck_tx_power_idx[6];
163	u8 ht40_1s_tx_power_idx[6];
164	u8 ht40_2s_tx_power_idx_diff[3];
165	u8 ht20_tx_power_idx_diff[3];
166	u8 ofdm_tx_power_idx_diff[3];
167	u8 ht40_max_power_offset[3];
168	u8 ht20_max_power_offset[3];
169	u8 channel_plan;
170	u8 thermal_meter;
171	u8 rf_option[5];
172	u8 version;
173	u8 oem_id;
174	u8 regulatory;
175	};
176
177	struct tx_power_struct {
178	u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
179	u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
180	u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
181	u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
182	u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
183	u8 legacy_ht_txpowerdiff;
184	u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
185	u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
186	u8 pwrgroup_cnt;
187	u32 mcs_original_offset[4][16];
188	};
189
e0b5a507 C	190	bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
e0b5a507 C	191	u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw,
0c817338	192	u32 regaddr, u32 bitmask);
e0b5a507	193	void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
0c817338	194	u32 regaddr, u32 bitmask, u32 data);
e0b5a507	195	u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
0c817338 LF	196	enum radio_path rfpath, u32 regaddr,
0c817338 LF	197	u32 bitmask);
1472d3a8	198	extern void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
e0b5a507 C	199	enum radio_path rfpath, u32 regaddr,
	200	u32 bitmask, u32 data);
	201	bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
1472d3a8	202	bool rtl92ce_phy_bb_config(struct ieee80211_hw *hw);
e0b5a507 C	203	bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
e0b5a507 C	204	bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
0c817338	205	enum radio_path rfpath);
e0b5a507 C	206	void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
e0b5a507 C	207	void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw,
0c817338	208	long *powerlevel);
e0b5a507 C	209	void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
e0b5a507 C	210	bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
0c817338	211	long power_indbm);
e0b5a507	212	void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw,
0c817338	213	u8 operation);
e0b5a507	214	void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
0c817338	215	enum nl80211_channel_type ch_type);
e0b5a507 C	216	void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
	217	u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
	218	void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
	219	void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw,
0c817338 LF	220	u16 beaconinterval);
	221	void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
	222	void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
e0b5a507	223	void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t);
0c817338 LF	224	void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
	225	bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
	226	enum radio_path rfpath);
e0b5a507	227	bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
0c817338 LF	228	u32 rfpath);
0c817338 LF	229	bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
1472d3a8	230	bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
0c817338	231	enum rf_pwrstate rfpwr_state);
0c817338 LF	232	void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
	233	bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
	234	void rtl92c_phy_set_io(struct ieee80211_hw *hw);
7ea47240	235	void rtl92c_bb_block_on(struct ieee80211_hw *hw);
1472d3a8 LF	236	u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
	237	enum radio_path rfpath, u32 offset);
	238	u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
	239	enum radio_path rfpath, u32 offset);
	240	u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
	241	void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
	242	enum radio_path rfpath, u32 offset,
	243	u32 data);
1472d3a8 LF	244	void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
	245	enum radio_path rfpath, u32 offset,
	246	u32 data);
	247	void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
	248	u32 regaddr, u32 bitmask,
	249	u32 data);
	250	bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
	251	void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
	252	bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
	253	void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw);
e0b5a507 C	254	bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
e0b5a507 C	255	enum rf_pwrstate rfpwr_state);
d3bb1429 LF	256	bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
	257	u8 configtype);
	258	bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
	259	u8 configtype);
099fb8ab	260	void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
0c817338 LF	261
0c817338 LF	262	#endif