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3affdf42 CL |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2009-2010 Realtek Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * wlanfae <wlanfae@realtek.com> | |
23 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | |
24 | * Hsinchu 300, Taiwan. | |
25 | * | |
26 | * Larry Finger <Larry.Finger@lwfinger.net> | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #include "../wifi.h" | |
31 | #include "../efuse.h" | |
32 | #include "../base.h" | |
33 | #include "../regd.h" | |
34 | #include "../cam.h" | |
35 | #include "../ps.h" | |
36 | #include "../pci.h" | |
37 | #include "reg.h" | |
38 | #include "def.h" | |
39 | #include "phy.h" | |
40 | #include "dm.h" | |
41 | #include "fw.h" | |
42 | #include "led.h" | |
43 | #include "sw.h" | |
44 | #include "hw.h" | |
45 | ||
46 | u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct) | |
47 | { | |
48 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
49 | u32 value; | |
50 | ||
51 | rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC)); | |
52 | rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct); | |
53 | udelay(10); | |
54 | value = rtl_read_dword(rtlpriv, REG_DBI_RDATA); | |
55 | return value; | |
56 | } | |
57 | ||
58 | void rtl92de_write_dword_dbi(struct ieee80211_hw *hw, | |
59 | u16 offset, u32 value, u8 direct) | |
60 | { | |
61 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
62 | ||
63 | rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000)); | |
64 | rtl_write_dword(rtlpriv, REG_DBI_WDATA, value); | |
65 | rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct); | |
66 | } | |
67 | ||
68 | static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw, | |
69 | u8 set_bits, u8 clear_bits) | |
70 | { | |
71 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
72 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
73 | ||
74 | rtlpci->reg_bcn_ctrl_val |= set_bits; | |
75 | rtlpci->reg_bcn_ctrl_val &= ~clear_bits; | |
76 | rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); | |
77 | } | |
78 | ||
79 | static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw) | |
80 | { | |
81 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
82 | u8 tmp1byte; | |
83 | ||
84 | tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); | |
85 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); | |
86 | rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); | |
87 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); | |
88 | tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); | |
89 | tmp1byte &= ~(BIT(0)); | |
90 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); | |
91 | } | |
92 | ||
93 | static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw) | |
94 | { | |
95 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
96 | u8 tmp1byte; | |
97 | ||
98 | tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); | |
99 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); | |
100 | rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); | |
101 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); | |
102 | tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); | |
103 | tmp1byte |= BIT(0); | |
104 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); | |
105 | } | |
106 | ||
107 | static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw) | |
108 | { | |
109 | _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1)); | |
110 | } | |
111 | ||
112 | static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw) | |
113 | { | |
114 | _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0); | |
115 | } | |
116 | ||
117 | void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) | |
118 | { | |
119 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
120 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
121 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
122 | ||
123 | switch (variable) { | |
124 | case HW_VAR_RCR: | |
125 | *((u32 *) (val)) = rtlpci->receive_config; | |
126 | break; | |
127 | case HW_VAR_RF_STATE: | |
128 | *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; | |
129 | break; | |
130 | case HW_VAR_FWLPS_RF_ON:{ | |
131 | enum rf_pwrstate rfState; | |
132 | u32 val_rcr; | |
133 | ||
134 | rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, | |
135 | (u8 *) (&rfState)); | |
136 | if (rfState == ERFOFF) { | |
137 | *((bool *) (val)) = true; | |
138 | } else { | |
139 | val_rcr = rtl_read_dword(rtlpriv, REG_RCR); | |
140 | val_rcr &= 0x00070000; | |
141 | if (val_rcr) | |
142 | *((bool *) (val)) = false; | |
143 | else | |
144 | *((bool *) (val)) = true; | |
145 | } | |
146 | break; | |
147 | } | |
148 | case HW_VAR_FW_PSMODE_STATUS: | |
149 | *((bool *) (val)) = ppsc->fw_current_inpsmode; | |
150 | break; | |
151 | case HW_VAR_CORRECT_TSF:{ | |
152 | u64 tsf; | |
153 | u32 *ptsf_low = (u32 *)&tsf; | |
154 | u32 *ptsf_high = ((u32 *)&tsf) + 1; | |
155 | ||
156 | *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); | |
157 | *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); | |
158 | *((u64 *) (val)) = tsf; | |
159 | break; | |
160 | } | |
161 | case HW_VAR_INT_MIGRATION: | |
162 | *((bool *)(val)) = rtlpriv->dm.interrupt_migration; | |
163 | break; | |
164 | case HW_VAR_INT_AC: | |
165 | *((bool *)(val)) = rtlpriv->dm.disable_tx_int; | |
166 | break; | |
167 | default: | |
168 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
169 | ("switch case not process\n")); | |
170 | break; | |
171 | } | |
172 | } | |
173 | ||
174 | void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) | |
175 | { | |
176 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
177 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
178 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
179 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
180 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
181 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
182 | u8 idx; | |
183 | ||
184 | switch (variable) { | |
185 | case HW_VAR_ETHER_ADDR: | |
186 | for (idx = 0; idx < ETH_ALEN; idx++) { | |
187 | rtl_write_byte(rtlpriv, (REG_MACID + idx), | |
188 | val[idx]); | |
189 | } | |
190 | break; | |
191 | case HW_VAR_BASIC_RATE: { | |
192 | u16 rate_cfg = ((u16 *) val)[0]; | |
193 | u8 rate_index = 0; | |
194 | ||
195 | rate_cfg = rate_cfg & 0x15f; | |
196 | if (mac->vendor == PEER_CISCO && | |
197 | ((rate_cfg & 0x150) == 0)) | |
198 | rate_cfg |= 0x01; | |
199 | rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); | |
200 | rtl_write_byte(rtlpriv, REG_RRSR + 1, | |
201 | (rate_cfg >> 8) & 0xff); | |
202 | while (rate_cfg > 0x1) { | |
203 | rate_cfg = (rate_cfg >> 1); | |
204 | rate_index++; | |
205 | } | |
206 | if (rtlhal->fw_version > 0xe) | |
207 | rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, | |
208 | rate_index); | |
209 | break; | |
210 | } | |
211 | case HW_VAR_BSSID: | |
212 | for (idx = 0; idx < ETH_ALEN; idx++) { | |
213 | rtl_write_byte(rtlpriv, (REG_BSSID + idx), | |
214 | val[idx]); | |
215 | } | |
216 | break; | |
217 | case HW_VAR_SIFS: | |
218 | rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); | |
219 | rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); | |
220 | rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); | |
221 | rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); | |
222 | if (!mac->ht_enable) | |
223 | rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, | |
224 | 0x0e0e); | |
225 | else | |
226 | rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, | |
227 | *((u16 *) val)); | |
228 | break; | |
229 | case HW_VAR_SLOT_TIME: { | |
230 | u8 e_aci; | |
231 | ||
232 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
233 | ("HW_VAR_SLOT_TIME %x\n", val[0])); | |
234 | rtl_write_byte(rtlpriv, REG_SLOT, val[0]); | |
235 | for (e_aci = 0; e_aci < AC_MAX; e_aci++) | |
236 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
237 | HW_VAR_AC_PARAM, | |
238 | (u8 *) (&e_aci)); | |
239 | break; | |
240 | } | |
241 | case HW_VAR_ACK_PREAMBLE: { | |
242 | u8 reg_tmp; | |
243 | u8 short_preamble = (bool) (*(u8 *) val); | |
244 | ||
245 | reg_tmp = (mac->cur_40_prime_sc) << 5; | |
246 | if (short_preamble) | |
247 | reg_tmp |= 0x80; | |
248 | rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); | |
249 | break; | |
250 | } | |
251 | case HW_VAR_AMPDU_MIN_SPACE: { | |
252 | u8 min_spacing_to_set; | |
253 | u8 sec_min_space; | |
254 | ||
255 | min_spacing_to_set = *((u8 *) val); | |
256 | if (min_spacing_to_set <= 7) { | |
257 | sec_min_space = 0; | |
258 | if (min_spacing_to_set < sec_min_space) | |
259 | min_spacing_to_set = sec_min_space; | |
260 | mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) | | |
261 | min_spacing_to_set); | |
262 | *val = min_spacing_to_set; | |
263 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
264 | ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", | |
265 | mac->min_space_cfg)); | |
266 | rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, | |
267 | mac->min_space_cfg); | |
268 | } | |
269 | break; | |
270 | } | |
271 | case HW_VAR_SHORTGI_DENSITY: { | |
272 | u8 density_to_set; | |
273 | ||
274 | density_to_set = *((u8 *) val); | |
275 | mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; | |
276 | mac->min_space_cfg |= (density_to_set << 3); | |
277 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
278 | ("Set HW_VAR_SHORTGI_DENSITY: %#x\n", | |
279 | mac->min_space_cfg)); | |
280 | rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, | |
281 | mac->min_space_cfg); | |
282 | break; | |
283 | } | |
284 | case HW_VAR_AMPDU_FACTOR: { | |
285 | u8 factor_toset; | |
286 | u32 regtoSet; | |
287 | u8 *ptmp_byte = NULL; | |
288 | u8 index; | |
289 | ||
290 | if (rtlhal->macphymode == DUALMAC_DUALPHY) | |
291 | regtoSet = 0xb9726641; | |
292 | else if (rtlhal->macphymode == DUALMAC_SINGLEPHY) | |
293 | regtoSet = 0x66626641; | |
294 | else | |
295 | regtoSet = 0xb972a841; | |
296 | factor_toset = *((u8 *) val); | |
297 | if (factor_toset <= 3) { | |
298 | factor_toset = (1 << (factor_toset + 2)); | |
299 | if (factor_toset > 0xf) | |
300 | factor_toset = 0xf; | |
301 | for (index = 0; index < 4; index++) { | |
302 | ptmp_byte = (u8 *) (®toSet) + index; | |
303 | if ((*ptmp_byte & 0xf0) > | |
304 | (factor_toset << 4)) | |
305 | *ptmp_byte = (*ptmp_byte & 0x0f) | |
306 | | (factor_toset << 4); | |
307 | if ((*ptmp_byte & 0x0f) > factor_toset) | |
308 | *ptmp_byte = (*ptmp_byte & 0xf0) | |
309 | | (factor_toset); | |
310 | } | |
311 | rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoSet); | |
312 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
313 | ("Set HW_VAR_AMPDU_FACTOR: %#x\n", | |
314 | factor_toset)); | |
315 | } | |
316 | break; | |
317 | } | |
318 | case HW_VAR_AC_PARAM: { | |
319 | u8 e_aci = *((u8 *) val); | |
320 | rtl92d_dm_init_edca_turbo(hw); | |
321 | if (rtlpci->acm_method != eAcmWay2_SW) | |
322 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, | |
323 | (u8 *) (&e_aci)); | |
324 | break; | |
325 | } | |
326 | case HW_VAR_ACM_CTRL: { | |
327 | u8 e_aci = *((u8 *) val); | |
328 | union aci_aifsn *p_aci_aifsn = | |
329 | (union aci_aifsn *)(&(mac->ac[0].aifs)); | |
330 | u8 acm = p_aci_aifsn->f.acm; | |
331 | u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); | |
332 | ||
333 | acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); | |
334 | if (acm) { | |
335 | switch (e_aci) { | |
336 | case AC0_BE: | |
337 | acm_ctrl |= ACMHW_BEQEN; | |
338 | break; | |
339 | case AC2_VI: | |
340 | acm_ctrl |= ACMHW_VIQEN; | |
341 | break; | |
342 | case AC3_VO: | |
343 | acm_ctrl |= ACMHW_VOQEN; | |
344 | break; | |
345 | default: | |
346 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
347 | ("HW_VAR_ACM_CTRL acm set " | |
348 | "failed: eACI is %d\n", acm)); | |
349 | break; | |
350 | } | |
351 | } else { | |
352 | switch (e_aci) { | |
353 | case AC0_BE: | |
354 | acm_ctrl &= (~ACMHW_BEQEN); | |
355 | break; | |
356 | case AC2_VI: | |
357 | acm_ctrl &= (~ACMHW_VIQEN); | |
358 | break; | |
359 | case AC3_VO: | |
360 | acm_ctrl &= (~ACMHW_VOQEN); | |
361 | break; | |
362 | default: | |
363 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
364 | ("switch case not process\n")); | |
365 | break; | |
366 | } | |
367 | } | |
368 | RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, | |
369 | ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] " | |
370 | "Write 0x%X\n", acm_ctrl)); | |
371 | rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); | |
372 | break; | |
373 | } | |
374 | case HW_VAR_RCR: | |
375 | rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); | |
376 | rtlpci->receive_config = ((u32 *) (val))[0]; | |
377 | break; | |
378 | case HW_VAR_RETRY_LIMIT: { | |
379 | u8 retry_limit = ((u8 *) (val))[0]; | |
380 | ||
381 | rtl_write_word(rtlpriv, REG_RL, | |
382 | retry_limit << RETRY_LIMIT_SHORT_SHIFT | | |
383 | retry_limit << RETRY_LIMIT_LONG_SHIFT); | |
384 | break; | |
385 | } | |
386 | case HW_VAR_DUAL_TSF_RST: | |
387 | rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); | |
388 | break; | |
389 | case HW_VAR_EFUSE_BYTES: | |
390 | rtlefuse->efuse_usedbytes = *((u16 *) val); | |
391 | break; | |
392 | case HW_VAR_EFUSE_USAGE: | |
393 | rtlefuse->efuse_usedpercentage = *((u8 *) val); | |
394 | break; | |
395 | case HW_VAR_IO_CMD: | |
396 | rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val)); | |
397 | break; | |
398 | case HW_VAR_WPA_CONFIG: | |
399 | rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val)); | |
400 | break; | |
401 | case HW_VAR_SET_RPWM: | |
402 | rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (u8 *) (val)); | |
403 | break; | |
404 | case HW_VAR_H2C_FW_PWRMODE: | |
405 | break; | |
406 | case HW_VAR_FW_PSMODE_STATUS: | |
407 | ppsc->fw_current_inpsmode = *((bool *) val); | |
408 | break; | |
409 | case HW_VAR_H2C_FW_JOINBSSRPT: { | |
410 | u8 mstatus = (*(u8 *) val); | |
411 | u8 tmp_regcr, tmp_reg422; | |
412 | bool recover = false; | |
413 | ||
414 | if (mstatus == RT_MEDIA_CONNECT) { | |
415 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
416 | HW_VAR_AID, NULL); | |
417 | tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); | |
418 | rtl_write_byte(rtlpriv, REG_CR + 1, | |
419 | (tmp_regcr | BIT(0))); | |
420 | _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); | |
421 | _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0); | |
422 | tmp_reg422 = rtl_read_byte(rtlpriv, | |
423 | REG_FWHW_TXQ_CTRL + 2); | |
424 | if (tmp_reg422 & BIT(6)) | |
425 | recover = true; | |
426 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, | |
427 | tmp_reg422 & (~BIT(6))); | |
428 | rtl92d_set_fw_rsvdpagepkt(hw, 0); | |
429 | _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); | |
430 | _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4)); | |
431 | if (recover) | |
432 | rtl_write_byte(rtlpriv, | |
433 | REG_FWHW_TXQ_CTRL + 2, | |
434 | tmp_reg422); | |
435 | rtl_write_byte(rtlpriv, REG_CR + 1, | |
436 | (tmp_regcr & ~(BIT(0)))); | |
437 | } | |
438 | rtl92d_set_fw_joinbss_report_cmd(hw, (*(u8 *) val)); | |
439 | break; | |
440 | } | |
441 | case HW_VAR_AID: { | |
442 | u16 u2btmp; | |
443 | u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); | |
444 | u2btmp &= 0xC000; | |
445 | rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | | |
446 | mac->assoc_id)); | |
447 | break; | |
448 | } | |
449 | case HW_VAR_CORRECT_TSF: { | |
450 | u8 btype_ibss = ((u8 *) (val))[0]; | |
451 | ||
9928c7d1 | 452 | if (btype_ibss) |
3affdf42 CL |
453 | _rtl92de_stop_tx_beacon(hw); |
454 | _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); | |
455 | rtl_write_dword(rtlpriv, REG_TSFTR, | |
456 | (u32) (mac->tsf & 0xffffffff)); | |
457 | rtl_write_dword(rtlpriv, REG_TSFTR + 4, | |
458 | (u32) ((mac->tsf >> 32) & 0xffffffff)); | |
459 | _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); | |
9928c7d1 | 460 | if (btype_ibss) |
3affdf42 CL |
461 | _rtl92de_resume_tx_beacon(hw); |
462 | ||
463 | break; | |
464 | } | |
465 | case HW_VAR_INT_MIGRATION: { | |
466 | bool int_migration = *(bool *) (val); | |
467 | ||
468 | if (int_migration) { | |
42b2aa86 JM |
469 | /* Set interrupt migration timer and |
470 | * corresponding Tx/Rx counter. | |
3affdf42 CL |
471 | * timer 25ns*0xfa0=100us for 0xf packets. |
472 | * 0x306:Rx, 0x307:Tx */ | |
473 | rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0); | |
474 | rtlpriv->dm.interrupt_migration = int_migration; | |
475 | } else { | |
476 | /* Reset all interrupt migration settings. */ | |
477 | rtl_write_dword(rtlpriv, REG_INT_MIG, 0); | |
478 | rtlpriv->dm.interrupt_migration = int_migration; | |
479 | } | |
480 | break; | |
481 | } | |
482 | case HW_VAR_INT_AC: { | |
483 | bool disable_ac_int = *((bool *) val); | |
484 | ||
485 | /* Disable four ACs interrupts. */ | |
486 | if (disable_ac_int) { | |
487 | /* Disable VO, VI, BE and BK four AC interrupts | |
488 | * to gain more efficient CPU utilization. | |
489 | * When extremely highly Rx OK occurs, | |
490 | * we will disable Tx interrupts. | |
491 | */ | |
492 | rtlpriv->cfg->ops->update_interrupt_mask(hw, 0, | |
493 | RT_AC_INT_MASKS); | |
494 | rtlpriv->dm.disable_tx_int = disable_ac_int; | |
495 | /* Enable four ACs interrupts. */ | |
496 | } else { | |
497 | rtlpriv->cfg->ops->update_interrupt_mask(hw, | |
498 | RT_AC_INT_MASKS, 0); | |
499 | rtlpriv->dm.disable_tx_int = disable_ac_int; | |
500 | } | |
501 | break; | |
502 | } | |
503 | default: | |
504 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
505 | ("switch case not process\n")); | |
506 | break; | |
507 | } | |
508 | } | |
509 | ||
510 | static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) | |
511 | { | |
512 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
513 | bool status = true; | |
514 | long count = 0; | |
515 | u32 value = _LLT_INIT_ADDR(address) | | |
516 | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); | |
517 | ||
518 | rtl_write_dword(rtlpriv, REG_LLT_INIT, value); | |
519 | do { | |
520 | value = rtl_read_dword(rtlpriv, REG_LLT_INIT); | |
521 | if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) | |
522 | break; | |
523 | if (count > POLLING_LLT_THRESHOLD) { | |
524 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
525 | ("Failed to polling write LLT done at " | |
526 | "address %d!\n", address)); | |
527 | status = false; | |
528 | break; | |
529 | } | |
530 | } while (++count); | |
531 | return status; | |
532 | } | |
533 | ||
534 | static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw) | |
535 | { | |
536 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
537 | unsigned short i; | |
538 | u8 txpktbuf_bndy; | |
539 | u8 maxPage; | |
540 | bool status; | |
541 | u32 value32; /* High+low page number */ | |
542 | u8 value8; /* normal page number */ | |
543 | ||
544 | if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { | |
545 | maxPage = 255; | |
546 | txpktbuf_bndy = 246; | |
547 | value8 = 0; | |
548 | value32 = 0x80bf0d29; | |
549 | } else if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { | |
550 | maxPage = 127; | |
551 | txpktbuf_bndy = 123; | |
552 | value8 = 0; | |
553 | value32 = 0x80750005; | |
554 | } | |
555 | ||
556 | /* Set reserved page for each queue */ | |
557 | /* 11. RQPN 0x200[31:0] = 0x80BD1C1C */ | |
558 | /* load RQPN */ | |
559 | rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); | |
560 | rtl_write_dword(rtlpriv, REG_RQPN, value32); | |
561 | ||
562 | /* 12. TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */ | |
563 | /* TXRKTBUG_PG_BNDY */ | |
564 | rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, | |
565 | (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 | | |
566 | txpktbuf_bndy)); | |
567 | ||
568 | /* 13. TDECTRL[15:8] 0x209[7:0] = 0xF6 */ | |
569 | /* Beacon Head for TXDMA */ | |
570 | rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); | |
571 | ||
572 | /* 14. BCNQ_PGBNDY 0x424[7:0] = 0xF6 */ | |
573 | /* BCNQ_PGBNDY */ | |
574 | rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); | |
575 | rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); | |
576 | ||
577 | /* 15. WMAC_LBK_BF_HD 0x45D[7:0] = 0xF6 */ | |
578 | /* WMAC_LBK_BF_HD */ | |
579 | rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); | |
580 | ||
581 | /* Set Tx/Rx page size (Tx must be 128 Bytes, */ | |
582 | /* Rx can be 64,128,256,512,1024 bytes) */ | |
583 | /* 16. PBP [7:0] = 0x11 */ | |
584 | /* TRX page size */ | |
585 | rtl_write_byte(rtlpriv, REG_PBP, 0x11); | |
586 | ||
587 | /* 17. DRV_INFO_SZ = 0x04 */ | |
588 | rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); | |
589 | ||
590 | /* 18. LLT_table_init(Adapter); */ | |
591 | for (i = 0; i < (txpktbuf_bndy - 1); i++) { | |
592 | status = _rtl92de_llt_write(hw, i, i + 1); | |
593 | if (true != status) | |
594 | return status; | |
595 | } | |
596 | ||
597 | /* end of list */ | |
598 | status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); | |
599 | if (true != status) | |
600 | return status; | |
601 | ||
602 | /* Make the other pages as ring buffer */ | |
603 | /* This ring buffer is used as beacon buffer if we */ | |
604 | /* config this MAC as two MAC transfer. */ | |
605 | /* Otherwise used as local loopback buffer. */ | |
606 | for (i = txpktbuf_bndy; i < maxPage; i++) { | |
607 | status = _rtl92de_llt_write(hw, i, (i + 1)); | |
608 | if (true != status) | |
609 | return status; | |
610 | } | |
611 | ||
612 | /* Let last entry point to the start entry of ring buffer */ | |
613 | status = _rtl92de_llt_write(hw, maxPage, txpktbuf_bndy); | |
614 | if (true != status) | |
615 | return status; | |
616 | ||
617 | return true; | |
618 | } | |
619 | ||
620 | static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw) | |
621 | { | |
622 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
623 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
624 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
625 | struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); | |
626 | ||
627 | if (rtlpci->up_first_time) | |
628 | return; | |
629 | if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) | |
ab049fbf | 630 | rtl92de_sw_led_on(hw, pLed0); |
3affdf42 | 631 | else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) |
ab049fbf | 632 | rtl92de_sw_led_on(hw, pLed0); |
3affdf42 | 633 | else |
ab049fbf | 634 | rtl92de_sw_led_off(hw, pLed0); |
3affdf42 CL |
635 | } |
636 | ||
637 | static bool _rtl92de_init_mac(struct ieee80211_hw *hw) | |
638 | { | |
639 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
640 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
641 | unsigned char bytetmp; | |
642 | unsigned short wordtmp; | |
643 | u16 retry; | |
644 | ||
645 | rtl92d_phy_set_poweron(hw); | |
646 | /* Add for resume sequence of power domain according | |
647 | * to power document V11. Chapter V.11.... */ | |
648 | /* 0. RSV_CTRL 0x1C[7:0] = 0x00 */ | |
649 | /* unlock ISO/CLK/Power control register */ | |
650 | rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); | |
651 | rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05); | |
652 | ||
653 | /* 1. AFE_XTAL_CTRL [7:0] = 0x0F enable XTAL */ | |
654 | /* 2. SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */ | |
655 | /* 3. delay (1ms) this is not necessary when initially power on */ | |
656 | ||
657 | /* C. Resume Sequence */ | |
658 | /* a. SPS0_CTRL 0x11[7:0] = 0x2b */ | |
659 | rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); | |
660 | ||
661 | /* b. AFE_XTAL_CTRL [7:0] = 0x0F */ | |
662 | rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); | |
663 | ||
664 | /* c. DRV runs power on init flow */ | |
665 | ||
666 | /* auto enable WLAN */ | |
667 | /* 4. APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0 */ | |
668 | /* Power On Reset for MAC Block */ | |
669 | bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); | |
670 | udelay(2); | |
671 | rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); | |
672 | udelay(2); | |
673 | ||
674 | /* 5. Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */ | |
675 | bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); | |
676 | udelay(50); | |
677 | retry = 0; | |
678 | while ((bytetmp & BIT(0)) && retry < 1000) { | |
679 | retry++; | |
680 | bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); | |
681 | udelay(50); | |
682 | } | |
683 | ||
684 | /* Enable Radio off, GPIO, and LED function */ | |
685 | /* 6. APS_FSMCO 0x04[15:0] = 0x0012 when enable HWPDN */ | |
686 | rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); | |
687 | ||
688 | /* release RF digital isolation */ | |
689 | /* 7. SYS_ISO_CTRL 0x01[1] = 0x0; */ | |
690 | /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */ | |
691 | rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); | |
692 | udelay(2); | |
693 | ||
694 | /* make sure that BB reset OK. */ | |
695 | /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */ | |
696 | ||
697 | /* Disable REG_CR before enable it to assure reset */ | |
698 | rtl_write_word(rtlpriv, REG_CR, 0x0); | |
699 | ||
700 | /* Release MAC IO register reset */ | |
701 | rtl_write_word(rtlpriv, REG_CR, 0x2ff); | |
702 | ||
703 | /* clear stopping tx/rx dma */ | |
704 | rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0); | |
705 | ||
706 | /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */ | |
707 | ||
708 | /* System init */ | |
709 | /* 18. LLT_table_init(Adapter); */ | |
710 | if (_rtl92de_llt_table_init(hw) == false) | |
711 | return false; | |
712 | ||
713 | /* Clear interrupt and enable interrupt */ | |
714 | /* 19. HISR 0x124[31:0] = 0xffffffff; */ | |
715 | /* HISRE 0x12C[7:0] = 0xFF */ | |
716 | rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); | |
717 | rtl_write_byte(rtlpriv, REG_HISRE, 0xff); | |
718 | ||
719 | /* 20. HIMR 0x120[31:0] |= [enable INT mask bit map]; */ | |
720 | /* 21. HIMRE 0x128[7:0] = [enable INT mask bit map] */ | |
721 | /* The IMR should be enabled later after all init sequence | |
722 | * is finished. */ | |
723 | ||
724 | /* 22. PCIE configuration space configuration */ | |
725 | /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */ | |
726 | /* and PCIe gated clock function is enabled. */ | |
727 | /* PCIE configuration space will be written after | |
728 | * all init sequence.(Or by BIOS) */ | |
729 | ||
730 | rtl92d_phy_config_maccoexist_rfpage(hw); | |
731 | ||
732 | /* THe below section is not related to power document Vxx . */ | |
733 | /* This is only useful for driver and OS setting. */ | |
734 | /* -------------------Software Relative Setting---------------------- */ | |
735 | wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); | |
736 | wordtmp &= 0xf; | |
737 | wordtmp |= 0xF771; | |
738 | rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); | |
739 | ||
740 | /* Reported Tx status from HW for rate adaptive. */ | |
741 | /* This should be realtive to power on step 14. But in document V11 */ | |
742 | /* still not contain the description.!!! */ | |
743 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); | |
744 | ||
745 | /* Set Tx/Rx page size (Tx must be 128 Bytes, | |
746 | * Rx can be 64,128,256,512,1024 bytes) */ | |
747 | /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */ | |
748 | ||
749 | /* Set RCR register */ | |
750 | rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); | |
751 | /* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */ | |
752 | ||
753 | /* Set TCR register */ | |
754 | rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); | |
755 | ||
756 | /* disable earlymode */ | |
757 | rtl_write_byte(rtlpriv, 0x4d0, 0x0); | |
758 | ||
759 | /* Set TX/RX descriptor physical address(from OS API). */ | |
760 | rtl_write_dword(rtlpriv, REG_BCNQ_DESA, | |
761 | rtlpci->tx_ring[BEACON_QUEUE].dma); | |
762 | rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma); | |
763 | rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma); | |
764 | rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma); | |
765 | rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma); | |
766 | rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma); | |
767 | rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma); | |
768 | /* Set RX Desc Address */ | |
769 | rtl_write_dword(rtlpriv, REG_RX_DESA, | |
770 | rtlpci->rx_ring[RX_MPDU_QUEUE].dma); | |
771 | ||
772 | /* if we want to support 64 bit DMA, we should set it here, | |
773 | * but now we do not support 64 bit DMA*/ | |
774 | ||
775 | rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33); | |
776 | ||
777 | /* Reset interrupt migration setting when initialization */ | |
778 | rtl_write_dword(rtlpriv, REG_INT_MIG, 0); | |
779 | ||
780 | /* Reconsider when to do this operation after asking HWSD. */ | |
781 | bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); | |
782 | rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); | |
783 | do { | |
784 | retry++; | |
785 | bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); | |
786 | } while ((retry < 200) && !(bytetmp & BIT(7))); | |
787 | ||
788 | /* After MACIO reset,we must refresh LED state. */ | |
789 | _rtl92de_gen_refresh_led_state(hw); | |
790 | ||
791 | /* Reset H2C protection register */ | |
792 | rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); | |
793 | ||
794 | return true; | |
795 | } | |
796 | ||
797 | static void _rtl92de_hw_configure(struct ieee80211_hw *hw) | |
798 | { | |
799 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
800 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
801 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
802 | u8 reg_bw_opmode = BW_OPMODE_20MHZ; | |
803 | u32 reg_rrsr; | |
804 | ||
805 | reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; | |
806 | rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); | |
807 | rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); | |
808 | rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); | |
809 | rtl_write_byte(rtlpriv, REG_SLOT, 0x09); | |
810 | rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); | |
811 | rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); | |
812 | rtl_write_word(rtlpriv, REG_RL, 0x0707); | |
813 | rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); | |
814 | rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); | |
815 | rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); | |
816 | rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); | |
817 | rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); | |
818 | rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); | |
819 | /* Aggregation threshold */ | |
820 | if (rtlhal->macphymode == DUALMAC_DUALPHY) | |
821 | rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641); | |
822 | else if (rtlhal->macphymode == DUALMAC_SINGLEPHY) | |
823 | rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641); | |
824 | else | |
825 | rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); | |
826 | rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); | |
827 | rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); | |
828 | rtlpci->reg_bcn_ctrl_val = 0x1f; | |
829 | rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); | |
830 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); | |
831 | rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); | |
832 | rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); | |
833 | rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); | |
834 | /* For throughput */ | |
835 | rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666); | |
836 | /* ACKTO for IOT issue. */ | |
837 | rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); | |
838 | /* Set Spec SIFS (used in NAV) */ | |
839 | rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); | |
840 | rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); | |
841 | /* Set SIFS for CCK */ | |
842 | rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); | |
843 | /* Set SIFS for OFDM */ | |
844 | rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); | |
845 | /* Set Multicast Address. */ | |
846 | rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); | |
847 | rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); | |
848 | switch (rtlpriv->phy.rf_type) { | |
849 | case RF_1T2R: | |
850 | case RF_1T1R: | |
851 | rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3); | |
852 | break; | |
853 | case RF_2T2R: | |
854 | case RF_2T2R_GREEN: | |
855 | rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3); | |
856 | break; | |
857 | } | |
858 | } | |
859 | ||
860 | static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw) | |
861 | { | |
862 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
863 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
864 | ||
865 | rtl_write_byte(rtlpriv, 0x34b, 0x93); | |
866 | rtl_write_word(rtlpriv, 0x350, 0x870c); | |
867 | rtl_write_byte(rtlpriv, 0x352, 0x1); | |
868 | if (ppsc->support_backdoor) | |
869 | rtl_write_byte(rtlpriv, 0x349, 0x1b); | |
870 | else | |
871 | rtl_write_byte(rtlpriv, 0x349, 0x03); | |
872 | rtl_write_word(rtlpriv, 0x350, 0x2718); | |
873 | rtl_write_byte(rtlpriv, 0x352, 0x1); | |
874 | } | |
875 | ||
876 | void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw) | |
877 | { | |
878 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
879 | u8 sec_reg_value; | |
880 | ||
881 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
882 | ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", | |
883 | rtlpriv->sec.pairwise_enc_algorithm, | |
884 | rtlpriv->sec.group_enc_algorithm)); | |
885 | if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { | |
886 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
887 | ("not open hw encryption\n")); | |
888 | return; | |
889 | } | |
890 | sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE; | |
891 | if (rtlpriv->sec.use_defaultkey) { | |
892 | sec_reg_value |= SCR_TXUSEDK; | |
893 | sec_reg_value |= SCR_RXUSEDK; | |
894 | } | |
895 | sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); | |
896 | rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); | |
897 | RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, | |
898 | ("The SECR-value %x\n", sec_reg_value)); | |
899 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); | |
900 | } | |
901 | ||
902 | int rtl92de_hw_init(struct ieee80211_hw *hw) | |
903 | { | |
904 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
905 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
906 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
907 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
908 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
909 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
910 | bool rtstatus = true; | |
9a4ba833 DC |
911 | u8 tmp_u1b; |
912 | int i; | |
3affdf42 CL |
913 | int err; |
914 | unsigned long flags; | |
915 | ||
916 | rtlpci->being_init_adapter = true; | |
917 | rtlpci->init_ready = false; | |
918 | spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags); | |
919 | /* we should do iqk after disable/enable */ | |
920 | rtl92d_phy_reset_iqk_result(hw); | |
921 | /* rtlpriv->intf_ops->disable_aspm(hw); */ | |
922 | rtstatus = _rtl92de_init_mac(hw); | |
923 | if (rtstatus != true) { | |
924 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Init MAC failed\n")); | |
925 | err = 1; | |
926 | spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags); | |
927 | return err; | |
928 | } | |
929 | err = rtl92d_download_fw(hw); | |
930 | spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags); | |
931 | if (err) { | |
932 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
933 | ("Failed to download FW. Init HW " | |
934 | "without FW..\n")); | |
3affdf42 | 935 | rtlhal->fw_ready = false; |
45a77138 | 936 | return 1; |
3affdf42 CL |
937 | } else { |
938 | rtlhal->fw_ready = true; | |
939 | } | |
940 | rtlhal->last_hmeboxnum = 0; | |
941 | rtlpriv->psc.fw_current_inpsmode = false; | |
942 | ||
943 | tmp_u1b = rtl_read_byte(rtlpriv, 0x605); | |
944 | tmp_u1b = tmp_u1b | 0x30; | |
945 | rtl_write_byte(rtlpriv, 0x605, tmp_u1b); | |
946 | ||
947 | if (rtlhal->earlymode_enable) { | |
948 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
949 | ("EarlyMode Enabled!!!\n")); | |
950 | ||
951 | tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0); | |
952 | tmp_u1b = tmp_u1b | 0x1f; | |
953 | rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b); | |
954 | ||
955 | rtl_write_byte(rtlpriv, 0x4d3, 0x80); | |
956 | ||
957 | tmp_u1b = rtl_read_byte(rtlpriv, 0x605); | |
958 | tmp_u1b = tmp_u1b | 0x40; | |
959 | rtl_write_byte(rtlpriv, 0x605, tmp_u1b); | |
960 | } | |
961 | ||
962 | if (mac->rdg_en) { | |
963 | rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff); | |
964 | rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200); | |
965 | rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05); | |
966 | } | |
967 | ||
968 | rtl92d_phy_mac_config(hw); | |
969 | /* because last function modify RCR, so we update | |
970 | * rcr var here, or TP will unstable for receive_config | |
971 | * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx | |
972 | * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/ | |
973 | rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); | |
974 | rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); | |
975 | ||
976 | rtl92d_phy_bb_config(hw); | |
977 | ||
978 | rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; | |
979 | /* set before initialize RF */ | |
980 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); | |
981 | ||
982 | /* config RF */ | |
983 | rtl92d_phy_rf_config(hw); | |
984 | ||
985 | /* After read predefined TXT, we must set BB/MAC/RF | |
986 | * register as our requirement */ | |
987 | /* After load BB,RF params,we need do more for 92D. */ | |
988 | rtl92d_update_bbrf_configuration(hw); | |
989 | /* set default value after initialize RF, */ | |
990 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); | |
991 | rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, | |
992 | RF_CHNLBW, BRFREGOFFSETMASK); | |
993 | rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, | |
994 | RF_CHNLBW, BRFREGOFFSETMASK); | |
995 | ||
996 | /*---- Set CCK and OFDM Block "ON"----*/ | |
997 | if (rtlhal->current_bandtype == BAND_ON_2_4G) | |
998 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); | |
999 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); | |
1000 | if (rtlhal->interfaceindex == 0) { | |
1001 | /* RFPGA0_ANALOGPARAMETER2: cck clock select, | |
1002 | * set to 20MHz by default */ | |
1003 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | | |
1004 | BIT(11), 3); | |
1005 | } else { | |
1006 | /* Mac1 */ | |
1007 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) | | |
1008 | BIT(10), 3); | |
1009 | } | |
1010 | ||
1011 | _rtl92de_hw_configure(hw); | |
1012 | ||
1013 | /* reset hw sec */ | |
1014 | rtl_cam_reset_all_entry(hw); | |
1015 | rtl92de_enable_hw_security_config(hw); | |
1016 | ||
1017 | /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */ | |
1018 | /* TX power index for different rate set. */ | |
1019 | rtl92d_phy_get_hw_reg_originalvalue(hw); | |
1020 | rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); | |
1021 | ||
1022 | ppsc->rfpwr_state = ERFON; | |
1023 | ||
1024 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); | |
1025 | ||
1026 | _rtl92de_enable_aspm_back_door(hw); | |
1027 | /* rtlpriv->intf_ops->enable_aspm(hw); */ | |
1028 | ||
1029 | rtl92d_dm_init(hw); | |
1030 | rtlpci->being_init_adapter = false; | |
1031 | ||
1032 | if (ppsc->rfpwr_state == ERFON) { | |
1033 | rtl92d_phy_lc_calibrate(hw); | |
1034 | /* 5G and 2.4G must wait sometime to let RF LO ready */ | |
1035 | if (rtlhal->macphymode == DUALMAC_DUALPHY) { | |
1036 | u32 tmp_rega; | |
1037 | for (i = 0; i < 10000; i++) { | |
1038 | udelay(MAX_STALL_TIME); | |
1039 | ||
1040 | tmp_rega = rtl_get_rfreg(hw, | |
1041 | (enum radio_path)RF90_PATH_A, | |
1042 | 0x2a, BMASKDWORD); | |
1043 | ||
1044 | if (((tmp_rega & BIT(11)) == BIT(11))) | |
1045 | break; | |
1046 | } | |
45a77138 LF |
1047 | /* check that loop was successful. If not, exit now */ |
1048 | if (i == 10000) { | |
1049 | rtlpci->init_ready = false; | |
1050 | return 1; | |
1051 | } | |
3affdf42 CL |
1052 | } |
1053 | } | |
1054 | rtlpci->init_ready = true; | |
1055 | return err; | |
1056 | } | |
1057 | ||
1058 | static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw) | |
1059 | { | |
1060 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1061 | enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; | |
1062 | u32 value32; | |
1063 | ||
1064 | value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); | |
1065 | if (!(value32 & 0x000f0000)) { | |
1066 | version = VERSION_TEST_CHIP_92D_SINGLEPHY; | |
1067 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("TEST CHIP!!!\n")); | |
1068 | } else { | |
1069 | version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; | |
1070 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Normal CHIP!!!\n")); | |
1071 | } | |
1072 | return version; | |
1073 | } | |
1074 | ||
1075 | static int _rtl92de_set_media_status(struct ieee80211_hw *hw, | |
1076 | enum nl80211_iftype type) | |
1077 | { | |
1078 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1079 | u8 bt_msr = rtl_read_byte(rtlpriv, MSR); | |
1080 | enum led_ctl_mode ledaction = LED_CTL_NO_LINK; | |
1081 | u8 bcnfunc_enable; | |
1082 | ||
1083 | bt_msr &= 0xfc; | |
1084 | ||
1085 | if (type == NL80211_IFTYPE_UNSPECIFIED || | |
1086 | type == NL80211_IFTYPE_STATION) { | |
1087 | _rtl92de_stop_tx_beacon(hw); | |
1088 | _rtl92de_enable_bcn_sub_func(hw); | |
1089 | } else if (type == NL80211_IFTYPE_ADHOC || | |
1090 | type == NL80211_IFTYPE_AP) { | |
1091 | _rtl92de_resume_tx_beacon(hw); | |
1092 | _rtl92de_disable_bcn_sub_func(hw); | |
1093 | } else { | |
1094 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
1095 | ("Set HW_VAR_MEDIA_STATUS: No such media " | |
1096 | "status(%x).\n", type)); | |
1097 | } | |
1098 | bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL); | |
1099 | switch (type) { | |
1100 | case NL80211_IFTYPE_UNSPECIFIED: | |
1101 | bt_msr |= MSR_NOLINK; | |
1102 | ledaction = LED_CTL_LINK; | |
1103 | bcnfunc_enable &= 0xF7; | |
1104 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
1105 | ("Set Network type to NO LINK!\n")); | |
1106 | break; | |
1107 | case NL80211_IFTYPE_ADHOC: | |
1108 | bt_msr |= MSR_ADHOC; | |
1109 | bcnfunc_enable |= 0x08; | |
1110 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
1111 | ("Set Network type to Ad Hoc!\n")); | |
1112 | break; | |
1113 | case NL80211_IFTYPE_STATION: | |
1114 | bt_msr |= MSR_INFRA; | |
1115 | ledaction = LED_CTL_LINK; | |
1116 | bcnfunc_enable &= 0xF7; | |
1117 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
1118 | ("Set Network type to STA!\n")); | |
1119 | break; | |
1120 | case NL80211_IFTYPE_AP: | |
1121 | bt_msr |= MSR_AP; | |
1122 | bcnfunc_enable |= 0x08; | |
1123 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
1124 | ("Set Network type to AP!\n")); | |
1125 | break; | |
1126 | default: | |
1127 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
1128 | ("Network type %d not support!\n", type)); | |
1129 | return 1; | |
1130 | break; | |
1131 | ||
1132 | } | |
1133 | rtl_write_byte(rtlpriv, REG_CR + 2, bt_msr); | |
1134 | rtlpriv->cfg->ops->led_control(hw, ledaction); | |
1135 | if ((bt_msr & 0xfc) == MSR_AP) | |
1136 | rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); | |
1137 | else | |
1138 | rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); | |
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) | |
1143 | { | |
1144 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1145 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1146 | u32 reg_rcr = rtlpci->receive_config; | |
1147 | ||
1148 | if (rtlpriv->psc.rfpwr_state != ERFON) | |
1149 | return; | |
9928c7d1 | 1150 | if (check_bssid) { |
3affdf42 CL |
1151 | reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); |
1152 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); | |
1153 | _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4)); | |
1154 | } else if (check_bssid == false) { | |
1155 | reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); | |
1156 | _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0); | |
1157 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); | |
1158 | } | |
1159 | } | |
1160 | ||
1161 | int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) | |
1162 | { | |
1163 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1164 | ||
1165 | if (_rtl92de_set_media_status(hw, type)) | |
1166 | return -EOPNOTSUPP; | |
1167 | ||
1168 | /* check bssid */ | |
1169 | if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { | |
1170 | if (type != NL80211_IFTYPE_AP) | |
1171 | rtl92de_set_check_bssid(hw, true); | |
1172 | } else { | |
1173 | rtl92de_set_check_bssid(hw, false); | |
1174 | } | |
1175 | return 0; | |
1176 | } | |
1177 | ||
1178 | /* do iqk or reload iqk */ | |
1179 | /* windows just rtl92d_phy_reload_iqk_setting in set channel, | |
1180 | * but it's very strict for time sequence so we add | |
1181 | * rtl92d_phy_reload_iqk_setting here */ | |
1182 | void rtl92d_linked_set_reg(struct ieee80211_hw *hw) | |
1183 | { | |
1184 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1185 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1186 | u8 indexforchannel; | |
1187 | u8 channel = rtlphy->current_channel; | |
1188 | ||
1189 | indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel); | |
1190 | if (!rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done) { | |
1191 | RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG, | |
1192 | ("Do IQK for channel:%d.\n", channel)); | |
1193 | rtl92d_phy_iq_calibrate(hw); | |
1194 | } | |
1195 | } | |
1196 | ||
1197 | /* don't set REG_EDCA_BE_PARAM here because | |
1198 | * mac80211 will send pkt when scan */ | |
1199 | void rtl92de_set_qos(struct ieee80211_hw *hw, int aci) | |
1200 | { | |
1201 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1202 | rtl92d_dm_init_edca_turbo(hw); | |
1203 | return; | |
1204 | switch (aci) { | |
1205 | case AC1_BK: | |
1206 | rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); | |
1207 | break; | |
1208 | case AC0_BE: | |
1209 | break; | |
1210 | case AC2_VI: | |
1211 | rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); | |
1212 | break; | |
1213 | case AC3_VO: | |
1214 | rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); | |
1215 | break; | |
1216 | default: | |
1217 | RT_ASSERT(false, ("invalid aci: %d !\n", aci)); | |
1218 | break; | |
1219 | } | |
1220 | } | |
1221 | ||
1222 | void rtl92de_enable_interrupt(struct ieee80211_hw *hw) | |
1223 | { | |
1224 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1225 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1226 | ||
1227 | rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); | |
1228 | rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); | |
3affdf42 CL |
1229 | } |
1230 | ||
1231 | void rtl92de_disable_interrupt(struct ieee80211_hw *hw) | |
1232 | { | |
1233 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1234 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1235 | ||
1236 | rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); | |
1237 | rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); | |
3affdf42 CL |
1238 | synchronize_irq(rtlpci->pdev->irq); |
1239 | } | |
1240 | ||
1241 | static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw) | |
1242 | { | |
1243 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1244 | u8 u1b_tmp; | |
1245 | unsigned long flags; | |
1246 | ||
1247 | rtlpriv->intf_ops->enable_aspm(hw); | |
1248 | rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); | |
1249 | rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0); | |
1250 | rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0); | |
1251 | ||
1252 | /* 0x20:value 05-->04 */ | |
1253 | rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); | |
1254 | ||
1255 | /* ==== Reset digital sequence ====== */ | |
1256 | rtl92d_firmware_selfreset(hw); | |
1257 | ||
1258 | /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */ | |
1259 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); | |
1260 | ||
1261 | /* g. MCUFWDL 0x80[1:0]=0 reset MCU ready status */ | |
1262 | rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); | |
1263 | ||
1264 | /* ==== Pull GPIO PIN to balance level and LED control ====== */ | |
1265 | ||
1266 | /* h. GPIO_PIN_CTRL 0x44[31:0]=0x000 */ | |
1267 | rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); | |
1268 | ||
1269 | /* i. Value = GPIO_PIN_CTRL[7:0] */ | |
1270 | u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL); | |
1271 | ||
1272 | /* j. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */ | |
1273 | /* write external PIN level */ | |
1274 | rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, | |
1275 | 0x00FF0000 | (u1b_tmp << 8)); | |
1276 | ||
1277 | /* k. GPIO_MUXCFG 0x42 [15:0] = 0x0780 */ | |
1278 | rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); | |
1279 | ||
1280 | /* l. LEDCFG 0x4C[15:0] = 0x8080 */ | |
1281 | rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); | |
1282 | ||
1283 | /* ==== Disable analog sequence === */ | |
1284 | ||
1285 | /* m. AFE_PLL_CTRL[7:0] = 0x80 disable PLL */ | |
1286 | rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); | |
1287 | ||
1288 | /* n. SPS0_CTRL 0x11[7:0] = 0x22 enter PFM mode */ | |
1289 | rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); | |
1290 | ||
1291 | /* o. AFE_XTAL_CTRL 0x24[7:0] = 0x0E disable XTAL, if No BT COEX */ | |
1292 | rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); | |
1293 | ||
1294 | /* p. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */ | |
1295 | rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); | |
1296 | ||
1297 | /* ==== interface into suspend === */ | |
1298 | ||
1299 | /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */ | |
1300 | /* According to power document V11, we need to set this */ | |
1301 | /* value as 0x18. Otherwise, we may not L0s sometimes. */ | |
1302 | /* This indluences power consumption. Bases on SD1's test, */ | |
1303 | /* set as 0x00 do not affect power current. And if it */ | |
1304 | /* is set as 0x18, they had ever met auto load fail problem. */ | |
1305 | rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); | |
1306 | ||
1307 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1308 | ("In PowerOff,reg0x%x=%X\n", REG_SPS0_CTRL, | |
1309 | rtl_read_byte(rtlpriv, REG_SPS0_CTRL))); | |
1310 | /* r. Note: for PCIe interface, PON will not turn */ | |
1311 | /* off m-bias and BandGap in PCIe suspend mode. */ | |
1312 | ||
1313 | /* 0x17[7] 1b': power off in process 0b' : power off over */ | |
1314 | if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { | |
1315 | spin_lock_irqsave(&globalmutex_power, flags); | |
1316 | u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); | |
1317 | u1b_tmp &= (~BIT(7)); | |
1318 | rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp); | |
1319 | spin_unlock_irqrestore(&globalmutex_power, flags); | |
1320 | } | |
1321 | ||
1322 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("<=======\n")); | |
1323 | } | |
1324 | ||
1325 | void rtl92de_card_disable(struct ieee80211_hw *hw) | |
1326 | { | |
1327 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1328 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
1329 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1330 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1331 | enum nl80211_iftype opmode; | |
1332 | ||
1333 | mac->link_state = MAC80211_NOLINK; | |
1334 | opmode = NL80211_IFTYPE_UNSPECIFIED; | |
1335 | _rtl92de_set_media_status(hw, opmode); | |
1336 | ||
1337 | if (rtlpci->driver_is_goingto_unload || | |
1338 | ppsc->rfoff_reason > RF_CHANGE_BY_PS) | |
1339 | rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); | |
1340 | RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); | |
1341 | /* Power sequence for each MAC. */ | |
1342 | /* a. stop tx DMA */ | |
1343 | /* b. close RF */ | |
1344 | /* c. clear rx buf */ | |
1345 | /* d. stop rx DMA */ | |
1346 | /* e. reset MAC */ | |
1347 | ||
1348 | /* a. stop tx DMA */ | |
1349 | rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); | |
1350 | udelay(50); | |
1351 | ||
1352 | /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ | |
1353 | ||
1354 | /* c. ========RF OFF sequence========== */ | |
1355 | /* 0x88c[23:20] = 0xf. */ | |
1356 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); | |
1357 | rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00); | |
1358 | ||
1359 | /* APSD_CTRL 0x600[7:0] = 0x40 */ | |
1360 | rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); | |
1361 | ||
1362 | /* Close antenna 0,0xc04,0xd04 */ | |
1363 | rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0); | |
1364 | rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0); | |
1365 | ||
1366 | /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */ | |
1367 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); | |
1368 | ||
1369 | /* Mac0 can not do Global reset. Mac1 can do. */ | |
1370 | /* SYS_FUNC_EN 0x02[7:0] = 0xE0 reset BB state machine */ | |
1371 | if (rtlpriv->rtlhal.interfaceindex == 1) | |
1372 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); | |
1373 | udelay(50); | |
1374 | ||
1375 | /* d. stop tx/rx dma before disable REG_CR (0x100) to fix */ | |
1376 | /* dma hang issue when disable/enable device. */ | |
1377 | rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff); | |
1378 | udelay(50); | |
1379 | rtl_write_byte(rtlpriv, REG_CR, 0x0); | |
1380 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("==> Do power off.......\n")); | |
1381 | if (rtl92d_phy_check_poweroff(hw)) | |
1382 | _rtl92de_poweroff_adapter(hw); | |
1383 | return; | |
1384 | } | |
1385 | ||
1386 | void rtl92de_interrupt_recognized(struct ieee80211_hw *hw, | |
1387 | u32 *p_inta, u32 *p_intb) | |
1388 | { | |
1389 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1390 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1391 | ||
1392 | *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; | |
1393 | rtl_write_dword(rtlpriv, ISR, *p_inta); | |
1394 | ||
1395 | /* | |
1396 | * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; | |
1397 | * rtl_write_dword(rtlpriv, ISR + 4, *p_intb); | |
1398 | */ | |
1399 | } | |
1400 | ||
1401 | void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw) | |
1402 | { | |
1403 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1404 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1405 | u16 bcn_interval, atim_window; | |
1406 | ||
1407 | bcn_interval = mac->beacon_interval; | |
1408 | atim_window = 2; | |
1409 | /*rtl92de_disable_interrupt(hw); */ | |
1410 | rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); | |
1411 | rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); | |
1412 | rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); | |
1413 | rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20); | |
1414 | if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) | |
1415 | rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30); | |
1416 | else | |
1417 | rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20); | |
1418 | rtl_write_byte(rtlpriv, 0x606, 0x30); | |
1419 | } | |
1420 | ||
1421 | void rtl92de_set_beacon_interval(struct ieee80211_hw *hw) | |
1422 | { | |
1423 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1424 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1425 | u16 bcn_interval = mac->beacon_interval; | |
1426 | ||
1427 | RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, | |
1428 | ("beacon_interval:%d\n", bcn_interval)); | |
1429 | /* rtl92de_disable_interrupt(hw); */ | |
1430 | rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); | |
1431 | /* rtl92de_enable_interrupt(hw); */ | |
1432 | } | |
1433 | ||
1434 | void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw, | |
1435 | u32 add_msr, u32 rm_msr) | |
1436 | { | |
1437 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1438 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1439 | ||
1440 | RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, | |
1441 | ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr)); | |
1442 | if (add_msr) | |
1443 | rtlpci->irq_mask[0] |= add_msr; | |
1444 | if (rm_msr) | |
1445 | rtlpci->irq_mask[0] &= (~rm_msr); | |
1446 | rtl92de_disable_interrupt(hw); | |
1447 | rtl92de_enable_interrupt(hw); | |
1448 | } | |
1449 | ||
1450 | static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, | |
1451 | u8 *rom_content, bool autoLoadfail) | |
1452 | { | |
1453 | u32 rfpath, eeaddr, group, offset1, offset2; | |
1454 | u8 i; | |
1455 | ||
1456 | memset(pwrinfo, 0, sizeof(struct txpower_info)); | |
1457 | if (autoLoadfail) { | |
1458 | for (group = 0; group < CHANNEL_GROUP_MAX; group++) { | |
1459 | for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { | |
1460 | if (group < CHANNEL_GROUP_MAX_2G) { | |
1461 | pwrinfo->cck_index[rfpath][group] = | |
1462 | EEPROM_DEFAULT_TXPOWERLEVEL_2G; | |
1463 | pwrinfo->ht40_1sindex[rfpath][group] = | |
1464 | EEPROM_DEFAULT_TXPOWERLEVEL_2G; | |
1465 | } else { | |
1466 | pwrinfo->ht40_1sindex[rfpath][group] = | |
1467 | EEPROM_DEFAULT_TXPOWERLEVEL_5G; | |
1468 | } | |
1469 | pwrinfo->ht40_2sindexdiff[rfpath][group] = | |
1470 | EEPROM_DEFAULT_HT40_2SDIFF; | |
1471 | pwrinfo->ht20indexdiff[rfpath][group] = | |
1472 | EEPROM_DEFAULT_HT20_DIFF; | |
1473 | pwrinfo->ofdmindexdiff[rfpath][group] = | |
1474 | EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; | |
1475 | pwrinfo->ht40maxoffset[rfpath][group] = | |
1476 | EEPROM_DEFAULT_HT40_PWRMAXOFFSET; | |
1477 | pwrinfo->ht20maxoffset[rfpath][group] = | |
1478 | EEPROM_DEFAULT_HT20_PWRMAXOFFSET; | |
1479 | } | |
1480 | } | |
1481 | for (i = 0; i < 3; i++) { | |
1482 | pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; | |
1483 | pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; | |
1484 | } | |
1485 | return; | |
1486 | } | |
1487 | ||
1488 | /* Maybe autoload OK,buf the tx power index value is not filled. | |
1489 | * If we find it, we set it to default value. */ | |
1490 | for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { | |
1491 | for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) { | |
1492 | eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3) | |
1493 | + group; | |
1494 | pwrinfo->cck_index[rfpath][group] = | |
1495 | (rom_content[eeaddr] == 0xFF) ? | |
1496 | (eeaddr > 0x7B ? | |
1497 | EEPROM_DEFAULT_TXPOWERLEVEL_5G : | |
1498 | EEPROM_DEFAULT_TXPOWERLEVEL_2G) : | |
1499 | rom_content[eeaddr]; | |
1500 | } | |
1501 | } | |
1502 | for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { | |
1503 | for (group = 0; group < CHANNEL_GROUP_MAX; group++) { | |
1504 | offset1 = group / 3; | |
1505 | offset2 = group % 3; | |
1506 | eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) + | |
1507 | offset2 + offset1 * 21; | |
1508 | pwrinfo->ht40_1sindex[rfpath][group] = | |
1509 | (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ? | |
1510 | EEPROM_DEFAULT_TXPOWERLEVEL_5G : | |
1511 | EEPROM_DEFAULT_TXPOWERLEVEL_2G) : | |
1512 | rom_content[eeaddr]; | |
1513 | } | |
1514 | } | |
1515 | /* These just for 92D efuse offset. */ | |
1516 | for (group = 0; group < CHANNEL_GROUP_MAX; group++) { | |
1517 | for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { | |
1518 | int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G; | |
1519 | ||
1520 | offset1 = group / 3; | |
1521 | offset2 = group % 3; | |
1522 | ||
1523 | if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF) | |
1524 | pwrinfo->ht40_2sindexdiff[rfpath][group] = | |
1525 | (rom_content[base1 + | |
1526 | offset2 + offset1 * 21] >> (rfpath * 4)) | |
1527 | & 0xF; | |
1528 | else | |
1529 | pwrinfo->ht40_2sindexdiff[rfpath][group] = | |
1530 | EEPROM_DEFAULT_HT40_2SDIFF; | |
1531 | if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2 | |
1532 | + offset1 * 21] != 0xFF) | |
1533 | pwrinfo->ht20indexdiff[rfpath][group] = | |
1534 | (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G | |
1535 | + offset2 + offset1 * 21] >> (rfpath * 4)) | |
1536 | & 0xF; | |
1537 | else | |
1538 | pwrinfo->ht20indexdiff[rfpath][group] = | |
1539 | EEPROM_DEFAULT_HT20_DIFF; | |
1540 | if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2 | |
1541 | + offset1 * 21] != 0xFF) | |
1542 | pwrinfo->ofdmindexdiff[rfpath][group] = | |
1543 | (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G | |
1544 | + offset2 + offset1 * 21] >> (rfpath * 4)) | |
1545 | & 0xF; | |
1546 | else | |
1547 | pwrinfo->ofdmindexdiff[rfpath][group] = | |
1548 | EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; | |
1549 | if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2 | |
1550 | + offset1 * 21] != 0xFF) | |
1551 | pwrinfo->ht40maxoffset[rfpath][group] = | |
1552 | (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G | |
1553 | + offset2 + offset1 * 21] >> (rfpath * 4)) | |
1554 | & 0xF; | |
1555 | else | |
1556 | pwrinfo->ht40maxoffset[rfpath][group] = | |
1557 | EEPROM_DEFAULT_HT40_PWRMAXOFFSET; | |
1558 | if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2 | |
1559 | + offset1 * 21] != 0xFF) | |
1560 | pwrinfo->ht20maxoffset[rfpath][group] = | |
1561 | (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + | |
1562 | offset2 + offset1 * 21] >> (rfpath * 4)) & | |
1563 | 0xF; | |
1564 | else | |
1565 | pwrinfo->ht20maxoffset[rfpath][group] = | |
1566 | EEPROM_DEFAULT_HT20_PWRMAXOFFSET; | |
1567 | } | |
1568 | } | |
1569 | if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) { | |
1570 | /* 5GL */ | |
1571 | pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F; | |
1572 | pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F; | |
1573 | /* 5GM */ | |
1574 | pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F; | |
1575 | pwrinfo->tssi_b[1] = | |
1576 | (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 | | |
1577 | (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2; | |
1578 | /* 5GH */ | |
1579 | pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] & | |
1580 | 0xF0) >> 4 | | |
1581 | (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4; | |
1582 | pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] & | |
1583 | 0xFC) >> 2; | |
1584 | } else { | |
1585 | for (i = 0; i < 3; i++) { | |
1586 | pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; | |
1587 | pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; | |
1588 | } | |
1589 | } | |
1590 | } | |
1591 | ||
1592 | static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw, | |
1593 | bool autoload_fail, u8 *hwinfo) | |
1594 | { | |
1595 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1596 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
1597 | struct txpower_info pwrinfo; | |
1598 | u8 tempval[2], i, pwr, diff; | |
1599 | u32 ch, rfPath, group; | |
1600 | ||
1601 | _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail); | |
1602 | if (!autoload_fail) { | |
1603 | /* bit0~2 */ | |
1604 | rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7); | |
1605 | rtlefuse->eeprom_thermalmeter = | |
1606 | hwinfo[EEPROM_THERMAL_METER] & 0x1f; | |
1607 | rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K]; | |
1608 | tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03; | |
1609 | tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2; | |
1610 | rtlefuse->txpwr_fromeprom = true; | |
d83579e2 CL |
1611 | if (IS_92D_D_CUT(rtlpriv->rtlhal.version) || |
1612 | IS_92D_E_CUT(rtlpriv->rtlhal.version)) { | |
3affdf42 | 1613 | rtlefuse->internal_pa_5g[0] = |
d83579e2 | 1614 | !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6); |
3affdf42 | 1615 | rtlefuse->internal_pa_5g[1] = |
d83579e2 CL |
1616 | !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6); |
1617 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
3affdf42 | 1618 | ("Is D cut,Internal PA0 %d Internal PA1 %d\n", |
d83579e2 CL |
1619 | rtlefuse->internal_pa_5g[0], |
1620 | rtlefuse->internal_pa_5g[1])) | |
3affdf42 CL |
1621 | } |
1622 | rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6]; | |
1623 | rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7]; | |
1624 | } else { | |
1625 | rtlefuse->eeprom_regulatory = 0; | |
1626 | rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; | |
1627 | rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP; | |
1628 | tempval[0] = tempval[1] = 3; | |
1629 | } | |
1630 | ||
1631 | /* Use default value to fill parameters if | |
1632 | * efuse is not filled on some place. */ | |
1633 | ||
1634 | /* ThermalMeter from EEPROM */ | |
1635 | if (rtlefuse->eeprom_thermalmeter < 0x06 || | |
1636 | rtlefuse->eeprom_thermalmeter > 0x1c) | |
1637 | rtlefuse->eeprom_thermalmeter = 0x12; | |
1638 | rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; | |
1639 | ||
1640 | /* check XTAL_K */ | |
1641 | if (rtlefuse->crystalcap == 0xFF) | |
1642 | rtlefuse->crystalcap = 0; | |
1643 | if (rtlefuse->eeprom_regulatory > 3) | |
1644 | rtlefuse->eeprom_regulatory = 0; | |
1645 | ||
1646 | for (i = 0; i < 2; i++) { | |
1647 | switch (tempval[i]) { | |
1648 | case 0: | |
1649 | tempval[i] = 5; | |
1650 | break; | |
1651 | case 1: | |
1652 | tempval[i] = 4; | |
1653 | break; | |
1654 | case 2: | |
1655 | tempval[i] = 3; | |
1656 | break; | |
1657 | case 3: | |
1658 | default: | |
1659 | tempval[i] = 0; | |
1660 | break; | |
1661 | } | |
1662 | } | |
1663 | ||
1664 | rtlefuse->delta_iqk = tempval[0]; | |
1665 | if (tempval[1] > 0) | |
1666 | rtlefuse->delta_lck = tempval[1] - 1; | |
1667 | if (rtlefuse->eeprom_c9 == 0xFF) | |
1668 | rtlefuse->eeprom_c9 = 0x00; | |
1669 | RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, | |
1670 | ("EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory)); | |
1671 | RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, | |
1672 | ("ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter)); | |
1673 | RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, | |
1674 | ("CrystalCap = 0x%x\n", rtlefuse->crystalcap)); | |
1675 | RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, | |
1676 | ("Delta_IQK = 0x%x Delta_LCK = 0x%x\n", rtlefuse->delta_iqk, | |
1677 | rtlefuse->delta_lck)); | |
1678 | ||
1679 | for (rfPath = 0; rfPath < RF6052_MAX_PATH; rfPath++) { | |
1680 | for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) { | |
1681 | group = rtl92d_get_chnlgroup_fromarray((u8) ch); | |
1682 | if (ch < CHANNEL_MAX_NUMBER_2G) | |
1683 | rtlefuse->txpwrlevel_cck[rfPath][ch] = | |
1684 | pwrinfo.cck_index[rfPath][group]; | |
1685 | rtlefuse->txpwrlevel_ht40_1s[rfPath][ch] = | |
1686 | pwrinfo.ht40_1sindex[rfPath][group]; | |
1687 | rtlefuse->txpwr_ht20diff[rfPath][ch] = | |
1688 | pwrinfo.ht20indexdiff[rfPath][group]; | |
1689 | rtlefuse->txpwr_legacyhtdiff[rfPath][ch] = | |
1690 | pwrinfo.ofdmindexdiff[rfPath][group]; | |
1691 | rtlefuse->pwrgroup_ht20[rfPath][ch] = | |
1692 | pwrinfo.ht20maxoffset[rfPath][group]; | |
1693 | rtlefuse->pwrgroup_ht40[rfPath][ch] = | |
1694 | pwrinfo.ht40maxoffset[rfPath][group]; | |
1695 | pwr = pwrinfo.ht40_1sindex[rfPath][group]; | |
1696 | diff = pwrinfo.ht40_2sindexdiff[rfPath][group]; | |
1697 | rtlefuse->txpwrlevel_ht40_2s[rfPath][ch] = | |
1698 | (pwr > diff) ? (pwr - diff) : 0; | |
1699 | } | |
1700 | } | |
1701 | } | |
1702 | ||
1703 | static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw, | |
1704 | u8 *content) | |
1705 | { | |
1706 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1707 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1708 | u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION]; | |
1709 | ||
1710 | if (macphy_crvalue & BIT(3)) { | |
1711 | rtlhal->macphymode = SINGLEMAC_SINGLEPHY; | |
1712 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1713 | ("MacPhyMode SINGLEMAC_SINGLEPHY\n")); | |
1714 | } else { | |
1715 | rtlhal->macphymode = DUALMAC_DUALPHY; | |
1716 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1717 | ("MacPhyMode DUALMAC_DUALPHY\n")); | |
1718 | } | |
1719 | } | |
1720 | ||
1721 | static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw, | |
1722 | u8 *content) | |
1723 | { | |
1724 | _rtl92de_read_macphymode_from_prom(hw, content); | |
1725 | rtl92d_phy_config_macphymode(hw); | |
1726 | rtl92d_phy_config_macphymode_info(hw); | |
1727 | } | |
1728 | ||
1729 | static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) | |
1730 | { | |
1731 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1732 | enum version_8192d chipver = rtlpriv->rtlhal.version; | |
1733 | u8 cutvalue[2]; | |
1734 | u16 chipvalue; | |
1735 | ||
1736 | rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H, | |
1737 | &cutvalue[1]); | |
1738 | rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L, | |
1739 | &cutvalue[0]); | |
1740 | chipvalue = (cutvalue[1] << 8) | cutvalue[0]; | |
1741 | switch (chipvalue) { | |
1742 | case 0xAA55: | |
1743 | chipver |= CHIP_92D_C_CUT; | |
1744 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("C-CUT!!!\n")); | |
1745 | break; | |
1746 | case 0x9966: | |
1747 | chipver |= CHIP_92D_D_CUT; | |
1748 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("D-CUT!!!\n")); | |
1749 | break; | |
1750 | default: | |
1751 | chipver |= CHIP_92D_D_CUT; | |
1752 | RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, ("Unkown CUT!\n")); | |
1753 | break; | |
1754 | } | |
1755 | rtlpriv->rtlhal.version = chipver; | |
1756 | } | |
1757 | ||
1758 | static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) | |
1759 | { | |
1760 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1761 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
1762 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1763 | u16 i, usvalue; | |
1764 | u8 hwinfo[HWSET_MAX_SIZE]; | |
1765 | u16 eeprom_id; | |
1766 | unsigned long flags; | |
1767 | ||
1768 | if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) { | |
1769 | spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags); | |
1770 | rtl_efuse_shadow_map_update(hw); | |
1771 | _rtl92de_efuse_update_chip_version(hw); | |
1772 | spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags); | |
1773 | memcpy((void *)hwinfo, (void *)&rtlefuse->efuse_map | |
1774 | [EFUSE_INIT_MAP][0], | |
1775 | HWSET_MAX_SIZE); | |
1776 | } else if (rtlefuse->epromtype == EEPROM_93C46) { | |
1777 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
1778 | ("RTL819X Not boot from eeprom, check it !!")); | |
1779 | } | |
1780 | RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"), | |
1781 | hwinfo, HWSET_MAX_SIZE); | |
1782 | ||
1783 | eeprom_id = *((u16 *)&hwinfo[0]); | |
1784 | if (eeprom_id != RTL8190_EEPROM_ID) { | |
1785 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
1786 | ("EEPROM ID(%#x) is invalid!!\n", eeprom_id)); | |
1787 | rtlefuse->autoload_failflag = true; | |
1788 | } else { | |
1789 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n")); | |
1790 | rtlefuse->autoload_failflag = false; | |
1791 | } | |
9928c7d1 | 1792 | if (rtlefuse->autoload_failflag) { |
3affdf42 CL |
1793 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, |
1794 | ("RTL819X Not boot from eeprom, check it !!")); | |
1795 | return; | |
1796 | } | |
1797 | rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID]; | |
1798 | _rtl92de_read_macphymode_and_bandtype(hw, hwinfo); | |
1799 | ||
1800 | /* VID, DID SE 0xA-D */ | |
1801 | rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID]; | |
1802 | rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID]; | |
1803 | rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID]; | |
1804 | rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID]; | |
1805 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1806 | ("EEPROMId = 0x%4x\n", eeprom_id)); | |
1807 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1808 | ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid)); | |
1809 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1810 | ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did)); | |
1811 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1812 | ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid)); | |
1813 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1814 | ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid)); | |
1815 | ||
1816 | /* Read Permanent MAC address */ | |
1817 | if (rtlhal->interfaceindex == 0) { | |
1818 | for (i = 0; i < 6; i += 2) { | |
1819 | usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC0_92D + i]; | |
1820 | *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; | |
1821 | } | |
1822 | } else { | |
1823 | for (i = 0; i < 6; i += 2) { | |
1824 | usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i]; | |
1825 | *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; | |
1826 | } | |
1827 | } | |
1828 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, | |
1829 | rtlefuse->dev_addr); | |
1830 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
1d15b5f2 | 1831 | ("%pM\n", rtlefuse->dev_addr)); |
3affdf42 CL |
1832 | _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo); |
1833 | ||
1834 | /* Read Channel Plan */ | |
1835 | switch (rtlhal->bandset) { | |
1836 | case BAND_ON_2_4G: | |
1837 | rtlefuse->channel_plan = COUNTRY_CODE_TELEC; | |
1838 | break; | |
1839 | case BAND_ON_5G: | |
1840 | rtlefuse->channel_plan = COUNTRY_CODE_FCC; | |
1841 | break; | |
1842 | case BAND_ON_BOTH: | |
1843 | rtlefuse->channel_plan = COUNTRY_CODE_FCC; | |
1844 | break; | |
1845 | default: | |
1846 | rtlefuse->channel_plan = COUNTRY_CODE_FCC; | |
1847 | break; | |
1848 | } | |
1849 | rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION]; | |
1850 | rtlefuse->txpwr_fromeprom = true; | |
1851 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1852 | ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid)); | |
1853 | } | |
1854 | ||
1855 | void rtl92de_read_eeprom_info(struct ieee80211_hw *hw) | |
1856 | { | |
1857 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1858 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
1859 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1860 | u8 tmp_u1b; | |
1861 | ||
1862 | rtlhal->version = _rtl92de_read_chip_version(hw); | |
1863 | tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); | |
1864 | rtlefuse->autoload_status = tmp_u1b; | |
1865 | if (tmp_u1b & BIT(4)) { | |
1866 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n")); | |
1867 | rtlefuse->epromtype = EEPROM_93C46; | |
1868 | } else { | |
1869 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n")); | |
1870 | rtlefuse->epromtype = EEPROM_BOOT_EFUSE; | |
1871 | } | |
1872 | if (tmp_u1b & BIT(5)) { | |
1873 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n")); | |
1874 | ||
1875 | rtlefuse->autoload_failflag = false; | |
1876 | _rtl92de_read_adapter_info(hw); | |
1877 | } else { | |
1878 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n")); | |
1879 | } | |
1880 | return; | |
1881 | } | |
1882 | ||
1883 | static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw, | |
1884 | struct ieee80211_sta *sta) | |
1885 | { | |
1886 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1887 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1888 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1889 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1890 | u32 ratr_value; | |
1891 | u8 ratr_index = 0; | |
1892 | u8 nmode = mac->ht_enable; | |
1893 | u8 mimo_ps = IEEE80211_SMPS_OFF; | |
1894 | u16 shortgi_rate; | |
1895 | u32 tmp_ratr_value; | |
1896 | u8 curtxbw_40mhz = mac->bw_40; | |
1897 | u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? | |
1898 | 1 : 0; | |
1899 | u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? | |
1900 | 1 : 0; | |
1901 | enum wireless_mode wirelessmode = mac->mode; | |
1902 | ||
1903 | if (rtlhal->current_bandtype == BAND_ON_5G) | |
1904 | ratr_value = sta->supp_rates[1] << 4; | |
1905 | else | |
1906 | ratr_value = sta->supp_rates[0]; | |
1907 | ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | | |
1908 | sta->ht_cap.mcs.rx_mask[0] << 12); | |
1909 | switch (wirelessmode) { | |
1910 | case WIRELESS_MODE_A: | |
1911 | ratr_value &= 0x00000FF0; | |
1912 | break; | |
1913 | case WIRELESS_MODE_B: | |
1914 | if (ratr_value & 0x0000000c) | |
1915 | ratr_value &= 0x0000000d; | |
1916 | else | |
1917 | ratr_value &= 0x0000000f; | |
1918 | break; | |
1919 | case WIRELESS_MODE_G: | |
1920 | ratr_value &= 0x00000FF5; | |
1921 | break; | |
1922 | case WIRELESS_MODE_N_24G: | |
1923 | case WIRELESS_MODE_N_5G: | |
1924 | nmode = 1; | |
1925 | if (mimo_ps == IEEE80211_SMPS_STATIC) { | |
1926 | ratr_value &= 0x0007F005; | |
1927 | } else { | |
1928 | u32 ratr_mask; | |
1929 | ||
1930 | if (get_rf_type(rtlphy) == RF_1T2R || | |
1931 | get_rf_type(rtlphy) == RF_1T1R) { | |
1932 | ratr_mask = 0x000ff005; | |
1933 | } else { | |
1934 | ratr_mask = 0x0f0ff005; | |
1935 | } | |
1936 | ||
1937 | ratr_value &= ratr_mask; | |
1938 | } | |
1939 | break; | |
1940 | default: | |
1941 | if (rtlphy->rf_type == RF_1T2R) | |
1942 | ratr_value &= 0x000ff0ff; | |
1943 | else | |
1944 | ratr_value &= 0x0f0ff0ff; | |
1945 | ||
1946 | break; | |
1947 | } | |
1948 | ratr_value &= 0x0FFFFFFF; | |
1949 | if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) || | |
1950 | (!curtxbw_40mhz && curshortgi_20mhz))) { | |
1951 | ratr_value |= 0x10000000; | |
1952 | tmp_ratr_value = (ratr_value >> 12); | |
1953 | for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { | |
1954 | if ((1 << shortgi_rate) & tmp_ratr_value) | |
1955 | break; | |
1956 | } | |
1957 | shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | | |
1958 | (shortgi_rate << 4) | (shortgi_rate); | |
1959 | } | |
1960 | rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); | |
1961 | RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, | |
1962 | ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0))); | |
1963 | } | |
1964 | ||
1965 | static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, | |
1966 | struct ieee80211_sta *sta, u8 rssi_level) | |
1967 | { | |
1968 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1969 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1970 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1971 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1972 | struct rtl_sta_info *sta_entry = NULL; | |
1973 | u32 ratr_bitmap; | |
1974 | u8 ratr_index; | |
1975 | u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) | |
1976 | ? 1 : 0; | |
1977 | u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? | |
1978 | 1 : 0; | |
1979 | u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? | |
1980 | 1 : 0; | |
1981 | enum wireless_mode wirelessmode = 0; | |
1982 | bool shortgi = false; | |
1983 | u32 value[2]; | |
1984 | u8 macid = 0; | |
1985 | u8 mimo_ps = IEEE80211_SMPS_OFF; | |
1986 | ||
1987 | sta_entry = (struct rtl_sta_info *) sta->drv_priv; | |
1988 | mimo_ps = sta_entry->mimo_ps; | |
1989 | wirelessmode = sta_entry->wireless_mode; | |
1990 | if (mac->opmode == NL80211_IFTYPE_STATION) | |
1991 | curtxbw_40mhz = mac->bw_40; | |
1992 | else if (mac->opmode == NL80211_IFTYPE_AP || | |
1993 | mac->opmode == NL80211_IFTYPE_ADHOC) | |
1994 | macid = sta->aid + 1; | |
1995 | ||
1996 | if (rtlhal->current_bandtype == BAND_ON_5G) | |
1997 | ratr_bitmap = sta->supp_rates[1] << 4; | |
1998 | else | |
1999 | ratr_bitmap = sta->supp_rates[0]; | |
2000 | ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | | |
2001 | sta->ht_cap.mcs.rx_mask[0] << 12); | |
2002 | switch (wirelessmode) { | |
2003 | case WIRELESS_MODE_B: | |
2004 | ratr_index = RATR_INX_WIRELESS_B; | |
2005 | if (ratr_bitmap & 0x0000000c) | |
2006 | ratr_bitmap &= 0x0000000d; | |
2007 | else | |
2008 | ratr_bitmap &= 0x0000000f; | |
2009 | break; | |
2010 | case WIRELESS_MODE_G: | |
2011 | ratr_index = RATR_INX_WIRELESS_GB; | |
2012 | ||
2013 | if (rssi_level == 1) | |
2014 | ratr_bitmap &= 0x00000f00; | |
2015 | else if (rssi_level == 2) | |
2016 | ratr_bitmap &= 0x00000ff0; | |
2017 | else | |
2018 | ratr_bitmap &= 0x00000ff5; | |
2019 | break; | |
2020 | case WIRELESS_MODE_A: | |
2021 | ratr_index = RATR_INX_WIRELESS_G; | |
2022 | ratr_bitmap &= 0x00000ff0; | |
2023 | break; | |
2024 | case WIRELESS_MODE_N_24G: | |
2025 | case WIRELESS_MODE_N_5G: | |
2026 | if (wirelessmode == WIRELESS_MODE_N_24G) | |
2027 | ratr_index = RATR_INX_WIRELESS_NGB; | |
2028 | else | |
2029 | ratr_index = RATR_INX_WIRELESS_NG; | |
2030 | if (mimo_ps == IEEE80211_SMPS_STATIC) { | |
2031 | if (rssi_level == 1) | |
2032 | ratr_bitmap &= 0x00070000; | |
2033 | else if (rssi_level == 2) | |
2034 | ratr_bitmap &= 0x0007f000; | |
2035 | else | |
2036 | ratr_bitmap &= 0x0007f005; | |
2037 | } else { | |
2038 | if (rtlphy->rf_type == RF_1T2R || | |
2039 | rtlphy->rf_type == RF_1T1R) { | |
2040 | if (curtxbw_40mhz) { | |
2041 | if (rssi_level == 1) | |
2042 | ratr_bitmap &= 0x000f0000; | |
2043 | else if (rssi_level == 2) | |
2044 | ratr_bitmap &= 0x000ff000; | |
2045 | else | |
2046 | ratr_bitmap &= 0x000ff015; | |
2047 | } else { | |
2048 | if (rssi_level == 1) | |
2049 | ratr_bitmap &= 0x000f0000; | |
2050 | else if (rssi_level == 2) | |
2051 | ratr_bitmap &= 0x000ff000; | |
2052 | else | |
2053 | ratr_bitmap &= 0x000ff005; | |
2054 | } | |
2055 | } else { | |
2056 | if (curtxbw_40mhz) { | |
2057 | if (rssi_level == 1) | |
2058 | ratr_bitmap &= 0x0f0f0000; | |
2059 | else if (rssi_level == 2) | |
2060 | ratr_bitmap &= 0x0f0ff000; | |
2061 | else | |
2062 | ratr_bitmap &= 0x0f0ff015; | |
2063 | } else { | |
2064 | if (rssi_level == 1) | |
2065 | ratr_bitmap &= 0x0f0f0000; | |
2066 | else if (rssi_level == 2) | |
2067 | ratr_bitmap &= 0x0f0ff000; | |
2068 | else | |
2069 | ratr_bitmap &= 0x0f0ff005; | |
2070 | } | |
2071 | } | |
2072 | } | |
2073 | if ((curtxbw_40mhz && curshortgi_40mhz) || | |
2074 | (!curtxbw_40mhz && curshortgi_20mhz)) { | |
2075 | ||
2076 | if (macid == 0) | |
2077 | shortgi = true; | |
2078 | else if (macid == 1) | |
2079 | shortgi = false; | |
2080 | } | |
2081 | break; | |
2082 | default: | |
2083 | ratr_index = RATR_INX_WIRELESS_NGB; | |
2084 | ||
2085 | if (rtlphy->rf_type == RF_1T2R) | |
2086 | ratr_bitmap &= 0x000ff0ff; | |
2087 | else | |
2088 | ratr_bitmap &= 0x0f0ff0ff; | |
2089 | break; | |
2090 | } | |
2091 | ||
2092 | value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28); | |
2093 | value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80; | |
2094 | RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, | |
2095 | ("ratr_bitmap :%x value0:%x value1:%x\n", | |
2096 | ratr_bitmap, value[0], value[1])); | |
2097 | rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value); | |
2098 | if (macid != 0) | |
2099 | sta_entry->ratr_index = ratr_index; | |
2100 | } | |
2101 | ||
2102 | void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, | |
2103 | struct ieee80211_sta *sta, u8 rssi_level) | |
2104 | { | |
2105 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2106 | ||
2107 | if (rtlpriv->dm.useramask) | |
2108 | rtl92de_update_hal_rate_mask(hw, sta, rssi_level); | |
2109 | else | |
2110 | rtl92de_update_hal_rate_table(hw, sta); | |
2111 | } | |
2112 | ||
2113 | void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw) | |
2114 | { | |
2115 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2116 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
2117 | u16 sifs_timer; | |
2118 | ||
2119 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, | |
2120 | (u8 *)&mac->slot_time); | |
2121 | if (!mac->ht_enable) | |
2122 | sifs_timer = 0x0a0a; | |
2123 | else | |
2124 | sifs_timer = 0x1010; | |
2125 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); | |
2126 | } | |
2127 | ||
2128 | bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) | |
2129 | { | |
2130 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2131 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
2132 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
2133 | enum rf_pwrstate e_rfpowerstate_toset; | |
2134 | u8 u1tmp; | |
2135 | bool actuallyset = false; | |
2136 | unsigned long flag; | |
2137 | ||
2138 | if (rtlpci->being_init_adapter) | |
2139 | return false; | |
2140 | if (ppsc->swrf_processing) | |
2141 | return false; | |
2142 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); | |
2143 | if (ppsc->rfchange_inprogress) { | |
2144 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); | |
2145 | return false; | |
2146 | } else { | |
2147 | ppsc->rfchange_inprogress = true; | |
2148 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); | |
2149 | } | |
2150 | rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, | |
2151 | REG_MAC_PINMUX_CFG) & ~(BIT(3))); | |
2152 | u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); | |
2153 | e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; | |
9928c7d1 | 2154 | if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) { |
3affdf42 CL |
2155 | RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, |
2156 | ("GPIOChangeRF - HW Radio ON, RF ON\n")); | |
2157 | e_rfpowerstate_toset = ERFON; | |
2158 | ppsc->hwradiooff = false; | |
2159 | actuallyset = true; | |
2160 | } else if ((ppsc->hwradiooff == false) | |
2161 | && (e_rfpowerstate_toset == ERFOFF)) { | |
2162 | RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, | |
2163 | ("GPIOChangeRF - HW Radio OFF, RF OFF\n")); | |
2164 | e_rfpowerstate_toset = ERFOFF; | |
2165 | ppsc->hwradiooff = true; | |
2166 | actuallyset = true; | |
2167 | } | |
2168 | if (actuallyset) { | |
2169 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); | |
2170 | ppsc->rfchange_inprogress = false; | |
2171 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); | |
2172 | } else { | |
2173 | if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) | |
2174 | RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); | |
2175 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); | |
2176 | ppsc->rfchange_inprogress = false; | |
2177 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); | |
2178 | } | |
2179 | *valid = 1; | |
2180 | return !ppsc->hwradiooff; | |
2181 | } | |
2182 | ||
2183 | void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, | |
2184 | u8 *p_macaddr, bool is_group, u8 enc_algo, | |
2185 | bool is_wepkey, bool clear_all) | |
2186 | { | |
2187 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2188 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
2189 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
2190 | u8 *macaddr = p_macaddr; | |
2191 | u32 entry_id; | |
2192 | bool is_pairwise = false; | |
2193 | static u8 cam_const_addr[4][6] = { | |
2194 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, | |
2195 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, | |
2196 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, | |
2197 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} | |
2198 | }; | |
2199 | static u8 cam_const_broad[] = { | |
2200 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff | |
2201 | }; | |
2202 | ||
2203 | if (clear_all) { | |
2204 | u8 idx; | |
2205 | u8 cam_offset = 0; | |
2206 | u8 clear_number = 5; | |
2207 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n")); | |
2208 | for (idx = 0; idx < clear_number; idx++) { | |
2209 | rtl_cam_mark_invalid(hw, cam_offset + idx); | |
2210 | rtl_cam_empty_entry(hw, cam_offset + idx); | |
2211 | ||
2212 | if (idx < 5) { | |
2213 | memset(rtlpriv->sec.key_buf[idx], 0, | |
2214 | MAX_KEY_LEN); | |
2215 | rtlpriv->sec.key_len[idx] = 0; | |
2216 | } | |
2217 | } | |
2218 | } else { | |
2219 | switch (enc_algo) { | |
2220 | case WEP40_ENCRYPTION: | |
2221 | enc_algo = CAM_WEP40; | |
2222 | break; | |
2223 | case WEP104_ENCRYPTION: | |
2224 | enc_algo = CAM_WEP104; | |
2225 | break; | |
2226 | case TKIP_ENCRYPTION: | |
2227 | enc_algo = CAM_TKIP; | |
2228 | break; | |
2229 | case AESCCMP_ENCRYPTION: | |
2230 | enc_algo = CAM_AES; | |
2231 | break; | |
2232 | default: | |
2233 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case " | |
2234 | "not process\n")); | |
2235 | enc_algo = CAM_TKIP; | |
2236 | break; | |
2237 | } | |
2238 | if (is_wepkey || rtlpriv->sec.use_defaultkey) { | |
2239 | macaddr = cam_const_addr[key_index]; | |
2240 | entry_id = key_index; | |
2241 | } else { | |
2242 | if (is_group) { | |
2243 | macaddr = cam_const_broad; | |
2244 | entry_id = key_index; | |
2245 | } else { | |
2246 | if (mac->opmode == NL80211_IFTYPE_AP) { | |
2247 | entry_id = rtl_cam_get_free_entry(hw, | |
2248 | p_macaddr); | |
2249 | if (entry_id >= TOTAL_CAM_ENTRY) { | |
2250 | RT_TRACE(rtlpriv, COMP_SEC, | |
2251 | DBG_EMERG, ("Can not " | |
2252 | "find free hw security" | |
2253 | " cam entry\n")); | |
2254 | return; | |
2255 | } | |
2256 | } else { | |
2257 | entry_id = CAM_PAIRWISE_KEY_POSITION; | |
2258 | } | |
2259 | key_index = PAIRWISE_KEYIDX; | |
2260 | is_pairwise = true; | |
2261 | } | |
2262 | } | |
2263 | if (rtlpriv->sec.key_len[key_index] == 0) { | |
2264 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
2265 | ("delete one entry, entry_id is %d\n", | |
2266 | entry_id)); | |
2267 | if (mac->opmode == NL80211_IFTYPE_AP) | |
2268 | rtl_cam_del_entry(hw, p_macaddr); | |
2269 | rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); | |
2270 | } else { | |
2271 | RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, | |
2272 | ("The insert KEY length is %d\n", | |
2273 | rtlpriv->sec.key_len[PAIRWISE_KEYIDX])); | |
2274 | RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, | |
2275 | ("The insert KEY is %x %x\n", | |
2276 | rtlpriv->sec.key_buf[0][0], | |
2277 | rtlpriv->sec.key_buf[0][1])); | |
2278 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
2279 | ("add one entry\n")); | |
2280 | if (is_pairwise) { | |
2281 | RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, | |
2282 | "Pairwiase Key content :", | |
2283 | rtlpriv->sec.pairwise_key, | |
2284 | rtlpriv-> | |
2285 | sec.key_len[PAIRWISE_KEYIDX]); | |
2286 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
2287 | ("set Pairwiase key\n")); | |
2288 | rtl_cam_add_one_entry(hw, macaddr, key_index, | |
2289 | entry_id, enc_algo, | |
2290 | CAM_CONFIG_NO_USEDK, | |
2291 | rtlpriv-> | |
2292 | sec.key_buf[key_index]); | |
2293 | } else { | |
2294 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
2295 | ("set group key\n")); | |
2296 | if (mac->opmode == NL80211_IFTYPE_ADHOC) { | |
2297 | rtl_cam_add_one_entry(hw, | |
2298 | rtlefuse->dev_addr, | |
2299 | PAIRWISE_KEYIDX, | |
2300 | CAM_PAIRWISE_KEY_POSITION, | |
2301 | enc_algo, CAM_CONFIG_NO_USEDK, | |
2302 | rtlpriv->sec.key_buf[entry_id]); | |
2303 | } | |
2304 | rtl_cam_add_one_entry(hw, macaddr, key_index, | |
2305 | entry_id, enc_algo, | |
2306 | CAM_CONFIG_NO_USEDK, | |
2307 | rtlpriv->sec.key_buf | |
2308 | [entry_id]); | |
2309 | } | |
2310 | } | |
2311 | } | |
2312 | } | |
2313 | ||
2314 | void rtl92de_suspend(struct ieee80211_hw *hw) | |
2315 | { | |
2316 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2317 | ||
2318 | rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv, | |
2319 | REG_MAC_PHY_CTRL_NORMAL); | |
2320 | } | |
2321 | ||
2322 | void rtl92de_resume(struct ieee80211_hw *hw) | |
2323 | { | |
2324 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2325 | ||
2326 | rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL, | |
2327 | rtlpriv->rtlhal.macphyctl_reg); | |
2328 | } |