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rtlwifi: Add headers for rtl8187cu
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rtlwifi / wifi.h
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0c817338
LF		 1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_WIFI_H__
31#define __RTL_WIFI_H__
32
33#include <linux/sched.h>
34#include <linux/firmware.h>
35#include <linux/version.h>
36#include <linux/etherdevice.h>
62e63975 37#include <linux/usb.h>
0c817338
LF		 38#include <net/mac80211.h>
39#include "debug.h"
40
41#define RF_CHANGE_BY_INIT 0
42#define RF_CHANGE_BY_IPS BIT(28)
43#define RF_CHANGE_BY_PS BIT(29)
44#define RF_CHANGE_BY_HW BIT(30)
45#define RF_CHANGE_BY_SW BIT(31)
46
47#define IQK_ADDA_REG_NUM 16
48#define IQK_MAC_REG_NUM 4
49
50#define MAX_KEY_LEN 61
51#define KEY_BUF_SIZE 5
52
53/* QoS related. */
54/*aci: 0x00 Best Effort*/
55/*aci: 0x01 Background*/
56/*aci: 0x10 Video*/
57/*aci: 0x11 Voice*/
58/*Max: define total number.*/
59#define AC0_BE 0
60#define AC1_BK 1
61#define AC2_VI 2
62#define AC3_VO 3
63#define AC_MAX 4
64#define QOS_QUEUE_NUM 4
65#define RTL_MAC80211_NUM_QUEUE 5
66
67#define QBSS_LOAD_SIZE 5
68#define MAX_WMMELE_LENGTH 64
69
70/*slot time for 11g. */
71#define RTL_SLOT_TIME_9 9
72#define RTL_SLOT_TIME_20 20
73
74/*related with tcp/ip. */
75/*if_ehther.h*/
76#define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
77#define ETH_P_IP 0x0800 /*Internet Protocol packet */
78#define ETH_P_ARP 0x0806 /*Address Resolution packet */
79#define SNAP_SIZE 6
80#define PROTOC_TYPE_SIZE 2
81
82/*related with 802.11 frame*/
83#define MAC80211_3ADDR_LEN 24
84#define MAC80211_4ADDR_LEN 30
85
86enum intf_type {
87 INTF_PCI = 0,
88 INTF_USB = 1,
89};
90
91enum radio_path {
92 RF90_PATH_A = 0,
93 RF90_PATH_B = 1,
94 RF90_PATH_C = 2,
95 RF90_PATH_D = 3,
96};
97
98enum rt_eeprom_type {
99 EEPROM_93C46,
100 EEPROM_93C56,
101 EEPROM_BOOT_EFUSE,
102};
103
104enum rtl_status {
105 RTL_STATUS_INTERFACE_START = 0,
106};
107
108enum hardware_type {
109 HARDWARE_TYPE_RTL8192E,
110 HARDWARE_TYPE_RTL8192U,
111 HARDWARE_TYPE_RTL8192SE,
112 HARDWARE_TYPE_RTL8192SU,
113 HARDWARE_TYPE_RTL8192CE,
114 HARDWARE_TYPE_RTL8192CU,
115 HARDWARE_TYPE_RTL8192DE,
116 HARDWARE_TYPE_RTL8192DU,
18d30067 117 HARDWARE_TYPE_RTL8723U,
0c817338
LF		 118
119 /*keep it last*/
120 HARDWARE_TYPE_NUM
121};
122
62e63975
LF		 123#define IS_HARDWARE_TYPE_8192CE(rtlhal) \
124 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
18d30067
G		 125#define IS_HARDWARE_TYPE_8192CU(rtlhal) \
126 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
127#define IS_HARDWARE_TYPE_8723U(rtlhal) \
128 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
62e63975 129
0c817338
LF		 130enum scan_operation_backup_opt {
131 SCAN_OPT_BACKUP = 0,
132 SCAN_OPT_RESTORE,
133 SCAN_OPT_MAX
134};
135
136/*RF state.*/
137enum rf_pwrstate {
138 ERFON,
139 ERFSLEEP,
140 ERFOFF
141};
142
143struct bb_reg_def {
144 u32 rfintfs;
145 u32 rfintfi;
146 u32 rfintfo;
147 u32 rfintfe;
148 u32 rf3wire_offset;
149 u32 rflssi_select;
150 u32 rftxgain_stage;
151 u32 rfhssi_para1;
152 u32 rfhssi_para2;
153 u32 rfswitch_control;
154 u32 rfagc_control1;
155 u32 rfagc_control2;
156 u32 rfrxiq_imbalance;
157 u32 rfrx_afe;
158 u32 rftxiq_imbalance;
159 u32 rftx_afe;
160 u32 rflssi_readback;
161 u32 rflssi_readbackpi;
162};
163
164enum io_type {
165 IO_CMD_PAUSE_DM_BY_SCAN = 0,
166 IO_CMD_RESUME_DM_BY_SCAN = 1,
167};
168
169enum hw_variables {
170 HW_VAR_ETHER_ADDR,
171 HW_VAR_MULTICAST_REG,
172 HW_VAR_BASIC_RATE,
173 HW_VAR_BSSID,
174 HW_VAR_MEDIA_STATUS,
175 HW_VAR_SECURITY_CONF,
176 HW_VAR_BEACON_INTERVAL,
177 HW_VAR_ATIM_WINDOW,
178 HW_VAR_LISTEN_INTERVAL,
179 HW_VAR_CS_COUNTER,
180 HW_VAR_DEFAULTKEY0,
181 HW_VAR_DEFAULTKEY1,
182 HW_VAR_DEFAULTKEY2,
183 HW_VAR_DEFAULTKEY3,
184 HW_VAR_SIFS,
185 HW_VAR_DIFS,
186 HW_VAR_EIFS,
187 HW_VAR_SLOT_TIME,
188 HW_VAR_ACK_PREAMBLE,
189 HW_VAR_CW_CONFIG,
190 HW_VAR_CW_VALUES,
191 HW_VAR_RATE_FALLBACK_CONTROL,
192 HW_VAR_CONTENTION_WINDOW,
193 HW_VAR_RETRY_COUNT,
194 HW_VAR_TR_SWITCH,
195 HW_VAR_COMMAND,
196 HW_VAR_WPA_CONFIG,
197 HW_VAR_AMPDU_MIN_SPACE,
198 HW_VAR_SHORTGI_DENSITY,
199 HW_VAR_AMPDU_FACTOR,
200 HW_VAR_MCS_RATE_AVAILABLE,
201 HW_VAR_AC_PARAM,
202 HW_VAR_ACM_CTRL,
203 HW_VAR_DIS_Req_Qsize,
204 HW_VAR_CCX_CHNL_LOAD,
205 HW_VAR_CCX_NOISE_HISTOGRAM,
206 HW_VAR_CCX_CLM_NHM,
207 HW_VAR_TxOPLimit,
208 HW_VAR_TURBO_MODE,
209 HW_VAR_RF_STATE,
210 HW_VAR_RF_OFF_BY_HW,
211 HW_VAR_BUS_SPEED,
212 HW_VAR_SET_DEV_POWER,
213
214 HW_VAR_RCR,
215 HW_VAR_RATR_0,
216 HW_VAR_RRSR,
217 HW_VAR_CPU_RST,
218 HW_VAR_CECHK_BSSID,
219 HW_VAR_LBK_MODE,
220 HW_VAR_AES_11N_FIX,
221 HW_VAR_USB_RX_AGGR,
222 HW_VAR_USER_CONTROL_TURBO_MODE,
223 HW_VAR_RETRY_LIMIT,
224 HW_VAR_INIT_TX_RATE,
225 HW_VAR_TX_RATE_REG,
226 HW_VAR_EFUSE_USAGE,
227 HW_VAR_EFUSE_BYTES,
228 HW_VAR_AUTOLOAD_STATUS,
229 HW_VAR_RF_2R_DISABLE,
230 HW_VAR_SET_RPWM,
231 HW_VAR_H2C_FW_PWRMODE,
232 HW_VAR_H2C_FW_JOINBSSRPT,
233 HW_VAR_FW_PSMODE_STATUS,
234 HW_VAR_1X1_RECV_COMBINE,
235 HW_VAR_STOP_SEND_BEACON,
236 HW_VAR_TSF_TIMER,
237 HW_VAR_IO_CMD,
238
239 HW_VAR_RF_RECOVERY,
240 HW_VAR_H2C_FW_UPDATE_GTK,
241 HW_VAR_WF_MASK,
242 HW_VAR_WF_CRC,
243 HW_VAR_WF_IS_MAC_ADDR,
244 HW_VAR_H2C_FW_OFFLOAD,
245 HW_VAR_RESET_WFCRC,
246
247 HW_VAR_HANDLE_FW_C2H,
248 HW_VAR_DL_FW_RSVD_PAGE,
249 HW_VAR_AID,
250 HW_VAR_HW_SEQ_ENABLE,
251 HW_VAR_CORRECT_TSF,
252 HW_VAR_BCN_VALID,
253 HW_VAR_FWLPS_RF_ON,
254 HW_VAR_DUAL_TSF_RST,
255 HW_VAR_SWITCH_EPHY_WoWLAN,
256 HW_VAR_INT_MIGRATION,
257 HW_VAR_INT_AC,
258 HW_VAR_RF_TIMING,
259
260 HW_VAR_MRC,
261
262 HW_VAR_MGT_FILTER,
263 HW_VAR_CTRL_FILTER,
264 HW_VAR_DATA_FILTER,
265};
266
267enum _RT_MEDIA_STATUS {
268 RT_MEDIA_DISCONNECT = 0,
269 RT_MEDIA_CONNECT = 1
270};
271
272enum rt_oem_id {
273 RT_CID_DEFAULT = 0,
274 RT_CID_8187_ALPHA0 = 1,
275 RT_CID_8187_SERCOMM_PS = 2,
276 RT_CID_8187_HW_LED = 3,
277 RT_CID_8187_NETGEAR = 4,
278 RT_CID_WHQL = 5,
279 RT_CID_819x_CAMEO = 6,
280 RT_CID_819x_RUNTOP = 7,
281 RT_CID_819x_Senao = 8,
282 RT_CID_TOSHIBA = 9,
283 RT_CID_819x_Netcore = 10,
284 RT_CID_Nettronix = 11,
285 RT_CID_DLINK = 12,
286 RT_CID_PRONET = 13,
287 RT_CID_COREGA = 14,
288 RT_CID_819x_ALPHA = 15,
289 RT_CID_819x_Sitecom = 16,
290 RT_CID_CCX = 17,
291 RT_CID_819x_Lenovo = 18,
292 RT_CID_819x_QMI = 19,
293 RT_CID_819x_Edimax_Belkin = 20,
294 RT_CID_819x_Sercomm_Belkin = 21,
295 RT_CID_819x_CAMEO1 = 22,
296 RT_CID_819x_MSI = 23,
297 RT_CID_819x_Acer = 24,
298 RT_CID_819x_HP = 27,
299 RT_CID_819x_CLEVO = 28,
300 RT_CID_819x_Arcadyan_Belkin = 29,
301 RT_CID_819x_SAMSUNG = 30,
302 RT_CID_819x_WNC_COREGA = 31,
303 RT_CID_819x_Foxcoon = 32,
304 RT_CID_819x_DELL = 33,
305};
306
307enum hw_descs {
308 HW_DESC_OWN,
309 HW_DESC_RXOWN,
310 HW_DESC_TX_NEXTDESC_ADDR,
311 HW_DESC_TXBUFF_ADDR,
312 HW_DESC_RXBUFF_ADDR,
313 HW_DESC_RXPKT_LEN,
314 HW_DESC_RXERO,
315};
316
317enum prime_sc {
318 PRIME_CHNL_OFFSET_DONT_CARE = 0,
319 PRIME_CHNL_OFFSET_LOWER = 1,
320 PRIME_CHNL_OFFSET_UPPER = 2,
321};
322
323enum rf_type {
324 RF_1T1R = 0,
325 RF_1T2R = 1,
326 RF_2T2R = 2,
327};
328
329enum ht_channel_width {
330 HT_CHANNEL_WIDTH_20 = 0,
331 HT_CHANNEL_WIDTH_20_40 = 1,
332};
333
334/* Ref: 802.11i sepc D10.0 7.3.2.25.1
335Cipher Suites Encryption Algorithms */
336enum rt_enc_alg {
337 NO_ENCRYPTION = 0,
338 WEP40_ENCRYPTION = 1,
339 TKIP_ENCRYPTION = 2,
340 RSERVED_ENCRYPTION = 3,
341 AESCCMP_ENCRYPTION = 4,
342 WEP104_ENCRYPTION = 5,
343};
344
345enum rtl_hal_state {
346 _HAL_STATE_STOP = 0,
347 _HAL_STATE_START = 1,
348};
349
350enum rtl_var_map {
351 /*reg map */
352 SYS_ISO_CTRL = 0,
353 SYS_FUNC_EN,
354 SYS_CLK,
355 MAC_RCR_AM,
356 MAC_RCR_AB,
357 MAC_RCR_ACRC32,
358 MAC_RCR_ACF,
359 MAC_RCR_AAP,
360
361 /*efuse map */
362 EFUSE_TEST,
363 EFUSE_CTRL,
364 EFUSE_CLK,
365 EFUSE_CLK_CTRL,
366 EFUSE_PWC_EV12V,
367 EFUSE_FEN_ELDR,
368 EFUSE_LOADER_CLK_EN,
369 EFUSE_ANA8M,
370 EFUSE_HWSET_MAX_SIZE,
18d30067
G		 371 EFUSE_MAX_SECTION_MAP,
372 EFUSE_REAL_CONTENT_SIZE,
0c817338
LF		 373
374 /*CAM map */
375 RWCAM,
376 WCAMI,
377 RCAMO,
378 CAMDBG,
379 SECR,
380 SEC_CAM_NONE,
381 SEC_CAM_WEP40,
382 SEC_CAM_TKIP,
383 SEC_CAM_AES,
384 SEC_CAM_WEP104,
385
386 /*IMR map */
387 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
388 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
389 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
390 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
391 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
392 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
393 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
394 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
395 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
396 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
397 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
398 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
399 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
400 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
401 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
402 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
403 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
404 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
405 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
406 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
407 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
408 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
409 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
410 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
411 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
412 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
413 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
414 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
415 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
416 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
417 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
418 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
419 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt|RTL_IMR_TBDOK|RTL_IMR_TBDER)*/
420
421 /*CCK Rates, TxHT = 0 */
422 RTL_RC_CCK_RATE1M,
423 RTL_RC_CCK_RATE2M,
424 RTL_RC_CCK_RATE5_5M,
425 RTL_RC_CCK_RATE11M,
426
427 /*OFDM Rates, TxHT = 0 */
428 RTL_RC_OFDM_RATE6M,
429 RTL_RC_OFDM_RATE9M,
430 RTL_RC_OFDM_RATE12M,
431 RTL_RC_OFDM_RATE18M,
432 RTL_RC_OFDM_RATE24M,
433 RTL_RC_OFDM_RATE36M,
434 RTL_RC_OFDM_RATE48M,
435 RTL_RC_OFDM_RATE54M,
436
437 RTL_RC_HT_RATEMCS7,
438 RTL_RC_HT_RATEMCS15,
439
440 /*keep it last */
441 RTL_VAR_MAP_MAX,
442};
443
444/*Firmware PS mode for control LPS.*/
445enum _fw_ps_mode {
446 FW_PS_ACTIVE_MODE = 0,
447 FW_PS_MIN_MODE = 1,
448 FW_PS_MAX_MODE = 2,
449 FW_PS_DTIM_MODE = 3,
450 FW_PS_VOIP_MODE = 4,
451 FW_PS_UAPSD_WMM_MODE = 5,
452 FW_PS_UAPSD_MODE = 6,
453 FW_PS_IBSS_MODE = 7,
454 FW_PS_WWLAN_MODE = 8,
455 FW_PS_PM_Radio_Off = 9,
456 FW_PS_PM_Card_Disable = 10,
457};
458
459enum rt_psmode {
460 EACTIVE, /*Active/Continuous access. */
461 EMAXPS, /*Max power save mode. */
462 EFASTPS, /*Fast power save mode. */
463 EAUTOPS, /*Auto power save mode. */
464};
465
466/*LED related.*/
467enum led_ctl_mode {
468 LED_CTL_POWER_ON = 1,
469 LED_CTL_LINK = 2,
470 LED_CTL_NO_LINK = 3,
471 LED_CTL_TX = 4,
472 LED_CTL_RX = 5,
473 LED_CTL_SITE_SURVEY = 6,
474 LED_CTL_POWER_OFF = 7,
475 LED_CTL_START_TO_LINK = 8,
476 LED_CTL_START_WPS = 9,
477 LED_CTL_STOP_WPS = 10,
478};
479
480enum rtl_led_pin {
481 LED_PIN_GPIO0,
482 LED_PIN_LED0,
483 LED_PIN_LED1,
484 LED_PIN_LED2
485};
486
487/*QoS related.*/
488/*acm implementation method.*/
489enum acm_method {
490 eAcmWay0_SwAndHw = 0,
491 eAcmWay1_HW = 1,
492 eAcmWay2_SW = 2,
493};
494
495/*aci/aifsn Field.
496Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
497union aci_aifsn {
498 u8 char_data;
499
500 struct {
501 u8 aifsn:4;
502 u8 acm:1;
503 u8 aci:2;
504 u8 reserved:1;
505 } f; /* Field */
506};
507
508/*mlme related.*/
509enum wireless_mode {
510 WIRELESS_MODE_UNKNOWN = 0x00,
511 WIRELESS_MODE_A = 0x01,
512 WIRELESS_MODE_B = 0x02,
513 WIRELESS_MODE_G = 0x04,
514 WIRELESS_MODE_AUTO = 0x08,
515 WIRELESS_MODE_N_24G = 0x10,
516 WIRELESS_MODE_N_5G = 0x20
517};
518
18d30067
G		 519#define IS_WIRELESS_MODE_A(wirelessmode) \
520 (wirelessmode == WIRELESS_MODE_A)
521#define IS_WIRELESS_MODE_B(wirelessmode) \
522 (wirelessmode == WIRELESS_MODE_B)
523#define IS_WIRELESS_MODE_G(wirelessmode) \
524 (wirelessmode == WIRELESS_MODE_G)
525#define IS_WIRELESS_MODE_N_24G(wirelessmode) \
526 (wirelessmode == WIRELESS_MODE_N_24G)
527#define IS_WIRELESS_MODE_N_5G(wirelessmode) \
528 (wirelessmode == WIRELESS_MODE_N_5G)
529
0c817338
LF		 530enum ratr_table_mode {
531 RATR_INX_WIRELESS_NGB = 0,
532 RATR_INX_WIRELESS_NG = 1,
533 RATR_INX_WIRELESS_NB = 2,
534 RATR_INX_WIRELESS_N = 3,
535 RATR_INX_WIRELESS_GB = 4,
536 RATR_INX_WIRELESS_G = 5,
537 RATR_INX_WIRELESS_B = 6,
538 RATR_INX_WIRELESS_MC = 7,
539 RATR_INX_WIRELESS_A = 8,
540};
541
542enum rtl_link_state {
543 MAC80211_NOLINK = 0,
544 MAC80211_LINKING = 1,
545 MAC80211_LINKED = 2,
546 MAC80211_LINKED_SCANNING = 3,
547};
548
549enum act_category {
550 ACT_CAT_QOS = 1,
551 ACT_CAT_DLS = 2,
552 ACT_CAT_BA = 3,
553 ACT_CAT_HT = 7,
554 ACT_CAT_WMM = 17,
555};
556
557enum ba_action {
558 ACT_ADDBAREQ = 0,
559 ACT_ADDBARSP = 1,
560 ACT_DELBA = 2,
561};
562
563struct octet_string {
564 u8 *octet;
565 u16 length;
566};
567
568struct rtl_hdr_3addr {
569 __le16 frame_ctl;
570 __le16 duration_id;
571 u8 addr1[ETH_ALEN];
572 u8 addr2[ETH_ALEN];
573 u8 addr3[ETH_ALEN];
574 __le16 seq_ctl;
575 u8 payload[0];
e137478b 576} __packed;
0c817338
LF		 577
578struct rtl_info_element {
579 u8 id;
580 u8 len;
581 u8 data[0];
e137478b 582} __packed;
0c817338
LF		 583
584struct rtl_probe_rsp {
585 struct rtl_hdr_3addr header;
586 u32 time_stamp[2];
587 __le16 beacon_interval;
588 __le16 capability;
589 /*SSID, supported rates, FH params, DS params,
590 CF params, IBSS params, TIM (if beacon), RSN */
591 struct rtl_info_element info_element[0];
e137478b 592} __packed;
0c817338
LF		 593
594/*LED related.*/
595/*ledpin Identify how to implement this SW led.*/
596struct rtl_led {
597 void *hw;
598 enum rtl_led_pin ledpin;
7ea47240 599 bool ledon;
0c817338
LF		 600};
601
602struct rtl_led_ctl {
7ea47240 603 bool led_opendrain;
0c817338
LF		 604 struct rtl_led sw_led0;
605 struct rtl_led sw_led1;
606};
607
608struct rtl_qos_parameters {
609 __le16 cw_min;
610 __le16 cw_max;
611 u8 aifs;
612 u8 flag;
613 __le16 tx_op;
e137478b 614} __packed;
0c817338
LF		 615
616struct rt_smooth_data {
617 u32 elements[100]; /*array to store values */
618 u32 index; /*index to current array to store */
619 u32 total_num; /*num of valid elements */
620 u32 total_val; /*sum of valid elements */
621};
622
623struct false_alarm_statistics {
624 u32 cnt_parity_fail;
625 u32 cnt_rate_illegal;
626 u32 cnt_crc8_fail;
627 u32 cnt_mcs_fail;
628 u32 cnt_ofdm_fail;
629 u32 cnt_cck_fail;
630 u32 cnt_all;
631};
632
633struct init_gain {
634 u8 xaagccore1;
635 u8 xbagccore1;
636 u8 xcagccore1;
637 u8 xdagccore1;
638 u8 cca;
639
640};
641
642struct wireless_stats {
643 unsigned long txbytesunicast;
644 unsigned long txbytesmulticast;
645 unsigned long txbytesbroadcast;
646 unsigned long rxbytesunicast;
647
648 long rx_snr_db[4];
649 /*Correct smoothed ss in Dbm, only used
650 in driver to report real power now. */
651 long recv_signal_power;
652 long signal_quality;
653 long last_sigstrength_inpercent;
654
655 u32 rssi_calculate_cnt;
656
657 /*Transformed, in dbm. Beautified signal
658 strength for UI, not correct. */
659 long signal_strength;
660
661 u8 rx_rssi_percentage[4];
662 u8 rx_evm_percentage[2];
663
664 struct rt_smooth_data ui_rssi;
665 struct rt_smooth_data ui_link_quality;
666};
667
668struct rate_adaptive {
669 u8 rate_adaptive_disabled;
670 u8 ratr_state;
671 u16 reserve;
672
673 u32 high_rssi_thresh_for_ra;
674 u32 high2low_rssi_thresh_for_ra;
675 u8 low2high_rssi_thresh_for_ra40m;
676 u32 low_rssi_thresh_for_ra40M;
677 u8 low2high_rssi_thresh_for_ra20m;
678 u32 low_rssi_thresh_for_ra20M;
679 u32 upper_rssi_threshold_ratr;
680 u32 middleupper_rssi_threshold_ratr;
681 u32 middle_rssi_threshold_ratr;
682 u32 middlelow_rssi_threshold_ratr;
683 u32 low_rssi_threshold_ratr;
684 u32 ultralow_rssi_threshold_ratr;
685 u32 low_rssi_threshold_ratr_40m;
686 u32 low_rssi_threshold_ratr_20m;
687 u8 ping_rssi_enable;
688 u32 ping_rssi_ratr;
689 u32 ping_rssi_thresh_for_ra;
690 u32 last_ratr;
691 u8 pre_ratr_state;
692};
693
694struct regd_pair_mapping {
695 u16 reg_dmnenum;
696 u16 reg_5ghz_ctl;
697 u16 reg_2ghz_ctl;
698};
699
700struct rtl_regulatory {
701 char alpha2[2];
702 u16 country_code;
703 u16 max_power_level;
704 u32 tp_scale;
705 u16 current_rd;
706 u16 current_rd_ext;
707 int16_t power_limit;
708 struct regd_pair_mapping *regpair;
709};
710
711struct rtl_rfkill {
712 bool rfkill_state; /*0 is off, 1 is on */
713};
714
18d30067
G		 715struct phy_parameters {
716 u16 length;
717 u32 *pdata;
718};
719
720enum hw_param_tab_index {
721 PHY_REG_2T,
722 PHY_REG_1T,
723 PHY_REG_PG,
724 RADIOA_2T,
725 RADIOB_2T,
726 RADIOA_1T,
727 RADIOB_1T,
728 MAC_REG,
729 AGCTAB_2T,
730 AGCTAB_1T,
731 MAX_TAB
732};
733
0c817338
LF		 734struct rtl_phy {
735 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
736 struct init_gain initgain_backup;
737 enum io_type current_io_type;
738
739 u8 rf_mode;
740 u8 rf_type;
741 u8 current_chan_bw;
742 u8 set_bwmode_inprogress;
743 u8 sw_chnl_inprogress;
744 u8 sw_chnl_stage;
745 u8 sw_chnl_step;
746 u8 current_channel;
747 u8 h2c_box_num;
748 u8 set_io_inprogress;
749
750 /*record for power tracking*/
751 s32 reg_e94;
752 s32 reg_e9c;
753 s32 reg_ea4;
754 s32 reg_eac;
755 s32 reg_eb4;
756 s32 reg_ebc;
757 s32 reg_ec4;
758 s32 reg_ecc;
759 u8 rfpienable;
760 u8 reserve_0;
761 u16 reserve_1;
762 u32 reg_c04, reg_c08, reg_874;
763 u32 adda_backup[16];
764 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
765 u32 iqk_bb_backup[10];
766
7ea47240 767 bool rfpi_enable;
0c817338
LF		 768
769 u8 pwrgroup_cnt;
7ea47240 770 u8 cck_high_power;
0c817338
LF		 771 /* 3 groups of pwr diff by rates*/
772 u32 mcs_txpwrlevel_origoffset[4][16];
773 u8 default_initialgain[4];
774
775 /*the current Tx power level*/
776 u8 cur_cck_txpwridx;
777 u8 cur_ofdm24g_txpwridx;
778
779 u32 rfreg_chnlval[2];
7ea47240 780 bool apk_done;
0c817338
LF		 781
782 /*fsync*/
783 u8 framesync;
784 u32 framesync_c34;
785
786 u8 num_total_rfpath;
18d30067 787 struct phy_parameters hwparam_tables[MAX_TAB];
0c817338
LF		 788};
789
790#define MAX_TID_COUNT 9
791#define RTL_AGG_OFF 0
792#define RTL_AGG_ON 1
793#define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
794#define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
795
796struct rtl_ht_agg {
797 u16 txq_id;
798 u16 wait_for_ba;
799 u16 start_idx;
800 u64 bitmap;
801 u32 rate_n_flags;
802 u8 agg_state;
803};
804
805struct rtl_tid_data {
806 u16 seq_number;
807 struct rtl_ht_agg agg;
808};
809
810struct rtl_priv;
811struct rtl_io {
812 struct device *dev;
62e63975 813 struct mutex bb_mutex;
0c817338
LF		 814
815 /*PCI MEM map */
816 unsigned long pci_mem_end; /*shared mem end */
817 unsigned long pci_mem_start; /*shared mem start */
818
819 /*PCI IO map */
820 unsigned long pci_base_addr; /*device I/O address */
821
822 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
823 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
824 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
62e63975
LF		 825 int (*writeN_async) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
826 u8 *pdata);
0c817338
LF		 827
828 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
829 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
830 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
62e63975
LF		 831 int (*readN_sync) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
832 u8 *pdata);
0c817338
LF		 833
834};
835
836struct rtl_mac {
837 u8 mac_addr[ETH_ALEN];
838 u8 mac80211_registered;
839 u8 beacon_enabled;
840
841 u32 tx_ss_num;
842 u32 rx_ss_num;
843
844 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
845 struct ieee80211_hw *hw;
846 struct ieee80211_vif *vif;
847 enum nl80211_iftype opmode;
848
849 /*Probe Beacon management */
850 struct rtl_tid_data tids[MAX_TID_COUNT];
851 enum rtl_link_state link_state;
852
853 int n_channels;
854 int n_bitrates;
855
856 /*filters */
857 u32 rx_conf;
858 u16 rx_mgt_filter;
859 u16 rx_ctrl_filter;
860 u16 rx_data_filter;
861
862 bool act_scanning;
863 u8 cnt_after_linked;
864
865 /*RDG*/ bool rdg_en;
866
867 /*AP*/ u8 bssid[6];
868 u8 mcs[16]; /*16 bytes mcs for HT rates.*/
869 u32 basic_rates; /*b/g rates*/
870 u8 ht_enable;
871 u8 sgi_40;
872 u8 sgi_20;
873 u8 bw_40;
874 u8 mode; /*wireless mode*/
875 u8 slot_time;
876 u8 short_preamble;
877 u8 use_cts_protect;
878 u8 cur_40_prime_sc;
879 u8 cur_40_prime_sc_bk;
880 u64 tsf;
881 u8 retry_short;
882 u8 retry_long;
883 u16 assoc_id;
884
885 /*IBSS*/ int beacon_interval;
886
887 /*AMPDU*/ u8 min_space_cfg; /*For Min spacing configurations */
888 u8 max_mss_density;
889 u8 current_ampdu_factor;
890 u8 current_ampdu_density;
891
892 /*QOS & EDCA */
893 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
894 struct rtl_qos_parameters ac[AC_MAX];
895};
896
897struct rtl_hal {
898 struct ieee80211_hw *hw;
899
900 enum intf_type interface;
901 u16 hw_type; /*92c or 92d or 92s and so on */
902 u8 oem_id;
18d30067 903 u32 version; /*version of chip */
0c817338
LF		 904 u8 state; /*stop 0, start 1 */
905
906 /*firmware */
907 u8 *pfirmware;
18d30067
G		 908 u16 fw_version;
909 u16 fw_subversion;
7ea47240 910 bool h2c_setinprogress;
0c817338 911 u8 last_hmeboxnum;
7ea47240 912 bool fw_ready;
0c817338
LF		 913 /*Reserve page start offset except beacon in TxQ. */
914 u8 fw_rsvdpage_startoffset;
915};
916
917struct rtl_security {
918 /*default 0 */
919 bool use_sw_sec;
920
921 bool being_setkey;
922 bool use_defaultkey;
923 /*Encryption Algorithm for Unicast Packet */
924 enum rt_enc_alg pairwise_enc_algorithm;
925 /*Encryption Algorithm for Brocast/Multicast */
926 enum rt_enc_alg group_enc_algorithm;
927
928 /*local Key buffer, indx 0 is for
929 pairwise key 1-4 is for agoup key. */
930 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
931 u8 key_len[KEY_BUF_SIZE];
932
933 /*The pointer of Pairwise Key,
934 it always points to KeyBuf[4] */
935 u8 *pairwise_key;
936};
937
938struct rtl_dm {
8c96fcf7 939 /*PHY status for DM (dynamic management) */
0c817338
LF		 940 long entry_min_undecoratedsmoothed_pwdb;
941 long undecorated_smoothed_pwdb; /*out dm */
942 long entry_max_undecoratedsmoothed_pwdb;
7ea47240
LF		 943 bool dm_initialgain_enable;
944 bool dynamic_txpower_enable;
945 bool current_turbo_edca;
946 bool is_any_nonbepkts; /*out dm */
947 bool is_cur_rdlstate;
948 bool txpower_trackingInit;
949 bool disable_framebursting;
950 bool cck_inch14;
951 bool txpower_tracking;
952 bool useramask;
953 bool rfpath_rxenable[4];
0c817338
LF		 954
955 u8 thermalvalue_iqk;
956 u8 thermalvalue_lck;
957 u8 thermalvalue;
958 u8 last_dtp_lvl;
959 u8 dynamic_txhighpower_lvl; /*Tx high power level */
960 u8 dm_flag; /*Indicate if each dynamic mechanism's status. */
961 u8 dm_type;
962 u8 txpower_track_control;
963
964 char ofdm_index[2];
965 char cck_index;
966};
967
18d30067 968#define EFUSE_MAX_LOGICAL_SIZE 256
0c817338
LF		 969
970struct rtl_efuse {
18d30067 971 bool autoload_ok;
0c817338
LF		 972 bool bootfromefuse;
973 u16 max_physical_size;
974 u8 contents[EFUSE_MAX_LOGICAL_SIZE];
975
976 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
977 u16 efuse_usedbytes;
978 u8 efuse_usedpercentage;
979
980 u8 autoload_failflag;
981
982 short epromtype;
983 u16 eeprom_vid;
984 u16 eeprom_did;
985 u16 eeprom_svid;
986 u16 eeprom_smid;
987 u8 eeprom_oemid;
988 u16 eeprom_channelplan;
989 u8 eeprom_version;
18d30067
G		 990 u8 board_type;
991 u8 external_pa;
0c817338
LF		 992
993 u8 dev_addr[6];
994
7ea47240 995 bool txpwr_fromeprom;
0c817338
LF		 996 u8 eeprom_tssi[2];
997 u8 eeprom_pwrlimit_ht20[3];
998 u8 eeprom_pwrlimit_ht40[3];
999 u8 eeprom_chnlarea_txpwr_cck[2][3];
1000 u8 eeprom_chnlarea_txpwr_ht40_1s[2][3];
1001 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][3];
1002 u8 txpwrlevel_cck[2][14];
1003 u8 txpwrlevel_ht40_1s[2][14]; /*For HT 40MHZ pwr */
1004 u8 txpwrlevel_ht40_2s[2][14]; /*For HT 40MHZ pwr */
1005
1006 /*For power group */
1007 u8 pwrgroup_ht20[2][14];
1008 u8 pwrgroup_ht40[2][14];
1009
1010 char txpwr_ht20diff[2][14]; /*HT 20<->40 Pwr diff */
1011 u8 txpwr_legacyhtdiff[2][14]; /*For HT<->legacy pwr diff */
1012
1013 u8 eeprom_regulatory;
1014 u8 eeprom_thermalmeter;
1015 /*ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
1016 u8 thermalmeter[2];
1017
1018 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
7ea47240 1019 bool apk_thermalmeterignore;
0c817338
LF		 1020};
1021
1022struct rtl_ps_ctl {
1023 bool set_rfpowerstate_inprogress;
7ea47240 1024 bool in_powersavemode;
0c817338 1025 bool rfchange_inprogress;
7ea47240
LF		 1026 bool swrf_processing;
1027 bool hwradiooff;
0c817338
LF		 1028
1029 u32 last_sleep_jiffies;
1030 u32 last_awake_jiffies;
1031 u32 last_delaylps_stamp_jiffies;
1032
1033 /*
1034 * just for PCIE ASPM
1035 * If it supports ASPM, Offset[560h] = 0x40,
1036 * otherwise Offset[560h] = 0x00.
1037 * */
7ea47240
LF		 1038 bool support_aspm;
1039 bool support_backdoor;
0c817338
LF		 1040
1041 /*for LPS */
1042 enum rt_psmode dot11_psmode; /*Power save mode configured. */
7ea47240
LF		 1043 bool leisure_ps;
1044 bool fwctrl_lps;
0c817338
LF		 1045 u8 fwctrl_psmode;
1046 /*For Fw control LPS mode */
7ea47240 1047 u8 reg_fwctrl_lps;
0c817338 1048 /*Record Fw PS mode status. */
7ea47240 1049 bool fw_current_inpsmode;
0c817338
LF		 1050 u8 reg_max_lps_awakeintvl;
1051 bool report_linked;
1052
1053 /*for IPS */
7ea47240 1054 bool inactiveps;
0c817338
LF		 1055
1056 u32 rfoff_reason;
1057
1058 /*RF OFF Level */
1059 u32 cur_ps_level;
1060 u32 reg_rfps_level;
1061
1062 /*just for PCIE ASPM */
1063 u8 const_amdpci_aspm;
1064
18d30067 1065 bool pwrdown_mode;
0c817338
LF		 1066 enum rf_pwrstate inactive_pwrstate;
1067 enum rf_pwrstate rfpwr_state; /*cur power state */
1068};
1069
1070struct rtl_stats {
1071 u32 mac_time[2];
1072 s8 rssi;
1073 u8 signal;
1074 u8 noise;
1075 u16 rate; /*in 100 kbps */
1076 u8 received_channel;
1077 u8 control;
1078 u8 mask;
1079 u8 freq;
1080 u16 len;
1081 u64 tsf;
1082 u32 beacon_time;
1083 u8 nic_type;
1084 u16 length;
1085 u8 signalquality; /*in 0-100 index. */
1086 /*
1087 * Real power in dBm for this packet,
1088 * no beautification and aggregation.
1089 * */
1090 s32 recvsignalpower;
1091 s8 rxpower; /*in dBm Translate from PWdB */
1092 u8 signalstrength; /*in 0-100 index. */
7ea47240
LF		 1093 u16 hwerror:1;
1094 u16 crc:1;
1095 u16 icv:1;
1096 u16 shortpreamble:1;
0c817338
LF		 1097 u16 antenna:1;
1098 u16 decrypted:1;
1099 u16 wakeup:1;
1100 u32 timestamp_low;
1101 u32 timestamp_high;
1102
1103 u8 rx_drvinfo_size;
1104 u8 rx_bufshift;
7ea47240 1105 bool isampdu;
0c817338
LF		 1106 bool rx_is40Mhzpacket;
1107 u32 rx_pwdb_all;
1108 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1109 s8 rx_mimo_signalquality[2];
7ea47240
LF		 1110 bool packet_matchbssid;
1111 bool is_cck;
1112 bool packet_toself;
1113 bool packet_beacon; /*for rssi */
0c817338
LF		 1114 char cck_adc_pwdb[4]; /*for rx path selection */
1115};
1116
1117struct rt_link_detect {
1118 u32 num_tx_in4period[4];
1119 u32 num_rx_in4period[4];
1120
1121 u32 num_tx_inperiod;
1122 u32 num_rx_inperiod;
1123
7ea47240
LF		 1124 bool busytraffic;
1125 bool higher_busytraffic;
1126 bool higher_busyrxtraffic;
0c817338
LF		 1127};
1128
1129struct rtl_tcb_desc {
7ea47240
LF		 1130 u8 packet_bw:1;
1131 u8 multicast:1;
1132 u8 broadcast:1;
1133
1134 u8 rts_stbc:1;
1135 u8 rts_enable:1;
1136 u8 cts_enable:1;
1137 u8 rts_use_shortpreamble:1;
1138 u8 rts_use_shortgi:1;
0c817338 1139 u8 rts_sc:1;
7ea47240 1140 u8 rts_bw:1;
0c817338
LF		 1141 u8 rts_rate;
1142
1143 u8 use_shortgi:1;
1144 u8 use_shortpreamble:1;
1145 u8 use_driver_rate:1;
1146 u8 disable_ratefallback:1;
1147
1148 u8 ratr_index;
1149 u8 mac_id;
1150 u8 hw_rate;
1151};
1152
1153struct rtl_hal_ops {
1154 int (*init_sw_vars) (struct ieee80211_hw *hw);
1155 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
62e63975 1156 void (*read_chip_version)(struct ieee80211_hw *hw);
0c817338
LF		 1157 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1158 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1159 u32 *p_inta, u32 *p_intb);
1160 int (*hw_init) (struct ieee80211_hw *hw);
1161 void (*hw_disable) (struct ieee80211_hw *hw);
1162 void (*enable_interrupt) (struct ieee80211_hw *hw);
1163 void (*disable_interrupt) (struct ieee80211_hw *hw);
1164 int (*set_network_type) (struct ieee80211_hw *hw,
1165 enum nl80211_iftype type);
18d30067
G		 1166 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1167 bool check_bssid);
0c817338
LF		 1168 void (*set_bw_mode) (struct ieee80211_hw *hw,
1169 enum nl80211_channel_type ch_type);
18d30067 1170 u8 (*switch_channel) (struct ieee80211_hw *hw);
0c817338
LF		 1171 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1172 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1173 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1174 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1175 u32 add_msr, u32 rm_msr);
1176 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1177 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1178 void (*update_rate_table) (struct ieee80211_hw *hw);
1179 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1180 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1181 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1182 struct ieee80211_tx_info *info,
1183 struct sk_buff *skb, unsigned int queue_index);
18d30067
G		 1184 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 * pDesc,
1185 u32 buffer_len, bool bIsPsPoll);
0c817338 1186 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
7ea47240 1187 bool firstseg, bool lastseg,
0c817338 1188 struct sk_buff *skb);
62e63975 1189 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
7ea47240 1190 bool (*query_rx_desc) (struct ieee80211_hw *hw,
0c817338
LF		 1191 struct rtl_stats *stats,
1192 struct ieee80211_rx_status *rx_status,
1193 u8 *pdesc, struct sk_buff *skb);
1194 void (*set_channel_access) (struct ieee80211_hw *hw);
7ea47240 1195 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
0c817338
LF		 1196 void (*dm_watchdog) (struct ieee80211_hw *hw);
1197 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
7ea47240 1198 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
0c817338
LF		 1199 enum rf_pwrstate rfpwr_state);
1200 void (*led_control) (struct ieee80211_hw *hw,
1201 enum led_ctl_mode ledaction);
1202 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
7ea47240 1203 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
0c817338
LF		 1204 void (*tx_polling) (struct ieee80211_hw *hw, unsigned int hw_queue);
1205 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1206 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1207 u8 *p_macaddr, bool is_group, u8 enc_algo,
1208 bool is_wepkey, bool clear_all);
1209 void (*init_sw_leds) (struct ieee80211_hw *hw);
1210 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
7ea47240 1211 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
0c817338
LF		 1212 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1213 u32 data);
7ea47240 1214 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
0c817338
LF		 1215 u32 regaddr, u32 bitmask);
1216 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1217 u32 regaddr, u32 bitmask, u32 data);
1218};
1219
1220struct rtl_intf_ops {
1221 /*com */
1222 int (*adapter_start) (struct ieee80211_hw *hw);
1223 void (*adapter_stop) (struct ieee80211_hw *hw);
1224
1225 int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb);
1226 int (*reset_trx_ring) (struct ieee80211_hw *hw);
62e63975 1227 bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
0c817338
LF		 1228
1229 /*pci */
1230 void (*disable_aspm) (struct ieee80211_hw *hw);
1231 void (*enable_aspm) (struct ieee80211_hw *hw);
1232
1233 /*usb */
1234};
1235
1236struct rtl_mod_params {
1237 /* default: 0 = using hardware encryption */
1238 int sw_crypto;
1239};
1240
62e63975
LF		 1241struct rtl_hal_usbint_cfg {
1242 /* data - rx */
1243 u32 in_ep_num;
1244 u32 rx_urb_num;
1245 u32 rx_max_size;
1246
1247 /* op - rx */
1248 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1249 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1250 struct sk_buff_head *);
1251
1252 /* tx */
1253 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1254 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1255 struct sk_buff *);
1256 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1257 struct sk_buff_head *);
1258
1259 /* endpoint mapping */
1260 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1261 u16 (*usb_mq_to_hwq)(u16 fc, u16 mac80211_queue_index);
1262};
1263
0c817338
LF		 1264struct rtl_hal_cfg {
1265 char *name;
1266 char *fw_name;
1267 struct rtl_hal_ops *ops;
1268 struct rtl_mod_params *mod_params;
62e63975 1269 struct rtl_hal_usbint_cfg *usb_interface_cfg;
0c817338
LF		 1270
1271 /*this map used for some registers or vars
1272 defined int HAL but used in MAIN */
1273 u32 maps[RTL_VAR_MAP_MAX];
1274
1275};
1276
1277struct rtl_locks {
d704300f 1278 /* mutex */
8a09d6d8 1279 struct mutex conf_mutex;
0c817338
LF		 1280
1281 /*spin lock */
d704300f 1282 spinlock_t ips_lock;
0c817338
LF		 1283 spinlock_t irq_th_lock;
1284 spinlock_t h2c_lock;
1285 spinlock_t rf_ps_lock;
1286 spinlock_t rf_lock;
1287 spinlock_t lps_lock;
62e63975 1288 spinlock_t tx_urb_lock;
0c817338
LF		 1289};
1290
1291struct rtl_works {
1292 struct ieee80211_hw *hw;
1293
1294 /*timer */
1295 struct timer_list watchdog_timer;
1296
1297 /*task */
1298 struct tasklet_struct irq_tasklet;
1299 struct tasklet_struct irq_prepare_bcn_tasklet;
1300
1301 /*work queue */
1302 struct workqueue_struct *rtl_wq;
1303 struct delayed_work watchdog_wq;
1304 struct delayed_work ips_nic_off_wq;
1305};
1306
1307struct rtl_debug {
1308 u32 dbgp_type[DBGP_TYPE_MAX];
1309 u32 global_debuglevel;
1310 u64 global_debugcomponents;
1311};
1312
1313struct rtl_priv {
1314 struct rtl_locks locks;
1315 struct rtl_works works;
1316 struct rtl_mac mac80211;
1317 struct rtl_hal rtlhal;
1318 struct rtl_regulatory regd;
1319 struct rtl_rfkill rfkill;
1320 struct rtl_io io;
1321 struct rtl_phy phy;
1322 struct rtl_dm dm;
1323 struct rtl_security sec;
1324 struct rtl_efuse efuse;
1325
1326 struct rtl_ps_ctl psc;
1327 struct rate_adaptive ra;
1328 struct wireless_stats stats;
1329 struct rt_link_detect link_info;
1330 struct false_alarm_statistics falsealm_cnt;
1331
1332 struct rtl_rate_priv *rate_priv;
1333
1334 struct rtl_debug dbg;
1335
1336 /*
1337 *hal_cfg : for diff cards
1338 *intf_ops : for diff interrface usb/pcie
1339 */
1340 struct rtl_hal_cfg *cfg;
1341 struct rtl_intf_ops *intf_ops;
1342
1343 /*this var will be set by set_bit,
1344 and was used to indicate status of
1345 interface or hardware */
1346 unsigned long status;
1347
1348 /*This must be the last item so
1349 that it points to the data allocated
1350 beyond this structure like:
1351 rtl_pci_priv or rtl_usb_priv */
1352 u8 priv[0];
1353};
1354
1355#define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
1356#define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
1357#define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
1358#define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1359#define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1360
18d30067
G		 1361/***************************************
1362 Bluetooth Co-existance Related
1363****************************************/
1364
1365enum bt_ant_num {
1366 ANT_X2 = 0,
1367 ANT_X1 = 1,
1368};
1369
1370enum bt_co_type {
1371 BT_2WIRE = 0,
1372 BT_ISSC_3WIRE = 1,
1373 BT_ACCEL = 2,
1374 BT_CSR_BC4 = 3,
1375 BT_CSR_BC8 = 4,
1376 BT_RTL8756 = 5,
1377};
1378
1379enum bt_cur_state {
1380 BT_OFF = 0,
1381 BT_ON = 1,
1382};
1383
1384enum bt_service_type {
1385 BT_SCO = 0,
1386 BT_A2DP = 1,
1387 BT_HID = 2,
1388 BT_HID_IDLE = 3,
1389 BT_SCAN = 4,
1390 BT_IDLE = 5,
1391 BT_OTHER_ACTION = 6,
1392 BT_BUSY = 7,
1393 BT_OTHERBUSY = 8,
1394 BT_PAN = 9,
1395};
1396
1397enum bt_radio_shared {
1398 BT_RADIO_SHARED = 0,
1399 BT_RADIO_INDIVIDUAL = 1,
1400};
1401
1402struct bt_coexist_info {
1403
1404 /* EEPROM BT info. */
1405 u8 eeprom_bt_coexist;
1406 u8 eeprom_bt_type;
1407 u8 eeprom_bt_ant_num;
1408 u8 eeprom_bt_ant_isolation;
1409 u8 eeprom_bt_radio_shared;
1410
1411 u8 bt_coexistence;
1412 u8 bt_ant_num;
1413 u8 bt_coexist_type;
1414 u8 bt_state;
1415 u8 bt_cur_state; /* 0:on, 1:off */
1416 u8 bt_ant_isolation; /* 0:good, 1:bad */
1417 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
1418 u8 bt_service;
1419 u8 bt_radio_shared_type;
1420 u8 bt_rfreg_origin_1e;
1421 u8 bt_rfreg_origin_1f;
1422 u8 bt_rssi_state;
1423 u32 ratio_tx;
1424 u32 ratio_pri;
1425 u32 bt_edca_ul;
1426 u32 bt_edca_dl;
1427
1428 bool b_init_set;
1429 bool b_bt_busy_traffic;
1430 bool b_bt_traffic_mode_set;
1431 bool b_bt_non_traffic_mode_set;
1432
1433 bool b_fw_coexist_all_off;
1434 bool b_sw_coexist_all_off;
1435 u32 current_state;
1436 u32 previous_state;
1437 u8 bt_pre_rssi_state;
1438
1439 u8 b_reg_bt_iso;
1440 u8 b_reg_bt_sco;
1441
1442};
1443
0c817338
LF		 1444/****************************************
1445 mem access macro define start
1446 Call endian free function when
1447 1. Read/write packet content.
1448 2. Before write integer to IO.
1449 3. After read integer from IO.
1450****************************************/
1451/* Convert little data endian to host */
1452#define EF1BYTE(_val) \
1453 ((u8)(_val))
1454#define EF2BYTE(_val) \
1455 (le16_to_cpu(_val))
1456#define EF4BYTE(_val) \
1457 (le32_to_cpu(_val))
1458
1459/* Read data from memory */
1460#define READEF1BYTE(_ptr) \
1461 EF1BYTE(*((u8 *)(_ptr)))
1462#define READEF2BYTE(_ptr) \
1463 EF2BYTE(*((u16 *)(_ptr)))
1464#define READEF4BYTE(_ptr) \
1465 EF4BYTE(*((u32 *)(_ptr)))
1466
1467/* Write data to memory */
1468#define WRITEEF1BYTE(_ptr, _val) \
1469 (*((u8 *)(_ptr))) = EF1BYTE(_val)
1470#define WRITEEF2BYTE(_ptr, _val) \
1471 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1472#define WRITEEF4BYTE(_ptr, _val) \
1473 (*((u32 *)(_ptr))) = EF4BYTE(_val)
1474
1475/*Example:
1476BIT_LEN_MASK_32(0) => 0x00000000
1477BIT_LEN_MASK_32(1) => 0x00000001
1478BIT_LEN_MASK_32(2) => 0x00000003
1479BIT_LEN_MASK_32(32) => 0xFFFFFFFF*/
1480#define BIT_LEN_MASK_32(__bitlen) \
1481 (0xFFFFFFFF >> (32 - (__bitlen)))
1482#define BIT_LEN_MASK_16(__bitlen) \
1483 (0xFFFF >> (16 - (__bitlen)))
1484#define BIT_LEN_MASK_8(__bitlen) \
1485 (0xFF >> (8 - (__bitlen)))
1486
1487/*Example:
1488BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1489BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000*/
1490#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1491 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1492#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1493 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1494#define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1495 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1496
1497/*Description:
1498Return 4-byte value in host byte ordering from
14994-byte pointer in little-endian system.*/
1500#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1501 (EF4BYTE(*((u32 *)(__pstart))))
1502#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1503 (EF2BYTE(*((u16 *)(__pstart))))
1504#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1505 (EF1BYTE(*((u8 *)(__pstart))))
1506
1507/*Description:
1508Translate subfield (continuous bits in little-endian) of 4-byte
1509value to host byte ordering.*/
1510#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1511 ( \
1512 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
1513 BIT_LEN_MASK_32(__bitlen) \
1514 )
1515#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1516 ( \
1517 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1518 BIT_LEN_MASK_16(__bitlen) \
1519 )
1520#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1521 ( \
1522 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1523 BIT_LEN_MASK_8(__bitlen) \
1524 )
1525
1526/*Description:
1527Mask subfield (continuous bits in little-endian) of 4-byte value
1528and return the result in 4-byte value in host byte ordering.*/
1529#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1530 ( \
1531 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
1532 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1533 )
1534#define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1535 ( \
1536 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1537 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1538 )
1539#define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1540 ( \
1541 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1542 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1543 )
1544
1545/*Description:
1546Set subfield of little-endian 4-byte value to specified value. */
1547#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1548 *((u32 *)(__pstart)) = EF4BYTE \
1549 ( \
1550 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1551 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1552 );
1553#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1554 *((u16 *)(__pstart)) = EF2BYTE \
1555 ( \
1556 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1557 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1558 );
1559#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1560 *((u8 *)(__pstart)) = EF1BYTE \
1561 ( \
1562 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1563 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1564 );
1565
1566/****************************************
1567 mem access macro define end
1568****************************************/
1569
1570#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1571#define RTL_WATCH_DOG_TIME 2000
1572#define MSECS(t) msecs_to_jiffies(t)
1573#define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS)
1574#define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE)
1575#define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE)
1576#define WLAN_FC_MORE_DATA(fc) ((fc) & IEEE80211_FCTL_MOREDATA)
1577#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1578#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1579#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
1580
1581#define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
1582#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
1583#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
1584/*NIC halt, re-initialize hw parameters*/
1585#define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
1586#define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
1587#define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
1588/*Always enable ASPM and Clock Req in initialization.*/
1589#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
1590/*When LPS is on, disable 2R if no packet is received or transmittd.*/
1591#define RT_RF_LPS_DISALBE_2R BIT(30)
1592#define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
1593#define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
1594 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1595#define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
1596 (ppsc->cur_ps_level &= (~(_ps_flg)))
1597#define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
1598 (ppsc->cur_ps_level |= _ps_flg)
1599
1600#define container_of_dwork_rtl(x, y, z) \
1601 container_of(container_of(x, struct delayed_work, work), y, z)
1602
1603#define FILL_OCTET_STRING(_os, _octet, _len) \
1604 (_os).octet = (u8 *)(_octet); \
1605 (_os).length = (_len);
1606
62e63975
LF		 1607#define CP_MACADDR(des, src) \
1608 memcpy((des), (src), ETH_ALEN)
0c817338
LF		 1609
1610static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1611{
1612 return rtlpriv->io.read8_sync(rtlpriv, addr);
1613}
1614
1615static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1616{
1617 return rtlpriv->io.read16_sync(rtlpriv, addr);
1618}
1619
1620static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1621{
1622 return rtlpriv->io.read32_sync(rtlpriv, addr);
1623}
1624
1625static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1626{
1627 rtlpriv->io.write8_async(rtlpriv, addr, val8);
1628}
1629
1630static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1631{
1632 rtlpriv->io.write16_async(rtlpriv, addr, val16);
1633}
1634
1635static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1636 u32 addr, u32 val32)
1637{
1638 rtlpriv->io.write32_async(rtlpriv, addr, val32);
1639}
1640
1641static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1642 u32 regaddr, u32 bitmask)
1643{
1644 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1645 regaddr,
1646 bitmask);
1647}
1648
1649static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1650 u32 bitmask, u32 data)
1651{
1652 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1653 regaddr, bitmask,
1654 data);
1655
1656}
1657
1658static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1659 enum radio_path rfpath, u32 regaddr,
1660 u32 bitmask)
1661{
1662 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1663 rfpath,
1664 regaddr,
1665 bitmask);
1666}
1667
1668static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1669 enum radio_path rfpath, u32 regaddr,
1670 u32 bitmask, u32 data)
1671{
1672 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1673 rfpath, regaddr,
1674 bitmask, data);
1675}
1676
1677static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1678{
1679 return (_HAL_STATE_STOP == rtlhal->state);
1680}
1681
1682static inline void set_hal_start(struct rtl_hal *rtlhal)
1683{
1684 rtlhal->state = _HAL_STATE_START;
1685}
1686
1687static inline void set_hal_stop(struct rtl_hal *rtlhal)
1688{
1689 rtlhal->state = _HAL_STATE_STOP;
1690}
1691
1692static inline u8 get_rf_type(struct rtl_phy *rtlphy)
1693{
1694 return rtlphy->rf_type;
1695}
1696
1697#endif
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