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0c817338 LF |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2009-2010 Realtek Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * wlanfae <wlanfae@realtek.com> | |
23 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | |
24 | * Hsinchu 300, Taiwan. | |
25 | * | |
26 | * Larry Finger <Larry.Finger@lwfinger.net> | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #ifndef __RTL_WIFI_H__ | |
31 | #define __RTL_WIFI_H__ | |
32 | ||
33 | #include <linux/sched.h> | |
34 | #include <linux/firmware.h> | |
35 | #include <linux/version.h> | |
36 | #include <linux/etherdevice.h> | |
b08cd667 | 37 | #include <linux/vmalloc.h> |
62e63975 | 38 | #include <linux/usb.h> |
0c817338 LF |
39 | #include <net/mac80211.h> |
40 | #include "debug.h" | |
41 | ||
42 | #define RF_CHANGE_BY_INIT 0 | |
43 | #define RF_CHANGE_BY_IPS BIT(28) | |
44 | #define RF_CHANGE_BY_PS BIT(29) | |
45 | #define RF_CHANGE_BY_HW BIT(30) | |
46 | #define RF_CHANGE_BY_SW BIT(31) | |
47 | ||
48 | #define IQK_ADDA_REG_NUM 16 | |
49 | #define IQK_MAC_REG_NUM 4 | |
50 | ||
51 | #define MAX_KEY_LEN 61 | |
52 | #define KEY_BUF_SIZE 5 | |
53 | ||
54 | /* QoS related. */ | |
55 | /*aci: 0x00 Best Effort*/ | |
56 | /*aci: 0x01 Background*/ | |
57 | /*aci: 0x10 Video*/ | |
58 | /*aci: 0x11 Voice*/ | |
59 | /*Max: define total number.*/ | |
60 | #define AC0_BE 0 | |
61 | #define AC1_BK 1 | |
62 | #define AC2_VI 2 | |
63 | #define AC3_VO 3 | |
64 | #define AC_MAX 4 | |
65 | #define QOS_QUEUE_NUM 4 | |
66 | #define RTL_MAC80211_NUM_QUEUE 5 | |
67 | ||
68 | #define QBSS_LOAD_SIZE 5 | |
69 | #define MAX_WMMELE_LENGTH 64 | |
70 | ||
71 | /*slot time for 11g. */ | |
72 | #define RTL_SLOT_TIME_9 9 | |
73 | #define RTL_SLOT_TIME_20 20 | |
74 | ||
75 | /*related with tcp/ip. */ | |
76 | /*if_ehther.h*/ | |
77 | #define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */ | |
78 | #define ETH_P_IP 0x0800 /*Internet Protocol packet */ | |
79 | #define ETH_P_ARP 0x0806 /*Address Resolution packet */ | |
80 | #define SNAP_SIZE 6 | |
81 | #define PROTOC_TYPE_SIZE 2 | |
82 | ||
83 | /*related with 802.11 frame*/ | |
84 | #define MAC80211_3ADDR_LEN 24 | |
85 | #define MAC80211_4ADDR_LEN 30 | |
86 | ||
e97b775d LF |
87 | #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */ |
88 | #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */ | |
89 | #define MAX_PG_GROUP 13 | |
90 | #define CHANNEL_GROUP_MAX_2G 3 | |
91 | #define CHANNEL_GROUP_IDX_5GL 3 | |
92 | #define CHANNEL_GROUP_IDX_5GM 6 | |
93 | #define CHANNEL_GROUP_IDX_5GH 9 | |
94 | #define CHANNEL_GROUP_MAX_5G 9 | |
95 | #define CHANNEL_MAX_NUMBER_2G 14 | |
96 | #define AVG_THERMAL_NUM 8 | |
97 | ||
98 | /* for early mode */ | |
99 | #define EM_HDR_LEN 8 | |
0c817338 LF |
100 | enum intf_type { |
101 | INTF_PCI = 0, | |
102 | INTF_USB = 1, | |
103 | }; | |
104 | ||
105 | enum radio_path { | |
106 | RF90_PATH_A = 0, | |
107 | RF90_PATH_B = 1, | |
108 | RF90_PATH_C = 2, | |
109 | RF90_PATH_D = 3, | |
110 | }; | |
111 | ||
112 | enum rt_eeprom_type { | |
113 | EEPROM_93C46, | |
114 | EEPROM_93C56, | |
115 | EEPROM_BOOT_EFUSE, | |
116 | }; | |
117 | ||
118 | enum rtl_status { | |
119 | RTL_STATUS_INTERFACE_START = 0, | |
120 | }; | |
121 | ||
122 | enum hardware_type { | |
123 | HARDWARE_TYPE_RTL8192E, | |
124 | HARDWARE_TYPE_RTL8192U, | |
125 | HARDWARE_TYPE_RTL8192SE, | |
126 | HARDWARE_TYPE_RTL8192SU, | |
127 | HARDWARE_TYPE_RTL8192CE, | |
128 | HARDWARE_TYPE_RTL8192CU, | |
129 | HARDWARE_TYPE_RTL8192DE, | |
130 | HARDWARE_TYPE_RTL8192DU, | |
e97b775d | 131 | HARDWARE_TYPE_RTL8723E, |
18d30067 | 132 | HARDWARE_TYPE_RTL8723U, |
0c817338 | 133 | |
e97b775d | 134 | /* keep it last */ |
0c817338 LF |
135 | HARDWARE_TYPE_NUM |
136 | }; | |
137 | ||
e97b775d LF |
138 | #define IS_HARDWARE_TYPE_8192SU(rtlhal) \ |
139 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU) | |
140 | #define IS_HARDWARE_TYPE_8192SE(rtlhal) \ | |
141 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) | |
62e63975 LF |
142 | #define IS_HARDWARE_TYPE_8192CE(rtlhal) \ |
143 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE) | |
18d30067 G |
144 | #define IS_HARDWARE_TYPE_8192CU(rtlhal) \ |
145 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU) | |
e97b775d LF |
146 | #define IS_HARDWARE_TYPE_8192DE(rtlhal) \ |
147 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) | |
148 | #define IS_HARDWARE_TYPE_8192DU(rtlhal) \ | |
149 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU) | |
150 | #define IS_HARDWARE_TYPE_8723E(rtlhal) \ | |
151 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E) | |
18d30067 G |
152 | #define IS_HARDWARE_TYPE_8723U(rtlhal) \ |
153 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U) | |
e97b775d LF |
154 | #define IS_HARDWARE_TYPE_8192S(rtlhal) \ |
155 | (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal)) | |
156 | #define IS_HARDWARE_TYPE_8192C(rtlhal) \ | |
157 | (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal)) | |
158 | #define IS_HARDWARE_TYPE_8192D(rtlhal) \ | |
159 | (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal)) | |
160 | #define IS_HARDWARE_TYPE_8723(rtlhal) \ | |
161 | (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal)) | |
62e63975 | 162 | |
0c817338 LF |
163 | enum scan_operation_backup_opt { |
164 | SCAN_OPT_BACKUP = 0, | |
165 | SCAN_OPT_RESTORE, | |
166 | SCAN_OPT_MAX | |
167 | }; | |
168 | ||
169 | /*RF state.*/ | |
170 | enum rf_pwrstate { | |
171 | ERFON, | |
172 | ERFSLEEP, | |
173 | ERFOFF | |
174 | }; | |
175 | ||
176 | struct bb_reg_def { | |
177 | u32 rfintfs; | |
178 | u32 rfintfi; | |
179 | u32 rfintfo; | |
180 | u32 rfintfe; | |
181 | u32 rf3wire_offset; | |
182 | u32 rflssi_select; | |
183 | u32 rftxgain_stage; | |
184 | u32 rfhssi_para1; | |
185 | u32 rfhssi_para2; | |
186 | u32 rfswitch_control; | |
187 | u32 rfagc_control1; | |
188 | u32 rfagc_control2; | |
189 | u32 rfrxiq_imbalance; | |
190 | u32 rfrx_afe; | |
191 | u32 rftxiq_imbalance; | |
192 | u32 rftx_afe; | |
193 | u32 rflssi_readback; | |
194 | u32 rflssi_readbackpi; | |
195 | }; | |
196 | ||
197 | enum io_type { | |
198 | IO_CMD_PAUSE_DM_BY_SCAN = 0, | |
199 | IO_CMD_RESUME_DM_BY_SCAN = 1, | |
200 | }; | |
201 | ||
202 | enum hw_variables { | |
203 | HW_VAR_ETHER_ADDR, | |
204 | HW_VAR_MULTICAST_REG, | |
205 | HW_VAR_BASIC_RATE, | |
206 | HW_VAR_BSSID, | |
207 | HW_VAR_MEDIA_STATUS, | |
208 | HW_VAR_SECURITY_CONF, | |
209 | HW_VAR_BEACON_INTERVAL, | |
210 | HW_VAR_ATIM_WINDOW, | |
211 | HW_VAR_LISTEN_INTERVAL, | |
212 | HW_VAR_CS_COUNTER, | |
213 | HW_VAR_DEFAULTKEY0, | |
214 | HW_VAR_DEFAULTKEY1, | |
215 | HW_VAR_DEFAULTKEY2, | |
216 | HW_VAR_DEFAULTKEY3, | |
217 | HW_VAR_SIFS, | |
218 | HW_VAR_DIFS, | |
219 | HW_VAR_EIFS, | |
220 | HW_VAR_SLOT_TIME, | |
221 | HW_VAR_ACK_PREAMBLE, | |
222 | HW_VAR_CW_CONFIG, | |
223 | HW_VAR_CW_VALUES, | |
224 | HW_VAR_RATE_FALLBACK_CONTROL, | |
225 | HW_VAR_CONTENTION_WINDOW, | |
226 | HW_VAR_RETRY_COUNT, | |
227 | HW_VAR_TR_SWITCH, | |
228 | HW_VAR_COMMAND, | |
229 | HW_VAR_WPA_CONFIG, | |
230 | HW_VAR_AMPDU_MIN_SPACE, | |
231 | HW_VAR_SHORTGI_DENSITY, | |
232 | HW_VAR_AMPDU_FACTOR, | |
233 | HW_VAR_MCS_RATE_AVAILABLE, | |
234 | HW_VAR_AC_PARAM, | |
235 | HW_VAR_ACM_CTRL, | |
236 | HW_VAR_DIS_Req_Qsize, | |
237 | HW_VAR_CCX_CHNL_LOAD, | |
238 | HW_VAR_CCX_NOISE_HISTOGRAM, | |
239 | HW_VAR_CCX_CLM_NHM, | |
240 | HW_VAR_TxOPLimit, | |
241 | HW_VAR_TURBO_MODE, | |
242 | HW_VAR_RF_STATE, | |
243 | HW_VAR_RF_OFF_BY_HW, | |
244 | HW_VAR_BUS_SPEED, | |
245 | HW_VAR_SET_DEV_POWER, | |
246 | ||
247 | HW_VAR_RCR, | |
248 | HW_VAR_RATR_0, | |
249 | HW_VAR_RRSR, | |
250 | HW_VAR_CPU_RST, | |
251 | HW_VAR_CECHK_BSSID, | |
252 | HW_VAR_LBK_MODE, | |
253 | HW_VAR_AES_11N_FIX, | |
254 | HW_VAR_USB_RX_AGGR, | |
255 | HW_VAR_USER_CONTROL_TURBO_MODE, | |
256 | HW_VAR_RETRY_LIMIT, | |
257 | HW_VAR_INIT_TX_RATE, | |
258 | HW_VAR_TX_RATE_REG, | |
259 | HW_VAR_EFUSE_USAGE, | |
260 | HW_VAR_EFUSE_BYTES, | |
261 | HW_VAR_AUTOLOAD_STATUS, | |
262 | HW_VAR_RF_2R_DISABLE, | |
263 | HW_VAR_SET_RPWM, | |
264 | HW_VAR_H2C_FW_PWRMODE, | |
265 | HW_VAR_H2C_FW_JOINBSSRPT, | |
266 | HW_VAR_FW_PSMODE_STATUS, | |
267 | HW_VAR_1X1_RECV_COMBINE, | |
268 | HW_VAR_STOP_SEND_BEACON, | |
269 | HW_VAR_TSF_TIMER, | |
270 | HW_VAR_IO_CMD, | |
271 | ||
272 | HW_VAR_RF_RECOVERY, | |
273 | HW_VAR_H2C_FW_UPDATE_GTK, | |
274 | HW_VAR_WF_MASK, | |
275 | HW_VAR_WF_CRC, | |
276 | HW_VAR_WF_IS_MAC_ADDR, | |
277 | HW_VAR_H2C_FW_OFFLOAD, | |
278 | HW_VAR_RESET_WFCRC, | |
279 | ||
280 | HW_VAR_HANDLE_FW_C2H, | |
281 | HW_VAR_DL_FW_RSVD_PAGE, | |
282 | HW_VAR_AID, | |
283 | HW_VAR_HW_SEQ_ENABLE, | |
284 | HW_VAR_CORRECT_TSF, | |
285 | HW_VAR_BCN_VALID, | |
286 | HW_VAR_FWLPS_RF_ON, | |
287 | HW_VAR_DUAL_TSF_RST, | |
288 | HW_VAR_SWITCH_EPHY_WoWLAN, | |
289 | HW_VAR_INT_MIGRATION, | |
290 | HW_VAR_INT_AC, | |
291 | HW_VAR_RF_TIMING, | |
292 | ||
293 | HW_VAR_MRC, | |
294 | ||
295 | HW_VAR_MGT_FILTER, | |
296 | HW_VAR_CTRL_FILTER, | |
297 | HW_VAR_DATA_FILTER, | |
298 | }; | |
299 | ||
300 | enum _RT_MEDIA_STATUS { | |
301 | RT_MEDIA_DISCONNECT = 0, | |
302 | RT_MEDIA_CONNECT = 1 | |
303 | }; | |
304 | ||
305 | enum rt_oem_id { | |
306 | RT_CID_DEFAULT = 0, | |
307 | RT_CID_8187_ALPHA0 = 1, | |
308 | RT_CID_8187_SERCOMM_PS = 2, | |
309 | RT_CID_8187_HW_LED = 3, | |
310 | RT_CID_8187_NETGEAR = 4, | |
311 | RT_CID_WHQL = 5, | |
312 | RT_CID_819x_CAMEO = 6, | |
313 | RT_CID_819x_RUNTOP = 7, | |
314 | RT_CID_819x_Senao = 8, | |
315 | RT_CID_TOSHIBA = 9, | |
316 | RT_CID_819x_Netcore = 10, | |
317 | RT_CID_Nettronix = 11, | |
318 | RT_CID_DLINK = 12, | |
319 | RT_CID_PRONET = 13, | |
320 | RT_CID_COREGA = 14, | |
321 | RT_CID_819x_ALPHA = 15, | |
322 | RT_CID_819x_Sitecom = 16, | |
323 | RT_CID_CCX = 17, | |
324 | RT_CID_819x_Lenovo = 18, | |
325 | RT_CID_819x_QMI = 19, | |
326 | RT_CID_819x_Edimax_Belkin = 20, | |
327 | RT_CID_819x_Sercomm_Belkin = 21, | |
328 | RT_CID_819x_CAMEO1 = 22, | |
329 | RT_CID_819x_MSI = 23, | |
330 | RT_CID_819x_Acer = 24, | |
331 | RT_CID_819x_HP = 27, | |
332 | RT_CID_819x_CLEVO = 28, | |
333 | RT_CID_819x_Arcadyan_Belkin = 29, | |
334 | RT_CID_819x_SAMSUNG = 30, | |
335 | RT_CID_819x_WNC_COREGA = 31, | |
336 | RT_CID_819x_Foxcoon = 32, | |
337 | RT_CID_819x_DELL = 33, | |
338 | }; | |
339 | ||
340 | enum hw_descs { | |
341 | HW_DESC_OWN, | |
342 | HW_DESC_RXOWN, | |
343 | HW_DESC_TX_NEXTDESC_ADDR, | |
344 | HW_DESC_TXBUFF_ADDR, | |
345 | HW_DESC_RXBUFF_ADDR, | |
346 | HW_DESC_RXPKT_LEN, | |
347 | HW_DESC_RXERO, | |
348 | }; | |
349 | ||
350 | enum prime_sc { | |
351 | PRIME_CHNL_OFFSET_DONT_CARE = 0, | |
352 | PRIME_CHNL_OFFSET_LOWER = 1, | |
353 | PRIME_CHNL_OFFSET_UPPER = 2, | |
354 | }; | |
355 | ||
356 | enum rf_type { | |
357 | RF_1T1R = 0, | |
358 | RF_1T2R = 1, | |
359 | RF_2T2R = 2, | |
e97b775d | 360 | RF_2T2R_GREEN = 3, |
0c817338 LF |
361 | }; |
362 | ||
363 | enum ht_channel_width { | |
364 | HT_CHANNEL_WIDTH_20 = 0, | |
365 | HT_CHANNEL_WIDTH_20_40 = 1, | |
366 | }; | |
367 | ||
368 | /* Ref: 802.11i sepc D10.0 7.3.2.25.1 | |
369 | Cipher Suites Encryption Algorithms */ | |
370 | enum rt_enc_alg { | |
371 | NO_ENCRYPTION = 0, | |
372 | WEP40_ENCRYPTION = 1, | |
373 | TKIP_ENCRYPTION = 2, | |
374 | RSERVED_ENCRYPTION = 3, | |
375 | AESCCMP_ENCRYPTION = 4, | |
376 | WEP104_ENCRYPTION = 5, | |
377 | }; | |
378 | ||
379 | enum rtl_hal_state { | |
380 | _HAL_STATE_STOP = 0, | |
381 | _HAL_STATE_START = 1, | |
382 | }; | |
383 | ||
384 | enum rtl_var_map { | |
385 | /*reg map */ | |
386 | SYS_ISO_CTRL = 0, | |
387 | SYS_FUNC_EN, | |
388 | SYS_CLK, | |
389 | MAC_RCR_AM, | |
390 | MAC_RCR_AB, | |
391 | MAC_RCR_ACRC32, | |
392 | MAC_RCR_ACF, | |
393 | MAC_RCR_AAP, | |
394 | ||
395 | /*efuse map */ | |
396 | EFUSE_TEST, | |
397 | EFUSE_CTRL, | |
398 | EFUSE_CLK, | |
399 | EFUSE_CLK_CTRL, | |
400 | EFUSE_PWC_EV12V, | |
401 | EFUSE_FEN_ELDR, | |
402 | EFUSE_LOADER_CLK_EN, | |
403 | EFUSE_ANA8M, | |
404 | EFUSE_HWSET_MAX_SIZE, | |
18d30067 G |
405 | EFUSE_MAX_SECTION_MAP, |
406 | EFUSE_REAL_CONTENT_SIZE, | |
0c817338 LF |
407 | |
408 | /*CAM map */ | |
409 | RWCAM, | |
410 | WCAMI, | |
411 | RCAMO, | |
412 | CAMDBG, | |
413 | SECR, | |
414 | SEC_CAM_NONE, | |
415 | SEC_CAM_WEP40, | |
416 | SEC_CAM_TKIP, | |
417 | SEC_CAM_AES, | |
418 | SEC_CAM_WEP104, | |
419 | ||
420 | /*IMR map */ | |
421 | RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */ | |
422 | RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */ | |
423 | RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */ | |
424 | RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */ | |
425 | RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */ | |
426 | RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */ | |
427 | RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */ | |
428 | RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */ | |
429 | RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */ | |
430 | RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */ | |
431 | RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */ | |
432 | RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */ | |
433 | RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */ | |
434 | RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */ | |
435 | RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */ | |
436 | RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */ | |
437 | RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */ | |
438 | RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */ | |
439 | RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */ | |
440 | RTL_IMR_RXFOVW, /*Receive FIFO Overflow */ | |
441 | RTL_IMR_RDU, /*Receive Descriptor Unavailable */ | |
442 | RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ | |
443 | RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ | |
444 | RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ | |
e97b775d | 445 | RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/ |
0c817338 LF |
446 | RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ |
447 | RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ | |
448 | RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ | |
449 | RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */ | |
450 | RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */ | |
451 | RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ | |
452 | RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ | |
453 | RTL_IMR_ROK, /*Receive DMA OK Interrupt */ | |
e97b775d LF |
454 | RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK | |
455 | * RTL_IMR_TBDER) */ | |
0c817338 LF |
456 | |
457 | /*CCK Rates, TxHT = 0 */ | |
458 | RTL_RC_CCK_RATE1M, | |
459 | RTL_RC_CCK_RATE2M, | |
460 | RTL_RC_CCK_RATE5_5M, | |
461 | RTL_RC_CCK_RATE11M, | |
462 | ||
463 | /*OFDM Rates, TxHT = 0 */ | |
464 | RTL_RC_OFDM_RATE6M, | |
465 | RTL_RC_OFDM_RATE9M, | |
466 | RTL_RC_OFDM_RATE12M, | |
467 | RTL_RC_OFDM_RATE18M, | |
468 | RTL_RC_OFDM_RATE24M, | |
469 | RTL_RC_OFDM_RATE36M, | |
470 | RTL_RC_OFDM_RATE48M, | |
471 | RTL_RC_OFDM_RATE54M, | |
472 | ||
473 | RTL_RC_HT_RATEMCS7, | |
474 | RTL_RC_HT_RATEMCS15, | |
475 | ||
476 | /*keep it last */ | |
477 | RTL_VAR_MAP_MAX, | |
478 | }; | |
479 | ||
480 | /*Firmware PS mode for control LPS.*/ | |
481 | enum _fw_ps_mode { | |
482 | FW_PS_ACTIVE_MODE = 0, | |
483 | FW_PS_MIN_MODE = 1, | |
484 | FW_PS_MAX_MODE = 2, | |
485 | FW_PS_DTIM_MODE = 3, | |
486 | FW_PS_VOIP_MODE = 4, | |
487 | FW_PS_UAPSD_WMM_MODE = 5, | |
488 | FW_PS_UAPSD_MODE = 6, | |
489 | FW_PS_IBSS_MODE = 7, | |
490 | FW_PS_WWLAN_MODE = 8, | |
491 | FW_PS_PM_Radio_Off = 9, | |
492 | FW_PS_PM_Card_Disable = 10, | |
493 | }; | |
494 | ||
495 | enum rt_psmode { | |
496 | EACTIVE, /*Active/Continuous access. */ | |
497 | EMAXPS, /*Max power save mode. */ | |
498 | EFASTPS, /*Fast power save mode. */ | |
499 | EAUTOPS, /*Auto power save mode. */ | |
500 | }; | |
501 | ||
502 | /*LED related.*/ | |
503 | enum led_ctl_mode { | |
504 | LED_CTL_POWER_ON = 1, | |
505 | LED_CTL_LINK = 2, | |
506 | LED_CTL_NO_LINK = 3, | |
507 | LED_CTL_TX = 4, | |
508 | LED_CTL_RX = 5, | |
509 | LED_CTL_SITE_SURVEY = 6, | |
510 | LED_CTL_POWER_OFF = 7, | |
511 | LED_CTL_START_TO_LINK = 8, | |
512 | LED_CTL_START_WPS = 9, | |
513 | LED_CTL_STOP_WPS = 10, | |
514 | }; | |
515 | ||
516 | enum rtl_led_pin { | |
517 | LED_PIN_GPIO0, | |
518 | LED_PIN_LED0, | |
519 | LED_PIN_LED1, | |
520 | LED_PIN_LED2 | |
521 | }; | |
522 | ||
523 | /*QoS related.*/ | |
524 | /*acm implementation method.*/ | |
525 | enum acm_method { | |
526 | eAcmWay0_SwAndHw = 0, | |
527 | eAcmWay1_HW = 1, | |
528 | eAcmWay2_SW = 2, | |
529 | }; | |
530 | ||
e97b775d LF |
531 | enum macphy_mode { |
532 | SINGLEMAC_SINGLEPHY = 0, | |
533 | DUALMAC_DUALPHY, | |
534 | DUALMAC_SINGLEPHY, | |
535 | }; | |
536 | ||
537 | enum band_type { | |
538 | BAND_ON_2_4G = 0, | |
539 | BAND_ON_5G, | |
540 | BAND_ON_BOTH, | |
541 | BANDMAX | |
542 | }; | |
543 | ||
0c817338 LF |
544 | /*aci/aifsn Field. |
545 | Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/ | |
546 | union aci_aifsn { | |
547 | u8 char_data; | |
548 | ||
549 | struct { | |
550 | u8 aifsn:4; | |
551 | u8 acm:1; | |
552 | u8 aci:2; | |
553 | u8 reserved:1; | |
554 | } f; /* Field */ | |
555 | }; | |
556 | ||
557 | /*mlme related.*/ | |
558 | enum wireless_mode { | |
559 | WIRELESS_MODE_UNKNOWN = 0x00, | |
560 | WIRELESS_MODE_A = 0x01, | |
561 | WIRELESS_MODE_B = 0x02, | |
562 | WIRELESS_MODE_G = 0x04, | |
563 | WIRELESS_MODE_AUTO = 0x08, | |
564 | WIRELESS_MODE_N_24G = 0x10, | |
565 | WIRELESS_MODE_N_5G = 0x20 | |
566 | }; | |
567 | ||
18d30067 G |
568 | #define IS_WIRELESS_MODE_A(wirelessmode) \ |
569 | (wirelessmode == WIRELESS_MODE_A) | |
570 | #define IS_WIRELESS_MODE_B(wirelessmode) \ | |
571 | (wirelessmode == WIRELESS_MODE_B) | |
572 | #define IS_WIRELESS_MODE_G(wirelessmode) \ | |
573 | (wirelessmode == WIRELESS_MODE_G) | |
574 | #define IS_WIRELESS_MODE_N_24G(wirelessmode) \ | |
575 | (wirelessmode == WIRELESS_MODE_N_24G) | |
576 | #define IS_WIRELESS_MODE_N_5G(wirelessmode) \ | |
577 | (wirelessmode == WIRELESS_MODE_N_5G) | |
578 | ||
0c817338 LF |
579 | enum ratr_table_mode { |
580 | RATR_INX_WIRELESS_NGB = 0, | |
581 | RATR_INX_WIRELESS_NG = 1, | |
582 | RATR_INX_WIRELESS_NB = 2, | |
583 | RATR_INX_WIRELESS_N = 3, | |
584 | RATR_INX_WIRELESS_GB = 4, | |
585 | RATR_INX_WIRELESS_G = 5, | |
586 | RATR_INX_WIRELESS_B = 6, | |
587 | RATR_INX_WIRELESS_MC = 7, | |
588 | RATR_INX_WIRELESS_A = 8, | |
589 | }; | |
590 | ||
591 | enum rtl_link_state { | |
592 | MAC80211_NOLINK = 0, | |
593 | MAC80211_LINKING = 1, | |
594 | MAC80211_LINKED = 2, | |
595 | MAC80211_LINKED_SCANNING = 3, | |
596 | }; | |
597 | ||
598 | enum act_category { | |
599 | ACT_CAT_QOS = 1, | |
600 | ACT_CAT_DLS = 2, | |
601 | ACT_CAT_BA = 3, | |
602 | ACT_CAT_HT = 7, | |
603 | ACT_CAT_WMM = 17, | |
604 | }; | |
605 | ||
606 | enum ba_action { | |
607 | ACT_ADDBAREQ = 0, | |
608 | ACT_ADDBARSP = 1, | |
609 | ACT_DELBA = 2, | |
610 | }; | |
611 | ||
612 | struct octet_string { | |
613 | u8 *octet; | |
614 | u16 length; | |
615 | }; | |
616 | ||
617 | struct rtl_hdr_3addr { | |
618 | __le16 frame_ctl; | |
619 | __le16 duration_id; | |
620 | u8 addr1[ETH_ALEN]; | |
621 | u8 addr2[ETH_ALEN]; | |
622 | u8 addr3[ETH_ALEN]; | |
623 | __le16 seq_ctl; | |
624 | u8 payload[0]; | |
e137478b | 625 | } __packed; |
0c817338 LF |
626 | |
627 | struct rtl_info_element { | |
628 | u8 id; | |
629 | u8 len; | |
630 | u8 data[0]; | |
e137478b | 631 | } __packed; |
0c817338 LF |
632 | |
633 | struct rtl_probe_rsp { | |
634 | struct rtl_hdr_3addr header; | |
635 | u32 time_stamp[2]; | |
636 | __le16 beacon_interval; | |
637 | __le16 capability; | |
638 | /*SSID, supported rates, FH params, DS params, | |
639 | CF params, IBSS params, TIM (if beacon), RSN */ | |
640 | struct rtl_info_element info_element[0]; | |
e137478b | 641 | } __packed; |
0c817338 LF |
642 | |
643 | /*LED related.*/ | |
644 | /*ledpin Identify how to implement this SW led.*/ | |
645 | struct rtl_led { | |
646 | void *hw; | |
647 | enum rtl_led_pin ledpin; | |
7ea47240 | 648 | bool ledon; |
0c817338 LF |
649 | }; |
650 | ||
651 | struct rtl_led_ctl { | |
7ea47240 | 652 | bool led_opendrain; |
0c817338 LF |
653 | struct rtl_led sw_led0; |
654 | struct rtl_led sw_led1; | |
655 | }; | |
656 | ||
657 | struct rtl_qos_parameters { | |
658 | __le16 cw_min; | |
659 | __le16 cw_max; | |
660 | u8 aifs; | |
661 | u8 flag; | |
662 | __le16 tx_op; | |
e137478b | 663 | } __packed; |
0c817338 LF |
664 | |
665 | struct rt_smooth_data { | |
666 | u32 elements[100]; /*array to store values */ | |
667 | u32 index; /*index to current array to store */ | |
668 | u32 total_num; /*num of valid elements */ | |
669 | u32 total_val; /*sum of valid elements */ | |
670 | }; | |
671 | ||
672 | struct false_alarm_statistics { | |
673 | u32 cnt_parity_fail; | |
674 | u32 cnt_rate_illegal; | |
675 | u32 cnt_crc8_fail; | |
676 | u32 cnt_mcs_fail; | |
e97b775d LF |
677 | u32 cnt_fast_fsync_fail; |
678 | u32 cnt_sb_search_fail; | |
0c817338 LF |
679 | u32 cnt_ofdm_fail; |
680 | u32 cnt_cck_fail; | |
681 | u32 cnt_all; | |
682 | }; | |
683 | ||
684 | struct init_gain { | |
685 | u8 xaagccore1; | |
686 | u8 xbagccore1; | |
687 | u8 xcagccore1; | |
688 | u8 xdagccore1; | |
689 | u8 cca; | |
690 | ||
691 | }; | |
692 | ||
693 | struct wireless_stats { | |
694 | unsigned long txbytesunicast; | |
695 | unsigned long txbytesmulticast; | |
696 | unsigned long txbytesbroadcast; | |
697 | unsigned long rxbytesunicast; | |
698 | ||
699 | long rx_snr_db[4]; | |
700 | /*Correct smoothed ss in Dbm, only used | |
701 | in driver to report real power now. */ | |
702 | long recv_signal_power; | |
703 | long signal_quality; | |
704 | long last_sigstrength_inpercent; | |
705 | ||
706 | u32 rssi_calculate_cnt; | |
707 | ||
708 | /*Transformed, in dbm. Beautified signal | |
709 | strength for UI, not correct. */ | |
710 | long signal_strength; | |
711 | ||
712 | u8 rx_rssi_percentage[4]; | |
713 | u8 rx_evm_percentage[2]; | |
714 | ||
715 | struct rt_smooth_data ui_rssi; | |
716 | struct rt_smooth_data ui_link_quality; | |
717 | }; | |
718 | ||
719 | struct rate_adaptive { | |
720 | u8 rate_adaptive_disabled; | |
721 | u8 ratr_state; | |
722 | u16 reserve; | |
723 | ||
724 | u32 high_rssi_thresh_for_ra; | |
725 | u32 high2low_rssi_thresh_for_ra; | |
726 | u8 low2high_rssi_thresh_for_ra40m; | |
727 | u32 low_rssi_thresh_for_ra40M; | |
728 | u8 low2high_rssi_thresh_for_ra20m; | |
729 | u32 low_rssi_thresh_for_ra20M; | |
730 | u32 upper_rssi_threshold_ratr; | |
731 | u32 middleupper_rssi_threshold_ratr; | |
732 | u32 middle_rssi_threshold_ratr; | |
733 | u32 middlelow_rssi_threshold_ratr; | |
734 | u32 low_rssi_threshold_ratr; | |
735 | u32 ultralow_rssi_threshold_ratr; | |
736 | u32 low_rssi_threshold_ratr_40m; | |
737 | u32 low_rssi_threshold_ratr_20m; | |
738 | u8 ping_rssi_enable; | |
739 | u32 ping_rssi_ratr; | |
740 | u32 ping_rssi_thresh_for_ra; | |
741 | u32 last_ratr; | |
742 | u8 pre_ratr_state; | |
743 | }; | |
744 | ||
745 | struct regd_pair_mapping { | |
746 | u16 reg_dmnenum; | |
747 | u16 reg_5ghz_ctl; | |
748 | u16 reg_2ghz_ctl; | |
749 | }; | |
750 | ||
751 | struct rtl_regulatory { | |
752 | char alpha2[2]; | |
753 | u16 country_code; | |
754 | u16 max_power_level; | |
755 | u32 tp_scale; | |
756 | u16 current_rd; | |
757 | u16 current_rd_ext; | |
758 | int16_t power_limit; | |
759 | struct regd_pair_mapping *regpair; | |
760 | }; | |
761 | ||
762 | struct rtl_rfkill { | |
763 | bool rfkill_state; /*0 is off, 1 is on */ | |
764 | }; | |
765 | ||
e97b775d LF |
766 | #define IQK_MATRIX_REG_NUM 8 |
767 | #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21) | |
768 | struct iqk_matrix_regs { | |
769 | bool b_iqk_done; | |
770 | long value[1][IQK_MATRIX_REG_NUM]; | |
771 | }; | |
772 | ||
18d30067 G |
773 | struct phy_parameters { |
774 | u16 length; | |
775 | u32 *pdata; | |
776 | }; | |
777 | ||
778 | enum hw_param_tab_index { | |
779 | PHY_REG_2T, | |
780 | PHY_REG_1T, | |
781 | PHY_REG_PG, | |
782 | RADIOA_2T, | |
783 | RADIOB_2T, | |
784 | RADIOA_1T, | |
785 | RADIOB_1T, | |
786 | MAC_REG, | |
787 | AGCTAB_2T, | |
788 | AGCTAB_1T, | |
789 | MAX_TAB | |
790 | }; | |
791 | ||
0c817338 LF |
792 | struct rtl_phy { |
793 | struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ | |
794 | struct init_gain initgain_backup; | |
795 | enum io_type current_io_type; | |
796 | ||
797 | u8 rf_mode; | |
798 | u8 rf_type; | |
799 | u8 current_chan_bw; | |
800 | u8 set_bwmode_inprogress; | |
801 | u8 sw_chnl_inprogress; | |
802 | u8 sw_chnl_stage; | |
803 | u8 sw_chnl_step; | |
804 | u8 current_channel; | |
805 | u8 h2c_box_num; | |
806 | u8 set_io_inprogress; | |
e97b775d | 807 | u8 lck_inprogress; |
0c817338 | 808 | |
e97b775d | 809 | /* record for power tracking */ |
0c817338 LF |
810 | s32 reg_e94; |
811 | s32 reg_e9c; | |
812 | s32 reg_ea4; | |
813 | s32 reg_eac; | |
814 | s32 reg_eb4; | |
815 | s32 reg_ebc; | |
816 | s32 reg_ec4; | |
817 | s32 reg_ecc; | |
818 | u8 rfpienable; | |
819 | u8 reserve_0; | |
820 | u16 reserve_1; | |
821 | u32 reg_c04, reg_c08, reg_874; | |
822 | u32 adda_backup[16]; | |
823 | u32 iqk_mac_backup[IQK_MAC_REG_NUM]; | |
824 | u32 iqk_bb_backup[10]; | |
825 | ||
e97b775d LF |
826 | /* Dual mac */ |
827 | bool need_iqk; | |
828 | struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM]; | |
829 | ||
7ea47240 | 830 | bool rfpi_enable; |
0c817338 LF |
831 | |
832 | u8 pwrgroup_cnt; | |
7ea47240 | 833 | u8 cck_high_power; |
e97b775d LF |
834 | /* MAX_PG_GROUP groups of pwr diff by rates */ |
835 | u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16]; | |
0c817338 LF |
836 | u8 default_initialgain[4]; |
837 | ||
e97b775d | 838 | /* the current Tx power level */ |
0c817338 LF |
839 | u8 cur_cck_txpwridx; |
840 | u8 cur_ofdm24g_txpwridx; | |
841 | ||
842 | u32 rfreg_chnlval[2]; | |
7ea47240 | 843 | bool apk_done; |
e97b775d | 844 | u32 reg_rf3c[2]; /* pathA / pathB */ |
0c817338 | 845 | |
0c817338 LF |
846 | u8 framesync; |
847 | u32 framesync_c34; | |
848 | ||
849 | u8 num_total_rfpath; | |
18d30067 | 850 | struct phy_parameters hwparam_tables[MAX_TAB]; |
e97b775d | 851 | u16 rf_pathmap; |
0c817338 LF |
852 | }; |
853 | ||
854 | #define MAX_TID_COUNT 9 | |
855 | #define RTL_AGG_OFF 0 | |
856 | #define RTL_AGG_ON 1 | |
857 | #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2 | |
858 | #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3 | |
859 | ||
860 | struct rtl_ht_agg { | |
861 | u16 txq_id; | |
862 | u16 wait_for_ba; | |
863 | u16 start_idx; | |
864 | u64 bitmap; | |
865 | u32 rate_n_flags; | |
866 | u8 agg_state; | |
867 | }; | |
868 | ||
869 | struct rtl_tid_data { | |
870 | u16 seq_number; | |
871 | struct rtl_ht_agg agg; | |
872 | }; | |
873 | ||
874 | struct rtl_priv; | |
875 | struct rtl_io { | |
876 | struct device *dev; | |
62e63975 | 877 | struct mutex bb_mutex; |
0c817338 LF |
878 | |
879 | /*PCI MEM map */ | |
880 | unsigned long pci_mem_end; /*shared mem end */ | |
881 | unsigned long pci_mem_start; /*shared mem start */ | |
882 | ||
883 | /*PCI IO map */ | |
884 | unsigned long pci_base_addr; /*device I/O address */ | |
885 | ||
886 | void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val); | |
887 | void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val); | |
888 | void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val); | |
62e63975 LF |
889 | int (*writeN_async) (struct rtl_priv *rtlpriv, u32 addr, u16 len, |
890 | u8 *pdata); | |
0c817338 | 891 | |
e97b775d LF |
892 | u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr); |
893 | u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr); | |
894 | u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr); | |
62e63975 LF |
895 | int (*readN_sync) (struct rtl_priv *rtlpriv, u32 addr, u16 len, |
896 | u8 *pdata); | |
0c817338 LF |
897 | }; |
898 | ||
899 | struct rtl_mac { | |
900 | u8 mac_addr[ETH_ALEN]; | |
901 | u8 mac80211_registered; | |
902 | u8 beacon_enabled; | |
903 | ||
904 | u32 tx_ss_num; | |
905 | u32 rx_ss_num; | |
906 | ||
907 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; | |
908 | struct ieee80211_hw *hw; | |
909 | struct ieee80211_vif *vif; | |
910 | enum nl80211_iftype opmode; | |
911 | ||
912 | /*Probe Beacon management */ | |
913 | struct rtl_tid_data tids[MAX_TID_COUNT]; | |
914 | enum rtl_link_state link_state; | |
915 | ||
916 | int n_channels; | |
917 | int n_bitrates; | |
918 | ||
919 | /*filters */ | |
920 | u32 rx_conf; | |
921 | u16 rx_mgt_filter; | |
922 | u16 rx_ctrl_filter; | |
923 | u16 rx_data_filter; | |
924 | ||
925 | bool act_scanning; | |
926 | u8 cnt_after_linked; | |
927 | ||
e97b775d LF |
928 | /* early mode */ |
929 | /* skb wait queue */ | |
930 | struct sk_buff_head skb_waitq[MAX_TID_COUNT]; | |
931 | u8 earlymode_threshold; | |
932 | ||
933 | /*RDG*/ | |
934 | bool rdg_en; | |
0c817338 | 935 | |
e97b775d LF |
936 | /*AP*/ |
937 | u8 bssid[6]; | |
938 | u32 vendor; | |
939 | u8 mcs[16]; /* 16 bytes mcs for HT rates. */ | |
940 | u32 basic_rates; /* b/g rates */ | |
0c817338 LF |
941 | u8 ht_enable; |
942 | u8 sgi_40; | |
943 | u8 sgi_20; | |
944 | u8 bw_40; | |
e97b775d | 945 | u8 mode; /* wireless mode */ |
0c817338 LF |
946 | u8 slot_time; |
947 | u8 short_preamble; | |
948 | u8 use_cts_protect; | |
949 | u8 cur_40_prime_sc; | |
950 | u8 cur_40_prime_sc_bk; | |
951 | u64 tsf; | |
952 | u8 retry_short; | |
953 | u8 retry_long; | |
954 | u16 assoc_id; | |
955 | ||
e97b775d LF |
956 | /*IBSS*/ |
957 | int beacon_interval; | |
0c817338 | 958 | |
e97b775d LF |
959 | /*AMPDU*/ |
960 | u8 min_space_cfg; /*For Min spacing configurations */ | |
0c817338 LF |
961 | u8 max_mss_density; |
962 | u8 current_ampdu_factor; | |
963 | u8 current_ampdu_density; | |
964 | ||
965 | /*QOS & EDCA */ | |
966 | struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE]; | |
967 | struct rtl_qos_parameters ac[AC_MAX]; | |
968 | }; | |
969 | ||
970 | struct rtl_hal { | |
971 | struct ieee80211_hw *hw; | |
972 | ||
973 | enum intf_type interface; | |
974 | u16 hw_type; /*92c or 92d or 92s and so on */ | |
e97b775d | 975 | u8 ic_class; |
0c817338 | 976 | u8 oem_id; |
18d30067 | 977 | u32 version; /*version of chip */ |
0c817338 LF |
978 | u8 state; /*stop 0, start 1 */ |
979 | ||
980 | /*firmware */ | |
e97b775d | 981 | u32 fwsize; |
0c817338 | 982 | u8 *pfirmware; |
18d30067 G |
983 | u16 fw_version; |
984 | u16 fw_subversion; | |
7ea47240 | 985 | bool h2c_setinprogress; |
0c817338 | 986 | u8 last_hmeboxnum; |
7ea47240 | 987 | bool fw_ready; |
0c817338 LF |
988 | /*Reserve page start offset except beacon in TxQ. */ |
989 | u8 fw_rsvdpage_startoffset; | |
e97b775d LF |
990 | u8 h2c_txcmd_seq; |
991 | ||
992 | /* FW Cmd IO related */ | |
993 | u16 fwcmd_iomap; | |
994 | u32 fwcmd_ioparam; | |
995 | bool set_fwcmd_inprogress; | |
996 | u8 current_fwcmd_io; | |
997 | ||
998 | /**/ | |
999 | bool driver_going2unload; | |
1000 | ||
1001 | /*AMPDU init min space*/ | |
1002 | u8 minspace_cfg; /*For Min spacing configurations */ | |
1003 | ||
1004 | /* Dual mac */ | |
1005 | enum macphy_mode macphymode; | |
1006 | enum band_type current_bandtype; /* 0:2.4G, 1:5G */ | |
1007 | enum band_type current_bandtypebackup; | |
1008 | enum band_type bandset; | |
1009 | /* dual MAC 0--Mac0 1--Mac1 */ | |
1010 | u32 interfaceindex; | |
1011 | /* just for DualMac S3S4 */ | |
1012 | u8 macphyctl_reg; | |
1013 | bool earlymode_enable; | |
1014 | /* Dual mac*/ | |
1015 | bool during_mac0init_radiob; | |
1016 | bool during_mac1init_radioa; | |
1017 | bool reloadtxpowerindex; | |
1018 | /* True if IMR or IQK have done | |
1019 | for 2.4G in scan progress */ | |
1020 | bool load_imrandiqk_setting_for2g; | |
1021 | ||
1022 | bool disable_amsdu_8k; | |
0c817338 LF |
1023 | }; |
1024 | ||
1025 | struct rtl_security { | |
1026 | /*default 0 */ | |
1027 | bool use_sw_sec; | |
1028 | ||
1029 | bool being_setkey; | |
1030 | bool use_defaultkey; | |
1031 | /*Encryption Algorithm for Unicast Packet */ | |
1032 | enum rt_enc_alg pairwise_enc_algorithm; | |
1033 | /*Encryption Algorithm for Brocast/Multicast */ | |
1034 | enum rt_enc_alg group_enc_algorithm; | |
1035 | ||
1036 | /*local Key buffer, indx 0 is for | |
1037 | pairwise key 1-4 is for agoup key. */ | |
1038 | u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN]; | |
1039 | u8 key_len[KEY_BUF_SIZE]; | |
1040 | ||
1041 | /*The pointer of Pairwise Key, | |
1042 | it always points to KeyBuf[4] */ | |
1043 | u8 *pairwise_key; | |
1044 | }; | |
1045 | ||
1046 | struct rtl_dm { | |
e97b775d | 1047 | /*PHY status for Dynamic Management */ |
0c817338 LF |
1048 | long entry_min_undecoratedsmoothed_pwdb; |
1049 | long undecorated_smoothed_pwdb; /*out dm */ | |
1050 | long entry_max_undecoratedsmoothed_pwdb; | |
7ea47240 LF |
1051 | bool dm_initialgain_enable; |
1052 | bool dynamic_txpower_enable; | |
1053 | bool current_turbo_edca; | |
1054 | bool is_any_nonbepkts; /*out dm */ | |
1055 | bool is_cur_rdlstate; | |
1056 | bool txpower_trackingInit; | |
1057 | bool disable_framebursting; | |
1058 | bool cck_inch14; | |
1059 | bool txpower_tracking; | |
1060 | bool useramask; | |
1061 | bool rfpath_rxenable[4]; | |
e97b775d LF |
1062 | bool inform_fw_driverctrldm; |
1063 | bool current_mrc_switch; | |
1064 | u8 txpowercount; | |
0c817338 | 1065 | |
e97b775d | 1066 | u8 thermalvalue_rxgain; |
0c817338 LF |
1067 | u8 thermalvalue_iqk; |
1068 | u8 thermalvalue_lck; | |
1069 | u8 thermalvalue; | |
1070 | u8 last_dtp_lvl; | |
e97b775d LF |
1071 | u8 thermalvalue_avg[AVG_THERMAL_NUM]; |
1072 | u8 thermalvalue_avg_index; | |
1073 | bool done_txpower; | |
0c817338 | 1074 | u8 dynamic_txhighpower_lvl; /*Tx high power level */ |
e97b775d | 1075 | u8 dm_flag; /*Indicate each dynamic mechanism's status. */ |
0c817338 LF |
1076 | u8 dm_type; |
1077 | u8 txpower_track_control; | |
e97b775d LF |
1078 | bool interrupt_migration; |
1079 | bool disable_tx_int; | |
0c817338 LF |
1080 | char ofdm_index[2]; |
1081 | char cck_index; | |
e97b775d | 1082 | u8 power_index_backup[6]; |
0c817338 LF |
1083 | }; |
1084 | ||
e97b775d | 1085 | #define EFUSE_MAX_LOGICAL_SIZE 256 |
0c817338 LF |
1086 | |
1087 | struct rtl_efuse { | |
e97b775d | 1088 | bool autoLoad_ok; |
0c817338 LF |
1089 | bool bootfromefuse; |
1090 | u16 max_physical_size; | |
0c817338 LF |
1091 | |
1092 | u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; | |
1093 | u16 efuse_usedbytes; | |
1094 | u8 efuse_usedpercentage; | |
e97b775d LF |
1095 | #ifdef EFUSE_REPG_WORKAROUND |
1096 | bool efuse_re_pg_sec1flag; | |
1097 | u8 efuse_re_pg_data[8]; | |
1098 | #endif | |
0c817338 LF |
1099 | |
1100 | u8 autoload_failflag; | |
e97b775d | 1101 | u8 autoload_status; |
0c817338 LF |
1102 | |
1103 | short epromtype; | |
1104 | u16 eeprom_vid; | |
1105 | u16 eeprom_did; | |
1106 | u16 eeprom_svid; | |
1107 | u16 eeprom_smid; | |
1108 | u8 eeprom_oemid; | |
1109 | u16 eeprom_channelplan; | |
1110 | u8 eeprom_version; | |
18d30067 G |
1111 | u8 board_type; |
1112 | u8 external_pa; | |
0c817338 LF |
1113 | |
1114 | u8 dev_addr[6]; | |
1115 | ||
7ea47240 | 1116 | bool txpwr_fromeprom; |
e97b775d | 1117 | u8 eeprom_crystalcap; |
0c817338 | 1118 | u8 eeprom_tssi[2]; |
e97b775d LF |
1119 | u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */ |
1120 | u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX]; | |
1121 | u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX]; | |
1122 | u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G]; | |
1123 | u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX]; | |
1124 | u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX]; | |
1125 | u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G]; | |
1126 | u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */ | |
1127 | u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */ | |
1128 | ||
1129 | u8 internal_pa_5g[2]; /* pathA / pathB */ | |
1130 | u8 eeprom_c9; | |
1131 | u8 eeprom_cc; | |
0c817338 LF |
1132 | |
1133 | /*For power group */ | |
e97b775d LF |
1134 | u8 eeprom_pwrgroup[2][3]; |
1135 | u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER]; | |
1136 | u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER]; | |
1137 | ||
1138 | char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */ | |
1139 | /*For HT<->legacy pwr diff*/ | |
1140 | u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER]; | |
1141 | u8 txpwr_safetyflag; /* Band edge enable flag */ | |
1142 | u16 eeprom_txpowerdiff; | |
1143 | u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */ | |
1144 | u8 antenna_txpwdiff[3]; | |
0c817338 LF |
1145 | |
1146 | u8 eeprom_regulatory; | |
1147 | u8 eeprom_thermalmeter; | |
e97b775d LF |
1148 | u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */ |
1149 | u16 tssi_13dbm; | |
1150 | u8 crystalcap; /* CrystalCap. */ | |
1151 | u8 delta_iqk; | |
1152 | u8 delta_lck; | |
0c817338 LF |
1153 | |
1154 | u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ | |
7ea47240 | 1155 | bool apk_thermalmeterignore; |
e97b775d LF |
1156 | |
1157 | bool b1x1_recvcombine; | |
1158 | bool b1ss_support; | |
1159 | ||
1160 | /*channel plan */ | |
1161 | u8 channel_plan; | |
0c817338 LF |
1162 | }; |
1163 | ||
1164 | struct rtl_ps_ctl { | |
e97b775d | 1165 | bool pwrdomain_protect; |
0c817338 | 1166 | bool set_rfpowerstate_inprogress; |
7ea47240 | 1167 | bool in_powersavemode; |
0c817338 | 1168 | bool rfchange_inprogress; |
7ea47240 LF |
1169 | bool swrf_processing; |
1170 | bool hwradiooff; | |
0c817338 | 1171 | |
0c817338 LF |
1172 | /* |
1173 | * just for PCIE ASPM | |
1174 | * If it supports ASPM, Offset[560h] = 0x40, | |
1175 | * otherwise Offset[560h] = 0x00. | |
1176 | * */ | |
7ea47240 LF |
1177 | bool support_aspm; |
1178 | bool support_backdoor; | |
0c817338 LF |
1179 | |
1180 | /*for LPS */ | |
1181 | enum rt_psmode dot11_psmode; /*Power save mode configured. */ | |
e97b775d | 1182 | bool swctrl_lps; |
7ea47240 LF |
1183 | bool leisure_ps; |
1184 | bool fwctrl_lps; | |
0c817338 LF |
1185 | u8 fwctrl_psmode; |
1186 | /*For Fw control LPS mode */ | |
7ea47240 | 1187 | u8 reg_fwctrl_lps; |
0c817338 | 1188 | /*Record Fw PS mode status. */ |
7ea47240 | 1189 | bool fw_current_inpsmode; |
0c817338 LF |
1190 | u8 reg_max_lps_awakeintvl; |
1191 | bool report_linked; | |
1192 | ||
1193 | /*for IPS */ | |
7ea47240 | 1194 | bool inactiveps; |
0c817338 LF |
1195 | |
1196 | u32 rfoff_reason; | |
1197 | ||
1198 | /*RF OFF Level */ | |
1199 | u32 cur_ps_level; | |
1200 | u32 reg_rfps_level; | |
1201 | ||
1202 | /*just for PCIE ASPM */ | |
1203 | u8 const_amdpci_aspm; | |
1204 | ||
18d30067 | 1205 | bool pwrdown_mode; |
e97b775d | 1206 | |
0c817338 LF |
1207 | enum rf_pwrstate inactive_pwrstate; |
1208 | enum rf_pwrstate rfpwr_state; /*cur power state */ | |
e97b775d LF |
1209 | |
1210 | /* for SW LPS*/ | |
1211 | bool sw_ps_enabled; | |
1212 | bool state; | |
1213 | bool state_inap; | |
1214 | bool multi_buffered; | |
1215 | u16 nullfunc_seq; | |
1216 | unsigned int dtim_counter; | |
1217 | unsigned int sleep_ms; | |
1218 | unsigned long last_sleep_jiffies; | |
1219 | unsigned long last_awake_jiffies; | |
1220 | unsigned long last_delaylps_stamp_jiffies; | |
1221 | unsigned long last_dtim; | |
1222 | unsigned long last_beacon; | |
1223 | unsigned long last_action; | |
1224 | unsigned long last_slept; | |
0c817338 LF |
1225 | }; |
1226 | ||
1227 | struct rtl_stats { | |
1228 | u32 mac_time[2]; | |
1229 | s8 rssi; | |
1230 | u8 signal; | |
1231 | u8 noise; | |
1232 | u16 rate; /*in 100 kbps */ | |
1233 | u8 received_channel; | |
1234 | u8 control; | |
1235 | u8 mask; | |
1236 | u8 freq; | |
1237 | u16 len; | |
1238 | u64 tsf; | |
1239 | u32 beacon_time; | |
1240 | u8 nic_type; | |
1241 | u16 length; | |
1242 | u8 signalquality; /*in 0-100 index. */ | |
1243 | /* | |
1244 | * Real power in dBm for this packet, | |
1245 | * no beautification and aggregation. | |
1246 | * */ | |
1247 | s32 recvsignalpower; | |
1248 | s8 rxpower; /*in dBm Translate from PWdB */ | |
1249 | u8 signalstrength; /*in 0-100 index. */ | |
7ea47240 LF |
1250 | u16 hwerror:1; |
1251 | u16 crc:1; | |
1252 | u16 icv:1; | |
1253 | u16 shortpreamble:1; | |
0c817338 LF |
1254 | u16 antenna:1; |
1255 | u16 decrypted:1; | |
1256 | u16 wakeup:1; | |
1257 | u32 timestamp_low; | |
1258 | u32 timestamp_high; | |
1259 | ||
1260 | u8 rx_drvinfo_size; | |
1261 | u8 rx_bufshift; | |
7ea47240 | 1262 | bool isampdu; |
e97b775d | 1263 | bool isfirst_ampdu; |
0c817338 LF |
1264 | bool rx_is40Mhzpacket; |
1265 | u32 rx_pwdb_all; | |
1266 | u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ | |
1267 | s8 rx_mimo_signalquality[2]; | |
7ea47240 LF |
1268 | bool packet_matchbssid; |
1269 | bool is_cck; | |
1270 | bool packet_toself; | |
1271 | bool packet_beacon; /*for rssi */ | |
0c817338 LF |
1272 | char cck_adc_pwdb[4]; /*for rx path selection */ |
1273 | }; | |
1274 | ||
1275 | struct rt_link_detect { | |
1276 | u32 num_tx_in4period[4]; | |
1277 | u32 num_rx_in4period[4]; | |
1278 | ||
1279 | u32 num_tx_inperiod; | |
1280 | u32 num_rx_inperiod; | |
1281 | ||
7ea47240 LF |
1282 | bool busytraffic; |
1283 | bool higher_busytraffic; | |
1284 | bool higher_busyrxtraffic; | |
0c817338 LF |
1285 | }; |
1286 | ||
1287 | struct rtl_tcb_desc { | |
7ea47240 LF |
1288 | u8 packet_bw:1; |
1289 | u8 multicast:1; | |
1290 | u8 broadcast:1; | |
1291 | ||
1292 | u8 rts_stbc:1; | |
1293 | u8 rts_enable:1; | |
1294 | u8 cts_enable:1; | |
1295 | u8 rts_use_shortpreamble:1; | |
1296 | u8 rts_use_shortgi:1; | |
0c817338 | 1297 | u8 rts_sc:1; |
7ea47240 | 1298 | u8 rts_bw:1; |
0c817338 LF |
1299 | u8 rts_rate; |
1300 | ||
1301 | u8 use_shortgi:1; | |
1302 | u8 use_shortpreamble:1; | |
1303 | u8 use_driver_rate:1; | |
1304 | u8 disable_ratefallback:1; | |
1305 | ||
1306 | u8 ratr_index; | |
1307 | u8 mac_id; | |
1308 | u8 hw_rate; | |
e97b775d LF |
1309 | |
1310 | u8 last_inipkt:1; | |
1311 | u8 cmd_or_init:1; | |
1312 | u8 queue_index; | |
1313 | ||
1314 | /* early mode */ | |
1315 | u8 empkt_num; | |
1316 | /* The max value by HW */ | |
1317 | u32 empkt_len[5]; | |
0c817338 LF |
1318 | }; |
1319 | ||
1320 | struct rtl_hal_ops { | |
1321 | int (*init_sw_vars) (struct ieee80211_hw *hw); | |
1322 | void (*deinit_sw_vars) (struct ieee80211_hw *hw); | |
62e63975 | 1323 | void (*read_chip_version)(struct ieee80211_hw *hw); |
0c817338 LF |
1324 | void (*read_eeprom_info) (struct ieee80211_hw *hw); |
1325 | void (*interrupt_recognized) (struct ieee80211_hw *hw, | |
1326 | u32 *p_inta, u32 *p_intb); | |
1327 | int (*hw_init) (struct ieee80211_hw *hw); | |
1328 | void (*hw_disable) (struct ieee80211_hw *hw); | |
e97b775d LF |
1329 | void (*hw_suspend) (struct ieee80211_hw *hw); |
1330 | void (*hw_resume) (struct ieee80211_hw *hw); | |
0c817338 LF |
1331 | void (*enable_interrupt) (struct ieee80211_hw *hw); |
1332 | void (*disable_interrupt) (struct ieee80211_hw *hw); | |
1333 | int (*set_network_type) (struct ieee80211_hw *hw, | |
1334 | enum nl80211_iftype type); | |
18d30067 G |
1335 | void (*set_chk_bssid)(struct ieee80211_hw *hw, |
1336 | bool check_bssid); | |
0c817338 LF |
1337 | void (*set_bw_mode) (struct ieee80211_hw *hw, |
1338 | enum nl80211_channel_type ch_type); | |
e97b775d | 1339 | u8(*switch_channel) (struct ieee80211_hw *hw); |
0c817338 LF |
1340 | void (*set_qos) (struct ieee80211_hw *hw, int aci); |
1341 | void (*set_bcn_reg) (struct ieee80211_hw *hw); | |
1342 | void (*set_bcn_intv) (struct ieee80211_hw *hw); | |
1343 | void (*update_interrupt_mask) (struct ieee80211_hw *hw, | |
1344 | u32 add_msr, u32 rm_msr); | |
1345 | void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); | |
1346 | void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); | |
1347 | void (*update_rate_table) (struct ieee80211_hw *hw); | |
1348 | void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level); | |
1349 | void (*fill_tx_desc) (struct ieee80211_hw *hw, | |
1350 | struct ieee80211_hdr *hdr, u8 *pdesc_tx, | |
1351 | struct ieee80211_tx_info *info, | |
1352 | struct sk_buff *skb, unsigned int queue_index); | |
18d30067 G |
1353 | void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 * pDesc, |
1354 | u32 buffer_len, bool bIsPsPoll); | |
0c817338 | 1355 | void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc, |
7ea47240 | 1356 | bool firstseg, bool lastseg, |
0c817338 | 1357 | struct sk_buff *skb); |
62e63975 | 1358 | bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb); |
7ea47240 | 1359 | bool (*query_rx_desc) (struct ieee80211_hw *hw, |
0c817338 LF |
1360 | struct rtl_stats *stats, |
1361 | struct ieee80211_rx_status *rx_status, | |
1362 | u8 *pdesc, struct sk_buff *skb); | |
1363 | void (*set_channel_access) (struct ieee80211_hw *hw); | |
7ea47240 | 1364 | bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid); |
0c817338 LF |
1365 | void (*dm_watchdog) (struct ieee80211_hw *hw); |
1366 | void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation); | |
7ea47240 | 1367 | bool (*set_rf_power_state) (struct ieee80211_hw *hw, |
0c817338 LF |
1368 | enum rf_pwrstate rfpwr_state); |
1369 | void (*led_control) (struct ieee80211_hw *hw, | |
1370 | enum led_ctl_mode ledaction); | |
1371 | void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val); | |
7ea47240 | 1372 | u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name); |
0c817338 LF |
1373 | void (*tx_polling) (struct ieee80211_hw *hw, unsigned int hw_queue); |
1374 | void (*enable_hw_sec) (struct ieee80211_hw *hw); | |
1375 | void (*set_key) (struct ieee80211_hw *hw, u32 key_index, | |
1376 | u8 *p_macaddr, bool is_group, u8 enc_algo, | |
1377 | bool is_wepkey, bool clear_all); | |
1378 | void (*init_sw_leds) (struct ieee80211_hw *hw); | |
1379 | void (*deinit_sw_leds) (struct ieee80211_hw *hw); | |
7ea47240 | 1380 | u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); |
0c817338 LF |
1381 | void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, |
1382 | u32 data); | |
7ea47240 | 1383 | u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, |
0c817338 LF |
1384 | u32 regaddr, u32 bitmask); |
1385 | void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, | |
1386 | u32 regaddr, u32 bitmask, u32 data); | |
1472d3a8 LF |
1387 | bool (*phy_rf6052_config) (struct ieee80211_hw *hw); |
1388 | void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw, | |
1389 | u8 *powerlevel); | |
1390 | void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw, | |
1391 | u8 *ppowerlevel, u8 channel); | |
1392 | bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw, | |
1393 | u8 configtype); | |
1394 | bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw, | |
1395 | u8 configtype); | |
1396 | void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t); | |
1397 | void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw); | |
1398 | void (*dm_dynamic_txpower) (struct ieee80211_hw *hw); | |
0c817338 LF |
1399 | }; |
1400 | ||
1401 | struct rtl_intf_ops { | |
1402 | /*com */ | |
e97b775d | 1403 | void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); |
0c817338 LF |
1404 | int (*adapter_start) (struct ieee80211_hw *hw); |
1405 | void (*adapter_stop) (struct ieee80211_hw *hw); | |
1406 | ||
1407 | int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb); | |
1408 | int (*reset_trx_ring) (struct ieee80211_hw *hw); | |
62e63975 | 1409 | bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb); |
0c817338 LF |
1410 | |
1411 | /*pci */ | |
1412 | void (*disable_aspm) (struct ieee80211_hw *hw); | |
1413 | void (*enable_aspm) (struct ieee80211_hw *hw); | |
1414 | ||
1415 | /*usb */ | |
1416 | }; | |
1417 | ||
1418 | struct rtl_mod_params { | |
1419 | /* default: 0 = using hardware encryption */ | |
1420 | int sw_crypto; | |
1421 | }; | |
1422 | ||
62e63975 LF |
1423 | struct rtl_hal_usbint_cfg { |
1424 | /* data - rx */ | |
1425 | u32 in_ep_num; | |
1426 | u32 rx_urb_num; | |
1427 | u32 rx_max_size; | |
1428 | ||
1429 | /* op - rx */ | |
1430 | void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *); | |
1431 | void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *, | |
1432 | struct sk_buff_head *); | |
1433 | ||
1434 | /* tx */ | |
1435 | void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *); | |
1436 | int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *, | |
1437 | struct sk_buff *); | |
1438 | struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *, | |
1439 | struct sk_buff_head *); | |
1440 | ||
1441 | /* endpoint mapping */ | |
1442 | int (*usb_endpoint_mapping)(struct ieee80211_hw *hw); | |
17c9ac62 | 1443 | u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index); |
62e63975 LF |
1444 | }; |
1445 | ||
0c817338 | 1446 | struct rtl_hal_cfg { |
e97b775d | 1447 | u8 bar_id; |
0c817338 LF |
1448 | char *name; |
1449 | char *fw_name; | |
1450 | struct rtl_hal_ops *ops; | |
1451 | struct rtl_mod_params *mod_params; | |
62e63975 | 1452 | struct rtl_hal_usbint_cfg *usb_interface_cfg; |
0c817338 LF |
1453 | |
1454 | /*this map used for some registers or vars | |
1455 | defined int HAL but used in MAIN */ | |
1456 | u32 maps[RTL_VAR_MAP_MAX]; | |
1457 | ||
1458 | }; | |
1459 | ||
1460 | struct rtl_locks { | |
d704300f | 1461 | /* mutex */ |
8a09d6d8 | 1462 | struct mutex conf_mutex; |
0c817338 LF |
1463 | |
1464 | /*spin lock */ | |
d704300f | 1465 | spinlock_t ips_lock; |
0c817338 LF |
1466 | spinlock_t irq_th_lock; |
1467 | spinlock_t h2c_lock; | |
1468 | spinlock_t rf_ps_lock; | |
1469 | spinlock_t rf_lock; | |
1470 | spinlock_t lps_lock; | |
e97b775d | 1471 | spinlock_t waitq_lock; |
62e63975 | 1472 | spinlock_t tx_urb_lock; |
e97b775d LF |
1473 | |
1474 | /*Dual mac*/ | |
1475 | spinlock_t cck_and_rw_pagea_lock; | |
0c817338 LF |
1476 | }; |
1477 | ||
1478 | struct rtl_works { | |
1479 | struct ieee80211_hw *hw; | |
1480 | ||
1481 | /*timer */ | |
1482 | struct timer_list watchdog_timer; | |
1483 | ||
1484 | /*task */ | |
1485 | struct tasklet_struct irq_tasklet; | |
1486 | struct tasklet_struct irq_prepare_bcn_tasklet; | |
1487 | ||
1488 | /*work queue */ | |
1489 | struct workqueue_struct *rtl_wq; | |
1490 | struct delayed_work watchdog_wq; | |
1491 | struct delayed_work ips_nic_off_wq; | |
e97b775d LF |
1492 | |
1493 | /* For SW LPS */ | |
1494 | struct delayed_work ps_work; | |
1495 | struct delayed_work ps_rfon_wq; | |
0c817338 LF |
1496 | }; |
1497 | ||
1498 | struct rtl_debug { | |
1499 | u32 dbgp_type[DBGP_TYPE_MAX]; | |
1500 | u32 global_debuglevel; | |
1501 | u64 global_debugcomponents; | |
e97b775d LF |
1502 | |
1503 | /* add for proc debug */ | |
1504 | struct proc_dir_entry *proc_dir; | |
1505 | char proc_name[20]; | |
0c817338 LF |
1506 | }; |
1507 | ||
1508 | struct rtl_priv { | |
1509 | struct rtl_locks locks; | |
1510 | struct rtl_works works; | |
1511 | struct rtl_mac mac80211; | |
1512 | struct rtl_hal rtlhal; | |
1513 | struct rtl_regulatory regd; | |
1514 | struct rtl_rfkill rfkill; | |
1515 | struct rtl_io io; | |
1516 | struct rtl_phy phy; | |
1517 | struct rtl_dm dm; | |
1518 | struct rtl_security sec; | |
1519 | struct rtl_efuse efuse; | |
1520 | ||
1521 | struct rtl_ps_ctl psc; | |
1522 | struct rate_adaptive ra; | |
1523 | struct wireless_stats stats; | |
1524 | struct rt_link_detect link_info; | |
1525 | struct false_alarm_statistics falsealm_cnt; | |
1526 | ||
1527 | struct rtl_rate_priv *rate_priv; | |
1528 | ||
1529 | struct rtl_debug dbg; | |
1530 | ||
1531 | /* | |
1532 | *hal_cfg : for diff cards | |
1533 | *intf_ops : for diff interrface usb/pcie | |
1534 | */ | |
1535 | struct rtl_hal_cfg *cfg; | |
1536 | struct rtl_intf_ops *intf_ops; | |
1537 | ||
1538 | /*this var will be set by set_bit, | |
1539 | and was used to indicate status of | |
1540 | interface or hardware */ | |
1541 | unsigned long status; | |
1542 | ||
1543 | /*This must be the last item so | |
1544 | that it points to the data allocated | |
1545 | beyond this structure like: | |
1546 | rtl_pci_priv or rtl_usb_priv */ | |
1547 | u8 priv[0]; | |
1548 | }; | |
1549 | ||
1550 | #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) | |
1551 | #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) | |
1552 | #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) | |
1553 | #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) | |
1554 | #define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) | |
1555 | ||
e97b775d | 1556 | |
18d30067 | 1557 | /*************************************** |
25985edc | 1558 | Bluetooth Co-existence Related |
18d30067 G |
1559 | ****************************************/ |
1560 | ||
1561 | enum bt_ant_num { | |
1562 | ANT_X2 = 0, | |
1563 | ANT_X1 = 1, | |
1564 | }; | |
1565 | ||
1566 | enum bt_co_type { | |
1567 | BT_2WIRE = 0, | |
1568 | BT_ISSC_3WIRE = 1, | |
1569 | BT_ACCEL = 2, | |
1570 | BT_CSR_BC4 = 3, | |
1571 | BT_CSR_BC8 = 4, | |
1572 | BT_RTL8756 = 5, | |
1573 | }; | |
1574 | ||
1575 | enum bt_cur_state { | |
1576 | BT_OFF = 0, | |
1577 | BT_ON = 1, | |
1578 | }; | |
1579 | ||
1580 | enum bt_service_type { | |
1581 | BT_SCO = 0, | |
1582 | BT_A2DP = 1, | |
1583 | BT_HID = 2, | |
1584 | BT_HID_IDLE = 3, | |
1585 | BT_SCAN = 4, | |
1586 | BT_IDLE = 5, | |
1587 | BT_OTHER_ACTION = 6, | |
1588 | BT_BUSY = 7, | |
1589 | BT_OTHERBUSY = 8, | |
1590 | BT_PAN = 9, | |
1591 | }; | |
1592 | ||
1593 | enum bt_radio_shared { | |
1594 | BT_RADIO_SHARED = 0, | |
1595 | BT_RADIO_INDIVIDUAL = 1, | |
1596 | }; | |
1597 | ||
1598 | struct bt_coexist_info { | |
1599 | ||
1600 | /* EEPROM BT info. */ | |
1601 | u8 eeprom_bt_coexist; | |
1602 | u8 eeprom_bt_type; | |
1603 | u8 eeprom_bt_ant_num; | |
1604 | u8 eeprom_bt_ant_isolation; | |
1605 | u8 eeprom_bt_radio_shared; | |
1606 | ||
1607 | u8 bt_coexistence; | |
1608 | u8 bt_ant_num; | |
1609 | u8 bt_coexist_type; | |
1610 | u8 bt_state; | |
1611 | u8 bt_cur_state; /* 0:on, 1:off */ | |
1612 | u8 bt_ant_isolation; /* 0:good, 1:bad */ | |
1613 | u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */ | |
1614 | u8 bt_service; | |
1615 | u8 bt_radio_shared_type; | |
1616 | u8 bt_rfreg_origin_1e; | |
1617 | u8 bt_rfreg_origin_1f; | |
1618 | u8 bt_rssi_state; | |
1619 | u32 ratio_tx; | |
1620 | u32 ratio_pri; | |
1621 | u32 bt_edca_ul; | |
1622 | u32 bt_edca_dl; | |
1623 | ||
1624 | bool b_init_set; | |
1625 | bool b_bt_busy_traffic; | |
1626 | bool b_bt_traffic_mode_set; | |
1627 | bool b_bt_non_traffic_mode_set; | |
1628 | ||
1629 | bool b_fw_coexist_all_off; | |
1630 | bool b_sw_coexist_all_off; | |
1631 | u32 current_state; | |
1632 | u32 previous_state; | |
1633 | u8 bt_pre_rssi_state; | |
1634 | ||
1635 | u8 b_reg_bt_iso; | |
1636 | u8 b_reg_bt_sco; | |
1637 | ||
1638 | }; | |
1639 | ||
e97b775d | 1640 | |
0c817338 LF |
1641 | /**************************************** |
1642 | mem access macro define start | |
1643 | Call endian free function when | |
1644 | 1. Read/write packet content. | |
1645 | 2. Before write integer to IO. | |
1646 | 3. After read integer from IO. | |
1647 | ****************************************/ | |
9e0bc671 | 1648 | /* Convert little data endian to host ordering */ |
0c817338 LF |
1649 | #define EF1BYTE(_val) \ |
1650 | ((u8)(_val)) | |
1651 | #define EF2BYTE(_val) \ | |
1652 | (le16_to_cpu(_val)) | |
1653 | #define EF4BYTE(_val) \ | |
1654 | (le32_to_cpu(_val)) | |
1655 | ||
9e0bc671 | 1656 | /* Read le16 data from memory and convert to host ordering */ |
0c817338 LF |
1657 | #define READEF2BYTE(_ptr) \ |
1658 | EF2BYTE(*((u16 *)(_ptr))) | |
0c817338 | 1659 | |
9e0bc671 | 1660 | /* Write le16 data to memory in host ordering */ |
0c817338 LF |
1661 | #define WRITEEF2BYTE(_ptr, _val) \ |
1662 | (*((u16 *)(_ptr))) = EF2BYTE(_val) | |
9e0bc671 LF |
1663 | |
1664 | /* Create a bit mask | |
1665 | * Examples: | |
1666 | * BIT_LEN_MASK_32(0) => 0x00000000 | |
1667 | * BIT_LEN_MASK_32(1) => 0x00000001 | |
1668 | * BIT_LEN_MASK_32(2) => 0x00000003 | |
1669 | * BIT_LEN_MASK_32(32) => 0xFFFFFFFF | |
1670 | */ | |
0c817338 LF |
1671 | #define BIT_LEN_MASK_32(__bitlen) \ |
1672 | (0xFFFFFFFF >> (32 - (__bitlen))) | |
1673 | #define BIT_LEN_MASK_16(__bitlen) \ | |
1674 | (0xFFFF >> (16 - (__bitlen))) | |
1675 | #define BIT_LEN_MASK_8(__bitlen) \ | |
1676 | (0xFF >> (8 - (__bitlen))) | |
1677 | ||
9e0bc671 LF |
1678 | /* Create an offset bit mask |
1679 | * Examples: | |
1680 | * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 | |
1681 | * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 | |
1682 | */ | |
0c817338 LF |
1683 | #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ |
1684 | (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) | |
1685 | #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ | |
1686 | (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) | |
1687 | #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ | |
1688 | (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) | |
1689 | ||
1690 | /*Description: | |
9e0bc671 LF |
1691 | * Return 4-byte value in host byte ordering from |
1692 | * 4-byte pointer in little-endian system. | |
1693 | */ | |
0c817338 LF |
1694 | #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ |
1695 | (EF4BYTE(*((u32 *)(__pstart)))) | |
1696 | #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ | |
1697 | (EF2BYTE(*((u16 *)(__pstart)))) | |
1698 | #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ | |
1699 | (EF1BYTE(*((u8 *)(__pstart)))) | |
1700 | ||
9e0bc671 LF |
1701 | /* Description: |
1702 | * Mask subfield (continuous bits in little-endian) of 4-byte value | |
1703 | * and return the result in 4-byte value in host byte ordering. | |
1704 | */ | |
0c817338 LF |
1705 | #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ |
1706 | ( \ | |
1707 | LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ | |
1708 | (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ | |
1709 | ) | |
1710 | #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ | |
1711 | ( \ | |
1712 | LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ | |
1713 | (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ | |
1714 | ) | |
1715 | #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ | |
1716 | ( \ | |
1717 | LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ | |
1718 | (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ | |
1719 | ) | |
1720 | ||
9e0bc671 LF |
1721 | /* Description: |
1722 | * Set subfield of little-endian 4-byte value to specified value. | |
1723 | */ | |
0c817338 LF |
1724 | #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ |
1725 | *((u8 *)(__pstart)) = EF1BYTE \ | |
1726 | ( \ | |
1727 | LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ | |
1728 | ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ | |
1729 | ); | |
1730 | ||
1731 | /**************************************** | |
1732 | mem access macro define end | |
1733 | ****************************************/ | |
1734 | ||
e97b775d LF |
1735 | #define byte(x, n) ((x >> (8 * n)) & 0xff) |
1736 | ||
0c817338 LF |
1737 | #define RTL_WATCH_DOG_TIME 2000 |
1738 | #define MSECS(t) msecs_to_jiffies(t) | |
17c9ac62 LF |
1739 | #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) |
1740 | #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) | |
1741 | #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) | |
1742 | #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) | |
0c817338 LF |
1743 | #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) |
1744 | #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) | |
1745 | #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) | |
1746 | ||
1747 | #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ | |
1748 | #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ | |
1749 | #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ | |
1750 | /*NIC halt, re-initialize hw parameters*/ | |
1751 | #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) | |
1752 | #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ | |
1753 | #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ | |
1754 | /*Always enable ASPM and Clock Req in initialization.*/ | |
1755 | #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) | |
e97b775d LF |
1756 | /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/ |
1757 | #define RT_PS_LEVEL_ASPM BIT(7) | |
0c817338 LF |
1758 | /*When LPS is on, disable 2R if no packet is received or transmittd.*/ |
1759 | #define RT_RF_LPS_DISALBE_2R BIT(30) | |
1760 | #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ | |
1761 | #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \ | |
1762 | ((ppsc->cur_ps_level & _ps_flg) ? true : false) | |
1763 | #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \ | |
1764 | (ppsc->cur_ps_level &= (~(_ps_flg))) | |
1765 | #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \ | |
1766 | (ppsc->cur_ps_level |= _ps_flg) | |
1767 | ||
1768 | #define container_of_dwork_rtl(x, y, z) \ | |
1769 | container_of(container_of(x, struct delayed_work, work), y, z) | |
1770 | ||
0c817338 LF |
1771 | static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) |
1772 | { | |
1773 | return rtlpriv->io.read8_sync(rtlpriv, addr); | |
1774 | } | |
1775 | ||
1776 | static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr) | |
1777 | { | |
1778 | return rtlpriv->io.read16_sync(rtlpriv, addr); | |
1779 | } | |
1780 | ||
1781 | static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr) | |
1782 | { | |
1783 | return rtlpriv->io.read32_sync(rtlpriv, addr); | |
1784 | } | |
1785 | ||
1786 | static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) | |
1787 | { | |
1788 | rtlpriv->io.write8_async(rtlpriv, addr, val8); | |
1789 | } | |
1790 | ||
1791 | static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16) | |
1792 | { | |
1793 | rtlpriv->io.write16_async(rtlpriv, addr, val16); | |
1794 | } | |
1795 | ||
1796 | static inline void rtl_write_dword(struct rtl_priv *rtlpriv, | |
1797 | u32 addr, u32 val32) | |
1798 | { | |
1799 | rtlpriv->io.write32_async(rtlpriv, addr, val32); | |
1800 | } | |
1801 | ||
1802 | static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw, | |
1803 | u32 regaddr, u32 bitmask) | |
1804 | { | |
1805 | return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw, | |
1806 | regaddr, | |
1807 | bitmask); | |
1808 | } | |
1809 | ||
1810 | static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr, | |
1811 | u32 bitmask, u32 data) | |
1812 | { | |
1813 | ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw, | |
1814 | regaddr, bitmask, | |
1815 | data); | |
1816 | ||
1817 | } | |
1818 | ||
1819 | static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw, | |
1820 | enum radio_path rfpath, u32 regaddr, | |
1821 | u32 bitmask) | |
1822 | { | |
1823 | return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw, | |
1824 | rfpath, | |
1825 | regaddr, | |
1826 | bitmask); | |
1827 | } | |
1828 | ||
1829 | static inline void rtl_set_rfreg(struct ieee80211_hw *hw, | |
1830 | enum radio_path rfpath, u32 regaddr, | |
1831 | u32 bitmask, u32 data) | |
1832 | { | |
1833 | ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw, | |
1834 | rfpath, regaddr, | |
1835 | bitmask, data); | |
1836 | } | |
1837 | ||
1838 | static inline bool is_hal_stop(struct rtl_hal *rtlhal) | |
1839 | { | |
1840 | return (_HAL_STATE_STOP == rtlhal->state); | |
1841 | } | |
1842 | ||
1843 | static inline void set_hal_start(struct rtl_hal *rtlhal) | |
1844 | { | |
1845 | rtlhal->state = _HAL_STATE_START; | |
1846 | } | |
1847 | ||
1848 | static inline void set_hal_stop(struct rtl_hal *rtlhal) | |
1849 | { | |
1850 | rtlhal->state = _HAL_STATE_STOP; | |
1851 | } | |
1852 | ||
1853 | static inline u8 get_rf_type(struct rtl_phy *rtlphy) | |
1854 | { | |
1855 | return rtlphy->rf_type; | |
1856 | } | |
1857 | ||
1858 | #endif |