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rtlwifi: Modify some rtl8192ce routines for merging rtl8192cu
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rtlwifi / wifi.h
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0c817338
LF		 1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_WIFI_H__
31#define __RTL_WIFI_H__
32
33#include <linux/sched.h>
34#include <linux/firmware.h>
35#include <linux/version.h>
36#include <linux/etherdevice.h>
62e63975 37#include <linux/usb.h>
0c817338
LF		 38#include <net/mac80211.h>
39#include "debug.h"
40
41#define RF_CHANGE_BY_INIT 0
42#define RF_CHANGE_BY_IPS BIT(28)
43#define RF_CHANGE_BY_PS BIT(29)
44#define RF_CHANGE_BY_HW BIT(30)
45#define RF_CHANGE_BY_SW BIT(31)
46
47#define IQK_ADDA_REG_NUM 16
48#define IQK_MAC_REG_NUM 4
49
50#define MAX_KEY_LEN 61
51#define KEY_BUF_SIZE 5
52
53/* QoS related. */
54/*aci: 0x00 Best Effort*/
55/*aci: 0x01 Background*/
56/*aci: 0x10 Video*/
57/*aci: 0x11 Voice*/
58/*Max: define total number.*/
59#define AC0_BE 0
60#define AC1_BK 1
61#define AC2_VI 2
62#define AC3_VO 3
63#define AC_MAX 4
64#define QOS_QUEUE_NUM 4
65#define RTL_MAC80211_NUM_QUEUE 5
66
67#define QBSS_LOAD_SIZE 5
68#define MAX_WMMELE_LENGTH 64
69
70/*slot time for 11g. */
71#define RTL_SLOT_TIME_9 9
72#define RTL_SLOT_TIME_20 20
73
74/*related with tcp/ip. */
75/*if_ehther.h*/
76#define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
77#define ETH_P_IP 0x0800 /*Internet Protocol packet */
78#define ETH_P_ARP 0x0806 /*Address Resolution packet */
79#define SNAP_SIZE 6
80#define PROTOC_TYPE_SIZE 2
81
82/*related with 802.11 frame*/
83#define MAC80211_3ADDR_LEN 24
84#define MAC80211_4ADDR_LEN 30
85
86enum intf_type {
87 INTF_PCI = 0,
88 INTF_USB = 1,
89};
90
91enum radio_path {
92 RF90_PATH_A = 0,
93 RF90_PATH_B = 1,
94 RF90_PATH_C = 2,
95 RF90_PATH_D = 3,
96};
97
98enum rt_eeprom_type {
99 EEPROM_93C46,
100 EEPROM_93C56,
101 EEPROM_BOOT_EFUSE,
102};
103
104enum rtl_status {
105 RTL_STATUS_INTERFACE_START = 0,
106};
107
108enum hardware_type {
109 HARDWARE_TYPE_RTL8192E,
110 HARDWARE_TYPE_RTL8192U,
111 HARDWARE_TYPE_RTL8192SE,
112 HARDWARE_TYPE_RTL8192SU,
113 HARDWARE_TYPE_RTL8192CE,
114 HARDWARE_TYPE_RTL8192CU,
115 HARDWARE_TYPE_RTL8192DE,
116 HARDWARE_TYPE_RTL8192DU,
117
118 /*keep it last*/
119 HARDWARE_TYPE_NUM
120};
121
62e63975
LF		 122#define IS_HARDWARE_TYPE_8192CE(rtlhal) \
123 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
124
0c817338
LF		 125enum scan_operation_backup_opt {
126 SCAN_OPT_BACKUP = 0,
127 SCAN_OPT_RESTORE,
128 SCAN_OPT_MAX
129};
130
131/*RF state.*/
132enum rf_pwrstate {
133 ERFON,
134 ERFSLEEP,
135 ERFOFF
136};
137
138struct bb_reg_def {
139 u32 rfintfs;
140 u32 rfintfi;
141 u32 rfintfo;
142 u32 rfintfe;
143 u32 rf3wire_offset;
144 u32 rflssi_select;
145 u32 rftxgain_stage;
146 u32 rfhssi_para1;
147 u32 rfhssi_para2;
148 u32 rfswitch_control;
149 u32 rfagc_control1;
150 u32 rfagc_control2;
151 u32 rfrxiq_imbalance;
152 u32 rfrx_afe;
153 u32 rftxiq_imbalance;
154 u32 rftx_afe;
155 u32 rflssi_readback;
156 u32 rflssi_readbackpi;
157};
158
159enum io_type {
160 IO_CMD_PAUSE_DM_BY_SCAN = 0,
161 IO_CMD_RESUME_DM_BY_SCAN = 1,
162};
163
164enum hw_variables {
165 HW_VAR_ETHER_ADDR,
166 HW_VAR_MULTICAST_REG,
167 HW_VAR_BASIC_RATE,
168 HW_VAR_BSSID,
169 HW_VAR_MEDIA_STATUS,
170 HW_VAR_SECURITY_CONF,
171 HW_VAR_BEACON_INTERVAL,
172 HW_VAR_ATIM_WINDOW,
173 HW_VAR_LISTEN_INTERVAL,
174 HW_VAR_CS_COUNTER,
175 HW_VAR_DEFAULTKEY0,
176 HW_VAR_DEFAULTKEY1,
177 HW_VAR_DEFAULTKEY2,
178 HW_VAR_DEFAULTKEY3,
179 HW_VAR_SIFS,
180 HW_VAR_DIFS,
181 HW_VAR_EIFS,
182 HW_VAR_SLOT_TIME,
183 HW_VAR_ACK_PREAMBLE,
184 HW_VAR_CW_CONFIG,
185 HW_VAR_CW_VALUES,
186 HW_VAR_RATE_FALLBACK_CONTROL,
187 HW_VAR_CONTENTION_WINDOW,
188 HW_VAR_RETRY_COUNT,
189 HW_VAR_TR_SWITCH,
190 HW_VAR_COMMAND,
191 HW_VAR_WPA_CONFIG,
192 HW_VAR_AMPDU_MIN_SPACE,
193 HW_VAR_SHORTGI_DENSITY,
194 HW_VAR_AMPDU_FACTOR,
195 HW_VAR_MCS_RATE_AVAILABLE,
196 HW_VAR_AC_PARAM,
197 HW_VAR_ACM_CTRL,
198 HW_VAR_DIS_Req_Qsize,
199 HW_VAR_CCX_CHNL_LOAD,
200 HW_VAR_CCX_NOISE_HISTOGRAM,
201 HW_VAR_CCX_CLM_NHM,
202 HW_VAR_TxOPLimit,
203 HW_VAR_TURBO_MODE,
204 HW_VAR_RF_STATE,
205 HW_VAR_RF_OFF_BY_HW,
206 HW_VAR_BUS_SPEED,
207 HW_VAR_SET_DEV_POWER,
208
209 HW_VAR_RCR,
210 HW_VAR_RATR_0,
211 HW_VAR_RRSR,
212 HW_VAR_CPU_RST,
213 HW_VAR_CECHK_BSSID,
214 HW_VAR_LBK_MODE,
215 HW_VAR_AES_11N_FIX,
216 HW_VAR_USB_RX_AGGR,
217 HW_VAR_USER_CONTROL_TURBO_MODE,
218 HW_VAR_RETRY_LIMIT,
219 HW_VAR_INIT_TX_RATE,
220 HW_VAR_TX_RATE_REG,
221 HW_VAR_EFUSE_USAGE,
222 HW_VAR_EFUSE_BYTES,
223 HW_VAR_AUTOLOAD_STATUS,
224 HW_VAR_RF_2R_DISABLE,
225 HW_VAR_SET_RPWM,
226 HW_VAR_H2C_FW_PWRMODE,
227 HW_VAR_H2C_FW_JOINBSSRPT,
228 HW_VAR_FW_PSMODE_STATUS,
229 HW_VAR_1X1_RECV_COMBINE,
230 HW_VAR_STOP_SEND_BEACON,
231 HW_VAR_TSF_TIMER,
232 HW_VAR_IO_CMD,
233
234 HW_VAR_RF_RECOVERY,
235 HW_VAR_H2C_FW_UPDATE_GTK,
236 HW_VAR_WF_MASK,
237 HW_VAR_WF_CRC,
238 HW_VAR_WF_IS_MAC_ADDR,
239 HW_VAR_H2C_FW_OFFLOAD,
240 HW_VAR_RESET_WFCRC,
241
242 HW_VAR_HANDLE_FW_C2H,
243 HW_VAR_DL_FW_RSVD_PAGE,
244 HW_VAR_AID,
245 HW_VAR_HW_SEQ_ENABLE,
246 HW_VAR_CORRECT_TSF,
247 HW_VAR_BCN_VALID,
248 HW_VAR_FWLPS_RF_ON,
249 HW_VAR_DUAL_TSF_RST,
250 HW_VAR_SWITCH_EPHY_WoWLAN,
251 HW_VAR_INT_MIGRATION,
252 HW_VAR_INT_AC,
253 HW_VAR_RF_TIMING,
254
255 HW_VAR_MRC,
256
257 HW_VAR_MGT_FILTER,
258 HW_VAR_CTRL_FILTER,
259 HW_VAR_DATA_FILTER,
260};
261
262enum _RT_MEDIA_STATUS {
263 RT_MEDIA_DISCONNECT = 0,
264 RT_MEDIA_CONNECT = 1
265};
266
267enum rt_oem_id {
268 RT_CID_DEFAULT = 0,
269 RT_CID_8187_ALPHA0 = 1,
270 RT_CID_8187_SERCOMM_PS = 2,
271 RT_CID_8187_HW_LED = 3,
272 RT_CID_8187_NETGEAR = 4,
273 RT_CID_WHQL = 5,
274 RT_CID_819x_CAMEO = 6,
275 RT_CID_819x_RUNTOP = 7,
276 RT_CID_819x_Senao = 8,
277 RT_CID_TOSHIBA = 9,
278 RT_CID_819x_Netcore = 10,
279 RT_CID_Nettronix = 11,
280 RT_CID_DLINK = 12,
281 RT_CID_PRONET = 13,
282 RT_CID_COREGA = 14,
283 RT_CID_819x_ALPHA = 15,
284 RT_CID_819x_Sitecom = 16,
285 RT_CID_CCX = 17,
286 RT_CID_819x_Lenovo = 18,
287 RT_CID_819x_QMI = 19,
288 RT_CID_819x_Edimax_Belkin = 20,
289 RT_CID_819x_Sercomm_Belkin = 21,
290 RT_CID_819x_CAMEO1 = 22,
291 RT_CID_819x_MSI = 23,
292 RT_CID_819x_Acer = 24,
293 RT_CID_819x_HP = 27,
294 RT_CID_819x_CLEVO = 28,
295 RT_CID_819x_Arcadyan_Belkin = 29,
296 RT_CID_819x_SAMSUNG = 30,
297 RT_CID_819x_WNC_COREGA = 31,
298 RT_CID_819x_Foxcoon = 32,
299 RT_CID_819x_DELL = 33,
300};
301
302enum hw_descs {
303 HW_DESC_OWN,
304 HW_DESC_RXOWN,
305 HW_DESC_TX_NEXTDESC_ADDR,
306 HW_DESC_TXBUFF_ADDR,
307 HW_DESC_RXBUFF_ADDR,
308 HW_DESC_RXPKT_LEN,
309 HW_DESC_RXERO,
310};
311
312enum prime_sc {
313 PRIME_CHNL_OFFSET_DONT_CARE = 0,
314 PRIME_CHNL_OFFSET_LOWER = 1,
315 PRIME_CHNL_OFFSET_UPPER = 2,
316};
317
318enum rf_type {
319 RF_1T1R = 0,
320 RF_1T2R = 1,
321 RF_2T2R = 2,
322};
323
324enum ht_channel_width {
325 HT_CHANNEL_WIDTH_20 = 0,
326 HT_CHANNEL_WIDTH_20_40 = 1,
327};
328
329/* Ref: 802.11i sepc D10.0 7.3.2.25.1
330Cipher Suites Encryption Algorithms */
331enum rt_enc_alg {
332 NO_ENCRYPTION = 0,
333 WEP40_ENCRYPTION = 1,
334 TKIP_ENCRYPTION = 2,
335 RSERVED_ENCRYPTION = 3,
336 AESCCMP_ENCRYPTION = 4,
337 WEP104_ENCRYPTION = 5,
338};
339
340enum rtl_hal_state {
341 _HAL_STATE_STOP = 0,
342 _HAL_STATE_START = 1,
343};
344
345enum rtl_var_map {
346 /*reg map */
347 SYS_ISO_CTRL = 0,
348 SYS_FUNC_EN,
349 SYS_CLK,
350 MAC_RCR_AM,
351 MAC_RCR_AB,
352 MAC_RCR_ACRC32,
353 MAC_RCR_ACF,
354 MAC_RCR_AAP,
355
356 /*efuse map */
357 EFUSE_TEST,
358 EFUSE_CTRL,
359 EFUSE_CLK,
360 EFUSE_CLK_CTRL,
361 EFUSE_PWC_EV12V,
362 EFUSE_FEN_ELDR,
363 EFUSE_LOADER_CLK_EN,
364 EFUSE_ANA8M,
365 EFUSE_HWSET_MAX_SIZE,
366
367 /*CAM map */
368 RWCAM,
369 WCAMI,
370 RCAMO,
371 CAMDBG,
372 SECR,
373 SEC_CAM_NONE,
374 SEC_CAM_WEP40,
375 SEC_CAM_TKIP,
376 SEC_CAM_AES,
377 SEC_CAM_WEP104,
378
379 /*IMR map */
380 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
381 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
382 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
383 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
384 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
385 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
386 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
387 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
388 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
389 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
390 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
391 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
392 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
393 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
394 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
395 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
396 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
397 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
398 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
399 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
400 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
401 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
402 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
403 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
404 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
405 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
406 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
407 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
408 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
409 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
410 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
411 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
412 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt|RTL_IMR_TBDOK|RTL_IMR_TBDER)*/
413
414 /*CCK Rates, TxHT = 0 */
415 RTL_RC_CCK_RATE1M,
416 RTL_RC_CCK_RATE2M,
417 RTL_RC_CCK_RATE5_5M,
418 RTL_RC_CCK_RATE11M,
419
420 /*OFDM Rates, TxHT = 0 */
421 RTL_RC_OFDM_RATE6M,
422 RTL_RC_OFDM_RATE9M,
423 RTL_RC_OFDM_RATE12M,
424 RTL_RC_OFDM_RATE18M,
425 RTL_RC_OFDM_RATE24M,
426 RTL_RC_OFDM_RATE36M,
427 RTL_RC_OFDM_RATE48M,
428 RTL_RC_OFDM_RATE54M,
429
430 RTL_RC_HT_RATEMCS7,
431 RTL_RC_HT_RATEMCS15,
432
433 /*keep it last */
434 RTL_VAR_MAP_MAX,
435};
436
437/*Firmware PS mode for control LPS.*/
438enum _fw_ps_mode {
439 FW_PS_ACTIVE_MODE = 0,
440 FW_PS_MIN_MODE = 1,
441 FW_PS_MAX_MODE = 2,
442 FW_PS_DTIM_MODE = 3,
443 FW_PS_VOIP_MODE = 4,
444 FW_PS_UAPSD_WMM_MODE = 5,
445 FW_PS_UAPSD_MODE = 6,
446 FW_PS_IBSS_MODE = 7,
447 FW_PS_WWLAN_MODE = 8,
448 FW_PS_PM_Radio_Off = 9,
449 FW_PS_PM_Card_Disable = 10,
450};
451
452enum rt_psmode {
453 EACTIVE, /*Active/Continuous access. */
454 EMAXPS, /*Max power save mode. */
455 EFASTPS, /*Fast power save mode. */
456 EAUTOPS, /*Auto power save mode. */
457};
458
459/*LED related.*/
460enum led_ctl_mode {
461 LED_CTL_POWER_ON = 1,
462 LED_CTL_LINK = 2,
463 LED_CTL_NO_LINK = 3,
464 LED_CTL_TX = 4,
465 LED_CTL_RX = 5,
466 LED_CTL_SITE_SURVEY = 6,
467 LED_CTL_POWER_OFF = 7,
468 LED_CTL_START_TO_LINK = 8,
469 LED_CTL_START_WPS = 9,
470 LED_CTL_STOP_WPS = 10,
471};
472
473enum rtl_led_pin {
474 LED_PIN_GPIO0,
475 LED_PIN_LED0,
476 LED_PIN_LED1,
477 LED_PIN_LED2
478};
479
480/*QoS related.*/
481/*acm implementation method.*/
482enum acm_method {
483 eAcmWay0_SwAndHw = 0,
484 eAcmWay1_HW = 1,
485 eAcmWay2_SW = 2,
486};
487
488/*aci/aifsn Field.
489Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
490union aci_aifsn {
491 u8 char_data;
492
493 struct {
494 u8 aifsn:4;
495 u8 acm:1;
496 u8 aci:2;
497 u8 reserved:1;
498 } f; /* Field */
499};
500
501/*mlme related.*/
502enum wireless_mode {
503 WIRELESS_MODE_UNKNOWN = 0x00,
504 WIRELESS_MODE_A = 0x01,
505 WIRELESS_MODE_B = 0x02,
506 WIRELESS_MODE_G = 0x04,
507 WIRELESS_MODE_AUTO = 0x08,
508 WIRELESS_MODE_N_24G = 0x10,
509 WIRELESS_MODE_N_5G = 0x20
510};
511
512enum ratr_table_mode {
513 RATR_INX_WIRELESS_NGB = 0,
514 RATR_INX_WIRELESS_NG = 1,
515 RATR_INX_WIRELESS_NB = 2,
516 RATR_INX_WIRELESS_N = 3,
517 RATR_INX_WIRELESS_GB = 4,
518 RATR_INX_WIRELESS_G = 5,
519 RATR_INX_WIRELESS_B = 6,
520 RATR_INX_WIRELESS_MC = 7,
521 RATR_INX_WIRELESS_A = 8,
522};
523
524enum rtl_link_state {
525 MAC80211_NOLINK = 0,
526 MAC80211_LINKING = 1,
527 MAC80211_LINKED = 2,
528 MAC80211_LINKED_SCANNING = 3,
529};
530
531enum act_category {
532 ACT_CAT_QOS = 1,
533 ACT_CAT_DLS = 2,
534 ACT_CAT_BA = 3,
535 ACT_CAT_HT = 7,
536 ACT_CAT_WMM = 17,
537};
538
539enum ba_action {
540 ACT_ADDBAREQ = 0,
541 ACT_ADDBARSP = 1,
542 ACT_DELBA = 2,
543};
544
545struct octet_string {
546 u8 *octet;
547 u16 length;
548};
549
550struct rtl_hdr_3addr {
551 __le16 frame_ctl;
552 __le16 duration_id;
553 u8 addr1[ETH_ALEN];
554 u8 addr2[ETH_ALEN];
555 u8 addr3[ETH_ALEN];
556 __le16 seq_ctl;
557 u8 payload[0];
e137478b 558} __packed;
0c817338
LF		 559
560struct rtl_info_element {
561 u8 id;
562 u8 len;
563 u8 data[0];
e137478b 564} __packed;
0c817338
LF		 565
566struct rtl_probe_rsp {
567 struct rtl_hdr_3addr header;
568 u32 time_stamp[2];
569 __le16 beacon_interval;
570 __le16 capability;
571 /*SSID, supported rates, FH params, DS params,
572 CF params, IBSS params, TIM (if beacon), RSN */
573 struct rtl_info_element info_element[0];
e137478b 574} __packed;
0c817338
LF		 575
576/*LED related.*/
577/*ledpin Identify how to implement this SW led.*/
578struct rtl_led {
579 void *hw;
580 enum rtl_led_pin ledpin;
7ea47240 581 bool ledon;
0c817338
LF		 582};
583
584struct rtl_led_ctl {
7ea47240 585 bool led_opendrain;
0c817338
LF		 586 struct rtl_led sw_led0;
587 struct rtl_led sw_led1;
588};
589
590struct rtl_qos_parameters {
591 __le16 cw_min;
592 __le16 cw_max;
593 u8 aifs;
594 u8 flag;
595 __le16 tx_op;
e137478b 596} __packed;
0c817338
LF		 597
598struct rt_smooth_data {
599 u32 elements[100]; /*array to store values */
600 u32 index; /*index to current array to store */
601 u32 total_num; /*num of valid elements */
602 u32 total_val; /*sum of valid elements */
603};
604
605struct false_alarm_statistics {
606 u32 cnt_parity_fail;
607 u32 cnt_rate_illegal;
608 u32 cnt_crc8_fail;
609 u32 cnt_mcs_fail;
610 u32 cnt_ofdm_fail;
611 u32 cnt_cck_fail;
612 u32 cnt_all;
613};
614
615struct init_gain {
616 u8 xaagccore1;
617 u8 xbagccore1;
618 u8 xcagccore1;
619 u8 xdagccore1;
620 u8 cca;
621
622};
623
624struct wireless_stats {
625 unsigned long txbytesunicast;
626 unsigned long txbytesmulticast;
627 unsigned long txbytesbroadcast;
628 unsigned long rxbytesunicast;
629
630 long rx_snr_db[4];
631 /*Correct smoothed ss in Dbm, only used
632 in driver to report real power now. */
633 long recv_signal_power;
634 long signal_quality;
635 long last_sigstrength_inpercent;
636
637 u32 rssi_calculate_cnt;
638
639 /*Transformed, in dbm. Beautified signal
640 strength for UI, not correct. */
641 long signal_strength;
642
643 u8 rx_rssi_percentage[4];
644 u8 rx_evm_percentage[2];
645
646 struct rt_smooth_data ui_rssi;
647 struct rt_smooth_data ui_link_quality;
648};
649
650struct rate_adaptive {
651 u8 rate_adaptive_disabled;
652 u8 ratr_state;
653 u16 reserve;
654
655 u32 high_rssi_thresh_for_ra;
656 u32 high2low_rssi_thresh_for_ra;
657 u8 low2high_rssi_thresh_for_ra40m;
658 u32 low_rssi_thresh_for_ra40M;
659 u8 low2high_rssi_thresh_for_ra20m;
660 u32 low_rssi_thresh_for_ra20M;
661 u32 upper_rssi_threshold_ratr;
662 u32 middleupper_rssi_threshold_ratr;
663 u32 middle_rssi_threshold_ratr;
664 u32 middlelow_rssi_threshold_ratr;
665 u32 low_rssi_threshold_ratr;
666 u32 ultralow_rssi_threshold_ratr;
667 u32 low_rssi_threshold_ratr_40m;
668 u32 low_rssi_threshold_ratr_20m;
669 u8 ping_rssi_enable;
670 u32 ping_rssi_ratr;
671 u32 ping_rssi_thresh_for_ra;
672 u32 last_ratr;
673 u8 pre_ratr_state;
674};
675
676struct regd_pair_mapping {
677 u16 reg_dmnenum;
678 u16 reg_5ghz_ctl;
679 u16 reg_2ghz_ctl;
680};
681
682struct rtl_regulatory {
683 char alpha2[2];
684 u16 country_code;
685 u16 max_power_level;
686 u32 tp_scale;
687 u16 current_rd;
688 u16 current_rd_ext;
689 int16_t power_limit;
690 struct regd_pair_mapping *regpair;
691};
692
693struct rtl_rfkill {
694 bool rfkill_state; /*0 is off, 1 is on */
695};
696
697struct rtl_phy {
698 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
699 struct init_gain initgain_backup;
700 enum io_type current_io_type;
701
702 u8 rf_mode;
703 u8 rf_type;
704 u8 current_chan_bw;
705 u8 set_bwmode_inprogress;
706 u8 sw_chnl_inprogress;
707 u8 sw_chnl_stage;
708 u8 sw_chnl_step;
709 u8 current_channel;
710 u8 h2c_box_num;
711 u8 set_io_inprogress;
712
713 /*record for power tracking*/
714 s32 reg_e94;
715 s32 reg_e9c;
716 s32 reg_ea4;
717 s32 reg_eac;
718 s32 reg_eb4;
719 s32 reg_ebc;
720 s32 reg_ec4;
721 s32 reg_ecc;
722 u8 rfpienable;
723 u8 reserve_0;
724 u16 reserve_1;
725 u32 reg_c04, reg_c08, reg_874;
726 u32 adda_backup[16];
727 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
728 u32 iqk_bb_backup[10];
729
7ea47240 730 bool rfpi_enable;
0c817338
LF		 731
732 u8 pwrgroup_cnt;
7ea47240 733 u8 cck_high_power;
0c817338
LF		 734 /* 3 groups of pwr diff by rates*/
735 u32 mcs_txpwrlevel_origoffset[4][16];
736 u8 default_initialgain[4];
737
738 /*the current Tx power level*/
739 u8 cur_cck_txpwridx;
740 u8 cur_ofdm24g_txpwridx;
741
742 u32 rfreg_chnlval[2];
7ea47240 743 bool apk_done;
0c817338
LF		 744
745 /*fsync*/
746 u8 framesync;
747 u32 framesync_c34;
748
749 u8 num_total_rfpath;
750};
751
752#define MAX_TID_COUNT 9
753#define RTL_AGG_OFF 0
754#define RTL_AGG_ON 1
755#define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
756#define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
757
758struct rtl_ht_agg {
759 u16 txq_id;
760 u16 wait_for_ba;
761 u16 start_idx;
762 u64 bitmap;
763 u32 rate_n_flags;
764 u8 agg_state;
765};
766
767struct rtl_tid_data {
768 u16 seq_number;
769 struct rtl_ht_agg agg;
770};
771
772struct rtl_priv;
773struct rtl_io {
774 struct device *dev;
62e63975 775 struct mutex bb_mutex;
0c817338
LF		 776
777 /*PCI MEM map */
778 unsigned long pci_mem_end; /*shared mem end */
779 unsigned long pci_mem_start; /*shared mem start */
780
781 /*PCI IO map */
782 unsigned long pci_base_addr; /*device I/O address */
783
784 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
785 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
786 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
62e63975
LF		 787 int (*writeN_async) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
788 u8 *pdata);
0c817338
LF		 789
790 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
791 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
792 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
62e63975
LF		 793 int (*readN_sync) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
794 u8 *pdata);
0c817338
LF		 795
796};
797
798struct rtl_mac {
799 u8 mac_addr[ETH_ALEN];
800 u8 mac80211_registered;
801 u8 beacon_enabled;
802
803 u32 tx_ss_num;
804 u32 rx_ss_num;
805
806 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
807 struct ieee80211_hw *hw;
808 struct ieee80211_vif *vif;
809 enum nl80211_iftype opmode;
810
811 /*Probe Beacon management */
812 struct rtl_tid_data tids[MAX_TID_COUNT];
813 enum rtl_link_state link_state;
814
815 int n_channels;
816 int n_bitrates;
817
818 /*filters */
819 u32 rx_conf;
820 u16 rx_mgt_filter;
821 u16 rx_ctrl_filter;
822 u16 rx_data_filter;
823
824 bool act_scanning;
825 u8 cnt_after_linked;
826
827 /*RDG*/ bool rdg_en;
828
829 /*AP*/ u8 bssid[6];
830 u8 mcs[16]; /*16 bytes mcs for HT rates.*/
831 u32 basic_rates; /*b/g rates*/
832 u8 ht_enable;
833 u8 sgi_40;
834 u8 sgi_20;
835 u8 bw_40;
836 u8 mode; /*wireless mode*/
837 u8 slot_time;
838 u8 short_preamble;
839 u8 use_cts_protect;
840 u8 cur_40_prime_sc;
841 u8 cur_40_prime_sc_bk;
842 u64 tsf;
843 u8 retry_short;
844 u8 retry_long;
845 u16 assoc_id;
846
847 /*IBSS*/ int beacon_interval;
848
849 /*AMPDU*/ u8 min_space_cfg; /*For Min spacing configurations */
850 u8 max_mss_density;
851 u8 current_ampdu_factor;
852 u8 current_ampdu_density;
853
854 /*QOS & EDCA */
855 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
856 struct rtl_qos_parameters ac[AC_MAX];
857};
858
859struct rtl_hal {
860 struct ieee80211_hw *hw;
861
862 enum intf_type interface;
863 u16 hw_type; /*92c or 92d or 92s and so on */
864 u8 oem_id;
865 u8 version; /*version of chip */
866 u8 state; /*stop 0, start 1 */
867
868 /*firmware */
869 u8 *pfirmware;
7ea47240 870 bool h2c_setinprogress;
0c817338 871 u8 last_hmeboxnum;
7ea47240 872 bool fw_ready;
0c817338
LF		 873 /*Reserve page start offset except beacon in TxQ. */
874 u8 fw_rsvdpage_startoffset;
875};
876
877struct rtl_security {
878 /*default 0 */
879 bool use_sw_sec;
880
881 bool being_setkey;
882 bool use_defaultkey;
883 /*Encryption Algorithm for Unicast Packet */
884 enum rt_enc_alg pairwise_enc_algorithm;
885 /*Encryption Algorithm for Brocast/Multicast */
886 enum rt_enc_alg group_enc_algorithm;
887
888 /*local Key buffer, indx 0 is for
889 pairwise key 1-4 is for agoup key. */
890 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
891 u8 key_len[KEY_BUF_SIZE];
892
893 /*The pointer of Pairwise Key,
894 it always points to KeyBuf[4] */
895 u8 *pairwise_key;
896};
897
898struct rtl_dm {
8c96fcf7 899 /*PHY status for DM (dynamic management) */
0c817338
LF		 900 long entry_min_undecoratedsmoothed_pwdb;
901 long undecorated_smoothed_pwdb; /*out dm */
902 long entry_max_undecoratedsmoothed_pwdb;
7ea47240
LF		 903 bool dm_initialgain_enable;
904 bool dynamic_txpower_enable;
905 bool current_turbo_edca;
906 bool is_any_nonbepkts; /*out dm */
907 bool is_cur_rdlstate;
908 bool txpower_trackingInit;
909 bool disable_framebursting;
910 bool cck_inch14;
911 bool txpower_tracking;
912 bool useramask;
913 bool rfpath_rxenable[4];
0c817338
LF		 914
915 u8 thermalvalue_iqk;
916 u8 thermalvalue_lck;
917 u8 thermalvalue;
918 u8 last_dtp_lvl;
919 u8 dynamic_txhighpower_lvl; /*Tx high power level */
920 u8 dm_flag; /*Indicate if each dynamic mechanism's status. */
921 u8 dm_type;
922 u8 txpower_track_control;
923
924 char ofdm_index[2];
925 char cck_index;
926};
927
928#define EFUSE_MAX_LOGICAL_SIZE 128
929
930struct rtl_efuse {
7ea47240 931 bool autoLoad_ok;
0c817338
LF		 932 bool bootfromefuse;
933 u16 max_physical_size;
934 u8 contents[EFUSE_MAX_LOGICAL_SIZE];
935
936 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
937 u16 efuse_usedbytes;
938 u8 efuse_usedpercentage;
939
940 u8 autoload_failflag;
941
942 short epromtype;
943 u16 eeprom_vid;
944 u16 eeprom_did;
945 u16 eeprom_svid;
946 u16 eeprom_smid;
947 u8 eeprom_oemid;
948 u16 eeprom_channelplan;
949 u8 eeprom_version;
950
951 u8 dev_addr[6];
952
7ea47240 953 bool txpwr_fromeprom;
0c817338
LF		 954 u8 eeprom_tssi[2];
955 u8 eeprom_pwrlimit_ht20[3];
956 u8 eeprom_pwrlimit_ht40[3];
957 u8 eeprom_chnlarea_txpwr_cck[2][3];
958 u8 eeprom_chnlarea_txpwr_ht40_1s[2][3];
959 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][3];
960 u8 txpwrlevel_cck[2][14];
961 u8 txpwrlevel_ht40_1s[2][14]; /*For HT 40MHZ pwr */
962 u8 txpwrlevel_ht40_2s[2][14]; /*For HT 40MHZ pwr */
963
964 /*For power group */
965 u8 pwrgroup_ht20[2][14];
966 u8 pwrgroup_ht40[2][14];
967
968 char txpwr_ht20diff[2][14]; /*HT 20<->40 Pwr diff */
969 u8 txpwr_legacyhtdiff[2][14]; /*For HT<->legacy pwr diff */
970
971 u8 eeprom_regulatory;
972 u8 eeprom_thermalmeter;
973 /*ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
974 u8 thermalmeter[2];
975
976 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
7ea47240 977 bool apk_thermalmeterignore;
0c817338
LF		 978};
979
980struct rtl_ps_ctl {
981 bool set_rfpowerstate_inprogress;
7ea47240 982 bool in_powersavemode;
0c817338 983 bool rfchange_inprogress;
7ea47240
LF		 984 bool swrf_processing;
985 bool hwradiooff;
0c817338
LF		 986
987 u32 last_sleep_jiffies;
988 u32 last_awake_jiffies;
989 u32 last_delaylps_stamp_jiffies;
990
991 /*
992 * just for PCIE ASPM
993 * If it supports ASPM, Offset[560h] = 0x40,
994 * otherwise Offset[560h] = 0x00.
995 * */
7ea47240
LF		 996 bool support_aspm;
997 bool support_backdoor;
0c817338
LF		 998
999 /*for LPS */
1000 enum rt_psmode dot11_psmode; /*Power save mode configured. */
7ea47240
LF		 1001 bool leisure_ps;
1002 bool fwctrl_lps;
0c817338
LF		 1003 u8 fwctrl_psmode;
1004 /*For Fw control LPS mode */
7ea47240 1005 u8 reg_fwctrl_lps;
0c817338 1006 /*Record Fw PS mode status. */
7ea47240 1007 bool fw_current_inpsmode;
0c817338
LF		 1008 u8 reg_max_lps_awakeintvl;
1009 bool report_linked;
1010
1011 /*for IPS */
7ea47240 1012 bool inactiveps;
0c817338
LF		 1013
1014 u32 rfoff_reason;
1015
1016 /*RF OFF Level */
1017 u32 cur_ps_level;
1018 u32 reg_rfps_level;
1019
1020 /*just for PCIE ASPM */
1021 u8 const_amdpci_aspm;
1022
1023 enum rf_pwrstate inactive_pwrstate;
1024 enum rf_pwrstate rfpwr_state; /*cur power state */
1025};
1026
1027struct rtl_stats {
1028 u32 mac_time[2];
1029 s8 rssi;
1030 u8 signal;
1031 u8 noise;
1032 u16 rate; /*in 100 kbps */
1033 u8 received_channel;
1034 u8 control;
1035 u8 mask;
1036 u8 freq;
1037 u16 len;
1038 u64 tsf;
1039 u32 beacon_time;
1040 u8 nic_type;
1041 u16 length;
1042 u8 signalquality; /*in 0-100 index. */
1043 /*
1044 * Real power in dBm for this packet,
1045 * no beautification and aggregation.
1046 * */
1047 s32 recvsignalpower;
1048 s8 rxpower; /*in dBm Translate from PWdB */
1049 u8 signalstrength; /*in 0-100 index. */
7ea47240
LF		 1050 u16 hwerror:1;
1051 u16 crc:1;
1052 u16 icv:1;
1053 u16 shortpreamble:1;
0c817338
LF		 1054 u16 antenna:1;
1055 u16 decrypted:1;
1056 u16 wakeup:1;
1057 u32 timestamp_low;
1058 u32 timestamp_high;
1059
1060 u8 rx_drvinfo_size;
1061 u8 rx_bufshift;
7ea47240 1062 bool isampdu;
0c817338
LF		 1063 bool rx_is40Mhzpacket;
1064 u32 rx_pwdb_all;
1065 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1066 s8 rx_mimo_signalquality[2];
7ea47240
LF		 1067 bool packet_matchbssid;
1068 bool is_cck;
1069 bool packet_toself;
1070 bool packet_beacon; /*for rssi */
0c817338
LF		 1071 char cck_adc_pwdb[4]; /*for rx path selection */
1072};
1073
1074struct rt_link_detect {
1075 u32 num_tx_in4period[4];
1076 u32 num_rx_in4period[4];
1077
1078 u32 num_tx_inperiod;
1079 u32 num_rx_inperiod;
1080
7ea47240
LF		 1081 bool busytraffic;
1082 bool higher_busytraffic;
1083 bool higher_busyrxtraffic;
0c817338
LF		 1084};
1085
1086struct rtl_tcb_desc {
7ea47240
LF		 1087 u8 packet_bw:1;
1088 u8 multicast:1;
1089 u8 broadcast:1;
1090
1091 u8 rts_stbc:1;
1092 u8 rts_enable:1;
1093 u8 cts_enable:1;
1094 u8 rts_use_shortpreamble:1;
1095 u8 rts_use_shortgi:1;
0c817338 1096 u8 rts_sc:1;
7ea47240 1097 u8 rts_bw:1;
0c817338
LF		 1098 u8 rts_rate;
1099
1100 u8 use_shortgi:1;
1101 u8 use_shortpreamble:1;
1102 u8 use_driver_rate:1;
1103 u8 disable_ratefallback:1;
1104
1105 u8 ratr_index;
1106 u8 mac_id;
1107 u8 hw_rate;
1108};
1109
1110struct rtl_hal_ops {
1111 int (*init_sw_vars) (struct ieee80211_hw *hw);
1112 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
62e63975 1113 void (*read_chip_version)(struct ieee80211_hw *hw);
0c817338
LF		 1114 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1115 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1116 u32 *p_inta, u32 *p_intb);
1117 int (*hw_init) (struct ieee80211_hw *hw);
1118 void (*hw_disable) (struct ieee80211_hw *hw);
1119 void (*enable_interrupt) (struct ieee80211_hw *hw);
1120 void (*disable_interrupt) (struct ieee80211_hw *hw);
1121 int (*set_network_type) (struct ieee80211_hw *hw,
1122 enum nl80211_iftype type);
1123 void (*set_bw_mode) (struct ieee80211_hw *hw,
1124 enum nl80211_channel_type ch_type);
1125 u8(*switch_channel) (struct ieee80211_hw *hw);
1126 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1127 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1128 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1129 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1130 u32 add_msr, u32 rm_msr);
1131 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1132 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1133 void (*update_rate_table) (struct ieee80211_hw *hw);
1134 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1135 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1136 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1137 struct ieee80211_tx_info *info,
1138 struct sk_buff *skb, unsigned int queue_index);
1139 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
7ea47240 1140 bool firstseg, bool lastseg,
0c817338 1141 struct sk_buff *skb);
62e63975 1142 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
7ea47240 1143 bool (*query_rx_desc) (struct ieee80211_hw *hw,
0c817338
LF		 1144 struct rtl_stats *stats,
1145 struct ieee80211_rx_status *rx_status,
1146 u8 *pdesc, struct sk_buff *skb);
1147 void (*set_channel_access) (struct ieee80211_hw *hw);
7ea47240 1148 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
0c817338
LF		 1149 void (*dm_watchdog) (struct ieee80211_hw *hw);
1150 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
7ea47240 1151 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
0c817338
LF		 1152 enum rf_pwrstate rfpwr_state);
1153 void (*led_control) (struct ieee80211_hw *hw,
1154 enum led_ctl_mode ledaction);
1155 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
7ea47240 1156 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
0c817338
LF		 1157 void (*tx_polling) (struct ieee80211_hw *hw, unsigned int hw_queue);
1158 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1159 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1160 u8 *p_macaddr, bool is_group, u8 enc_algo,
1161 bool is_wepkey, bool clear_all);
1162 void (*init_sw_leds) (struct ieee80211_hw *hw);
1163 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
7ea47240 1164 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
0c817338
LF		 1165 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1166 u32 data);
7ea47240 1167 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
0c817338
LF		 1168 u32 regaddr, u32 bitmask);
1169 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1170 u32 regaddr, u32 bitmask, u32 data);
1171};
1172
1173struct rtl_intf_ops {
1174 /*com */
1175 int (*adapter_start) (struct ieee80211_hw *hw);
1176 void (*adapter_stop) (struct ieee80211_hw *hw);
1177
1178 int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb);
1179 int (*reset_trx_ring) (struct ieee80211_hw *hw);
62e63975 1180 bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
0c817338
LF		 1181
1182 /*pci */
1183 void (*disable_aspm) (struct ieee80211_hw *hw);
1184 void (*enable_aspm) (struct ieee80211_hw *hw);
1185
1186 /*usb */
1187};
1188
1189struct rtl_mod_params {
1190 /* default: 0 = using hardware encryption */
1191 int sw_crypto;
1192};
1193
62e63975
LF		 1194struct rtl_hal_usbint_cfg {
1195 /* data - rx */
1196 u32 in_ep_num;
1197 u32 rx_urb_num;
1198 u32 rx_max_size;
1199
1200 /* op - rx */
1201 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1202 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1203 struct sk_buff_head *);
1204
1205 /* tx */
1206 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1207 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1208 struct sk_buff *);
1209 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1210 struct sk_buff_head *);
1211
1212 /* endpoint mapping */
1213 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1214 u16 (*usb_mq_to_hwq)(u16 fc, u16 mac80211_queue_index);
1215};
1216
0c817338
LF		 1217struct rtl_hal_cfg {
1218 char *name;
1219 char *fw_name;
1220 struct rtl_hal_ops *ops;
1221 struct rtl_mod_params *mod_params;
62e63975 1222 struct rtl_hal_usbint_cfg *usb_interface_cfg;
0c817338
LF		 1223
1224 /*this map used for some registers or vars
1225 defined int HAL but used in MAIN */
1226 u32 maps[RTL_VAR_MAP_MAX];
1227
1228};
1229
1230struct rtl_locks {
d704300f 1231 /* mutex */
8a09d6d8 1232 struct mutex conf_mutex;
0c817338
LF		 1233
1234 /*spin lock */
d704300f 1235 spinlock_t ips_lock;
0c817338
LF		 1236 spinlock_t irq_th_lock;
1237 spinlock_t h2c_lock;
1238 spinlock_t rf_ps_lock;
1239 spinlock_t rf_lock;
1240 spinlock_t lps_lock;
62e63975 1241 spinlock_t tx_urb_lock;
0c817338
LF		 1242};
1243
1244struct rtl_works {
1245 struct ieee80211_hw *hw;
1246
1247 /*timer */
1248 struct timer_list watchdog_timer;
1249
1250 /*task */
1251 struct tasklet_struct irq_tasklet;
1252 struct tasklet_struct irq_prepare_bcn_tasklet;
1253
1254 /*work queue */
1255 struct workqueue_struct *rtl_wq;
1256 struct delayed_work watchdog_wq;
1257 struct delayed_work ips_nic_off_wq;
1258};
1259
1260struct rtl_debug {
1261 u32 dbgp_type[DBGP_TYPE_MAX];
1262 u32 global_debuglevel;
1263 u64 global_debugcomponents;
1264};
1265
1266struct rtl_priv {
1267 struct rtl_locks locks;
1268 struct rtl_works works;
1269 struct rtl_mac mac80211;
1270 struct rtl_hal rtlhal;
1271 struct rtl_regulatory regd;
1272 struct rtl_rfkill rfkill;
1273 struct rtl_io io;
1274 struct rtl_phy phy;
1275 struct rtl_dm dm;
1276 struct rtl_security sec;
1277 struct rtl_efuse efuse;
1278
1279 struct rtl_ps_ctl psc;
1280 struct rate_adaptive ra;
1281 struct wireless_stats stats;
1282 struct rt_link_detect link_info;
1283 struct false_alarm_statistics falsealm_cnt;
1284
1285 struct rtl_rate_priv *rate_priv;
1286
1287 struct rtl_debug dbg;
1288
1289 /*
1290 *hal_cfg : for diff cards
1291 *intf_ops : for diff interrface usb/pcie
1292 */
1293 struct rtl_hal_cfg *cfg;
1294 struct rtl_intf_ops *intf_ops;
1295
1296 /*this var will be set by set_bit,
1297 and was used to indicate status of
1298 interface or hardware */
1299 unsigned long status;
1300
1301 /*This must be the last item so
1302 that it points to the data allocated
1303 beyond this structure like:
1304 rtl_pci_priv or rtl_usb_priv */
1305 u8 priv[0];
1306};
1307
1308#define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
1309#define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
1310#define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
1311#define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1312#define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1313
1314/****************************************
1315 mem access macro define start
1316 Call endian free function when
1317 1. Read/write packet content.
1318 2. Before write integer to IO.
1319 3. After read integer from IO.
1320****************************************/
1321/* Convert little data endian to host */
1322#define EF1BYTE(_val) \
1323 ((u8)(_val))
1324#define EF2BYTE(_val) \
1325 (le16_to_cpu(_val))
1326#define EF4BYTE(_val) \
1327 (le32_to_cpu(_val))
1328
1329/* Read data from memory */
1330#define READEF1BYTE(_ptr) \
1331 EF1BYTE(*((u8 *)(_ptr)))
1332#define READEF2BYTE(_ptr) \
1333 EF2BYTE(*((u16 *)(_ptr)))
1334#define READEF4BYTE(_ptr) \
1335 EF4BYTE(*((u32 *)(_ptr)))
1336
1337/* Write data to memory */
1338#define WRITEEF1BYTE(_ptr, _val) \
1339 (*((u8 *)(_ptr))) = EF1BYTE(_val)
1340#define WRITEEF2BYTE(_ptr, _val) \
1341 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1342#define WRITEEF4BYTE(_ptr, _val) \
1343 (*((u32 *)(_ptr))) = EF4BYTE(_val)
1344
1345/*Example:
1346BIT_LEN_MASK_32(0) => 0x00000000
1347BIT_LEN_MASK_32(1) => 0x00000001
1348BIT_LEN_MASK_32(2) => 0x00000003
1349BIT_LEN_MASK_32(32) => 0xFFFFFFFF*/
1350#define BIT_LEN_MASK_32(__bitlen) \
1351 (0xFFFFFFFF >> (32 - (__bitlen)))
1352#define BIT_LEN_MASK_16(__bitlen) \
1353 (0xFFFF >> (16 - (__bitlen)))
1354#define BIT_LEN_MASK_8(__bitlen) \
1355 (0xFF >> (8 - (__bitlen)))
1356
1357/*Example:
1358BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1359BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000*/
1360#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1361 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1362#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1363 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1364#define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1365 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1366
1367/*Description:
1368Return 4-byte value in host byte ordering from
13694-byte pointer in little-endian system.*/
1370#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1371 (EF4BYTE(*((u32 *)(__pstart))))
1372#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1373 (EF2BYTE(*((u16 *)(__pstart))))
1374#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1375 (EF1BYTE(*((u8 *)(__pstart))))
1376
1377/*Description:
1378Translate subfield (continuous bits in little-endian) of 4-byte
1379value to host byte ordering.*/
1380#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1381 ( \
1382 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
1383 BIT_LEN_MASK_32(__bitlen) \
1384 )
1385#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1386 ( \
1387 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1388 BIT_LEN_MASK_16(__bitlen) \
1389 )
1390#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1391 ( \
1392 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1393 BIT_LEN_MASK_8(__bitlen) \
1394 )
1395
1396/*Description:
1397Mask subfield (continuous bits in little-endian) of 4-byte value
1398and return the result in 4-byte value in host byte ordering.*/
1399#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1400 ( \
1401 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
1402 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1403 )
1404#define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1405 ( \
1406 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1407 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1408 )
1409#define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1410 ( \
1411 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1412 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1413 )
1414
1415/*Description:
1416Set subfield of little-endian 4-byte value to specified value. */
1417#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1418 *((u32 *)(__pstart)) = EF4BYTE \
1419 ( \
1420 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1421 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1422 );
1423#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1424 *((u16 *)(__pstart)) = EF2BYTE \
1425 ( \
1426 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1427 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1428 );
1429#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1430 *((u8 *)(__pstart)) = EF1BYTE \
1431 ( \
1432 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1433 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1434 );
1435
1436/****************************************
1437 mem access macro define end
1438****************************************/
1439
1440#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1441#define RTL_WATCH_DOG_TIME 2000
1442#define MSECS(t) msecs_to_jiffies(t)
1443#define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS)
1444#define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE)
1445#define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE)
1446#define WLAN_FC_MORE_DATA(fc) ((fc) & IEEE80211_FCTL_MOREDATA)
1447#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1448#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1449#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
1450
1451#define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
1452#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
1453#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
1454/*NIC halt, re-initialize hw parameters*/
1455#define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
1456#define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
1457#define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
1458/*Always enable ASPM and Clock Req in initialization.*/
1459#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
1460/*When LPS is on, disable 2R if no packet is received or transmittd.*/
1461#define RT_RF_LPS_DISALBE_2R BIT(30)
1462#define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
1463#define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
1464 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1465#define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
1466 (ppsc->cur_ps_level &= (~(_ps_flg)))
1467#define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
1468 (ppsc->cur_ps_level |= _ps_flg)
1469
1470#define container_of_dwork_rtl(x, y, z) \
1471 container_of(container_of(x, struct delayed_work, work), y, z)
1472
1473#define FILL_OCTET_STRING(_os, _octet, _len) \
1474 (_os).octet = (u8 *)(_octet); \
1475 (_os).length = (_len);
1476
62e63975
LF		 1477#define CP_MACADDR(des, src) \
1478 memcpy((des), (src), ETH_ALEN)
0c817338
LF		 1479
1480static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1481{
1482 return rtlpriv->io.read8_sync(rtlpriv, addr);
1483}
1484
1485static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1486{
1487 return rtlpriv->io.read16_sync(rtlpriv, addr);
1488}
1489
1490static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1491{
1492 return rtlpriv->io.read32_sync(rtlpriv, addr);
1493}
1494
1495static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1496{
1497 rtlpriv->io.write8_async(rtlpriv, addr, val8);
1498}
1499
1500static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1501{
1502 rtlpriv->io.write16_async(rtlpriv, addr, val16);
1503}
1504
1505static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1506 u32 addr, u32 val32)
1507{
1508 rtlpriv->io.write32_async(rtlpriv, addr, val32);
1509}
1510
1511static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1512 u32 regaddr, u32 bitmask)
1513{
1514 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1515 regaddr,
1516 bitmask);
1517}
1518
1519static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1520 u32 bitmask, u32 data)
1521{
1522 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1523 regaddr, bitmask,
1524 data);
1525
1526}
1527
1528static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1529 enum radio_path rfpath, u32 regaddr,
1530 u32 bitmask)
1531{
1532 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1533 rfpath,
1534 regaddr,
1535 bitmask);
1536}
1537
1538static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1539 enum radio_path rfpath, u32 regaddr,
1540 u32 bitmask, u32 data)
1541{
1542 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1543 rfpath, regaddr,
1544 bitmask, data);
1545}
1546
1547static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1548{
1549 return (_HAL_STATE_STOP == rtlhal->state);
1550}
1551
1552static inline void set_hal_start(struct rtl_hal *rtlhal)
1553{
1554 rtlhal->state = _HAL_STATE_START;
1555}
1556
1557static inline void set_hal_stop(struct rtl_hal *rtlhal)
1558{
1559 rtlhal->state = _HAL_STATE_STOP;
1560}
1561
1562static inline u8 get_rf_type(struct rtl_phy *rtlphy)
1563{
1564 return rtlphy->rf_type;
1565}
1566
1567#endif
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