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Commit | Line | Data |
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521a5b21 TP |
1 | /* |
2 | * This file is part of wl1271 | |
3 | * | |
4 | * Copyright (C) 1998-2009 Texas Instruments. All rights reserved. | |
5 | * Copyright (C) 2008-2010 Nokia Corporation | |
6 | * | |
7 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
00d20100 SL |
25 | #ifndef __IO_H__ |
26 | #define __IO_H__ | |
521a5b21 | 27 | |
a6b7a407 | 28 | #include <linux/irqreturn.h> |
760d969f TP |
29 | |
30 | #define HW_ACCESS_MEMORY_MAX_RANGE 0x1FFC0 | |
31 | ||
32 | #define HW_PARTITION_REGISTERS_ADDR 0x1FFC0 | |
33 | #define HW_PART0_SIZE_ADDR (HW_PARTITION_REGISTERS_ADDR) | |
34 | #define HW_PART0_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 4) | |
35 | #define HW_PART1_SIZE_ADDR (HW_PARTITION_REGISTERS_ADDR + 8) | |
36 | #define HW_PART1_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 12) | |
37 | #define HW_PART2_SIZE_ADDR (HW_PARTITION_REGISTERS_ADDR + 16) | |
38 | #define HW_PART2_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 20) | |
39 | #define HW_PART3_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 24) | |
40 | ||
41 | #define HW_ACCESS_REGISTER_SIZE 4 | |
42 | ||
43 | #define HW_ACCESS_PRAM_MAX_RANGE 0x3c000 | |
44 | ||
521a5b21 TP |
45 | struct wl1271; |
46 | ||
dd5512eb | 47 | void wlcore_disable_interrupts(struct wl1271 *wl); |
b666bb7f | 48 | void wlcore_disable_interrupts_nosync(struct wl1271 *wl); |
dd5512eb | 49 | void wlcore_enable_interrupts(struct wl1271 *wl); |
54f7e503 | 50 | |
9b280722 TP |
51 | void wl1271_io_reset(struct wl1271 *wl); |
52 | void wl1271_io_init(struct wl1271 *wl); | |
25a43d78 | 53 | int wlcore_translate_addr(struct wl1271 *wl, int addr); |
521a5b21 | 54 | |
b42f91ba | 55 | /* Raw target IO, address is not translated */ |
0c2a6ce0 IY |
56 | static inline int wlcore_raw_write(struct wl1271 *wl, int addr, void *buf, |
57 | size_t len, bool fixed) | |
b42f91ba | 58 | { |
0c2a6ce0 | 59 | return wl->if_ops->write(wl->dev, addr, buf, len, fixed); |
b42f91ba | 60 | } |
7b048c52 | 61 | |
0c2a6ce0 IY |
62 | static inline int wlcore_raw_read(struct wl1271 *wl, int addr, void *buf, |
63 | size_t len, bool fixed) | |
b42f91ba | 64 | { |
0c2a6ce0 | 65 | return wl->if_ops->read(wl->dev, addr, buf, len, fixed); |
b42f91ba | 66 | } |
7b048c52 | 67 | |
8b7c0fc3 IY |
68 | static inline int wlcore_raw_read_data(struct wl1271 *wl, int reg, void *buf, |
69 | size_t len, bool fixed) | |
00782136 | 70 | { |
8b7c0fc3 | 71 | return wlcore_raw_read(wl, wl->rtable[reg], buf, len, fixed); |
00782136 LC |
72 | } |
73 | ||
8b7c0fc3 IY |
74 | static inline int wlcore_raw_write_data(struct wl1271 *wl, int reg, void *buf, |
75 | size_t len, bool fixed) | |
00782136 | 76 | { |
8b7c0fc3 | 77 | return wlcore_raw_write(wl, wl->rtable[reg], buf, len, fixed); |
00782136 LC |
78 | } |
79 | ||
6134323f | 80 | static inline int wlcore_raw_read32(struct wl1271 *wl, int addr, u32 *val) |
7b048c52 | 81 | { |
6134323f IY |
82 | int ret; |
83 | ||
84 | ret = wlcore_raw_read(wl, addr, &wl->buffer_32, | |
85 | sizeof(wl->buffer_32), false); | |
86 | if (ret < 0) | |
87 | return ret; | |
88 | ||
89 | if (val) | |
90 | *val = le32_to_cpu(wl->buffer_32); | |
7b048c52 | 91 | |
6134323f | 92 | return 0; |
7b048c52 TP |
93 | } |
94 | ||
b0f0ad39 | 95 | static inline int wlcore_raw_write32(struct wl1271 *wl, int addr, u32 val) |
7b048c52 | 96 | { |
554d7209 | 97 | wl->buffer_32 = cpu_to_le32(val); |
b0f0ad39 IY |
98 | return wlcore_raw_write(wl, addr, &wl->buffer_32, |
99 | sizeof(wl->buffer_32), false); | |
7b048c52 | 100 | } |
2d5e82b8 | 101 | |
045b9b5f IY |
102 | static inline int wlcore_read(struct wl1271 *wl, int addr, void *buf, |
103 | size_t len, bool fixed) | |
b42f91ba TP |
104 | { |
105 | int physical; | |
106 | ||
25a43d78 | 107 | physical = wlcore_translate_addr(wl, addr); |
b42f91ba | 108 | |
045b9b5f | 109 | return wlcore_raw_read(wl, physical, buf, len, fixed); |
b42f91ba TP |
110 | } |
111 | ||
eb96f841 IY |
112 | static inline int wlcore_write(struct wl1271 *wl, int addr, void *buf, |
113 | size_t len, bool fixed) | |
b42f91ba TP |
114 | { |
115 | int physical; | |
116 | ||
25a43d78 | 117 | physical = wlcore_translate_addr(wl, addr); |
b42f91ba | 118 | |
eb96f841 | 119 | return wlcore_raw_write(wl, physical, buf, len, fixed); |
b42f91ba TP |
120 | } |
121 | ||
eb96f841 IY |
122 | static inline int wlcore_write_data(struct wl1271 *wl, int reg, void *buf, |
123 | size_t len, bool fixed) | |
00782136 | 124 | { |
eb96f841 | 125 | return wlcore_write(wl, wl->rtable[reg], buf, len, fixed); |
00782136 LC |
126 | } |
127 | ||
045b9b5f | 128 | static inline int wlcore_read_data(struct wl1271 *wl, int reg, void *buf, |
00782136 LC |
129 | size_t len, bool fixed) |
130 | { | |
045b9b5f | 131 | return wlcore_read(wl, wl->rtable[reg], buf, len, fixed); |
00782136 LC |
132 | } |
133 | ||
95dac04f IY |
134 | static inline void wl1271_read_hwaddr(struct wl1271 *wl, int hwaddr, |
135 | void *buf, size_t len, bool fixed) | |
136 | { | |
137 | int physical; | |
138 | int addr; | |
139 | ||
140 | /* Addresses are stored internally as addresses to 32 bytes blocks */ | |
141 | addr = hwaddr << 5; | |
142 | ||
25a43d78 | 143 | physical = wlcore_translate_addr(wl, addr); |
95dac04f | 144 | |
0c2a6ce0 | 145 | wlcore_raw_read(wl, physical, buf, len, fixed); |
95dac04f IY |
146 | } |
147 | ||
6134323f | 148 | static inline int wlcore_read32(struct wl1271 *wl, int addr, u32 *val) |
b42f91ba | 149 | { |
6134323f | 150 | return wlcore_raw_read32(wl, wlcore_translate_addr(wl, addr), val); |
b42f91ba TP |
151 | } |
152 | ||
b0f0ad39 | 153 | static inline int wlcore_write32(struct wl1271 *wl, int addr, u32 val) |
b42f91ba | 154 | { |
b0f0ad39 | 155 | return wlcore_raw_write32(wl, wlcore_translate_addr(wl, addr), val); |
b42f91ba TP |
156 | } |
157 | ||
6134323f | 158 | static inline int wlcore_read_reg(struct wl1271 *wl, int reg, u32 *val) |
00782136 | 159 | { |
6134323f IY |
160 | return wlcore_raw_read32(wl, |
161 | wlcore_translate_addr(wl, wl->rtable[reg]), | |
162 | val); | |
00782136 LC |
163 | } |
164 | ||
b0f0ad39 | 165 | static inline int wlcore_write_reg(struct wl1271 *wl, int reg, u32 val) |
00782136 | 166 | { |
b0f0ad39 IY |
167 | return wlcore_raw_write32(wl, |
168 | wlcore_translate_addr(wl, wl->rtable[reg]), | |
169 | val); | |
00782136 LC |
170 | } |
171 | ||
becd551c TP |
172 | static inline void wl1271_power_off(struct wl1271 *wl) |
173 | { | |
645865fc IY |
174 | int ret; |
175 | ||
176 | if (!test_bit(WL1271_FLAG_GPIO_POWER, &wl->flags)) | |
177 | return; | |
178 | ||
179 | ret = wl->if_ops->power(wl->dev, false); | |
180 | if (!ret) | |
181 | clear_bit(WL1271_FLAG_GPIO_POWER, &wl->flags); | |
becd551c TP |
182 | } |
183 | ||
2cc78ff7 | 184 | static inline int wl1271_power_on(struct wl1271 *wl) |
becd551c | 185 | { |
a390e85c | 186 | int ret = wl->if_ops->power(wl->dev, true); |
2cc78ff7 OBC |
187 | if (ret == 0) |
188 | set_bit(WL1271_FLAG_GPIO_POWER, &wl->flags); | |
189 | ||
190 | return ret; | |
becd551c TP |
191 | } |
192 | ||
b0f0ad39 IY |
193 | int wlcore_set_partition(struct wl1271 *wl, |
194 | const struct wlcore_partition_set *p); | |
b42f91ba | 195 | |
4b32a2c9 FB |
196 | bool wl1271_set_block_size(struct wl1271 *wl); |
197 | ||
2d5e82b8 TP |
198 | /* Functions from wl1271_main.c */ |
199 | ||
ae47c45f | 200 | int wl1271_tx_dummy_packet(struct wl1271 *wl); |
2d5e82b8 | 201 | |
521a5b21 | 202 | #endif |