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f5fc0f86 LC |
1 | /* |
2 | * This file is part of wl1271 | |
3 | * | |
4 | * Copyright (C) 1998-2009 Texas Instruments. All rights reserved. | |
5 | * Copyright (C) 2009 Nokia Corporation | |
6 | * | |
7 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
00d20100 SL |
25 | #ifndef __TX_H__ |
26 | #define __TX_H__ | |
f5fc0f86 | 27 | |
f5fc0f86 | 28 | #define TX_HW_MGMT_PKT_LIFETIME_TU 2000 |
beb6c880 | 29 | #define TX_HW_AP_MODE_PKT_LIFETIME_TU 8000 |
f5fc0f86 LC |
30 | |
31 | #define TX_HW_ATTR_SAVE_RETRIES BIT(0) | |
32 | #define TX_HW_ATTR_HEADER_PAD BIT(1) | |
33 | #define TX_HW_ATTR_SESSION_COUNTER (BIT(2) | BIT(3) | BIT(4)) | |
34 | #define TX_HW_ATTR_RATE_POLICY (BIT(5) | BIT(6) | BIT(7) | \ | |
35 | BIT(8) | BIT(9)) | |
36 | #define TX_HW_ATTR_LAST_WORD_PAD (BIT(10) | BIT(11)) | |
37 | #define TX_HW_ATTR_TX_CMPLT_REQ BIT(12) | |
ae47c45f | 38 | #define TX_HW_ATTR_TX_DUMMY_REQ BIT(13) |
f4f57943 | 39 | #define TX_HW_ATTR_HOST_ENCRYPT BIT(14) |
2a5ad92e | 40 | #define TX_HW_ATTR_EAPOL_FRAME BIT(15) |
ae47c45f | 41 | |
f5fc0f86 LC |
42 | #define TX_HW_ATTR_OFST_SAVE_RETRIES 0 |
43 | #define TX_HW_ATTR_OFST_HEADER_PAD 1 | |
44 | #define TX_HW_ATTR_OFST_SESSION_COUNTER 2 | |
45 | #define TX_HW_ATTR_OFST_RATE_POLICY 5 | |
46 | #define TX_HW_ATTR_OFST_LAST_WORD_PAD 10 | |
47 | #define TX_HW_ATTR_OFST_TX_CMPLT_REQ 12 | |
48 | ||
49 | #define TX_HW_RESULT_QUEUE_LEN 16 | |
50 | #define TX_HW_RESULT_QUEUE_LEN_MASK 0xf | |
51 | ||
52 | #define WL1271_TX_ALIGN_TO 4 | |
5ec8a448 EP |
53 | #define WL1271_EXTRA_SPACE_TKIP 4 |
54 | #define WL1271_EXTRA_SPACE_AES 8 | |
55 | #define WL1271_EXTRA_SPACE_MAX 8 | |
f5fc0f86 | 56 | |
ae47c45f SL |
57 | /* Used for management frames and dummy packets */ |
58 | #define WL1271_TID_MGMT 7 | |
59 | ||
187e52cc AN |
60 | /* stop a ROC for pending authentication reply after this time (ms) */ |
61 | #define WLCORE_PEND_AUTH_ROC_TIMEOUT 1000 | |
62 | ||
48a61477 SL |
63 | struct wl127x_tx_mem { |
64 | /* | |
65 | * Number of extra memory blocks to allocate for this packet | |
66 | * in addition to the number of blocks derived from the packet | |
67 | * length. | |
68 | */ | |
69 | u8 extra_blocks; | |
70 | /* | |
71 | * Total number of memory blocks allocated by the host for | |
72 | * this packet. Must be equal or greater than the actual | |
73 | * blocks number allocated by HW. | |
74 | */ | |
75 | u8 total_mem_blocks; | |
76 | } __packed; | |
77 | ||
78 | struct wl128x_tx_mem { | |
79 | /* | |
80 | * Total number of memory blocks allocated by the host for | |
81 | * this packet. | |
82 | */ | |
83 | u8 total_mem_blocks; | |
84 | /* | |
85 | * Number of extra bytes, at the end of the frame. the host | |
86 | * uses this padding to complete each frame to integer number | |
87 | * of SDIO blocks. | |
88 | */ | |
89 | u8 extra_bytes; | |
90 | } __packed; | |
91 | ||
fb0f2e4a AN |
92 | struct wl18xx_tx_mem { |
93 | /* | |
94 | * Total number of memory blocks allocated by the host for | |
95 | * this packet. | |
96 | */ | |
97 | u8 total_mem_blocks; | |
98 | ||
99 | /* | |
9fccc82e | 100 | * control bits |
fb0f2e4a | 101 | */ |
9fccc82e | 102 | u8 ctrl; |
fb0f2e4a AN |
103 | } __packed; |
104 | ||
0da13da7 IY |
105 | /* |
106 | * On wl128x based devices, when TX packets are aggregated, each packet | |
107 | * size must be aligned to the SDIO block size. The maximum block size | |
108 | * is bounded by the type of the padded bytes field that is sent to the | |
109 | * FW. Currently the type is u8, so the maximum block size is 256 bytes. | |
110 | */ | |
111 | #define WL12XX_BUS_BLOCK_SIZE min(512u, \ | |
112 | (1u << (8 * sizeof(((struct wl128x_tx_mem *) 0)->extra_bytes)))) | |
113 | ||
f5fc0f86 LC |
114 | struct wl1271_tx_hw_descr { |
115 | /* Length of packet in words, including descriptor+header+data */ | |
d0f63b20 | 116 | __le16 length; |
48a61477 SL |
117 | union { |
118 | struct wl127x_tx_mem wl127x_mem; | |
119 | struct wl128x_tx_mem wl128x_mem; | |
fb0f2e4a | 120 | struct wl18xx_tx_mem wl18xx_mem; |
48a61477 | 121 | } __packed; |
f5fc0f86 | 122 | /* Device time (in us) when the packet arrived to the driver */ |
d0f63b20 | 123 | __le32 start_time; |
48a61477 SL |
124 | /* |
125 | * Max delay in TUs until transmission. The last device time the | |
126 | * packet can be transmitted is: start_time + (1024 * life_time) | |
127 | */ | |
d0f63b20 | 128 | __le16 life_time; |
f5fc0f86 | 129 | /* Bitwise fields - see TX_ATTR... definitions above. */ |
d0f63b20 | 130 | __le16 tx_attr; |
f5fc0f86 LC |
131 | /* Packet identifier used also in the Tx-Result. */ |
132 | u8 id; | |
133 | /* The packet TID value (as User-Priority) */ | |
134 | u8 tid; | |
79b122dc EP |
135 | /* host link ID (HLID) */ |
136 | u8 hlid; | |
2fc28de5 AN |
137 | |
138 | union { | |
139 | u8 wl12xx_reserved; | |
140 | ||
141 | /* | |
142 | * bit 0 -> 0 = udp, 1 = tcp | |
143 | * bit 1:7 -> IP header offset | |
144 | */ | |
145 | u8 wl18xx_checksum_data; | |
146 | } __packed; | |
ba2d3587 | 147 | } __packed; |
f5fc0f86 LC |
148 | |
149 | enum wl1271_tx_hw_res_status { | |
150 | TX_SUCCESS = 0, | |
151 | TX_HW_ERROR = 1, | |
152 | TX_DISABLED = 2, | |
153 | TX_RETRY_EXCEEDED = 3, | |
154 | TX_TIMEOUT = 4, | |
155 | TX_KEY_NOT_FOUND = 5, | |
156 | TX_PEER_NOT_FOUND = 6, | |
79b122dc EP |
157 | TX_SESSION_MISMATCH = 7, |
158 | TX_LINK_NOT_VALID = 8, | |
f5fc0f86 LC |
159 | }; |
160 | ||
161 | struct wl1271_tx_hw_res_descr { | |
162 | /* Packet Identifier - same value used in the Tx descriptor.*/ | |
163 | u8 id; | |
164 | /* The status of the transmission, indicating success or one of | |
165 | several possible reasons for failure. */ | |
166 | u8 status; | |
167 | /* Total air access duration including all retrys and overheads.*/ | |
d0f63b20 | 168 | __le16 medium_usage; |
f5fc0f86 | 169 | /* The time passed from host xfer to Tx-complete.*/ |
d0f63b20 | 170 | __le32 fw_handling_time; |
f5fc0f86 LC |
171 | /* Total media delay |
172 | (from 1st EDCA AIFS counter until TX Complete). */ | |
d0f63b20 | 173 | __le32 medium_delay; |
f5fc0f86 | 174 | /* LS-byte of last TKIP seq-num (saved per AC for recovery). */ |
b992c682 | 175 | u8 tx_security_sequence_number_lsb; |
f5fc0f86 LC |
176 | /* Retry count - number of transmissions without successful ACK.*/ |
177 | u8 ack_failures; | |
178 | /* The rate that succeeded getting ACK | |
179 | (Valid only if status=SUCCESS). */ | |
180 | u8 rate_class_index; | |
181 | /* for 4-byte alignment. */ | |
182 | u8 spare; | |
ba2d3587 | 183 | } __packed; |
f5fc0f86 LC |
184 | |
185 | struct wl1271_tx_hw_res_if { | |
d0f63b20 LC |
186 | __le32 tx_result_fw_counter; |
187 | __le32 tx_result_host_counter; | |
f5fc0f86 | 188 | struct wl1271_tx_hw_res_descr tx_results_queue[TX_HW_RESULT_QUEUE_LEN]; |
ba2d3587 | 189 | } __packed; |
f5fc0f86 | 190 | |
66396114 AN |
191 | enum wlcore_queue_stop_reason { |
192 | WLCORE_QUEUE_STOP_REASON_WATERMARK, | |
193 | WLCORE_QUEUE_STOP_REASON_FW_RESTART, | |
2c38849f | 194 | WLCORE_QUEUE_STOP_REASON_FLUSH, |
a1c597f2 | 195 | WLCORE_QUEUE_STOP_REASON_SPARE_BLK, /* 18xx specific */ |
66396114 AN |
196 | }; |
197 | ||
c6999d83 KV |
198 | static inline int wl1271_tx_get_queue(int queue) |
199 | { | |
c6999d83 KV |
200 | switch (queue) { |
201 | case 0: | |
202 | return CONF_TX_AC_VO; | |
203 | case 1: | |
204 | return CONF_TX_AC_VI; | |
205 | case 2: | |
206 | return CONF_TX_AC_BE; | |
207 | case 3: | |
208 | return CONF_TX_AC_BK; | |
209 | default: | |
210 | return CONF_TX_AC_BE; | |
211 | } | |
212 | } | |
213 | ||
1c33db78 AN |
214 | static inline |
215 | int wlcore_tx_get_mac80211_queue(struct wl12xx_vif *wlvif, int queue) | |
708bb3cf | 216 | { |
1c33db78 AN |
217 | int mac_queue = wlvif->hw_queue_base; |
218 | ||
708bb3cf AN |
219 | switch (queue) { |
220 | case CONF_TX_AC_VO: | |
1c33db78 | 221 | return mac_queue + 0; |
708bb3cf | 222 | case CONF_TX_AC_VI: |
1c33db78 | 223 | return mac_queue + 1; |
708bb3cf | 224 | case CONF_TX_AC_BE: |
1c33db78 | 225 | return mac_queue + 2; |
708bb3cf | 226 | case CONF_TX_AC_BK: |
1c33db78 | 227 | return mac_queue + 3; |
708bb3cf | 228 | default: |
1c33db78 | 229 | return mac_queue + 2; |
708bb3cf AN |
230 | } |
231 | } | |
232 | ||
f1a46384 AN |
233 | static inline int wl1271_tx_total_queue_count(struct wl1271 *wl) |
234 | { | |
235 | int i, count = 0; | |
236 | ||
237 | for (i = 0; i < NUM_TX_QUEUES; i++) | |
238 | count += wl->tx_queue_count[i]; | |
239 | ||
240 | return count; | |
241 | } | |
242 | ||
f5fc0f86 | 243 | void wl1271_tx_work(struct work_struct *work); |
eb96f841 | 244 | int wlcore_tx_work_locked(struct wl1271 *wl); |
045b9b5f | 245 | int wlcore_tx_complete(struct wl1271 *wl); |
d6a3cc2e | 246 | void wl12xx_tx_reset_wlvif(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
66396114 | 247 | void wl12xx_tx_reset(struct wl1271 *wl); |
f5fc0f86 | 248 | void wl1271_tx_flush(struct wl1271 *wl); |
57fbcce3 | 249 | u8 wlcore_rate_to_idx(struct wl1271 *wl, u8 rate, enum nl80211_band band); |
af7fbb28 | 250 | u32 wl1271_tx_enabled_rates_get(struct wl1271 *wl, u32 rate_set, |
57fbcce3 | 251 | enum nl80211_band rate_band); |
af7fbb28 | 252 | u32 wl1271_tx_min_rate_get(struct wl1271 *wl, u32 rate_set); |
d6a3cc2e | 253 | u8 wl12xx_tx_get_hlid(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
2b2b6438 | 254 | struct sk_buff *skb, struct ieee80211_sta *sta); |
a8c0ddb5 AN |
255 | void wl1271_tx_reset_link_queues(struct wl1271 *wl, u8 hlid); |
256 | void wl1271_handle_tx_low_watermark(struct wl1271 *wl); | |
f8e0af6b | 257 | bool wl12xx_is_dummy_packet(struct wl1271 *wl, struct sk_buff *skb); |
9eb599e9 | 258 | void wl12xx_rearm_rx_streaming(struct wl1271 *wl, unsigned long *active_hlids); |
b3b4b4b8 AN |
259 | unsigned int wlcore_calc_packet_alignment(struct wl1271 *wl, |
260 | unsigned int packet_length); | |
872b345f | 261 | void wl1271_free_tx_id(struct wl1271 *wl, int id); |
1c33db78 AN |
262 | void wlcore_stop_queue_locked(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
263 | u8 queue, enum wlcore_queue_stop_reason reason); | |
264 | void wlcore_stop_queue(struct wl1271 *wl, struct wl12xx_vif *wlvif, u8 queue, | |
66396114 | 265 | enum wlcore_queue_stop_reason reason); |
1c33db78 | 266 | void wlcore_wake_queue(struct wl1271 *wl, struct wl12xx_vif *wlvif, u8 queue, |
66396114 AN |
267 | enum wlcore_queue_stop_reason reason); |
268 | void wlcore_stop_queues(struct wl1271 *wl, | |
269 | enum wlcore_queue_stop_reason reason); | |
270 | void wlcore_wake_queues(struct wl1271 *wl, | |
271 | enum wlcore_queue_stop_reason reason); | |
1c33db78 AN |
272 | bool wlcore_is_queue_stopped_by_reason(struct wl1271 *wl, |
273 | struct wl12xx_vif *wlvif, u8 queue, | |
66396114 | 274 | enum wlcore_queue_stop_reason reason); |
d6037d22 AN |
275 | bool |
276 | wlcore_is_queue_stopped_by_reason_locked(struct wl1271 *wl, | |
277 | struct wl12xx_vif *wlvif, | |
278 | u8 queue, | |
279 | enum wlcore_queue_stop_reason reason); | |
280 | bool wlcore_is_queue_stopped_locked(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
281 | u8 queue); | |
f5fc0f86 | 282 | |
f1acea9a | 283 | /* from main.c */ |
c7ffb902 | 284 | void wl1271_free_sta(struct wl1271 *wl, struct wl12xx_vif *wlvif, u8 hlid); |
55df5afb | 285 | void wl12xx_rearm_tx_watchdog_locked(struct wl1271 *wl); |
f1acea9a | 286 | |
f5fc0f86 | 287 | #endif |