[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ti / wlcore / wlcore.h

/*
 * This file is part of wlcore
 *
 * Copyright (C) 2011 Texas Instruments Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#ifndef __WLCORE_H__
#define __WLCORE_H__

#include <linux/platform_device.h>

#include "wl12xx.h"
#include "event.h"

/* The maximum number of Tx descriptors in all chip families */
#define WLCORE_MAX_TX_DESCRIPTORS 32

/* forward declaration */
struct wl1271_tx_hw_descr;
enum wl_rx_buf_align;

struct wlcore_ops {
	int (*identify_chip)(struct wl1271 *wl);
	int (*identify_fw)(struct wl1271 *wl);
	int (*boot)(struct wl1271 *wl);
	void (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
			    void *buf, size_t len);
	void (*ack_event)(struct wl1271 *wl);
	u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
	void (*set_tx_desc_blocks)(struct wl1271 *wl,
				   struct wl1271_tx_hw_descr *desc,
				   u32 blks, u32 spare_blks);
	void (*set_tx_desc_data_len)(struct wl1271 *wl,
				     struct wl1271_tx_hw_descr *desc,
				     struct sk_buff *skb);
	enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
						 u32 rx_desc);
	void (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
	u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
				 u32 data_len);
	void (*tx_delayed_compl)(struct wl1271 *wl);
	void (*tx_immediate_compl)(struct wl1271 *wl);
	int (*hw_init)(struct wl1271 *wl);
	int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
	u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
				    struct wl12xx_vif *wlvif);
	s8 (*get_pg_ver)(struct wl1271 *wl);
	void (*get_mac)(struct wl1271 *wl);
};

enum wlcore_partitions {
	PART_DOWN,
	PART_WORK,
	PART_BOOT,
	PART_DRPW,
	PART_TOP_PRCM_ELP_SOC,
	PART_PHY_INIT,

	PART_TABLE_LEN,
};

struct wlcore_partition {
	u32 size;
	u32 start;
};

struct wlcore_partition_set {
	struct wlcore_partition mem;
	struct wlcore_partition reg;
	struct wlcore_partition mem2;
	struct wlcore_partition mem3;
};

enum wlcore_registers {
	/* register addresses, used with partition translation */
	REG_ECPU_CONTROL,
	REG_INTERRUPT_NO_CLEAR,
	REG_INTERRUPT_ACK,
	REG_COMMAND_MAILBOX_PTR,
	REG_EVENT_MAILBOX_PTR,
	REG_INTERRUPT_TRIG,
	REG_INTERRUPT_MASK,
	REG_PC_ON_RECOVERY,
	REG_CHIP_ID_B,
	REG_CMD_MBOX_ADDRESS,

	/* data access memory addresses, used with partition translation */
	REG_SLV_MEM_DATA,
	REG_SLV_REG_DATA,

	/* raw data access memory addresses */
	REG_RAW_FW_STATUS_ADDR,

	REG_TABLE_LEN,
};

struct wl1271 {
	struct ieee80211_hw *hw;
	bool mac80211_registered;

	struct device *dev;

	void *if_priv;

	struct wl1271_if_operations *if_ops;

	void (*set_power)(bool enable);
	int irq;
	int ref_clock;

	spinlock_t wl_lock;

	enum wl1271_state state;
	enum wl12xx_fw_type fw_type;
	bool plt;
	u8 last_vif_count;
	struct mutex mutex;

	unsigned long flags;

	struct wlcore_partition_set curr_part;

	struct wl1271_chip chip;

	int cmd_box_addr;

	u8 *fw;
	size_t fw_len;
	void *nvs;
	size_t nvs_len;

	s8 hw_pg_ver;

	/* address read from the fuse ROM */
	u32 fuse_oui_addr;
	u32 fuse_nic_addr;

	/* we have up to 2 MAC addresses */
	struct mac_address addresses[2];
	int channel;
	u8 system_hlid;

	unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
	unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
	unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
	unsigned long rate_policies_map[
			BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];

	struct list_head wlvif_list;

	u8 sta_count;
	u8 ap_count;

	struct wl1271_acx_mem_map *target_mem_map;

	/* Accounting for allocated / available TX blocks on HW */
	u32 tx_blocks_freed;
	u32 tx_blocks_available;
	u32 tx_allocated_blocks;
	u32 tx_results_count;

	/* Accounting for allocated / available Tx packets in HW */
	u32 tx_pkts_freed[NUM_TX_QUEUES];
	u32 tx_allocated_pkts[NUM_TX_QUEUES];

	/* Transmitted TX packets counter for chipset interface */
	u32 tx_packets_count;

	/* Time-offset between host and chipset clocks */
	s64 time_offset;

	/* Frames scheduled for transmission, not handled yet */
	int tx_queue_count[NUM_TX_QUEUES];
	long stopped_queues_map;

	/* Frames received, not handled yet by mac80211 */
	struct sk_buff_head deferred_rx_queue;

	/* Frames sent, not returned yet to mac80211 */
	struct sk_buff_head deferred_tx_queue;

	struct work_struct tx_work;
	struct workqueue_struct *freezable_wq;

	/* Pending TX frames */
	unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
	struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
	int tx_frames_cnt;

	/* FW Rx counter */
	u32 rx_counter;

	/* Rx memory pool address */
	struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;

	/* Intermediate buffer, used for packet aggregation */
	u8 *aggr_buf;

	/* Reusable dummy packet template */
	struct sk_buff *dummy_packet;

	/* Network stack work  */
	struct work_struct netstack_work;

	/* FW log buffer */
	u8 *fwlog;

	/* Number of valid bytes in the FW log buffer */
	ssize_t fwlog_size;

	/* Sysfs FW log entry readers wait queue */
	wait_queue_head_t fwlog_waitq;

	/* Hardware recovery work */
	struct work_struct recovery_work;

	/* Pointer that holds DMA-friendly block for the mailbox */
	struct event_mailbox *mbox;

	/* The mbox event mask */
	u32 event_mask;

	/* Mailbox pointers */
	u32 mbox_ptr[2];

	/* Are we currently scanning */
	struct ieee80211_vif *scan_vif;
	struct wl1271_scan scan;
	struct delayed_work scan_complete_work;

	/* Connection loss work */
	struct delayed_work connection_loss_work;

	bool sched_scanning;

	/* The current band */
	enum ieee80211_band band;

	struct completion *elp_compl;
	struct delayed_work elp_work;

	/* in dBm */
	int power_level;

	struct wl1271_stats stats;

	__le32 buffer_32;
	u32 buffer_cmd;
	u32 buffer_busyword[WL1271_BUSY_WORD_CNT];

	struct wl_fw_status *fw_status;
	struct wl1271_tx_hw_res_if *tx_res_if;

	/* Current chipset configuration */
	struct wlcore_conf conf;

	bool sg_enabled;

	bool enable_11a;

	/* Most recently reported noise in dBm */
	s8 noise;

	/* bands supported by this instance of wl12xx */
	struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];

	int tcxo_clock;

	/*
	 * wowlan trigger was configured during suspend.
	 * (currently, only "ANY" trigger is supported)
	 */
	bool wow_enabled;
	bool irq_wake_enabled;

	/*
	 * AP-mode - links indexed by HLID. The global and broadcast links
	 * are always active.
	 */
	struct wl1271_link links[WL12XX_MAX_LINKS];

	/* AP-mode - a bitmap of links currently in PS mode according to FW */
	u32 ap_fw_ps_map;

	/* AP-mode - a bitmap of links currently in PS mode in mac80211 */
	unsigned long ap_ps_map;

	/* Quirks of specific hardware revisions */
	unsigned int quirks;

	/* Platform limitations */
	unsigned int platform_quirks;

	/* number of currently active RX BA sessions */
	int ba_rx_session_count;

	/* AP-mode - number of currently connected stations */
	int active_sta_count;

	/* last wlvif we transmitted from */
	struct wl12xx_vif *last_wlvif;

	/* work to fire when Tx is stuck */
	struct delayed_work tx_watchdog_work;

	struct wlcore_ops *ops;
	/* pointer to the lower driver partition table */
	const struct wlcore_partition_set *ptable;
	/* pointer to the lower driver register table */
	const int *rtable;
	/* name of the firmwares to load - for PLT, single role, multi-role */
	const char *plt_fw_name;
	const char *sr_fw_name;
	const char *mr_fw_name;

	/* per-chip-family private structure */
	void *priv;

	/* number of TX descriptors the HW supports. */
	u32 num_tx_desc;

	/* spare Tx blocks for normal/GEM operating modes */
	u32 normal_tx_spare;
	u32 gem_tx_spare;

	/* translate HW Tx rates to standard rate-indices */
	const u8 **band_rate_to_idx;

	/* size of table for HW rates that can be received from chip */
	u8 hw_tx_rate_tbl_size;

	/* this HW rate and below are considered HT rates for this chip */
	u8 hw_min_ht_rate;

	/* HW HT (11n) capabilities */
	struct ieee80211_sta_ht_cap ht_cap;

	/* size of the private FW status data */
	size_t fw_status_priv_len;

	/* RX Data filter rule state - enabled/disabled */
	bool rx_filter_enabled[WL1271_MAX_RX_FILTERS];
};

int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
int __devexit wlcore_remove(struct platform_device *pdev);
struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size);
int wlcore_free_hw(struct wl1271 *wl);

/* Firmware image load chunk size */
#define CHUNK_SIZE	16384

/* Quirks */

/* Each RX/TX transaction requires an end-of-transaction transfer */
#define WLCORE_QUIRK_END_OF_TRANSACTION		BIT(0)

/* wl127x and SPI don't support SDIO block size alignment */
#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN		BIT(2)

/* means aggregated Rx packets are aligned to a SDIO block */
#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN		BIT(3)

/* Older firmwares did not implement the FW logger over bus feature */
#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED	BIT(4)

/* Older firmwares use an old NVS format */
#define WLCORE_QUIRK_LEGACY_NVS			BIT(5)

/* Some firmwares may not support ELP */
#define WLCORE_QUIRK_NO_ELP			BIT(6)

/* TODO: move to the lower drivers when all usages are abstracted */
#define CHIP_ID_1271_PG10              (0x4030101)
#define CHIP_ID_1271_PG20              (0x4030111)
#define CHIP_ID_1283_PG10              (0x05030101)
#define CHIP_ID_1283_PG20              (0x05030111)

/* TODO: move all these common registers and values elsewhere */
#define HW_ACCESS_ELP_CTRL_REG		0x1FFFC

/* ELP register commands */
#define ELPCTRL_WAKE_UP             0x1
#define ELPCTRL_WAKE_UP_WLAN_READY  0x5
#define ELPCTRL_SLEEP               0x0
/* ELP WLAN_READY bit */
#define ELPCTRL_WLAN_READY          0x2

/*************************************************************************

    Interrupt Trigger Register (Host -> WiLink)

**************************************************************************/

/* Hardware to Embedded CPU Interrupts - first 32-bit register set */

/*
 * The host sets this bit to inform the Wlan
 * FW that a TX packet is in the XFER
 * Buffer #0.
 */
#define INTR_TRIG_TX_PROC0 BIT(2)

/*
 * The host sets this bit to inform the FW
 * that it read a packet from RX XFER
 * Buffer #0.
 */
#define INTR_TRIG_RX_PROC0 BIT(3)

#define INTR_TRIG_DEBUG_ACK BIT(4)

#define INTR_TRIG_STATE_CHANGED BIT(5)

/* Hardware to Embedded CPU Interrupts - second 32-bit register set */

/*
 * The host sets this bit to inform the FW
 * that it read a packet from RX XFER
 * Buffer #1.
 */
#define INTR_TRIG_RX_PROC1 BIT(17)

/*
 * The host sets this bit to inform the Wlan
 * hardware that a TX packet is in the XFER
 * Buffer #1.
 */
#define INTR_TRIG_TX_PROC1 BIT(18)

#define ACX_SLV_SOFT_RESET_BIT	BIT(1)
#define SOFT_RESET_MAX_TIME	1000000
#define SOFT_RESET_STALL_TIME	1000

#define ECPU_CONTROL_HALT	0x00000101

#define WELP_ARM_COMMAND_VAL	0x4

#endif /* __WLCORE_H__ */
Commit	Line	Data
b2ba99ff LC	1	/*
	2	* This file is part of wlcore
	3	*
	4	* Copyright (C) 2011 Texas Instruments Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* version 2 as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	18	* 02110-1301 USA
	19	*
	20	*/
	21
	22	#ifndef __WLCORE_H__
	23	#define __WLCORE_H__
	24
c31be25a LC	25	#include <linux/platform_device.h>
c31be25a LC	26
ffeb501c	27	#include "wl12xx.h"
c31be25a LC	28	#include "event.h"
c31be25a LC	29
72b0624f AN	30	/* The maximum number of Tx descriptors in all chip families */
	31	#define WLCORE_MAX_TX_DESCRIPTORS 32
	32
cd70f6a4 AN	33	/* forward declaration */
	34	struct wl1271_tx_hw_descr;
	35	enum wl_rx_buf_align;
4158149c	36
c31be25a	37	struct wlcore_ops {
6f7dd16c	38	int (identify_chip)(struct wl1271 wl);
80cd6610	39	int (identify_fw)(struct wl1271 wl);
dd5512eb	40	int (boot)(struct wl1271 wl);
5d10b195 AN	41	void (trigger_cmd)(struct wl1271 wl, int cmd_box_addr,
5d10b195 AN	42	void *buf, size_t len);
f16ff758	43	void (ack_event)(struct wl1271 wl);
b3b4b4b8	44	u32 (calc_tx_blocks)(struct wl1271 wl, u32 len, u32 spare_blks);
4a3b97ee AN	45	void (set_tx_desc_blocks)(struct wl1271 wl,
	46	struct wl1271_tx_hw_descr *desc,
	47	u32 blks, u32 spare_blks);
6f266e91 AN	48	void (set_tx_desc_data_len)(struct wl1271 wl,
	49	struct wl1271_tx_hw_descr *desc,
	50	struct sk_buff *skb);
cd70f6a4 AN	51	enum wl_rx_buf_align (get_rx_buf_align)(struct wl1271 wl,
cd70f6a4 AN	52	u32 rx_desc);
b14684a0	53	void (prepare_read)(struct wl1271 wl, u32 rx_desc, u32 len);
4158149c AN	54	u32 (get_rx_packet_len)(struct wl1271 wl, void *rx_data,
4158149c AN	55	u32 data_len);
53d67a50 AN	56	void (tx_delayed_compl)(struct wl1271 wl);
53d67a50 AN	57	void (tx_immediate_compl)(struct wl1271 wl);
9d68d1ee	58	int (hw_init)(struct wl1271 wl);
8a9affc0	59	int (init_vif)(struct wl1271 wl, struct wl12xx_vif *wlvif);
fa7930af AN	60	u32 (sta_get_ap_rate_mask)(struct wl1271 wl,
fa7930af AN	61	struct wl12xx_vif *wlvif);
4ded91ce	62	s8 (get_pg_ver)(struct wl1271 wl);
30d9b4a5	63	void (get_mac)(struct wl1271 wl);
c31be25a LC	64	};
c31be25a LC	65
25a43d78 LC	66	enum wlcore_partitions {
	67	PART_DOWN,
	68	PART_WORK,
	69	PART_BOOT,
	70	PART_DRPW,
	71	PART_TOP_PRCM_ELP_SOC,
	72	PART_PHY_INIT,
	73
	74	PART_TABLE_LEN,
	75	};
	76
	77	struct wlcore_partition {
	78	u32 size;
	79	u32 start;
	80	};
	81
	82	struct wlcore_partition_set {
	83	struct wlcore_partition mem;
	84	struct wlcore_partition reg;
	85	struct wlcore_partition mem2;
	86	struct wlcore_partition mem3;
	87	};
	88
00782136 LC	89	enum wlcore_registers {
	90	/* register addresses, used with partition translation */
	91	REG_ECPU_CONTROL,
	92	REG_INTERRUPT_NO_CLEAR,
	93	REG_INTERRUPT_ACK,
	94	REG_COMMAND_MAILBOX_PTR,
	95	REG_EVENT_MAILBOX_PTR,
	96	REG_INTERRUPT_TRIG,
	97	REG_INTERRUPT_MASK,
	98	REG_PC_ON_RECOVERY,
	99	REG_CHIP_ID_B,
	100	REG_CMD_MBOX_ADDRESS,
	101
	102	/* data access memory addresses, used with partition translation */
	103	REG_SLV_MEM_DATA,
	104	REG_SLV_REG_DATA,
	105
	106	/* raw data access memory addresses */
	107	REG_RAW_FW_STATUS_ADDR,
	108
	109	REG_TABLE_LEN,
	110	};
	111
c31be25a LC	112	struct wl1271 {
	113	struct ieee80211_hw *hw;
	114	bool mac80211_registered;
	115
	116	struct device *dev;
	117
	118	void *if_priv;
	119
	120	struct wl1271_if_operations *if_ops;
	121
	122	void (*set_power)(bool enable);
	123	int irq;
	124	int ref_clock;
	125
	126	spinlock_t wl_lock;
	127
	128	enum wl1271_state state;
	129	enum wl12xx_fw_type fw_type;
	130	bool plt;
	131	u8 last_vif_count;
	132	struct mutex mutex;
	133
	134	unsigned long flags;
	135
25a43d78	136	struct wlcore_partition_set curr_part;
c31be25a LC	137
	138	struct wl1271_chip chip;
	139
	140	int cmd_box_addr;
c31be25a LC	141
	142	u8 *fw;
	143	size_t fw_len;
	144	void *nvs;
	145	size_t nvs_len;
	146
	147	s8 hw_pg_ver;
	148
	149	/* address read from the fuse ROM */
	150	u32 fuse_oui_addr;
	151	u32 fuse_nic_addr;
	152
	153	/* we have up to 2 MAC addresses */
	154	struct mac_address addresses[2];
	155	int channel;
	156	u8 system_hlid;
	157
	158	unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
	159	unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
	160	unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
	161	unsigned long rate_policies_map[
	162	BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
	163
	164	struct list_head wlvif_list;
	165
	166	u8 sta_count;
	167	u8 ap_count;
	168
	169	struct wl1271_acx_mem_map *target_mem_map;
	170
	171	/* Accounting for allocated / available TX blocks on HW */
	172	u32 tx_blocks_freed;
	173	u32 tx_blocks_available;
	174	u32 tx_allocated_blocks;
	175	u32 tx_results_count;
	176
c31be25a LC	177	/* Accounting for allocated / available Tx packets in HW */
	178	u32 tx_pkts_freed[NUM_TX_QUEUES];
	179	u32 tx_allocated_pkts[NUM_TX_QUEUES];
	180
	181	/* Transmitted TX packets counter for chipset interface */
	182	u32 tx_packets_count;
	183
	184	/* Time-offset between host and chipset clocks */
	185	s64 time_offset;
	186
	187	/* Frames scheduled for transmission, not handled yet */
	188	int tx_queue_count[NUM_TX_QUEUES];
	189	long stopped_queues_map;
	190
	191	/* Frames received, not handled yet by mac80211 */
	192	struct sk_buff_head deferred_rx_queue;
	193
	194	/* Frames sent, not returned yet to mac80211 */
	195	struct sk_buff_head deferred_tx_queue;
	196
	197	struct work_struct tx_work;
	198	struct workqueue_struct *freezable_wq;
	199
	200	/* Pending TX frames */
72b0624f AN	201	unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
72b0624f AN	202	struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
c31be25a LC	203	int tx_frames_cnt;
	204
	205	/* FW Rx counter */
	206	u32 rx_counter;
	207
	208	/* Rx memory pool address */
	209	struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;
	210
	211	/* Intermediate buffer, used for packet aggregation */
	212	u8 *aggr_buf;
	213
	214	/* Reusable dummy packet template */
	215	struct sk_buff *dummy_packet;
	216
	217	/* Network stack work */
	218	struct work_struct netstack_work;
	219
	220	/* FW log buffer */
	221	u8 *fwlog;
	222
	223	/* Number of valid bytes in the FW log buffer */
	224	ssize_t fwlog_size;
	225
	226	/* Sysfs FW log entry readers wait queue */
	227	wait_queue_head_t fwlog_waitq;
	228
	229	/* Hardware recovery work */
	230	struct work_struct recovery_work;
	231
	232	/* Pointer that holds DMA-friendly block for the mailbox */
	233	struct event_mailbox *mbox;
	234
	235	/* The mbox event mask */
	236	u32 event_mask;
	237
	238	/* Mailbox pointers */
	239	u32 mbox_ptr[2];
	240
	241	/* Are we currently scanning */
	242	struct ieee80211_vif *scan_vif;
	243	struct wl1271_scan scan;
	244	struct delayed_work scan_complete_work;
	245
5f561f68 BM	246	/* Connection loss work */
	247	struct delayed_work connection_loss_work;
	248
c31be25a LC	249	bool sched_scanning;
	250
	251	/* The current band */
	252	enum ieee80211_band band;
	253
	254	struct completion *elp_compl;
	255	struct delayed_work elp_work;
	256
	257	/* in dBm */
	258	int power_level;
	259
	260	struct wl1271_stats stats;
	261
	262	__le32 buffer_32;
	263	u32 buffer_cmd;
	264	u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
	265
6bac40a6	266	struct wl_fw_status *fw_status;
c31be25a LC	267	struct wl1271_tx_hw_res_if *tx_res_if;
	268
	269	/* Current chipset configuration */
e87288f0	270	struct wlcore_conf conf;
c31be25a LC	271
	272	bool sg_enabled;
	273
	274	bool enable_11a;
	275
	276	/* Most recently reported noise in dBm */
	277	s8 noise;
	278
	279	/* bands supported by this instance of wl12xx */
	280	struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
	281
	282	int tcxo_clock;
	283
	284	/*
	285	* wowlan trigger was configured during suspend.
	286	* (currently, only "ANY" trigger is supported)
	287	*/
	288	bool wow_enabled;
	289	bool irq_wake_enabled;
	290
	291	/*
	292	* AP-mode - links indexed by HLID. The global and broadcast links
	293	* are always active.
	294	*/
	295	struct wl1271_link links[WL12XX_MAX_LINKS];
	296
	297	/* AP-mode - a bitmap of links currently in PS mode according to FW */
	298	u32 ap_fw_ps_map;
	299
	300	/* AP-mode - a bitmap of links currently in PS mode in mac80211 */
	301	unsigned long ap_ps_map;
	302
	303	/* Quirks of specific hardware revisions */
	304	unsigned int quirks;
	305
	306	/* Platform limitations */
	307	unsigned int platform_quirks;
	308
	309	/* number of currently active RX BA sessions */
	310	int ba_rx_session_count;
	311
	312	/* AP-mode - number of currently connected stations */
	313	int active_sta_count;
	314
	315	/* last wlvif we transmitted from */
	316	struct wl12xx_vif *last_wlvif;
	317
	318	/* work to fire when Tx is stuck */
	319	struct delayed_work tx_watchdog_work;
	320
	321	struct wlcore_ops *ops;
25a43d78 LC	322	/* pointer to the lower driver partition table */
25a43d78 LC	323	const struct wlcore_partition_set *ptable;
00782136 LC	324	/* pointer to the lower driver register table */
00782136 LC	325	const int *rtable;
6f7dd16c LC	326	/* name of the firmwares to load - for PLT, single role, multi-role */
	327	const char *plt_fw_name;
	328	const char *sr_fw_name;
	329	const char *mr_fw_name;
96e0c683 AN	330
	331	/* per-chip-family private structure */
	332	void *priv;
72b0624f AN	333
	334	/* number of TX descriptors the HW supports. */
	335	u32 num_tx_desc;
3edab305 AN	336
	337	/* spare Tx blocks for normal/GEM operating modes */
	338	u32 normal_tx_spare;
	339	u32 gem_tx_spare;
43a8bc5a AN	340
	341	/* translate HW Tx rates to standard rate-indices */
	342	const u8 **band_rate_to_idx;
	343
	344	/* size of table for HW rates that can be received from chip */
	345	u8 hw_tx_rate_tbl_size;
	346
	347	/* this HW rate and below are considered HT rates for this chip */
	348	u8 hw_min_ht_rate;
4a589a6f AN	349
	350	/* HW HT (11n) capabilities */
	351	struct ieee80211_sta_ht_cap ht_cap;
6bac40a6 AN	352
	353	/* size of the private FW status data */
	354	size_t fw_status_priv_len;
dbe0a8cd ES	355
	356	/* RX Data filter rule state - enabled/disabled */
	357	bool rx_filter_enabled[WL1271_MAX_RX_FILTERS];
c31be25a	358	};
ffeb501c LC	359
ffeb501c LC	360	int __devinit wlcore_probe(struct wl1271 wl, struct platform_device pdev);
b2ba99ff	361	int __devexit wlcore_remove(struct platform_device *pdev);
96e0c683	362	struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size);
ffeb501c LC	363	int wlcore_free_hw(struct wl1271 *wl);
ffeb501c LC	364
00782136 LC	365	/* Firmware image load chunk size */
	366	#define CHUNK_SIZE 16384
	367
6f7dd16c LC	368	/* Quirks */
	369
	370	/* Each RX/TX transaction requires an end-of-transaction transfer */
	371	#define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
	372
	373	/* wl127x and SPI don't support SDIO block size alignment */
f83985bb	374	#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
6f7dd16c	375
5766435e AN	376	/* means aggregated Rx packets are aligned to a SDIO block */
	377	#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
	378
6f7dd16c LC	379	/* Older firmwares did not implement the FW logger over bus feature */
	380	#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
	381
d203e59c LC	382	/* Older firmwares use an old NVS format */
	383	#define WLCORE_QUIRK_LEGACY_NVS BIT(5)
	384
441101f6 LC	385	/* Some firmwares may not support ELP */
	386	#define WLCORE_QUIRK_NO_ELP BIT(6)
	387
00782136 LC	388	/* TODO: move to the lower drivers when all usages are abstracted */
	389	#define CHIP_ID_1271_PG10 (0x4030101)
	390	#define CHIP_ID_1271_PG20 (0x4030111)
	391	#define CHIP_ID_1283_PG10 (0x05030101)
	392	#define CHIP_ID_1283_PG20 (0x05030111)
	393
	394	/* TODO: move all these common registers and values elsewhere */
	395	#define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
	396
	397	/* ELP register commands */
	398	#define ELPCTRL_WAKE_UP 0x1
	399	#define ELPCTRL_WAKE_UP_WLAN_READY 0x5
	400	#define ELPCTRL_SLEEP 0x0
	401	/* ELP WLAN_READY bit */
	402	#define ELPCTRL_WLAN_READY 0x2
	403
	404	/*************************************************************************
	405
	406	Interrupt Trigger Register (Host -> WiLink)
	407
	408	**************************************************************************/
	409
	410	/* Hardware to Embedded CPU Interrupts - first 32-bit register set */
	411
00782136 LC	412	/*
	413	* The host sets this bit to inform the Wlan
	414	* FW that a TX packet is in the XFER
	415	* Buffer #0.
	416	*/
	417	#define INTR_TRIG_TX_PROC0 BIT(2)
	418
	419	/*
	420	* The host sets this bit to inform the FW
	421	* that it read a packet from RX XFER
	422	* Buffer #0.
	423	*/
	424	#define INTR_TRIG_RX_PROC0 BIT(3)
	425
	426	#define INTR_TRIG_DEBUG_ACK BIT(4)
	427
	428	#define INTR_TRIG_STATE_CHANGED BIT(5)
	429
	430	/* Hardware to Embedded CPU Interrupts - second 32-bit register set */
	431
	432	/*
	433	* The host sets this bit to inform the FW
	434	* that it read a packet from RX XFER
	435	* Buffer #1.
	436	*/
	437	#define INTR_TRIG_RX_PROC1 BIT(17)
	438
	439	/*
	440	* The host sets this bit to inform the Wlan
	441	* hardware that a TX packet is in the XFER
	442	* Buffer #1.
	443	*/
	444	#define INTR_TRIG_TX_PROC1 BIT(18)
	445
	446	#define ACX_SLV_SOFT_RESET_BIT BIT(1)
	447	#define SOFT_RESET_MAX_TIME 1000000
	448	#define SOFT_RESET_STALL_TIME 1000
	449
	450	#define ECPU_CONTROL_HALT 0x00000101
b2ba99ff	451
6f7dd16c LC	452	#define WELP_ARM_COMMAND_VAL 0x4
6f7dd16c LC	453
b2ba99ff	454	#endif /* __WLCORE_H__ */