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Commit | Line | Data |
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2f01a1f5 | 1 | /* |
80301cdc | 2 | * This file is part of wl1251 |
2f01a1f5 KV |
3 | * |
4 | * Copyright (c) 1998-2007 Texas Instruments Incorporated | |
5 | * Copyright (C) 2008-2009 Nokia Corporation | |
6 | * | |
7 | * Contact: Kalle Valo <kalle.valo@nokia.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
80301cdc KV |
25 | #ifndef __WL1251_H__ |
26 | #define __WL1251_H__ | |
2f01a1f5 KV |
27 | |
28 | #include <linux/mutex.h> | |
29 | #include <linux/list.h> | |
30 | #include <linux/bitops.h> | |
31 | #include <net/mac80211.h> | |
32 | ||
80301cdc | 33 | #define DRIVER_NAME "wl1251" |
2f01a1f5 KV |
34 | #define DRIVER_PREFIX DRIVER_NAME ": " |
35 | ||
36 | enum { | |
37 | DEBUG_NONE = 0, | |
38 | DEBUG_IRQ = BIT(0), | |
39 | DEBUG_SPI = BIT(1), | |
40 | DEBUG_BOOT = BIT(2), | |
41 | DEBUG_MAILBOX = BIT(3), | |
42 | DEBUG_NETLINK = BIT(4), | |
43 | DEBUG_EVENT = BIT(5), | |
44 | DEBUG_TX = BIT(6), | |
45 | DEBUG_RX = BIT(7), | |
46 | DEBUG_SCAN = BIT(8), | |
47 | DEBUG_CRYPT = BIT(9), | |
48 | DEBUG_PSM = BIT(10), | |
49 | DEBUG_MAC80211 = BIT(11), | |
50 | DEBUG_CMD = BIT(12), | |
51 | DEBUG_ACX = BIT(13), | |
52 | DEBUG_ALL = ~0, | |
53 | }; | |
54 | ||
55 | #define DEBUG_LEVEL (DEBUG_NONE) | |
56 | ||
57 | #define DEBUG_DUMP_LIMIT 1024 | |
58 | ||
80301cdc | 59 | #define wl1251_error(fmt, arg...) \ |
2f01a1f5 KV |
60 | printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg) |
61 | ||
80301cdc | 62 | #define wl1251_warning(fmt, arg...) \ |
2f01a1f5 KV |
63 | printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg) |
64 | ||
80301cdc | 65 | #define wl1251_notice(fmt, arg...) \ |
2f01a1f5 KV |
66 | printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg) |
67 | ||
80301cdc | 68 | #define wl1251_info(fmt, arg...) \ |
2f01a1f5 KV |
69 | printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg) |
70 | ||
80301cdc | 71 | #define wl1251_debug(level, fmt, arg...) \ |
2f01a1f5 KV |
72 | do { \ |
73 | if (level & DEBUG_LEVEL) \ | |
74 | printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \ | |
75 | } while (0) | |
76 | ||
80301cdc | 77 | #define wl1251_dump(level, prefix, buf, len) \ |
2f01a1f5 KV |
78 | do { \ |
79 | if (level & DEBUG_LEVEL) \ | |
80 | print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ | |
81 | DUMP_PREFIX_OFFSET, 16, 1, \ | |
82 | buf, \ | |
83 | min_t(size_t, len, DEBUG_DUMP_LIMIT), \ | |
84 | 0); \ | |
85 | } while (0) | |
86 | ||
80301cdc | 87 | #define wl1251_dump_ascii(level, prefix, buf, len) \ |
2f01a1f5 KV |
88 | do { \ |
89 | if (level & DEBUG_LEVEL) \ | |
90 | print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ | |
91 | DUMP_PREFIX_OFFSET, 16, 1, \ | |
92 | buf, \ | |
93 | min_t(size_t, len, DEBUG_DUMP_LIMIT), \ | |
94 | true); \ | |
95 | } while (0) | |
96 | ||
80301cdc | 97 | #define WL1251_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN | \ |
2f01a1f5 KV |
98 | CFG_BSSID_FILTER_EN) |
99 | ||
80301cdc | 100 | #define WL1251_DEFAULT_RX_FILTER (CFG_RX_PRSP_EN | \ |
2f01a1f5 KV |
101 | CFG_RX_MGMT_EN | \ |
102 | CFG_RX_DATA_EN | \ | |
103 | CFG_RX_CTL_EN | \ | |
104 | CFG_RX_BCN_EN | \ | |
105 | CFG_RX_AUTH_EN | \ | |
106 | CFG_RX_ASSOC_EN) | |
107 | ||
80301cdc | 108 | #define WL1251_BUSY_WORD_LEN 8 |
2f01a1f5 KV |
109 | |
110 | struct boot_attr { | |
111 | u32 radio_type; | |
112 | u8 mac_clock; | |
113 | u8 arm_clock; | |
114 | int firmware_debug; | |
115 | u32 minor; | |
116 | u32 major; | |
117 | u32 bugfix; | |
118 | }; | |
119 | ||
80301cdc KV |
120 | enum wl1251_state { |
121 | WL1251_STATE_OFF, | |
122 | WL1251_STATE_ON, | |
123 | WL1251_STATE_PLT, | |
2f01a1f5 KV |
124 | }; |
125 | ||
80301cdc | 126 | enum wl1251_partition_type { |
2f01a1f5 KV |
127 | PART_DOWN, |
128 | PART_WORK, | |
129 | PART_DRPW, | |
130 | ||
131 | PART_TABLE_LEN | |
132 | }; | |
133 | ||
80301cdc | 134 | struct wl1251_partition { |
2f01a1f5 KV |
135 | u32 size; |
136 | u32 start; | |
137 | }; | |
138 | ||
80301cdc KV |
139 | struct wl1251_partition_set { |
140 | struct wl1251_partition mem; | |
141 | struct wl1251_partition reg; | |
2f01a1f5 KV |
142 | }; |
143 | ||
80301cdc | 144 | struct wl1251; |
2f01a1f5 KV |
145 | |
146 | /* FIXME: I'm not sure about this structure name */ | |
80301cdc | 147 | struct wl1251_chip { |
2f01a1f5 KV |
148 | u32 id; |
149 | ||
150 | const char *fw_filename; | |
151 | const char *nvs_filename; | |
152 | ||
153 | char fw_ver[21]; | |
154 | ||
155 | unsigned int power_on_sleep; | |
156 | int intr_cmd_complete; | |
157 | int intr_init_complete; | |
158 | ||
80301cdc KV |
159 | int (*op_upload_fw)(struct wl1251 *wl); |
160 | int (*op_upload_nvs)(struct wl1251 *wl); | |
161 | int (*op_boot)(struct wl1251 *wl); | |
162 | void (*op_set_ecpu_ctrl)(struct wl1251 *wl, u32 flag); | |
163 | void (*op_target_enable_interrupts)(struct wl1251 *wl); | |
164 | int (*op_hw_init)(struct wl1251 *wl); | |
165 | int (*op_plt_init)(struct wl1251 *wl); | |
166 | void (*op_tx_flush)(struct wl1251 *wl); | |
167 | void (*op_fw_version)(struct wl1251 *wl); | |
168 | int (*op_cmd_join)(struct wl1251 *wl, u8 bss_type, u8 dtim_interval, | |
77cc9e43 | 169 | u16 beacon_interval, u8 wait); |
2f01a1f5 | 170 | |
80301cdc | 171 | struct wl1251_partition_set *p_table; |
2f01a1f5 KV |
172 | enum wl12xx_acx_int_reg *acx_reg_table; |
173 | }; | |
174 | ||
80301cdc | 175 | struct wl1251_stats { |
2f01a1f5 KV |
176 | struct acx_statistics *fw_stats; |
177 | unsigned long fw_stats_update; | |
178 | ||
179 | unsigned int retry_count; | |
180 | unsigned int excessive_retries; | |
181 | }; | |
182 | ||
80301cdc | 183 | struct wl1251_debugfs { |
2f01a1f5 KV |
184 | struct dentry *rootdir; |
185 | struct dentry *fw_statistics; | |
186 | ||
187 | struct dentry *tx_internal_desc_overflow; | |
188 | ||
189 | struct dentry *rx_out_of_mem; | |
190 | struct dentry *rx_hdr_overflow; | |
191 | struct dentry *rx_hw_stuck; | |
192 | struct dentry *rx_dropped; | |
193 | struct dentry *rx_fcs_err; | |
194 | struct dentry *rx_xfr_hint_trig; | |
195 | struct dentry *rx_path_reset; | |
196 | struct dentry *rx_reset_counter; | |
197 | ||
198 | struct dentry *dma_rx_requested; | |
199 | struct dentry *dma_rx_errors; | |
200 | struct dentry *dma_tx_requested; | |
201 | struct dentry *dma_tx_errors; | |
202 | ||
203 | struct dentry *isr_cmd_cmplt; | |
204 | struct dentry *isr_fiqs; | |
205 | struct dentry *isr_rx_headers; | |
206 | struct dentry *isr_rx_mem_overflow; | |
207 | struct dentry *isr_rx_rdys; | |
208 | struct dentry *isr_irqs; | |
209 | struct dentry *isr_tx_procs; | |
210 | struct dentry *isr_decrypt_done; | |
211 | struct dentry *isr_dma0_done; | |
212 | struct dentry *isr_dma1_done; | |
213 | struct dentry *isr_tx_exch_complete; | |
214 | struct dentry *isr_commands; | |
215 | struct dentry *isr_rx_procs; | |
216 | struct dentry *isr_hw_pm_mode_changes; | |
217 | struct dentry *isr_host_acknowledges; | |
218 | struct dentry *isr_pci_pm; | |
219 | struct dentry *isr_wakeups; | |
220 | struct dentry *isr_low_rssi; | |
221 | ||
222 | struct dentry *wep_addr_key_count; | |
223 | struct dentry *wep_default_key_count; | |
224 | /* skipping wep.reserved */ | |
225 | struct dentry *wep_key_not_found; | |
226 | struct dentry *wep_decrypt_fail; | |
227 | struct dentry *wep_packets; | |
228 | struct dentry *wep_interrupt; | |
229 | ||
230 | struct dentry *pwr_ps_enter; | |
231 | struct dentry *pwr_elp_enter; | |
232 | struct dentry *pwr_missing_bcns; | |
233 | struct dentry *pwr_wake_on_host; | |
234 | struct dentry *pwr_wake_on_timer_exp; | |
235 | struct dentry *pwr_tx_with_ps; | |
236 | struct dentry *pwr_tx_without_ps; | |
237 | struct dentry *pwr_rcvd_beacons; | |
238 | struct dentry *pwr_power_save_off; | |
239 | struct dentry *pwr_enable_ps; | |
240 | struct dentry *pwr_disable_ps; | |
241 | struct dentry *pwr_fix_tsf_ps; | |
242 | /* skipping cont_miss_bcns_spread for now */ | |
243 | struct dentry *pwr_rcvd_awake_beacons; | |
244 | ||
245 | struct dentry *mic_rx_pkts; | |
246 | struct dentry *mic_calc_failure; | |
247 | ||
248 | struct dentry *aes_encrypt_fail; | |
249 | struct dentry *aes_decrypt_fail; | |
250 | struct dentry *aes_encrypt_packets; | |
251 | struct dentry *aes_decrypt_packets; | |
252 | struct dentry *aes_encrypt_interrupt; | |
253 | struct dentry *aes_decrypt_interrupt; | |
254 | ||
255 | struct dentry *event_heart_beat; | |
256 | struct dentry *event_calibration; | |
257 | struct dentry *event_rx_mismatch; | |
258 | struct dentry *event_rx_mem_empty; | |
259 | struct dentry *event_rx_pool; | |
260 | struct dentry *event_oom_late; | |
261 | struct dentry *event_phy_transmit_error; | |
262 | struct dentry *event_tx_stuck; | |
263 | ||
264 | struct dentry *ps_pspoll_timeouts; | |
265 | struct dentry *ps_upsd_timeouts; | |
266 | struct dentry *ps_upsd_max_sptime; | |
267 | struct dentry *ps_upsd_max_apturn; | |
268 | struct dentry *ps_pspoll_max_apturn; | |
269 | struct dentry *ps_pspoll_utilization; | |
270 | struct dentry *ps_upsd_utilization; | |
271 | ||
272 | struct dentry *rxpipe_rx_prep_beacon_drop; | |
273 | struct dentry *rxpipe_descr_host_int_trig_rx_data; | |
274 | struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data; | |
275 | struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data; | |
276 | struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data; | |
277 | ||
278 | struct dentry *tx_queue_len; | |
279 | ||
280 | struct dentry *retry_count; | |
281 | struct dentry *excessive_retries; | |
282 | }; | |
283 | ||
08d9f572 BC |
284 | struct wl1251_if_operations { |
285 | void (*read)(struct wl1251 *wl, int addr, void *buf, size_t len); | |
286 | void (*write)(struct wl1251 *wl, int addr, void *buf, size_t len); | |
287 | void (*reset)(struct wl1251 *wl); | |
288 | }; | |
289 | ||
80301cdc | 290 | struct wl1251 { |
2f01a1f5 KV |
291 | struct ieee80211_hw *hw; |
292 | bool mac80211_registered; | |
293 | ||
294 | struct spi_device *spi; | |
8e639c06 | 295 | const struct wl1251_if_operations *if_ops; |
2f01a1f5 KV |
296 | |
297 | void (*set_power)(bool enable); | |
298 | int irq; | |
299 | ||
80301cdc | 300 | enum wl1251_state state; |
2f01a1f5 KV |
301 | struct mutex mutex; |
302 | ||
303 | int physical_mem_addr; | |
304 | int physical_reg_addr; | |
305 | int virtual_mem_addr; | |
306 | int virtual_reg_addr; | |
307 | ||
80301cdc | 308 | struct wl1251_chip chip; |
2f01a1f5 KV |
309 | |
310 | int cmd_box_addr; | |
311 | int event_box_addr; | |
312 | struct boot_attr boot_attr; | |
313 | ||
314 | u8 *fw; | |
315 | size_t fw_len; | |
316 | u8 *nvs; | |
317 | size_t nvs_len; | |
318 | ||
319 | u8 bssid[ETH_ALEN]; | |
320 | u8 mac_addr[ETH_ALEN]; | |
321 | u8 bss_type; | |
322 | u8 listen_int; | |
323 | int channel; | |
324 | ||
325 | void *target_mem_map; | |
326 | struct acx_data_path_params_resp *data_path; | |
327 | ||
328 | /* Number of TX packets transferred to the FW, modulo 16 */ | |
329 | u32 data_in_count; | |
330 | ||
331 | /* Frames scheduled for transmission, not handled yet */ | |
332 | struct sk_buff_head tx_queue; | |
333 | bool tx_queue_stopped; | |
334 | ||
335 | struct work_struct tx_work; | |
336 | struct work_struct filter_work; | |
337 | ||
338 | /* Pending TX frames */ | |
339 | struct sk_buff *tx_frames[16]; | |
340 | ||
341 | /* | |
342 | * Index pointing to the next TX complete entry | |
343 | * in the cyclic XT complete array we get from | |
344 | * the FW. | |
345 | */ | |
346 | u32 next_tx_complete; | |
347 | ||
348 | /* FW Rx counter */ | |
349 | u32 rx_counter; | |
350 | ||
351 | /* Rx frames handled */ | |
352 | u32 rx_handled; | |
353 | ||
354 | /* Current double buffer */ | |
355 | u32 rx_current_buffer; | |
356 | u32 rx_last_id; | |
357 | ||
358 | /* The target interrupt mask */ | |
359 | u32 intr_mask; | |
360 | struct work_struct irq_work; | |
361 | ||
362 | /* The mbox event mask */ | |
363 | u32 event_mask; | |
364 | ||
365 | /* Mailbox pointers */ | |
366 | u32 mbox_ptr[2]; | |
367 | ||
368 | /* Are we currently scanning */ | |
369 | bool scanning; | |
370 | ||
371 | /* Our association ID */ | |
372 | u16 aid; | |
373 | ||
374 | /* Default key (for WEP) */ | |
375 | u32 default_key; | |
376 | ||
377 | unsigned int tx_mgmt_frm_rate; | |
378 | unsigned int tx_mgmt_frm_mod; | |
379 | ||
380 | unsigned int rx_config; | |
381 | unsigned int rx_filter; | |
382 | ||
383 | /* is firmware in elp mode */ | |
384 | bool elp; | |
385 | ||
386 | /* we can be in psm, but not in elp, we have to differentiate */ | |
387 | bool psm; | |
388 | ||
389 | /* PSM mode requested */ | |
390 | bool psm_requested; | |
391 | ||
392 | /* in dBm */ | |
393 | int power_level; | |
394 | ||
80301cdc KV |
395 | struct wl1251_stats stats; |
396 | struct wl1251_debugfs debugfs; | |
1d3b8130 KV |
397 | |
398 | u32 buffer_32; | |
56343a3c | 399 | u32 buffer_cmd; |
80301cdc KV |
400 | u8 buffer_busyword[WL1251_BUSY_WORD_LEN]; |
401 | struct wl1251_rx_descriptor *rx_descriptor; | |
2f01a1f5 KV |
402 | }; |
403 | ||
80301cdc KV |
404 | int wl1251_plt_start(struct wl1251 *wl); |
405 | int wl1251_plt_stop(struct wl1251 *wl); | |
2f01a1f5 | 406 | |
8e639c06 BC |
407 | irqreturn_t wl1251_irq(int irq, void *cookie); |
408 | struct ieee80211_hw *wl1251_alloc_hw(void); | |
409 | int wl1251_free_hw(struct wl1251 *wl); | |
410 | int wl1251_init_ieee80211(struct wl1251 *wl); | |
411 | ||
2f01a1f5 KV |
412 | #define DEFAULT_HW_GEN_MODULATION_TYPE CCK_LONG /* Long Preamble */ |
413 | #define DEFAULT_HW_GEN_TX_RATE RATE_2MBPS | |
414 | #define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */ | |
415 | ||
80301cdc | 416 | #define WL1251_DEFAULT_POWER_LEVEL 20 |
2f01a1f5 | 417 | |
80301cdc | 418 | #define WL1251_TX_QUEUE_MAX_LENGTH 20 |
2f01a1f5 KV |
419 | |
420 | /* Different chips need different sleep times after power on. WL1271 needs | |
421 | * 200ms, WL1251 needs only 10ms. By default we use 200ms, but as soon as we | |
80301cdc | 422 | * know the chip ID, we change the sleep value in the wl1251 chip structure, |
2f01a1f5 | 423 | * so in subsequent power ons, we don't waste more time then needed. */ |
80301cdc | 424 | #define WL1251_DEFAULT_POWER_ON_SLEEP 200 |
2f01a1f5 KV |
425 | |
426 | #define CHIP_ID_1251_PG10 (0x7010101) | |
427 | #define CHIP_ID_1251_PG11 (0x7020101) | |
428 | #define CHIP_ID_1251_PG12 (0x7030101) | |
429 | #define CHIP_ID_1271_PG10 (0x4030101) | |
27797d68 | 430 | #define CHIP_ID_1271_PG20 (0x4030111) |
2f01a1f5 KV |
431 | |
432 | #endif |