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Commit | Line | Data |
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f5fc0f86 LC |
1 | /* |
2 | * This file is part of wl1271 | |
3 | * | |
4 | * Copyright (C) 1998-2009 Texas Instruments. All rights reserved. | |
5 | * Copyright (C) 2008-2009 Nokia Corporation | |
6 | * | |
7 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef __WL1271_H__ | |
26 | #define __WL1271_H__ | |
27 | ||
28 | #include <linux/mutex.h> | |
29 | #include <linux/completion.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/list.h> | |
32 | #include <linux/bitops.h> | |
33 | #include <net/mac80211.h> | |
34 | ||
2b60100b JO |
35 | #include "wl1271_conf.h" |
36 | ||
f5fc0f86 LC |
37 | #define DRIVER_NAME "wl1271" |
38 | #define DRIVER_PREFIX DRIVER_NAME ": " | |
39 | ||
40 | enum { | |
41 | DEBUG_NONE = 0, | |
42 | DEBUG_IRQ = BIT(0), | |
43 | DEBUG_SPI = BIT(1), | |
44 | DEBUG_BOOT = BIT(2), | |
45 | DEBUG_MAILBOX = BIT(3), | |
c8c90873 | 46 | DEBUG_TESTMODE = BIT(4), |
f5fc0f86 LC |
47 | DEBUG_EVENT = BIT(5), |
48 | DEBUG_TX = BIT(6), | |
49 | DEBUG_RX = BIT(7), | |
50 | DEBUG_SCAN = BIT(8), | |
51 | DEBUG_CRYPT = BIT(9), | |
52 | DEBUG_PSM = BIT(10), | |
53 | DEBUG_MAC80211 = BIT(11), | |
54 | DEBUG_CMD = BIT(12), | |
55 | DEBUG_ACX = BIT(13), | |
a3b8ea75 | 56 | DEBUG_SDIO = BIT(14), |
f5fc0f86 LC |
57 | DEBUG_ALL = ~0, |
58 | }; | |
59 | ||
60 | #define DEBUG_LEVEL (DEBUG_NONE) | |
61 | ||
62 | #define DEBUG_DUMP_LIMIT 1024 | |
63 | ||
64 | #define wl1271_error(fmt, arg...) \ | |
65 | printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg) | |
66 | ||
67 | #define wl1271_warning(fmt, arg...) \ | |
68 | printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg) | |
69 | ||
70 | #define wl1271_notice(fmt, arg...) \ | |
71 | printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg) | |
72 | ||
73 | #define wl1271_info(fmt, arg...) \ | |
74 | printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg) | |
75 | ||
76 | #define wl1271_debug(level, fmt, arg...) \ | |
77 | do { \ | |
78 | if (level & DEBUG_LEVEL) \ | |
79 | printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \ | |
80 | } while (0) | |
81 | ||
82 | #define wl1271_dump(level, prefix, buf, len) \ | |
83 | do { \ | |
84 | if (level & DEBUG_LEVEL) \ | |
85 | print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ | |
86 | DUMP_PREFIX_OFFSET, 16, 1, \ | |
87 | buf, \ | |
88 | min_t(size_t, len, DEBUG_DUMP_LIMIT), \ | |
89 | 0); \ | |
90 | } while (0) | |
91 | ||
92 | #define wl1271_dump_ascii(level, prefix, buf, len) \ | |
93 | do { \ | |
94 | if (level & DEBUG_LEVEL) \ | |
95 | print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ | |
96 | DUMP_PREFIX_OFFSET, 16, 1, \ | |
97 | buf, \ | |
98 | min_t(size_t, len, DEBUG_DUMP_LIMIT), \ | |
99 | true); \ | |
100 | } while (0) | |
101 | ||
102 | #define WL1271_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN | \ | |
c87dec9f JO |
103 | CFG_BSSID_FILTER_EN | \ |
104 | CFG_MC_FILTER_EN) | |
f5fc0f86 LC |
105 | |
106 | #define WL1271_DEFAULT_RX_FILTER (CFG_RX_RCTS_ACK | CFG_RX_PRSP_EN | \ | |
107 | CFG_RX_MGMT_EN | CFG_RX_DATA_EN | \ | |
108 | CFG_RX_CTL_EN | CFG_RX_BCN_EN | \ | |
109 | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN) | |
110 | ||
111 | #define WL1271_FW_NAME "wl1271-fw.bin" | |
112 | #define WL1271_NVS_NAME "wl1271-nvs.bin" | |
152ee6e0 | 113 | |
04e36fc5 JO |
114 | #define WL1271_TX_SECURITY_LO16(s) ((u16)((s) & 0xffff)) |
115 | #define WL1271_TX_SECURITY_HI32(s) ((u32)(((s) >> 16) & 0xffffffff)) | |
116 | ||
152ee6e0 JO |
117 | /* NVS data structure */ |
118 | #define WL1271_NVS_SECTION_SIZE 468 | |
119 | ||
120 | #define WL1271_NVS_GENERAL_PARAMS_SIZE 57 | |
121 | #define WL1271_NVS_GENERAL_PARAMS_SIZE_PADDED \ | |
122 | (WL1271_NVS_GENERAL_PARAMS_SIZE + 1) | |
123 | #define WL1271_NVS_STAT_RADIO_PARAMS_SIZE 17 | |
124 | #define WL1271_NVS_STAT_RADIO_PARAMS_SIZE_PADDED \ | |
125 | (WL1271_NVS_STAT_RADIO_PARAMS_SIZE + 1) | |
126 | #define WL1271_NVS_DYN_RADIO_PARAMS_SIZE 65 | |
127 | #define WL1271_NVS_DYN_RADIO_PARAMS_SIZE_PADDED \ | |
128 | (WL1271_NVS_DYN_RADIO_PARAMS_SIZE + 1) | |
129 | #define WL1271_NVS_FEM_COUNT 2 | |
130 | #define WL1271_NVS_INI_SPARE_SIZE 124 | |
131 | ||
132 | struct wl1271_nvs_file { | |
133 | /* NVS section */ | |
134 | u8 nvs[WL1271_NVS_SECTION_SIZE]; | |
135 | ||
136 | /* INI section */ | |
137 | u8 general_params[WL1271_NVS_GENERAL_PARAMS_SIZE_PADDED]; | |
138 | u8 stat_radio_params[WL1271_NVS_STAT_RADIO_PARAMS_SIZE_PADDED]; | |
139 | u8 dyn_radio_params[WL1271_NVS_FEM_COUNT] | |
140 | [WL1271_NVS_DYN_RADIO_PARAMS_SIZE_PADDED]; | |
141 | u8 ini_spare[WL1271_NVS_INI_SPARE_SIZE]; | |
142 | } __attribute__ ((packed)); | |
f5fc0f86 | 143 | |
1ebec3d7 TP |
144 | /* |
145 | * Enable/disable 802.11a support for WL1273 | |
146 | */ | |
147 | #undef WL1271_80211A_ENABLED | |
148 | ||
545f1da8 JO |
149 | /* |
150 | * FIXME: for the wl1271, a busy word count of 1 here will result in a more | |
151 | * optimal SPI interface. There is some SPI bug however, causing RXS time outs | |
c6d5d06e JO |
152 | * with this mode occasionally on boot, so lets have three for now. A value of |
153 | * three should make sure, that the chipset will always be ready, though this | |
154 | * will impact throughput and latencies slightly. | |
545f1da8 | 155 | */ |
c6d5d06e | 156 | #define WL1271_BUSY_WORD_CNT 3 |
545f1da8 | 157 | #define WL1271_BUSY_WORD_LEN (WL1271_BUSY_WORD_CNT * sizeof(u32)) |
f5fc0f86 LC |
158 | |
159 | #define WL1271_ELP_HW_STATE_ASLEEP 0 | |
160 | #define WL1271_ELP_HW_STATE_IRQ 1 | |
161 | ||
d94cd297 JO |
162 | #define WL1271_DEFAULT_BEACON_INT 100 |
163 | #define WL1271_DEFAULT_DTIM_PERIOD 1 | |
164 | ||
c87dec9f | 165 | #define ACX_TX_DESCRIPTORS 32 |
be7078c2 | 166 | |
f5fc0f86 LC |
167 | enum wl1271_state { |
168 | WL1271_STATE_OFF, | |
169 | WL1271_STATE_ON, | |
170 | WL1271_STATE_PLT, | |
171 | }; | |
172 | ||
173 | enum wl1271_partition_type { | |
174 | PART_DOWN, | |
175 | PART_WORK, | |
176 | PART_DRPW, | |
177 | ||
178 | PART_TABLE_LEN | |
179 | }; | |
180 | ||
181 | struct wl1271_partition { | |
182 | u32 size; | |
183 | u32 start; | |
184 | }; | |
185 | ||
186 | struct wl1271_partition_set { | |
187 | struct wl1271_partition mem; | |
188 | struct wl1271_partition reg; | |
451de97a JO |
189 | struct wl1271_partition mem2; |
190 | struct wl1271_partition mem3; | |
f5fc0f86 LC |
191 | }; |
192 | ||
193 | struct wl1271; | |
194 | ||
195 | /* FIXME: I'm not sure about this structure name */ | |
196 | struct wl1271_chip { | |
197 | u32 id; | |
198 | char fw_ver[21]; | |
199 | }; | |
200 | ||
201 | struct wl1271_stats { | |
202 | struct acx_statistics *fw_stats; | |
203 | unsigned long fw_stats_update; | |
204 | ||
205 | unsigned int retry_count; | |
206 | unsigned int excessive_retries; | |
207 | }; | |
208 | ||
209 | struct wl1271_debugfs { | |
210 | struct dentry *rootdir; | |
211 | struct dentry *fw_statistics; | |
212 | ||
213 | struct dentry *tx_internal_desc_overflow; | |
214 | ||
215 | struct dentry *rx_out_of_mem; | |
216 | struct dentry *rx_hdr_overflow; | |
217 | struct dentry *rx_hw_stuck; | |
218 | struct dentry *rx_dropped; | |
219 | struct dentry *rx_fcs_err; | |
220 | struct dentry *rx_xfr_hint_trig; | |
221 | struct dentry *rx_path_reset; | |
222 | struct dentry *rx_reset_counter; | |
223 | ||
224 | struct dentry *dma_rx_requested; | |
225 | struct dentry *dma_rx_errors; | |
226 | struct dentry *dma_tx_requested; | |
227 | struct dentry *dma_tx_errors; | |
228 | ||
229 | struct dentry *isr_cmd_cmplt; | |
230 | struct dentry *isr_fiqs; | |
231 | struct dentry *isr_rx_headers; | |
232 | struct dentry *isr_rx_mem_overflow; | |
233 | struct dentry *isr_rx_rdys; | |
234 | struct dentry *isr_irqs; | |
235 | struct dentry *isr_tx_procs; | |
236 | struct dentry *isr_decrypt_done; | |
237 | struct dentry *isr_dma0_done; | |
238 | struct dentry *isr_dma1_done; | |
239 | struct dentry *isr_tx_exch_complete; | |
240 | struct dentry *isr_commands; | |
241 | struct dentry *isr_rx_procs; | |
242 | struct dentry *isr_hw_pm_mode_changes; | |
243 | struct dentry *isr_host_acknowledges; | |
244 | struct dentry *isr_pci_pm; | |
245 | struct dentry *isr_wakeups; | |
246 | struct dentry *isr_low_rssi; | |
247 | ||
248 | struct dentry *wep_addr_key_count; | |
249 | struct dentry *wep_default_key_count; | |
250 | /* skipping wep.reserved */ | |
251 | struct dentry *wep_key_not_found; | |
252 | struct dentry *wep_decrypt_fail; | |
253 | struct dentry *wep_packets; | |
254 | struct dentry *wep_interrupt; | |
255 | ||
256 | struct dentry *pwr_ps_enter; | |
257 | struct dentry *pwr_elp_enter; | |
258 | struct dentry *pwr_missing_bcns; | |
259 | struct dentry *pwr_wake_on_host; | |
260 | struct dentry *pwr_wake_on_timer_exp; | |
261 | struct dentry *pwr_tx_with_ps; | |
262 | struct dentry *pwr_tx_without_ps; | |
263 | struct dentry *pwr_rcvd_beacons; | |
264 | struct dentry *pwr_power_save_off; | |
265 | struct dentry *pwr_enable_ps; | |
266 | struct dentry *pwr_disable_ps; | |
267 | struct dentry *pwr_fix_tsf_ps; | |
268 | /* skipping cont_miss_bcns_spread for now */ | |
269 | struct dentry *pwr_rcvd_awake_beacons; | |
270 | ||
271 | struct dentry *mic_rx_pkts; | |
272 | struct dentry *mic_calc_failure; | |
273 | ||
274 | struct dentry *aes_encrypt_fail; | |
275 | struct dentry *aes_decrypt_fail; | |
276 | struct dentry *aes_encrypt_packets; | |
277 | struct dentry *aes_decrypt_packets; | |
278 | struct dentry *aes_encrypt_interrupt; | |
279 | struct dentry *aes_decrypt_interrupt; | |
280 | ||
281 | struct dentry *event_heart_beat; | |
282 | struct dentry *event_calibration; | |
283 | struct dentry *event_rx_mismatch; | |
284 | struct dentry *event_rx_mem_empty; | |
285 | struct dentry *event_rx_pool; | |
286 | struct dentry *event_oom_late; | |
287 | struct dentry *event_phy_transmit_error; | |
288 | struct dentry *event_tx_stuck; | |
289 | ||
290 | struct dentry *ps_pspoll_timeouts; | |
291 | struct dentry *ps_upsd_timeouts; | |
292 | struct dentry *ps_upsd_max_sptime; | |
293 | struct dentry *ps_upsd_max_apturn; | |
294 | struct dentry *ps_pspoll_max_apturn; | |
295 | struct dentry *ps_pspoll_utilization; | |
296 | struct dentry *ps_upsd_utilization; | |
297 | ||
298 | struct dentry *rxpipe_rx_prep_beacon_drop; | |
299 | struct dentry *rxpipe_descr_host_int_trig_rx_data; | |
300 | struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data; | |
301 | struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data; | |
302 | struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data; | |
303 | ||
304 | struct dentry *tx_queue_len; | |
305 | ||
306 | struct dentry *retry_count; | |
307 | struct dentry *excessive_retries; | |
98b2a684 | 308 | struct dentry *gpio_power; |
f5fc0f86 LC |
309 | }; |
310 | ||
311 | #define NUM_TX_QUEUES 4 | |
312 | #define NUM_RX_PKT_DESC 8 | |
313 | ||
314 | /* FW status registers */ | |
315 | struct wl1271_fw_status { | |
d0f63b20 | 316 | __le32 intr; |
f5fc0f86 LC |
317 | u8 fw_rx_counter; |
318 | u8 drv_rx_counter; | |
319 | u8 reserved; | |
320 | u8 tx_results_counter; | |
d0f63b20 LC |
321 | __le32 rx_pkt_descs[NUM_RX_PKT_DESC]; |
322 | __le32 tx_released_blks[NUM_TX_QUEUES]; | |
323 | __le32 fw_localtime; | |
324 | __le32 padding[2]; | |
f5fc0f86 LC |
325 | } __attribute__ ((packed)); |
326 | ||
327 | struct wl1271_rx_mem_pool_addr { | |
328 | u32 addr; | |
329 | u32 addr_extra; | |
330 | }; | |
331 | ||
abb0b3bf TP |
332 | struct wl1271_scan { |
333 | u8 state; | |
334 | u8 ssid[IW_ESSID_MAX_SIZE+1]; | |
335 | size_t ssid_len; | |
336 | u8 active; | |
337 | u8 high_prio; | |
338 | u8 probe_requests; | |
339 | }; | |
340 | ||
8197b711 TP |
341 | struct wl1271_if_operations { |
342 | void (*read)(struct wl1271 *wl, int addr, void *buf, size_t len, | |
343 | bool fixed); | |
344 | void (*write)(struct wl1271 *wl, int addr, void *buf, size_t len, | |
345 | bool fixed); | |
346 | void (*reset)(struct wl1271 *wl); | |
347 | void (*init)(struct wl1271 *wl); | |
becd551c | 348 | void (*power)(struct wl1271 *wl, bool enable); |
8197b711 TP |
349 | struct device* (*dev)(struct wl1271 *wl); |
350 | void (*enable_irq)(struct wl1271 *wl); | |
351 | void (*disable_irq)(struct wl1271 *wl); | |
352 | }; | |
353 | ||
f5fc0f86 LC |
354 | struct wl1271 { |
355 | struct ieee80211_hw *hw; | |
356 | bool mac80211_registered; | |
357 | ||
8197b711 TP |
358 | void *if_priv; |
359 | ||
360 | struct wl1271_if_operations *if_ops; | |
f5fc0f86 LC |
361 | |
362 | void (*set_power)(bool enable); | |
363 | int irq; | |
364 | ||
365 | spinlock_t wl_lock; | |
366 | ||
367 | enum wl1271_state state; | |
368 | struct mutex mutex; | |
369 | ||
830fb67b JO |
370 | #define WL1271_FLAG_STA_RATES_CHANGED (0) |
371 | #define WL1271_FLAG_STA_ASSOCIATED (1) | |
71449f8d JO |
372 | #define WL1271_FLAG_JOINED (2) |
373 | #define WL1271_FLAG_GPIO_POWER (3) | |
374 | #define WL1271_FLAG_TX_QUEUE_STOPPED (4) | |
375 | #define WL1271_FLAG_SCANNING (5) | |
376 | #define WL1271_FLAG_IN_ELP (6) | |
377 | #define WL1271_FLAG_PSM (7) | |
378 | #define WL1271_FLAG_PSM_REQUESTED (8) | |
1e73eb62 JO |
379 | #define WL1271_FLAG_IRQ_PENDING (9) |
380 | #define WL1271_FLAG_IRQ_RUNNING (10) | |
830fb67b JO |
381 | unsigned long flags; |
382 | ||
451de97a | 383 | struct wl1271_partition_set part; |
f5fc0f86 LC |
384 | |
385 | struct wl1271_chip chip; | |
386 | ||
387 | int cmd_box_addr; | |
388 | int event_box_addr; | |
389 | ||
390 | u8 *fw; | |
391 | size_t fw_len; | |
152ee6e0 | 392 | struct wl1271_nvs_file *nvs; |
f5fc0f86 LC |
393 | |
394 | u8 bssid[ETH_ALEN]; | |
395 | u8 mac_addr[ETH_ALEN]; | |
396 | u8 bss_type; | |
397 | u8 ssid[IW_ESSID_MAX_SIZE + 1]; | |
398 | u8 ssid_len; | |
f5fc0f86 LC |
399 | int channel; |
400 | ||
401 | struct wl1271_acx_mem_map *target_mem_map; | |
402 | ||
403 | /* Accounting for allocated / available TX blocks on HW */ | |
404 | u32 tx_blocks_freed[NUM_TX_QUEUES]; | |
405 | u32 tx_blocks_available; | |
ffb591cd | 406 | u32 tx_results_count; |
f5fc0f86 LC |
407 | |
408 | /* Transmitted TX packets counter for chipset interface */ | |
ffb591cd | 409 | u32 tx_packets_count; |
f5fc0f86 LC |
410 | |
411 | /* Time-offset between host and chipset clocks */ | |
ac5e1e39 | 412 | s64 time_offset; |
f5fc0f86 LC |
413 | |
414 | /* Session counter for the chipset */ | |
415 | int session_counter; | |
416 | ||
417 | /* Frames scheduled for transmission, not handled yet */ | |
418 | struct sk_buff_head tx_queue; | |
f5fc0f86 LC |
419 | |
420 | struct work_struct tx_work; | |
c87dec9f | 421 | |
f5fc0f86 | 422 | /* Pending TX frames */ |
be7078c2 | 423 | struct sk_buff *tx_frames[ACX_TX_DESCRIPTORS]; |
f5fc0f86 | 424 | |
ac4e4ce5 JO |
425 | /* Security sequence number counters */ |
426 | u8 tx_security_last_seq; | |
04e36fc5 | 427 | s64 tx_security_seq; |
ac4e4ce5 | 428 | |
f5fc0f86 LC |
429 | /* FW Rx counter */ |
430 | u32 rx_counter; | |
431 | ||
432 | /* Rx memory pool address */ | |
433 | struct wl1271_rx_mem_pool_addr rx_mem_pool_addr; | |
434 | ||
435 | /* The target interrupt mask */ | |
436 | struct work_struct irq_work; | |
437 | ||
438 | /* The mbox event mask */ | |
439 | u32 event_mask; | |
440 | ||
441 | /* Mailbox pointers */ | |
442 | u32 mbox_ptr[2]; | |
443 | ||
444 | /* Are we currently scanning */ | |
abb0b3bf | 445 | struct wl1271_scan scan; |
f5fc0f86 LC |
446 | |
447 | /* Our association ID */ | |
448 | u16 aid; | |
449 | ||
d94cd297 | 450 | /* currently configured rate set */ |
830fb67b | 451 | u32 sta_rate_set; |
d94cd297 | 452 | u32 basic_rate_set; |
830fb67b | 453 | u32 rate_set; |
d94cd297 | 454 | |
8a5a37a6 JO |
455 | /* The current band */ |
456 | enum ieee80211_band band; | |
457 | ||
f5fc0f86 LC |
458 | /* Default key (for WEP) */ |
459 | u32 default_key; | |
460 | ||
461 | unsigned int rx_config; | |
462 | unsigned int rx_filter; | |
463 | ||
f5fc0f86 | 464 | struct completion *elp_compl; |
37b70a81 | 465 | struct delayed_work elp_work; |
f5fc0f86 | 466 | |
19ad0715 JO |
467 | /* retry counter for PSM entries */ |
468 | u8 psm_entry_retry; | |
469 | ||
f5fc0f86 LC |
470 | /* in dBm */ |
471 | int power_level; | |
472 | ||
473 | struct wl1271_stats stats; | |
474 | struct wl1271_debugfs debugfs; | |
475 | ||
476 | u32 buffer_32; | |
477 | u32 buffer_cmd; | |
545f1da8 | 478 | u32 buffer_busyword[WL1271_BUSY_WORD_CNT]; |
f5fc0f86 LC |
479 | |
480 | struct wl1271_fw_status *fw_status; | |
481 | struct wl1271_tx_hw_res_if *tx_res_if; | |
b771eee5 JO |
482 | |
483 | struct ieee80211_vif *vif; | |
d6e19d13 | 484 | |
2b60100b JO |
485 | /* Current chipset configuration */ |
486 | struct conf_drv_settings conf; | |
01c09162 | 487 | |
7fc3a864 JO |
488 | bool sg_enabled; |
489 | ||
01c09162 | 490 | struct list_head list; |
f5fc0f86 LC |
491 | }; |
492 | ||
493 | int wl1271_plt_start(struct wl1271 *wl); | |
494 | int wl1271_plt_stop(struct wl1271 *wl); | |
495 | ||
496 | #define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */ | |
497 | ||
498 | #define SESSION_COUNTER_MAX 7 /* maximum value for the session counter */ | |
499 | ||
500 | #define WL1271_DEFAULT_POWER_LEVEL 0 | |
501 | ||
06f7bc7d JO |
502 | #define WL1271_TX_QUEUE_LOW_WATERMARK 10 |
503 | #define WL1271_TX_QUEUE_HIGH_WATERMARK 25 | |
f5fc0f86 | 504 | |
01ac17ec JO |
505 | /* WL1271 needs a 200ms sleep after power on, and a 20ms sleep before power |
506 | on in case is has been shut down shortly before */ | |
507 | #define WL1271_PRE_POWER_ON_SLEEP 20 /* in miliseconds */ | |
f5fc0f86 LC |
508 | #define WL1271_POWER_ON_SLEEP 200 /* in miliseconds */ |
509 | ||
1ebec3d7 TP |
510 | static inline bool wl1271_11a_enabled(void) |
511 | { | |
152ee6e0 | 512 | /* FIXME: this could be determined based on the NVS-INI file */ |
1ebec3d7 TP |
513 | #ifdef WL1271_80211A_ENABLED |
514 | return true; | |
515 | #else | |
516 | return false; | |
517 | #endif | |
518 | } | |
519 | ||
f5fc0f86 | 520 | #endif |