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f5fc0f86 LC |
1 | /* |
2 | * This file is part of wl1271 | |
3 | * | |
4 | * Copyright (C) 1998-2009 Texas Instruments. All rights reserved. | |
1937e742 | 5 | * Copyright (C) 2008-2010 Nokia Corporation |
f5fc0f86 LC |
6 | * |
7 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef __WL1271_ACX_H__ | |
26 | #define __WL1271_ACX_H__ | |
27 | ||
28 | #include "wl1271.h" | |
29 | #include "wl1271_cmd.h" | |
30 | ||
31 | /************************************************************************* | |
32 | ||
33 | Host Interrupt Register (WiLink -> Host) | |
34 | ||
35 | **************************************************************************/ | |
36 | /* HW Initiated interrupt Watchdog timer expiration */ | |
37 | #define WL1271_ACX_INTR_WATCHDOG BIT(0) | |
38 | /* Init sequence is done (masked interrupt, detection through polling only ) */ | |
39 | #define WL1271_ACX_INTR_INIT_COMPLETE BIT(1) | |
40 | /* Event was entered to Event MBOX #A*/ | |
41 | #define WL1271_ACX_INTR_EVENT_A BIT(2) | |
42 | /* Event was entered to Event MBOX #B*/ | |
43 | #define WL1271_ACX_INTR_EVENT_B BIT(3) | |
44 | /* Command processing completion*/ | |
45 | #define WL1271_ACX_INTR_CMD_COMPLETE BIT(4) | |
46 | /* Signaling the host on HW wakeup */ | |
47 | #define WL1271_ACX_INTR_HW_AVAILABLE BIT(5) | |
48 | /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */ | |
49 | #define WL1271_ACX_INTR_DATA BIT(6) | |
50 | /* Trace meassge on MBOX #A */ | |
51 | #define WL1271_ACX_INTR_TRACE_A BIT(7) | |
52 | /* Trace meassge on MBOX #B */ | |
53 | #define WL1271_ACX_INTR_TRACE_B BIT(8) | |
54 | ||
55 | #define WL1271_ACX_INTR_ALL 0xFFFFFFFF | |
56 | #define WL1271_ACX_ALL_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \ | |
57 | WL1271_ACX_INTR_INIT_COMPLETE | \ | |
58 | WL1271_ACX_INTR_EVENT_A | \ | |
59 | WL1271_ACX_INTR_EVENT_B | \ | |
60 | WL1271_ACX_INTR_CMD_COMPLETE | \ | |
61 | WL1271_ACX_INTR_HW_AVAILABLE | \ | |
62 | WL1271_ACX_INTR_DATA) | |
63 | ||
37079a83 LC |
64 | #define WL1271_INTR_MASK (WL1271_ACX_INTR_EVENT_A | \ |
65 | WL1271_ACX_INTR_EVENT_B | \ | |
66 | WL1271_ACX_INTR_HW_AVAILABLE | \ | |
f5fc0f86 LC |
67 | WL1271_ACX_INTR_DATA) |
68 | ||
69 | /* Target's information element */ | |
70 | struct acx_header { | |
71 | struct wl1271_cmd_header cmd; | |
72 | ||
73 | /* acx (or information element) header */ | |
d0f63b20 | 74 | __le16 id; |
f5fc0f86 LC |
75 | |
76 | /* payload length (not including headers */ | |
d0f63b20 | 77 | __le16 len; |
0b5b72da | 78 | } __attribute__ ((packed)); |
f5fc0f86 LC |
79 | |
80 | struct acx_error_counter { | |
81 | struct acx_header header; | |
82 | ||
83 | /* The number of PLCP errors since the last time this */ | |
84 | /* information element was interrogated. This field is */ | |
85 | /* automatically cleared when it is interrogated.*/ | |
d0f63b20 | 86 | __le32 PLCP_error; |
f5fc0f86 LC |
87 | |
88 | /* The number of FCS errors since the last time this */ | |
89 | /* information element was interrogated. This field is */ | |
90 | /* automatically cleared when it is interrogated.*/ | |
d0f63b20 | 91 | __le32 FCS_error; |
f5fc0f86 LC |
92 | |
93 | /* The number of MPDUs without PLCP header errors received*/ | |
94 | /* since the last time this information element was interrogated. */ | |
95 | /* This field is automatically cleared when it is interrogated.*/ | |
d0f63b20 | 96 | __le32 valid_frame; |
f5fc0f86 LC |
97 | |
98 | /* the number of missed sequence numbers in the squentially */ | |
99 | /* values of frames seq numbers */ | |
d0f63b20 | 100 | __le32 seq_num_miss; |
f5fc0f86 LC |
101 | } __attribute__ ((packed)); |
102 | ||
103 | struct acx_revision { | |
104 | struct acx_header header; | |
105 | ||
106 | /* | |
107 | * The WiLink firmware version, an ASCII string x.x.x.x, | |
108 | * that uniquely identifies the current firmware. | |
109 | * The left most digit is incremented each time a | |
110 | * significant change is made to the firmware, such as | |
111 | * code redesign or new platform support. | |
112 | * The second digit is incremented when major enhancements | |
113 | * are added or major fixes are made. | |
114 | * The third digit is incremented for each GA release. | |
115 | * The fourth digit is incremented for each build. | |
116 | * The first two digits identify a firmware release version, | |
117 | * in other words, a unique set of features. | |
118 | * The first three digits identify a GA release. | |
119 | */ | |
120 | char fw_version[20]; | |
121 | ||
122 | /* | |
123 | * This 4 byte field specifies the WiLink hardware version. | |
124 | * bits 0 - 15: Reserved. | |
125 | * bits 16 - 23: Version ID - The WiLink version ID | |
126 | * (1 = first spin, 2 = second spin, and so on). | |
127 | * bits 24 - 31: Chip ID - The WiLink chip ID. | |
128 | */ | |
d0f63b20 | 129 | __le32 hw_version; |
f5fc0f86 LC |
130 | } __attribute__ ((packed)); |
131 | ||
132 | enum wl1271_psm_mode { | |
133 | /* Active mode */ | |
134 | WL1271_PSM_CAM = 0, | |
135 | ||
136 | /* Power save mode */ | |
137 | WL1271_PSM_PS = 1, | |
138 | ||
139 | /* Extreme low power */ | |
140 | WL1271_PSM_ELP = 2, | |
141 | }; | |
142 | ||
143 | struct acx_sleep_auth { | |
144 | struct acx_header header; | |
145 | ||
146 | /* The sleep level authorization of the device. */ | |
147 | /* 0 - Always active*/ | |
148 | /* 1 - Power down mode: light / fast sleep*/ | |
149 | /* 2 - ELP mode: Deep / Max sleep*/ | |
150 | u8 sleep_auth; | |
151 | u8 padding[3]; | |
152 | } __attribute__ ((packed)); | |
153 | ||
154 | enum { | |
155 | HOSTIF_PCI_MASTER_HOST_INDIRECT, | |
156 | HOSTIF_PCI_MASTER_HOST_DIRECT, | |
157 | HOSTIF_SLAVE, | |
158 | HOSTIF_PKT_RING, | |
159 | HOSTIF_DONTCARE = 0xFF | |
160 | }; | |
161 | ||
162 | #define DEFAULT_UCAST_PRIORITY 0 | |
163 | #define DEFAULT_RX_Q_PRIORITY 0 | |
164 | #define DEFAULT_NUM_STATIONS 1 | |
165 | #define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */ | |
166 | #define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */ | |
167 | #define TRACE_BUFFER_MAX_SIZE 256 | |
168 | ||
169 | #define DP_RX_PACKET_RING_CHUNK_SIZE 1600 | |
170 | #define DP_TX_PACKET_RING_CHUNK_SIZE 1600 | |
171 | #define DP_RX_PACKET_RING_CHUNK_NUM 2 | |
172 | #define DP_TX_PACKET_RING_CHUNK_NUM 2 | |
173 | #define DP_TX_COMPLETE_TIME_OUT 20 | |
f5fc0f86 LC |
174 | |
175 | #define TX_MSDU_LIFETIME_MIN 0 | |
176 | #define TX_MSDU_LIFETIME_MAX 3000 | |
177 | #define TX_MSDU_LIFETIME_DEF 512 | |
178 | #define RX_MSDU_LIFETIME_MIN 0 | |
179 | #define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF | |
180 | #define RX_MSDU_LIFETIME_DEF 512000 | |
181 | ||
182 | struct acx_rx_msdu_lifetime { | |
183 | struct acx_header header; | |
184 | ||
185 | /* | |
186 | * The maximum amount of time, in TU, before the | |
187 | * firmware discards the MSDU. | |
188 | */ | |
d0f63b20 | 189 | __le32 lifetime; |
f5fc0f86 LC |
190 | } __attribute__ ((packed)); |
191 | ||
192 | /* | |
193 | * RX Config Options Table | |
194 | * Bit Definition | |
195 | * === ========== | |
196 | * 31:14 Reserved | |
197 | * 13 Copy RX Status - when set, write three receive status words | |
198 | * to top of rx'd MPDUs. | |
199 | * When cleared, do not write three status words (added rev 1.5) | |
200 | * 12 Reserved | |
201 | * 11 RX Complete upon FCS error - when set, give rx complete | |
202 | * interrupt for FCS errors, after the rx filtering, e.g. unicast | |
203 | * frames not to us with FCS error will not generate an interrupt. | |
204 | * 10 SSID Filter Enable - When set, the WiLink discards all beacon, | |
205 | * probe request, and probe response frames with an SSID that does | |
206 | * not match the SSID specified by the host in the START/JOIN | |
207 | * command. | |
208 | * When clear, the WiLink receives frames with any SSID. | |
209 | * 9 Broadcast Filter Enable - When set, the WiLink discards all | |
210 | * broadcast frames. When clear, the WiLink receives all received | |
211 | * broadcast frames. | |
212 | * 8:6 Reserved | |
213 | * 5 BSSID Filter Enable - When set, the WiLink discards any frames | |
214 | * with a BSSID that does not match the BSSID specified by the | |
215 | * host. | |
216 | * When clear, the WiLink receives frames from any BSSID. | |
217 | * 4 MAC Addr Filter - When set, the WiLink discards any frames | |
218 | * with a destination address that does not match the MAC address | |
219 | * of the adaptor. | |
220 | * When clear, the WiLink receives frames destined to any MAC | |
221 | * address. | |
222 | * 3 Promiscuous - When set, the WiLink receives all valid frames | |
223 | * (i.e., all frames that pass the FCS check). | |
224 | * When clear, only frames that pass the other filters specified | |
225 | * are received. | |
226 | * 2 FCS - When set, the WiLink includes the FCS with the received | |
227 | * frame. | |
228 | * When cleared, the FCS is discarded. | |
229 | * 1 PLCP header - When set, write all data from baseband to frame | |
230 | * buffer including PHY header. | |
231 | * 0 Reserved - Always equal to 0. | |
232 | * | |
233 | * RX Filter Options Table | |
234 | * Bit Definition | |
235 | * === ========== | |
236 | * 31:12 Reserved - Always equal to 0. | |
237 | * 11 Association - When set, the WiLink receives all association | |
238 | * related frames (association request/response, reassocation | |
239 | * request/response, and disassociation). When clear, these frames | |
240 | * are discarded. | |
241 | * 10 Auth/De auth - When set, the WiLink receives all authentication | |
242 | * and de-authentication frames. When clear, these frames are | |
243 | * discarded. | |
244 | * 9 Beacon - When set, the WiLink receives all beacon frames. | |
245 | * When clear, these frames are discarded. | |
246 | * 8 Contention Free - When set, the WiLink receives all contention | |
247 | * free frames. | |
248 | * When clear, these frames are discarded. | |
249 | * 7 Control - When set, the WiLink receives all control frames. | |
250 | * When clear, these frames are discarded. | |
251 | * 6 Data - When set, the WiLink receives all data frames. | |
252 | * When clear, these frames are discarded. | |
253 | * 5 FCS Error - When set, the WiLink receives frames that have FCS | |
254 | * errors. | |
255 | * When clear, these frames are discarded. | |
256 | * 4 Management - When set, the WiLink receives all management | |
257 | * frames. | |
258 | * When clear, these frames are discarded. | |
259 | * 3 Probe Request - When set, the WiLink receives all probe request | |
260 | * frames. | |
261 | * When clear, these frames are discarded. | |
262 | * 2 Probe Response - When set, the WiLink receives all probe | |
263 | * response frames. | |
264 | * When clear, these frames are discarded. | |
265 | * 1 RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK | |
266 | * frames. | |
267 | * When clear, these frames are discarded. | |
268 | * 0 Rsvd Type/Sub Type - When set, the WiLink receives all frames | |
269 | * that have reserved frame types and sub types as defined by the | |
270 | * 802.11 specification. | |
271 | * When clear, these frames are discarded. | |
272 | */ | |
273 | struct acx_rx_config { | |
274 | struct acx_header header; | |
275 | ||
d0f63b20 LC |
276 | __le32 config_options; |
277 | __le32 filter_options; | |
f5fc0f86 LC |
278 | } __attribute__ ((packed)); |
279 | ||
280 | struct acx_packet_detection { | |
281 | struct acx_header header; | |
282 | ||
d0f63b20 | 283 | __le32 threshold; |
f5fc0f86 LC |
284 | } __attribute__ ((packed)); |
285 | ||
286 | ||
287 | enum acx_slot_type { | |
288 | SLOT_TIME_LONG = 0, | |
289 | SLOT_TIME_SHORT = 1, | |
290 | DEFAULT_SLOT_TIME = SLOT_TIME_SHORT, | |
291 | MAX_SLOT_TIMES = 0xFF | |
292 | }; | |
293 | ||
294 | #define STATION_WONE_INDEX 0 | |
295 | ||
296 | struct acx_slot { | |
297 | struct acx_header header; | |
298 | ||
299 | u8 wone_index; /* Reserved */ | |
300 | u8 slot_time; | |
301 | u8 reserved[6]; | |
302 | } __attribute__ ((packed)); | |
303 | ||
304 | ||
c87dec9f JO |
305 | #define ACX_MC_ADDRESS_GROUP_MAX (8) |
306 | #define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX) | |
f5fc0f86 LC |
307 | |
308 | struct acx_dot11_grp_addr_tbl { | |
309 | struct acx_header header; | |
310 | ||
311 | u8 enabled; | |
312 | u8 num_groups; | |
313 | u8 pad[2]; | |
314 | u8 mac_table[ADDRESS_GROUP_MAX_LEN]; | |
315 | } __attribute__ ((packed)); | |
316 | ||
f5fc0f86 LC |
317 | struct acx_rx_timeout { |
318 | struct acx_header header; | |
319 | ||
d0f63b20 LC |
320 | __le16 ps_poll_timeout; |
321 | __le16 upsd_timeout; | |
f5fc0f86 LC |
322 | } __attribute__ ((packed)); |
323 | ||
f5fc0f86 LC |
324 | struct acx_rts_threshold { |
325 | struct acx_header header; | |
326 | ||
d0f63b20 | 327 | __le16 threshold; |
f5fc0f86 LC |
328 | u8 pad[2]; |
329 | } __attribute__ ((packed)); | |
330 | ||
331 | struct acx_beacon_filter_option { | |
332 | struct acx_header header; | |
333 | ||
334 | u8 enable; | |
335 | ||
336 | /* | |
337 | * The number of beacons without the unicast TIM | |
338 | * bit set that the firmware buffers before | |
339 | * signaling the host about ready frames. | |
340 | * When set to 0 and the filter is enabled, beacons | |
341 | * without the unicast TIM bit set are dropped. | |
342 | */ | |
343 | u8 max_num_beacons; | |
344 | u8 pad[2]; | |
345 | } __attribute__ ((packed)); | |
346 | ||
347 | /* | |
348 | * ACXBeaconFilterEntry (not 221) | |
349 | * Byte Offset Size (Bytes) Definition | |
350 | * =========== ============ ========== | |
1937e742 | 351 | * 0 1 IE identifier |
f5fc0f86 LC |
352 | * 1 1 Treatment bit mask |
353 | * | |
354 | * ACXBeaconFilterEntry (221) | |
355 | * Byte Offset Size (Bytes) Definition | |
356 | * =========== ============ ========== | |
357 | * 0 1 IE identifier | |
358 | * 1 1 Treatment bit mask | |
359 | * 2 3 OUI | |
360 | * 5 1 Type | |
361 | * 6 2 Version | |
362 | * | |
363 | * | |
364 | * Treatment bit mask - The information element handling: | |
365 | * bit 0 - The information element is compared and transferred | |
366 | * in case of change. | |
367 | * bit 1 - The information element is transferred to the host | |
368 | * with each appearance or disappearance. | |
369 | * Note that both bits can be set at the same time. | |
370 | */ | |
371 | #define BEACON_FILTER_TABLE_MAX_IE_NUM (32) | |
372 | #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6) | |
373 | #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2) | |
374 | #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6) | |
375 | #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \ | |
376 | BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \ | |
377 | (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \ | |
378 | BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE)) | |
379 | ||
380 | struct acx_beacon_filter_ie_table { | |
381 | struct acx_header header; | |
382 | ||
383 | u8 num_ie; | |
f5fc0f86 | 384 | u8 pad[3]; |
1937e742 | 385 | u8 table[BEACON_FILTER_TABLE_MAX_SIZE]; |
f5fc0f86 LC |
386 | } __attribute__ ((packed)); |
387 | ||
34415236 JO |
388 | struct acx_conn_monit_params { |
389 | struct acx_header header; | |
390 | ||
d0f63b20 LC |
391 | __le32 synch_fail_thold; /* number of beacons missed */ |
392 | __le32 bss_lose_timeout; /* number of TU's from synch fail */ | |
0b5b72da | 393 | } __attribute__ ((packed)); |
34415236 | 394 | |
f5fc0f86 LC |
395 | struct acx_bt_wlan_coex { |
396 | struct acx_header header; | |
397 | ||
f5fc0f86 LC |
398 | u8 enable; |
399 | u8 pad[3]; | |
400 | } __attribute__ ((packed)); | |
401 | ||
885c9907 | 402 | struct acx_bt_wlan_coex_param { |
6e92b416 LC |
403 | struct acx_header header; |
404 | ||
1b00f546 | 405 | __le32 params[CONF_SG_PARAMS_MAX]; |
885c9907 | 406 | u8 param_idx; |
6e92b416 | 407 | u8 padding[3]; |
6e92b416 LC |
408 | } __attribute__ ((packed)); |
409 | ||
885c9907 | 410 | struct acx_dco_itrim_params { |
f5fc0f86 LC |
411 | struct acx_header header; |
412 | ||
885c9907 | 413 | u8 enable; |
2b60100b | 414 | u8 padding[3]; |
885c9907 | 415 | __le32 timeout; |
f5fc0f86 LC |
416 | } __attribute__ ((packed)); |
417 | ||
f5fc0f86 LC |
418 | struct acx_energy_detection { |
419 | struct acx_header header; | |
420 | ||
421 | /* The RX Clear Channel Assessment threshold in the PHY */ | |
d0f63b20 | 422 | __le16 rx_cca_threshold; |
f5fc0f86 LC |
423 | u8 tx_energy_detection; |
424 | u8 pad; | |
425 | } __attribute__ ((packed)); | |
426 | ||
f5fc0f86 LC |
427 | struct acx_beacon_broadcast { |
428 | struct acx_header header; | |
429 | ||
d0f63b20 LC |
430 | __le16 beacon_rx_timeout; |
431 | __le16 broadcast_timeout; | |
f5fc0f86 LC |
432 | |
433 | /* Enables receiving of broadcast packets in PS mode */ | |
434 | u8 rx_broadcast_in_ps; | |
435 | ||
436 | /* Consecutive PS Poll failures before updating the host */ | |
437 | u8 ps_poll_threshold; | |
438 | u8 pad[2]; | |
439 | } __attribute__ ((packed)); | |
440 | ||
441 | struct acx_event_mask { | |
442 | struct acx_header header; | |
443 | ||
d0f63b20 LC |
444 | __le32 event_mask; |
445 | __le32 high_event_mask; /* Unused */ | |
f5fc0f86 LC |
446 | } __attribute__ ((packed)); |
447 | ||
448 | #define CFG_RX_FCS BIT(2) | |
449 | #define CFG_RX_ALL_GOOD BIT(3) | |
450 | #define CFG_UNI_FILTER_EN BIT(4) | |
451 | #define CFG_BSSID_FILTER_EN BIT(5) | |
452 | #define CFG_MC_FILTER_EN BIT(6) | |
453 | #define CFG_MC_ADDR0_EN BIT(7) | |
454 | #define CFG_MC_ADDR1_EN BIT(8) | |
455 | #define CFG_BC_REJECT_EN BIT(9) | |
456 | #define CFG_SSID_FILTER_EN BIT(10) | |
457 | #define CFG_RX_INT_FCS_ERROR BIT(11) | |
458 | #define CFG_RX_INT_ENCRYPTED BIT(12) | |
459 | #define CFG_RX_WR_RX_STATUS BIT(13) | |
460 | #define CFG_RX_FILTER_NULTI BIT(14) | |
461 | #define CFG_RX_RESERVE BIT(15) | |
462 | #define CFG_RX_TIMESTAMP_TSF BIT(16) | |
463 | ||
464 | #define CFG_RX_RSV_EN BIT(0) | |
465 | #define CFG_RX_RCTS_ACK BIT(1) | |
466 | #define CFG_RX_PRSP_EN BIT(2) | |
467 | #define CFG_RX_PREQ_EN BIT(3) | |
468 | #define CFG_RX_MGMT_EN BIT(4) | |
469 | #define CFG_RX_FCS_ERROR BIT(5) | |
470 | #define CFG_RX_DATA_EN BIT(6) | |
471 | #define CFG_RX_CTL_EN BIT(7) | |
472 | #define CFG_RX_CF_EN BIT(8) | |
473 | #define CFG_RX_BCN_EN BIT(9) | |
474 | #define CFG_RX_AUTH_EN BIT(10) | |
475 | #define CFG_RX_ASSOC_EN BIT(11) | |
476 | ||
477 | #define SCAN_PASSIVE BIT(0) | |
478 | #define SCAN_5GHZ_BAND BIT(1) | |
479 | #define SCAN_TRIGGERED BIT(2) | |
480 | #define SCAN_PRIORITY_HIGH BIT(3) | |
481 | ||
2b60100b JO |
482 | /* When set, disable HW encryption */ |
483 | #define DF_ENCRYPTION_DISABLE 0x01 | |
484 | #define DF_SNIFF_MODE_ENABLE 0x80 | |
485 | ||
f5fc0f86 LC |
486 | struct acx_feature_config { |
487 | struct acx_header header; | |
488 | ||
d0f63b20 LC |
489 | __le32 options; |
490 | __le32 data_flow_options; | |
f5fc0f86 LC |
491 | } __attribute__ ((packed)); |
492 | ||
493 | struct acx_current_tx_power { | |
494 | struct acx_header header; | |
495 | ||
496 | u8 current_tx_power; | |
497 | u8 padding[3]; | |
498 | } __attribute__ ((packed)); | |
499 | ||
f5fc0f86 LC |
500 | struct acx_wake_up_condition { |
501 | struct acx_header header; | |
502 | ||
503 | u8 wake_up_event; /* Only one bit can be set */ | |
504 | u8 listen_interval; | |
505 | u8 pad[2]; | |
506 | } __attribute__ ((packed)); | |
507 | ||
508 | struct acx_aid { | |
509 | struct acx_header header; | |
510 | ||
511 | /* | |
512 | * To be set when associated with an AP. | |
513 | */ | |
d0f63b20 | 514 | __le16 aid; |
f5fc0f86 LC |
515 | u8 pad[2]; |
516 | } __attribute__ ((packed)); | |
517 | ||
518 | enum acx_preamble_type { | |
519 | ACX_PREAMBLE_LONG = 0, | |
520 | ACX_PREAMBLE_SHORT = 1 | |
521 | }; | |
522 | ||
523 | struct acx_preamble { | |
524 | struct acx_header header; | |
525 | ||
526 | /* | |
527 | * When set, the WiLink transmits the frames with a short preamble and | |
528 | * when cleared, the WiLink transmits the frames with a long preamble. | |
529 | */ | |
530 | u8 preamble; | |
531 | u8 padding[3]; | |
532 | } __attribute__ ((packed)); | |
533 | ||
534 | enum acx_ctsprotect_type { | |
535 | CTSPROTECT_DISABLE = 0, | |
536 | CTSPROTECT_ENABLE = 1 | |
537 | }; | |
538 | ||
539 | struct acx_ctsprotect { | |
540 | struct acx_header header; | |
541 | u8 ctsprotect; | |
542 | u8 padding[3]; | |
543 | } __attribute__ ((packed)); | |
544 | ||
545 | struct acx_tx_statistics { | |
d0f63b20 | 546 | __le32 internal_desc_overflow; |
f5fc0f86 LC |
547 | } __attribute__ ((packed)); |
548 | ||
549 | struct acx_rx_statistics { | |
d0f63b20 LC |
550 | __le32 out_of_mem; |
551 | __le32 hdr_overflow; | |
552 | __le32 hw_stuck; | |
553 | __le32 dropped; | |
554 | __le32 fcs_err; | |
555 | __le32 xfr_hint_trig; | |
556 | __le32 path_reset; | |
557 | __le32 reset_counter; | |
f5fc0f86 LC |
558 | } __attribute__ ((packed)); |
559 | ||
560 | struct acx_dma_statistics { | |
d0f63b20 LC |
561 | __le32 rx_requested; |
562 | __le32 rx_errors; | |
563 | __le32 tx_requested; | |
564 | __le32 tx_errors; | |
f5fc0f86 LC |
565 | } __attribute__ ((packed)); |
566 | ||
567 | struct acx_isr_statistics { | |
568 | /* host command complete */ | |
d0f63b20 | 569 | __le32 cmd_cmplt; |
f5fc0f86 LC |
570 | |
571 | /* fiqisr() */ | |
d0f63b20 | 572 | __le32 fiqs; |
f5fc0f86 LC |
573 | |
574 | /* (INT_STS_ND & INT_TRIG_RX_HEADER) */ | |
d0f63b20 | 575 | __le32 rx_headers; |
f5fc0f86 LC |
576 | |
577 | /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */ | |
d0f63b20 | 578 | __le32 rx_completes; |
f5fc0f86 LC |
579 | |
580 | /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */ | |
d0f63b20 | 581 | __le32 rx_mem_overflow; |
f5fc0f86 LC |
582 | |
583 | /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */ | |
d0f63b20 | 584 | __le32 rx_rdys; |
f5fc0f86 LC |
585 | |
586 | /* irqisr() */ | |
d0f63b20 | 587 | __le32 irqs; |
f5fc0f86 LC |
588 | |
589 | /* (INT_STS_ND & INT_TRIG_TX_PROC) */ | |
d0f63b20 | 590 | __le32 tx_procs; |
f5fc0f86 LC |
591 | |
592 | /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */ | |
d0f63b20 | 593 | __le32 decrypt_done; |
f5fc0f86 LC |
594 | |
595 | /* (INT_STS_ND & INT_TRIG_DMA0) */ | |
d0f63b20 | 596 | __le32 dma0_done; |
f5fc0f86 LC |
597 | |
598 | /* (INT_STS_ND & INT_TRIG_DMA1) */ | |
d0f63b20 | 599 | __le32 dma1_done; |
f5fc0f86 LC |
600 | |
601 | /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */ | |
d0f63b20 | 602 | __le32 tx_exch_complete; |
f5fc0f86 LC |
603 | |
604 | /* (INT_STS_ND & INT_TRIG_COMMAND) */ | |
d0f63b20 | 605 | __le32 commands; |
f5fc0f86 LC |
606 | |
607 | /* (INT_STS_ND & INT_TRIG_RX_PROC) */ | |
d0f63b20 | 608 | __le32 rx_procs; |
f5fc0f86 LC |
609 | |
610 | /* (INT_STS_ND & INT_TRIG_PM_802) */ | |
d0f63b20 | 611 | __le32 hw_pm_mode_changes; |
f5fc0f86 LC |
612 | |
613 | /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */ | |
d0f63b20 | 614 | __le32 host_acknowledges; |
f5fc0f86 LC |
615 | |
616 | /* (INT_STS_ND & INT_TRIG_PM_PCI) */ | |
d0f63b20 | 617 | __le32 pci_pm; |
f5fc0f86 LC |
618 | |
619 | /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */ | |
d0f63b20 | 620 | __le32 wakeups; |
f5fc0f86 LC |
621 | |
622 | /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */ | |
d0f63b20 | 623 | __le32 low_rssi; |
f5fc0f86 LC |
624 | } __attribute__ ((packed)); |
625 | ||
626 | struct acx_wep_statistics { | |
627 | /* WEP address keys configured */ | |
d0f63b20 | 628 | __le32 addr_key_count; |
f5fc0f86 LC |
629 | |
630 | /* default keys configured */ | |
d0f63b20 | 631 | __le32 default_key_count; |
f5fc0f86 | 632 | |
d0f63b20 | 633 | __le32 reserved; |
f5fc0f86 LC |
634 | |
635 | /* number of times that WEP key not found on lookup */ | |
d0f63b20 | 636 | __le32 key_not_found; |
f5fc0f86 LC |
637 | |
638 | /* number of times that WEP key decryption failed */ | |
d0f63b20 | 639 | __le32 decrypt_fail; |
f5fc0f86 LC |
640 | |
641 | /* WEP packets decrypted */ | |
d0f63b20 | 642 | __le32 packets; |
f5fc0f86 LC |
643 | |
644 | /* WEP decrypt interrupts */ | |
d0f63b20 | 645 | __le32 interrupt; |
f5fc0f86 LC |
646 | } __attribute__ ((packed)); |
647 | ||
648 | #define ACX_MISSED_BEACONS_SPREAD 10 | |
649 | ||
650 | struct acx_pwr_statistics { | |
651 | /* the amount of enters into power save mode (both PD & ELP) */ | |
d0f63b20 | 652 | __le32 ps_enter; |
f5fc0f86 LC |
653 | |
654 | /* the amount of enters into ELP mode */ | |
d0f63b20 | 655 | __le32 elp_enter; |
f5fc0f86 LC |
656 | |
657 | /* the amount of missing beacon interrupts to the host */ | |
d0f63b20 | 658 | __le32 missing_bcns; |
f5fc0f86 LC |
659 | |
660 | /* the amount of wake on host-access times */ | |
d0f63b20 | 661 | __le32 wake_on_host; |
f5fc0f86 LC |
662 | |
663 | /* the amount of wake on timer-expire */ | |
d0f63b20 | 664 | __le32 wake_on_timer_exp; |
f5fc0f86 LC |
665 | |
666 | /* the number of packets that were transmitted with PS bit set */ | |
d0f63b20 | 667 | __le32 tx_with_ps; |
f5fc0f86 LC |
668 | |
669 | /* the number of packets that were transmitted with PS bit clear */ | |
d0f63b20 | 670 | __le32 tx_without_ps; |
f5fc0f86 LC |
671 | |
672 | /* the number of received beacons */ | |
d0f63b20 | 673 | __le32 rcvd_beacons; |
f5fc0f86 LC |
674 | |
675 | /* the number of entering into PowerOn (power save off) */ | |
d0f63b20 | 676 | __le32 power_save_off; |
f5fc0f86 LC |
677 | |
678 | /* the number of entries into power save mode */ | |
d0f63b20 | 679 | __le16 enable_ps; |
f5fc0f86 LC |
680 | |
681 | /* | |
682 | * the number of exits from power save, not including failed PS | |
683 | * transitions | |
684 | */ | |
d0f63b20 | 685 | __le16 disable_ps; |
f5fc0f86 LC |
686 | |
687 | /* | |
688 | * the number of times the TSF counter was adjusted because | |
689 | * of drift | |
690 | */ | |
d0f63b20 | 691 | __le32 fix_tsf_ps; |
f5fc0f86 LC |
692 | |
693 | /* Gives statistics about the spread continuous missed beacons. | |
694 | * The 16 LSB are dedicated for the PS mode. | |
695 | * The 16 MSB are dedicated for the PS mode. | |
696 | * cont_miss_bcns_spread[0] - single missed beacon. | |
697 | * cont_miss_bcns_spread[1] - two continuous missed beacons. | |
698 | * cont_miss_bcns_spread[2] - three continuous missed beacons. | |
699 | * ... | |
700 | * cont_miss_bcns_spread[9] - ten and more continuous missed beacons. | |
701 | */ | |
d0f63b20 | 702 | __le32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD]; |
f5fc0f86 LC |
703 | |
704 | /* the number of beacons in awake mode */ | |
d0f63b20 | 705 | __le32 rcvd_awake_beacons; |
f5fc0f86 LC |
706 | } __attribute__ ((packed)); |
707 | ||
708 | struct acx_mic_statistics { | |
d0f63b20 LC |
709 | __le32 rx_pkts; |
710 | __le32 calc_failure; | |
f5fc0f86 LC |
711 | } __attribute__ ((packed)); |
712 | ||
713 | struct acx_aes_statistics { | |
d0f63b20 LC |
714 | __le32 encrypt_fail; |
715 | __le32 decrypt_fail; | |
716 | __le32 encrypt_packets; | |
717 | __le32 decrypt_packets; | |
718 | __le32 encrypt_interrupt; | |
719 | __le32 decrypt_interrupt; | |
f5fc0f86 LC |
720 | } __attribute__ ((packed)); |
721 | ||
722 | struct acx_event_statistics { | |
d0f63b20 LC |
723 | __le32 heart_beat; |
724 | __le32 calibration; | |
725 | __le32 rx_mismatch; | |
726 | __le32 rx_mem_empty; | |
727 | __le32 rx_pool; | |
728 | __le32 oom_late; | |
729 | __le32 phy_transmit_error; | |
730 | __le32 tx_stuck; | |
f5fc0f86 LC |
731 | } __attribute__ ((packed)); |
732 | ||
733 | struct acx_ps_statistics { | |
d0f63b20 LC |
734 | __le32 pspoll_timeouts; |
735 | __le32 upsd_timeouts; | |
736 | __le32 upsd_max_sptime; | |
737 | __le32 upsd_max_apturn; | |
738 | __le32 pspoll_max_apturn; | |
739 | __le32 pspoll_utilization; | |
740 | __le32 upsd_utilization; | |
f5fc0f86 LC |
741 | } __attribute__ ((packed)); |
742 | ||
743 | struct acx_rxpipe_statistics { | |
d0f63b20 LC |
744 | __le32 rx_prep_beacon_drop; |
745 | __le32 descr_host_int_trig_rx_data; | |
746 | __le32 beacon_buffer_thres_host_int_trig_rx_data; | |
747 | __le32 missed_beacon_host_int_trig_rx_data; | |
748 | __le32 tx_xfr_host_int_trig_rx_data; | |
f5fc0f86 LC |
749 | } __attribute__ ((packed)); |
750 | ||
751 | struct acx_statistics { | |
752 | struct acx_header header; | |
753 | ||
754 | struct acx_tx_statistics tx; | |
755 | struct acx_rx_statistics rx; | |
756 | struct acx_dma_statistics dma; | |
757 | struct acx_isr_statistics isr; | |
758 | struct acx_wep_statistics wep; | |
759 | struct acx_pwr_statistics pwr; | |
760 | struct acx_aes_statistics aes; | |
761 | struct acx_mic_statistics mic; | |
762 | struct acx_event_statistics event; | |
763 | struct acx_ps_statistics ps; | |
764 | struct acx_rxpipe_statistics rxpipe; | |
765 | } __attribute__ ((packed)); | |
766 | ||
f5fc0f86 | 767 | struct acx_rate_class { |
d0f63b20 | 768 | __le32 enabled_rates; |
f5fc0f86 LC |
769 | u8 short_retry_limit; |
770 | u8 long_retry_limit; | |
771 | u8 aflags; | |
772 | u8 reserved; | |
773 | }; | |
774 | ||
830fb67b JO |
775 | #define ACX_TX_BASIC_RATE 0 |
776 | #define ACX_TX_AP_FULL_RATE 1 | |
777 | #define ACX_TX_RATE_POLICY_CNT 2 | |
f5fc0f86 LC |
778 | struct acx_rate_policy { |
779 | struct acx_header header; | |
780 | ||
d0f63b20 | 781 | __le32 rate_class_cnt; |
45b531a8 | 782 | struct acx_rate_class rate_class[CONF_TX_MAX_RATE_CLASSES]; |
f5fc0f86 LC |
783 | } __attribute__ ((packed)); |
784 | ||
f5fc0f86 LC |
785 | struct acx_ac_cfg { |
786 | struct acx_header header; | |
787 | u8 ac; | |
788 | u8 cw_min; | |
d0f63b20 | 789 | __le16 cw_max; |
f5fc0f86 LC |
790 | u8 aifsn; |
791 | u8 reserved; | |
d0f63b20 | 792 | __le16 tx_op_limit; |
f5fc0f86 LC |
793 | } __attribute__ ((packed)); |
794 | ||
f5fc0f86 LC |
795 | struct acx_tid_config { |
796 | struct acx_header header; | |
797 | u8 queue_id; | |
798 | u8 channel_type; | |
799 | u8 tsid; | |
800 | u8 ps_scheme; | |
801 | u8 ack_policy; | |
802 | u8 padding[3]; | |
d0f63b20 | 803 | __le32 apsd_conf[2]; |
f5fc0f86 LC |
804 | } __attribute__ ((packed)); |
805 | ||
806 | struct acx_frag_threshold { | |
807 | struct acx_header header; | |
d0f63b20 | 808 | __le16 frag_threshold; |
f5fc0f86 LC |
809 | u8 padding[2]; |
810 | } __attribute__ ((packed)); | |
811 | ||
f5fc0f86 LC |
812 | struct acx_tx_config_options { |
813 | struct acx_header header; | |
d0f63b20 LC |
814 | __le16 tx_compl_timeout; /* msec */ |
815 | __le16 tx_compl_threshold; /* number of packets */ | |
f5fc0f86 LC |
816 | } __attribute__ ((packed)); |
817 | ||
3ed8f2c6 LC |
818 | #define ACX_RX_MEM_BLOCKS 70 |
819 | #define ACX_TX_MIN_MEM_BLOCKS 40 | |
f5fc0f86 LC |
820 | #define ACX_TX_DESCRIPTORS 32 |
821 | #define ACX_NUM_SSID_PROFILES 1 | |
822 | ||
823 | struct wl1271_acx_config_memory { | |
824 | struct acx_header header; | |
825 | ||
826 | u8 rx_mem_block_num; | |
827 | u8 tx_min_mem_block_num; | |
828 | u8 num_stations; | |
829 | u8 num_ssid_profiles; | |
d0f63b20 | 830 | __le32 total_tx_descriptors; |
f5fc0f86 LC |
831 | } __attribute__ ((packed)); |
832 | ||
833 | struct wl1271_acx_mem_map { | |
834 | struct acx_header header; | |
835 | ||
d0f63b20 LC |
836 | __le32 code_start; |
837 | __le32 code_end; | |
f5fc0f86 | 838 | |
d0f63b20 LC |
839 | __le32 wep_defkey_start; |
840 | __le32 wep_defkey_end; | |
f5fc0f86 | 841 | |
d0f63b20 LC |
842 | __le32 sta_table_start; |
843 | __le32 sta_table_end; | |
f5fc0f86 | 844 | |
d0f63b20 LC |
845 | __le32 packet_template_start; |
846 | __le32 packet_template_end; | |
f5fc0f86 LC |
847 | |
848 | /* Address of the TX result interface (control block) */ | |
d0f63b20 LC |
849 | __le32 tx_result; |
850 | __le32 tx_result_queue_start; | |
f5fc0f86 | 851 | |
d0f63b20 LC |
852 | __le32 queue_memory_start; |
853 | __le32 queue_memory_end; | |
f5fc0f86 | 854 | |
d0f63b20 LC |
855 | __le32 packet_memory_pool_start; |
856 | __le32 packet_memory_pool_end; | |
f5fc0f86 | 857 | |
d0f63b20 LC |
858 | __le32 debug_buffer1_start; |
859 | __le32 debug_buffer1_end; | |
f5fc0f86 | 860 | |
d0f63b20 LC |
861 | __le32 debug_buffer2_start; |
862 | __le32 debug_buffer2_end; | |
f5fc0f86 LC |
863 | |
864 | /* Number of blocks FW allocated for TX packets */ | |
d0f63b20 | 865 | __le32 num_tx_mem_blocks; |
f5fc0f86 LC |
866 | |
867 | /* Number of blocks FW allocated for RX packets */ | |
d0f63b20 | 868 | __le32 num_rx_mem_blocks; |
f5fc0f86 LC |
869 | |
870 | /* the following 4 fields are valid in SLAVE mode only */ | |
871 | u8 *tx_cbuf; | |
872 | u8 *rx_cbuf; | |
d0f63b20 LC |
873 | __le32 rx_ctrl; |
874 | __le32 tx_ctrl; | |
f5fc0f86 LC |
875 | } __attribute__ ((packed)); |
876 | ||
f5fc0f86 LC |
877 | struct wl1271_acx_rx_config_opt { |
878 | struct acx_header header; | |
879 | ||
d0f63b20 LC |
880 | __le16 mblk_threshold; |
881 | __le16 threshold; | |
882 | __le16 timeout; | |
f5fc0f86 LC |
883 | u8 queue_type; |
884 | u8 reserved; | |
885 | } __attribute__ ((packed)); | |
886 | ||
11f70f97 JO |
887 | |
888 | struct wl1271_acx_bet_enable { | |
889 | struct acx_header header; | |
890 | ||
891 | u8 enable; | |
892 | u8 max_consecutive; | |
893 | u8 padding[2]; | |
894 | } __attribute__ ((packed)); | |
895 | ||
01c09162 JO |
896 | #define ACX_IPV4_VERSION 4 |
897 | #define ACX_IPV6_VERSION 6 | |
898 | #define ACX_IPV4_ADDR_SIZE 4 | |
899 | struct wl1271_acx_arp_filter { | |
900 | struct acx_header header; | |
901 | u8 version; /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */ | |
902 | u8 enable; /* 1 to enable ARP filtering, 0 to disable */ | |
903 | u8 padding[2]; | |
904 | u8 address[16]; /* The configured device IP address - all ARP | |
905 | requests directed to this IP address will pass | |
906 | through. For IPv4, the first four bytes are | |
907 | used. */ | |
908 | } __attribute__((packed)); | |
909 | ||
38ad2d87 JO |
910 | struct wl1271_acx_pm_config { |
911 | struct acx_header header; | |
912 | ||
913 | __le32 host_clk_settling_time; | |
914 | u8 host_fast_wakeup_support; | |
915 | u8 padding[3]; | |
916 | } __attribute__ ((packed)); | |
01c09162 | 917 | |
c1899554 JO |
918 | struct wl1271_acx_keep_alive_mode { |
919 | struct acx_header header; | |
920 | ||
921 | u8 enabled; | |
922 | u8 padding[3]; | |
923 | } __attribute__ ((packed)); | |
924 | ||
925 | enum { | |
926 | ACX_KEEP_ALIVE_NO_TX = 0, | |
927 | ACX_KEEP_ALIVE_PERIOD_ONLY | |
928 | }; | |
929 | ||
930 | enum { | |
931 | ACX_KEEP_ALIVE_TPL_INVALID = 0, | |
932 | ACX_KEEP_ALIVE_TPL_VALID | |
933 | }; | |
934 | ||
935 | struct wl1271_acx_keep_alive_config { | |
936 | struct acx_header header; | |
937 | ||
938 | __le32 period; | |
939 | u8 index; | |
940 | u8 tpl_validation; | |
941 | u8 trigger; | |
942 | u8 padding; | |
943 | } __attribute__ ((packed)); | |
944 | ||
00236aed JO |
945 | enum { |
946 | WL1271_ACX_TRIG_TYPE_LEVEL = 0, | |
947 | WL1271_ACX_TRIG_TYPE_EDGE, | |
948 | }; | |
949 | ||
950 | enum { | |
951 | WL1271_ACX_TRIG_DIR_LOW = 0, | |
952 | WL1271_ACX_TRIG_DIR_HIGH, | |
953 | WL1271_ACX_TRIG_DIR_BIDIR, | |
954 | }; | |
955 | ||
956 | enum { | |
957 | WL1271_ACX_TRIG_ENABLE = 1, | |
958 | WL1271_ACX_TRIG_DISABLE, | |
959 | }; | |
960 | ||
961 | enum { | |
962 | WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0, | |
963 | WL1271_ACX_TRIG_METRIC_RSSI_DATA, | |
964 | WL1271_ACX_TRIG_METRIC_SNR_BEACON, | |
965 | WL1271_ACX_TRIG_METRIC_SNR_DATA, | |
966 | }; | |
967 | ||
968 | enum { | |
969 | WL1271_ACX_TRIG_IDX_RSSI = 0, | |
970 | WL1271_ACX_TRIG_COUNT = 8, | |
971 | }; | |
972 | ||
973 | struct wl1271_acx_rssi_snr_trigger { | |
974 | struct acx_header header; | |
975 | ||
976 | __le16 threshold; | |
977 | __le16 pacing; /* 0 - 60000 ms */ | |
978 | u8 metric; | |
979 | u8 type; | |
980 | u8 dir; | |
981 | u8 hysteresis; | |
982 | u8 index; | |
983 | u8 enable; | |
984 | u8 padding[2]; | |
985 | }; | |
986 | ||
987 | struct wl1271_acx_rssi_snr_avg_weights { | |
988 | struct acx_header header; | |
989 | ||
990 | u8 rssi_beacon; | |
991 | u8 rssi_data; | |
992 | u8 snr_beacon; | |
993 | u8 snr_data; | |
994 | }; | |
995 | ||
f5fc0f86 LC |
996 | enum { |
997 | ACX_WAKE_UP_CONDITIONS = 0x0002, | |
998 | ACX_MEM_CFG = 0x0003, | |
999 | ACX_SLOT = 0x0004, | |
1000 | ACX_AC_CFG = 0x0007, | |
1001 | ACX_MEM_MAP = 0x0008, | |
1002 | ACX_AID = 0x000A, | |
1003 | /* ACX_FW_REV is missing in the ref driver, but seems to work */ | |
1004 | ACX_FW_REV = 0x000D, | |
1005 | ACX_MEDIUM_USAGE = 0x000F, | |
1006 | ACX_RX_CFG = 0x0010, | |
1007 | ACX_TX_QUEUE_CFG = 0x0011, /* FIXME: only used by wl1251 */ | |
1008 | ACX_STATISTICS = 0x0013, /* Debug API */ | |
1009 | ACX_PWR_CONSUMPTION_STATISTICS = 0x0014, | |
1010 | ACX_FEATURE_CFG = 0x0015, | |
1011 | ACX_TID_CFG = 0x001A, | |
1012 | ACX_PS_RX_STREAMING = 0x001B, | |
1013 | ACX_BEACON_FILTER_OPT = 0x001F, | |
1014 | ACX_NOISE_HIST = 0x0021, | |
1015 | ACX_HDK_VERSION = 0x0022, /* ??? */ | |
1016 | ACX_PD_THRESHOLD = 0x0023, | |
1017 | ACX_TX_CONFIG_OPT = 0x0024, | |
1018 | ACX_CCA_THRESHOLD = 0x0025, | |
1019 | ACX_EVENT_MBOX_MASK = 0x0026, | |
1020 | ACX_CONN_MONIT_PARAMS = 0x002D, | |
1021 | ACX_CONS_TX_FAILURE = 0x002F, | |
1022 | ACX_BCN_DTIM_OPTIONS = 0x0031, | |
1023 | ACX_SG_ENABLE = 0x0032, | |
1024 | ACX_SG_CFG = 0x0033, | |
1025 | ACX_BEACON_FILTER_TABLE = 0x0038, | |
1026 | ACX_ARP_IP_FILTER = 0x0039, | |
1027 | ACX_ROAMING_STATISTICS_TBL = 0x003B, | |
1028 | ACX_RATE_POLICY = 0x003D, | |
1029 | ACX_CTS_PROTECTION = 0x003E, | |
1030 | ACX_SLEEP_AUTH = 0x003F, | |
1031 | ACX_PREAMBLE_TYPE = 0x0040, | |
1032 | ACX_ERROR_CNT = 0x0041, | |
1033 | ACX_IBSS_FILTER = 0x0044, | |
1034 | ACX_SERVICE_PERIOD_TIMEOUT = 0x0045, | |
1035 | ACX_TSF_INFO = 0x0046, | |
1036 | ACX_CONFIG_PS_WMM = 0x0049, | |
1037 | ACX_ENABLE_RX_DATA_FILTER = 0x004A, | |
1038 | ACX_SET_RX_DATA_FILTER = 0x004B, | |
1039 | ACX_GET_DATA_FILTER_STATISTICS = 0x004C, | |
1040 | ACX_RX_CONFIG_OPT = 0x004E, | |
1041 | ACX_FRAG_CFG = 0x004F, | |
1042 | ACX_BET_ENABLE = 0x0050, | |
1043 | ACX_RSSI_SNR_TRIGGER = 0x0051, | |
00236aed | 1044 | ACX_RSSI_SNR_WEIGHTS = 0x0052, |
c1899554 | 1045 | ACX_KEEP_ALIVE_MODE = 0x0053, |
f5fc0f86 LC |
1046 | ACX_SET_KEEP_ALIVE_CONFIG = 0x0054, |
1047 | ACX_BA_SESSION_RESPONDER_POLICY = 0x0055, | |
1048 | ACX_BA_SESSION_INITIATOR_POLICY = 0x0056, | |
1049 | ACX_PEER_HT_CAP = 0x0057, | |
1050 | ACX_HT_BSS_OPERATION = 0x0058, | |
1051 | ACX_COEX_ACTIVITY = 0x0059, | |
3cfd6cf9 | 1052 | ACX_SET_SMART_REFLEX_DEBUG = 0x005A, |
6e92b416 | 1053 | ACX_SET_DCO_ITRIM_PARAMS = 0x0061, |
f5fc0f86 LC |
1054 | DOT11_RX_MSDU_LIFE_TIME = 0x1004, |
1055 | DOT11_CUR_TX_PWR = 0x100D, | |
1056 | DOT11_RX_DOT11_MODE = 0x1012, | |
1057 | DOT11_RTS_THRESHOLD = 0x1013, | |
1058 | DOT11_GROUP_ADDRESS_TBL = 0x1014, | |
38ad2d87 | 1059 | ACX_PM_CONFIG = 0x1016, |
f5fc0f86 LC |
1060 | |
1061 | MAX_DOT11_IE = DOT11_GROUP_ADDRESS_TBL, | |
1062 | ||
1063 | MAX_IE = 0xFFFF | |
1064 | }; | |
1065 | ||
1066 | ||
51f2be24 | 1067 | int wl1271_acx_wake_up_conditions(struct wl1271 *wl); |
f5fc0f86 LC |
1068 | int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth); |
1069 | int wl1271_acx_fw_version(struct wl1271 *wl, char *buf, size_t len); | |
1070 | int wl1271_acx_tx_power(struct wl1271 *wl, int power); | |
1071 | int wl1271_acx_feature_cfg(struct wl1271 *wl); | |
1072 | int wl1271_acx_mem_map(struct wl1271 *wl, | |
1073 | struct acx_header *mem_map, size_t len); | |
8793f9bb | 1074 | int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl); |
f5fc0f86 LC |
1075 | int wl1271_acx_rx_config(struct wl1271 *wl, u32 config, u32 filter); |
1076 | int wl1271_acx_pd_threshold(struct wl1271 *wl); | |
1077 | int wl1271_acx_slot(struct wl1271 *wl, enum acx_slot_type slot_time); | |
c87dec9f JO |
1078 | int wl1271_acx_group_address_tbl(struct wl1271 *wl, bool enable, |
1079 | void *mc_list, u32 mc_list_len); | |
f5fc0f86 LC |
1080 | int wl1271_acx_service_period_timeout(struct wl1271 *wl); |
1081 | int wl1271_acx_rts_threshold(struct wl1271 *wl, u16 rts_threshold); | |
6e92b416 | 1082 | int wl1271_acx_dco_itrim_params(struct wl1271 *wl); |
1922167b | 1083 | int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, bool enable_filter); |
f5fc0f86 | 1084 | int wl1271_acx_beacon_filter_table(struct wl1271 *wl); |
6ccbb92e | 1085 | int wl1271_acx_conn_monit_params(struct wl1271 *wl, bool enable); |
7fc3a864 | 1086 | int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable); |
f5fc0f86 LC |
1087 | int wl1271_acx_sg_cfg(struct wl1271 *wl); |
1088 | int wl1271_acx_cca_threshold(struct wl1271 *wl); | |
1089 | int wl1271_acx_bcn_dtim_options(struct wl1271 *wl); | |
1090 | int wl1271_acx_aid(struct wl1271 *wl, u16 aid); | |
1091 | int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask); | |
1092 | int wl1271_acx_set_preamble(struct wl1271 *wl, enum acx_preamble_type preamble); | |
1093 | int wl1271_acx_cts_protect(struct wl1271 *wl, | |
11f70f97 | 1094 | enum acx_ctsprotect_type ctsprotect); |
f5fc0f86 | 1095 | int wl1271_acx_statistics(struct wl1271 *wl, struct acx_statistics *stats); |
830fb67b | 1096 | int wl1271_acx_rate_policies(struct wl1271 *wl); |
243eeb51 KV |
1097 | int wl1271_acx_ac_cfg(struct wl1271 *wl, u8 ac, u8 cw_min, u16 cw_max, |
1098 | u8 aifsn, u16 txop); | |
f2054df5 KV |
1099 | int wl1271_acx_tid_cfg(struct wl1271 *wl, u8 queue_id, u8 channel_type, |
1100 | u8 tsid, u8 ps_scheme, u8 ack_policy, | |
1101 | u32 apsd_conf0, u32 apsd_conf1); | |
f5fc0f86 LC |
1102 | int wl1271_acx_frag_threshold(struct wl1271 *wl); |
1103 | int wl1271_acx_tx_config_options(struct wl1271 *wl); | |
1104 | int wl1271_acx_mem_cfg(struct wl1271 *wl); | |
1105 | int wl1271_acx_init_mem_config(struct wl1271 *wl); | |
1106 | int wl1271_acx_init_rx_interrupt(struct wl1271 *wl); | |
3cfd6cf9 | 1107 | int wl1271_acx_smart_reflex(struct wl1271 *wl); |
11f70f97 | 1108 | int wl1271_acx_bet_enable(struct wl1271 *wl, bool enable); |
01c09162 JO |
1109 | int wl1271_acx_arp_ip_filter(struct wl1271 *wl, bool enable, u8 *address, |
1110 | u8 version); | |
38ad2d87 | 1111 | int wl1271_acx_pm_config(struct wl1271 *wl); |
c1899554 JO |
1112 | int wl1271_acx_keep_alive_mode(struct wl1271 *wl, bool enable); |
1113 | int wl1271_acx_keep_alive_config(struct wl1271 *wl, u8 index, u8 tpl_valid); | |
00236aed JO |
1114 | int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, bool enable, |
1115 | s16 thold, u8 hyst); | |
1116 | int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl); | |
f5fc0f86 LC |
1117 | |
1118 | #endif /* __WL1271_ACX_H__ */ |