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e85d0918 DD |
1 | /* zd_chip.c |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License as published by | |
5 | * the Free Software Foundation; either version 2 of the License, or | |
6 | * (at your option) any later version. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
16 | */ | |
17 | ||
18 | /* This file implements all the hardware specific functions for the ZD1211 | |
19 | * and ZD1211B chips. Support for the ZD1211B was possible after Timothy | |
20 | * Legge sent me a ZD1211B device. Thank you Tim. -- Uli | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/errno.h> | |
25 | ||
26 | #include "zd_def.h" | |
27 | #include "zd_chip.h" | |
28 | #include "zd_ieee80211.h" | |
29 | #include "zd_mac.h" | |
30 | #include "zd_rf.h" | |
e85d0918 DD |
31 | |
32 | void zd_chip_init(struct zd_chip *chip, | |
459c51ad | 33 | struct ieee80211_hw *hw, |
e85d0918 DD |
34 | struct usb_interface *intf) |
35 | { | |
36 | memset(chip, 0, sizeof(*chip)); | |
37 | mutex_init(&chip->mutex); | |
459c51ad | 38 | zd_usb_init(&chip->usb, hw, intf); |
e85d0918 DD |
39 | zd_rf_init(&chip->rf); |
40 | } | |
41 | ||
42 | void zd_chip_clear(struct zd_chip *chip) | |
43 | { | |
c48cf125 | 44 | ZD_ASSERT(!mutex_is_locked(&chip->mutex)); |
e85d0918 DD |
45 | zd_usb_clear(&chip->usb); |
46 | zd_rf_clear(&chip->rf); | |
e85d0918 | 47 | mutex_destroy(&chip->mutex); |
c48cf125 | 48 | ZD_MEMCLEAR(chip, sizeof(*chip)); |
e85d0918 DD |
49 | } |
50 | ||
74553aed | 51 | static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size) |
e85d0918 | 52 | { |
459c51ad | 53 | u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip)); |
e85d0918 DD |
54 | return scnprintf(buffer, size, "%02x-%02x-%02x", |
55 | addr[0], addr[1], addr[2]); | |
56 | } | |
57 | ||
58 | /* Prints an identifier line, which will support debugging. */ | |
59 | static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size) | |
60 | { | |
61 | int i = 0; | |
62 | ||
63 | i = scnprintf(buffer, size, "zd1211%s chip ", | |
74553aed | 64 | zd_chip_is_zd1211b(chip) ? "b" : ""); |
e85d0918 DD |
65 | i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i); |
66 | i += scnprintf(buffer+i, size-i, " "); | |
74553aed | 67 | i += scnprint_mac_oui(chip, buffer+i, size-i); |
e85d0918 DD |
68 | i += scnprintf(buffer+i, size-i, " "); |
69 | i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i); | |
f2a81a16 | 70 | i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type, |
e85d0918 DD |
71 | chip->patch_cck_gain ? 'g' : '-', |
72 | chip->patch_cr157 ? '7' : '-', | |
20fe2176 | 73 | chip->patch_6m_band_edge ? '6' : '-', |
f2a81a16 DD |
74 | chip->new_phy_layout ? 'N' : '-', |
75 | chip->al2230s_bit ? 'S' : '-'); | |
e85d0918 DD |
76 | return i; |
77 | } | |
78 | ||
79 | static void print_id(struct zd_chip *chip) | |
80 | { | |
81 | char buffer[80]; | |
82 | ||
83 | scnprint_id(chip, buffer, sizeof(buffer)); | |
84 | buffer[sizeof(buffer)-1] = 0; | |
85 | dev_info(zd_chip_dev(chip), "%s\n", buffer); | |
86 | } | |
87 | ||
0ce34bc8 DD |
88 | static zd_addr_t inc_addr(zd_addr_t addr) |
89 | { | |
90 | u16 a = (u16)addr; | |
91 | /* Control registers use byte addressing, but everything else uses word | |
92 | * addressing. */ | |
93 | if ((a & 0xf000) == CR_START) | |
94 | a += 2; | |
95 | else | |
96 | a += 1; | |
97 | return (zd_addr_t)a; | |
98 | } | |
99 | ||
e85d0918 DD |
100 | /* Read a variable number of 32-bit values. Parameter count is not allowed to |
101 | * exceed USB_MAX_IOREAD32_COUNT. | |
102 | */ | |
103 | int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr, | |
104 | unsigned int count) | |
105 | { | |
106 | int r; | |
107 | int i; | |
fa46081c | 108 | zd_addr_t *a16; |
e85d0918 DD |
109 | u16 *v16; |
110 | unsigned int count16; | |
111 | ||
112 | if (count > USB_MAX_IOREAD32_COUNT) | |
113 | return -EINVAL; | |
114 | ||
115 | /* Allocate a single memory block for values and addresses. */ | |
116 | count16 = 2*count; | |
44956855 | 117 | a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)), |
35c3404e | 118 | GFP_KERNEL); |
e85d0918 DD |
119 | if (!a16) { |
120 | dev_dbg_f(zd_chip_dev(chip), | |
121 | "error ENOMEM in allocation of a16\n"); | |
122 | r = -ENOMEM; | |
123 | goto out; | |
124 | } | |
125 | v16 = (u16 *)(a16 + count16); | |
126 | ||
127 | for (i = 0; i < count; i++) { | |
128 | int j = 2*i; | |
129 | /* We read the high word always first. */ | |
0ce34bc8 | 130 | a16[j] = inc_addr(addr[i]); |
e85d0918 DD |
131 | a16[j+1] = addr[i]; |
132 | } | |
133 | ||
134 | r = zd_ioread16v_locked(chip, v16, a16, count16); | |
135 | if (r) { | |
136 | dev_dbg_f(zd_chip_dev(chip), | |
137 | "error: zd_ioread16v_locked. Error number %d\n", r); | |
138 | goto out; | |
139 | } | |
140 | ||
141 | for (i = 0; i < count; i++) { | |
142 | int j = 2*i; | |
143 | values[i] = (v16[j] << 16) | v16[j+1]; | |
144 | } | |
145 | ||
146 | out: | |
147 | kfree((void *)a16); | |
148 | return r; | |
149 | } | |
150 | ||
151 | int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
152 | unsigned int count) | |
153 | { | |
154 | int i, j, r; | |
155 | struct zd_ioreq16 *ioreqs16; | |
156 | unsigned int count16; | |
157 | ||
158 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
159 | ||
160 | if (count == 0) | |
161 | return 0; | |
162 | if (count > USB_MAX_IOWRITE32_COUNT) | |
163 | return -EINVAL; | |
164 | ||
165 | /* Allocate a single memory block for values and addresses. */ | |
166 | count16 = 2*count; | |
35c3404e | 167 | ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL); |
e85d0918 DD |
168 | if (!ioreqs16) { |
169 | r = -ENOMEM; | |
170 | dev_dbg_f(zd_chip_dev(chip), | |
171 | "error %d in ioreqs16 allocation\n", r); | |
172 | goto out; | |
173 | } | |
174 | ||
175 | for (i = 0; i < count; i++) { | |
176 | j = 2*i; | |
177 | /* We write the high word always first. */ | |
178 | ioreqs16[j].value = ioreqs[i].value >> 16; | |
0ce34bc8 | 179 | ioreqs16[j].addr = inc_addr(ioreqs[i].addr); |
e85d0918 DD |
180 | ioreqs16[j+1].value = ioreqs[i].value; |
181 | ioreqs16[j+1].addr = ioreqs[i].addr; | |
182 | } | |
183 | ||
184 | r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16); | |
185 | #ifdef DEBUG | |
186 | if (r) { | |
187 | dev_dbg_f(zd_chip_dev(chip), | |
188 | "error %d in zd_usb_write16v\n", r); | |
189 | } | |
190 | #endif /* DEBUG */ | |
191 | out: | |
192 | kfree(ioreqs16); | |
193 | return r; | |
194 | } | |
195 | ||
196 | int zd_iowrite16a_locked(struct zd_chip *chip, | |
197 | const struct zd_ioreq16 *ioreqs, unsigned int count) | |
198 | { | |
199 | int r; | |
200 | unsigned int i, j, t, max; | |
201 | ||
202 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
203 | for (i = 0; i < count; i += j + t) { | |
204 | t = 0; | |
205 | max = count-i; | |
206 | if (max > USB_MAX_IOWRITE16_COUNT) | |
207 | max = USB_MAX_IOWRITE16_COUNT; | |
208 | for (j = 0; j < max; j++) { | |
209 | if (!ioreqs[i+j].addr) { | |
210 | t = 1; | |
211 | break; | |
212 | } | |
213 | } | |
214 | ||
215 | r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j); | |
216 | if (r) { | |
217 | dev_dbg_f(zd_chip_dev(chip), | |
218 | "error zd_usb_iowrite16v. Error number %d\n", | |
219 | r); | |
220 | return r; | |
221 | } | |
222 | } | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | /* Writes a variable number of 32 bit registers. The functions will split | |
228 | * that in several USB requests. A split can be forced by inserting an IO | |
229 | * request with an zero address field. | |
230 | */ | |
231 | int zd_iowrite32a_locked(struct zd_chip *chip, | |
232 | const struct zd_ioreq32 *ioreqs, unsigned int count) | |
233 | { | |
234 | int r; | |
235 | unsigned int i, j, t, max; | |
236 | ||
237 | for (i = 0; i < count; i += j + t) { | |
238 | t = 0; | |
239 | max = count-i; | |
240 | if (max > USB_MAX_IOWRITE32_COUNT) | |
241 | max = USB_MAX_IOWRITE32_COUNT; | |
242 | for (j = 0; j < max; j++) { | |
243 | if (!ioreqs[i+j].addr) { | |
244 | t = 1; | |
245 | break; | |
246 | } | |
247 | } | |
248 | ||
249 | r = _zd_iowrite32v_locked(chip, &ioreqs[i], j); | |
250 | if (r) { | |
251 | dev_dbg_f(zd_chip_dev(chip), | |
252 | "error _zd_iowrite32v_locked." | |
253 | " Error number %d\n", r); | |
254 | return r; | |
255 | } | |
256 | } | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value) | |
262 | { | |
263 | int r; | |
264 | ||
e85d0918 DD |
265 | mutex_lock(&chip->mutex); |
266 | r = zd_ioread16_locked(chip, value, addr); | |
267 | mutex_unlock(&chip->mutex); | |
268 | return r; | |
269 | } | |
270 | ||
271 | int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value) | |
272 | { | |
273 | int r; | |
274 | ||
e85d0918 DD |
275 | mutex_lock(&chip->mutex); |
276 | r = zd_ioread32_locked(chip, value, addr); | |
277 | mutex_unlock(&chip->mutex); | |
278 | return r; | |
279 | } | |
280 | ||
281 | int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value) | |
282 | { | |
283 | int r; | |
284 | ||
e85d0918 DD |
285 | mutex_lock(&chip->mutex); |
286 | r = zd_iowrite16_locked(chip, value, addr); | |
287 | mutex_unlock(&chip->mutex); | |
288 | return r; | |
289 | } | |
290 | ||
291 | int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value) | |
292 | { | |
293 | int r; | |
294 | ||
e85d0918 DD |
295 | mutex_lock(&chip->mutex); |
296 | r = zd_iowrite32_locked(chip, value, addr); | |
297 | mutex_unlock(&chip->mutex); | |
298 | return r; | |
299 | } | |
300 | ||
301 | int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, | |
302 | u32 *values, unsigned int count) | |
303 | { | |
304 | int r; | |
305 | ||
e85d0918 DD |
306 | mutex_lock(&chip->mutex); |
307 | r = zd_ioread32v_locked(chip, values, addresses, count); | |
308 | mutex_unlock(&chip->mutex); | |
309 | return r; | |
310 | } | |
311 | ||
312 | int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
313 | unsigned int count) | |
314 | { | |
315 | int r; | |
316 | ||
e85d0918 DD |
317 | mutex_lock(&chip->mutex); |
318 | r = zd_iowrite32a_locked(chip, ioreqs, count); | |
319 | mutex_unlock(&chip->mutex); | |
320 | return r; | |
321 | } | |
322 | ||
323 | static int read_pod(struct zd_chip *chip, u8 *rf_type) | |
324 | { | |
325 | int r; | |
326 | u32 value; | |
327 | ||
328 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
329 | r = zd_ioread32_locked(chip, &value, E2P_POD); | |
330 | if (r) | |
331 | goto error; | |
332 | dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value); | |
333 | ||
334 | /* FIXME: AL2230 handling (Bit 7 in POD) */ | |
335 | *rf_type = value & 0x0f; | |
336 | chip->pa_type = (value >> 16) & 0x0f; | |
337 | chip->patch_cck_gain = (value >> 8) & 0x1; | |
338 | chip->patch_cr157 = (value >> 13) & 0x1; | |
339 | chip->patch_6m_band_edge = (value >> 21) & 0x1; | |
20fe2176 | 340 | chip->new_phy_layout = (value >> 31) & 0x1; |
ae6ead46 | 341 | chip->al2230s_bit = (value >> 7) & 0x1; |
583afd1e UK |
342 | chip->link_led = ((value >> 4) & 1) ? LED1 : LED2; |
343 | chip->supports_tx_led = 1; | |
344 | if (value & (1 << 24)) { /* LED scenario */ | |
345 | if (value & (1 << 29)) | |
346 | chip->supports_tx_led = 0; | |
347 | } | |
e85d0918 DD |
348 | |
349 | dev_dbg_f(zd_chip_dev(chip), | |
350 | "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d " | |
583afd1e | 351 | "patch 6M %d new PHY %d link LED%d tx led %d\n", |
e85d0918 DD |
352 | zd_rf_name(*rf_type), *rf_type, |
353 | chip->pa_type, chip->patch_cck_gain, | |
583afd1e UK |
354 | chip->patch_cr157, chip->patch_6m_band_edge, |
355 | chip->new_phy_layout, | |
356 | chip->link_led == LED1 ? 1 : 2, | |
357 | chip->supports_tx_led); | |
e85d0918 DD |
358 | return 0; |
359 | error: | |
360 | *rf_type = 0; | |
361 | chip->pa_type = 0; | |
362 | chip->patch_cck_gain = 0; | |
363 | chip->patch_cr157 = 0; | |
364 | chip->patch_6m_band_edge = 0; | |
20fe2176 | 365 | chip->new_phy_layout = 0; |
e85d0918 DD |
366 | return r; |
367 | } | |
368 | ||
e85d0918 DD |
369 | /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and |
370 | * CR_MAC_ADDR_P2 must be overwritten | |
371 | */ | |
e85d0918 DD |
372 | int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr) |
373 | { | |
374 | int r; | |
375 | struct zd_ioreq32 reqs[2] = { | |
376 | [0] = { .addr = CR_MAC_ADDR_P1 }, | |
377 | [1] = { .addr = CR_MAC_ADDR_P2 }, | |
378 | }; | |
0795af57 | 379 | DECLARE_MAC_BUF(mac); |
e85d0918 | 380 | |
459c51ad DD |
381 | if (mac_addr) { |
382 | reqs[0].value = (mac_addr[3] << 24) | |
383 | | (mac_addr[2] << 16) | |
384 | | (mac_addr[1] << 8) | |
385 | | mac_addr[0]; | |
386 | reqs[1].value = (mac_addr[5] << 8) | |
387 | | mac_addr[4]; | |
388 | dev_dbg_f(zd_chip_dev(chip), | |
389 | "mac addr %s\n", print_mac(mac, mac_addr)); | |
390 | } else { | |
391 | dev_dbg_f(zd_chip_dev(chip), "set NULL mac\n"); | |
392 | } | |
e85d0918 DD |
393 | |
394 | mutex_lock(&chip->mutex); | |
395 | r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); | |
e85d0918 DD |
396 | mutex_unlock(&chip->mutex); |
397 | return r; | |
398 | } | |
399 | ||
400 | int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain) | |
401 | { | |
402 | int r; | |
403 | u32 value; | |
404 | ||
405 | mutex_lock(&chip->mutex); | |
406 | r = zd_ioread32_locked(chip, &value, E2P_SUBID); | |
407 | mutex_unlock(&chip->mutex); | |
408 | if (r) | |
409 | return r; | |
410 | ||
411 | *regdomain = value >> 16; | |
412 | dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain); | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
417 | static int read_values(struct zd_chip *chip, u8 *values, size_t count, | |
418 | zd_addr_t e2p_addr, u32 guard) | |
419 | { | |
420 | int r; | |
421 | int i; | |
422 | u32 v; | |
423 | ||
424 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
425 | for (i = 0;;) { | |
0ce34bc8 DD |
426 | r = zd_ioread32_locked(chip, &v, |
427 | (zd_addr_t)((u16)e2p_addr+i/2)); | |
e85d0918 DD |
428 | if (r) |
429 | return r; | |
430 | v -= guard; | |
431 | if (i+4 < count) { | |
432 | values[i++] = v; | |
433 | values[i++] = v >> 8; | |
434 | values[i++] = v >> 16; | |
435 | values[i++] = v >> 24; | |
436 | continue; | |
437 | } | |
438 | for (;i < count; i++) | |
439 | values[i] = v >> (8*(i%3)); | |
440 | return 0; | |
441 | } | |
442 | } | |
443 | ||
444 | static int read_pwr_cal_values(struct zd_chip *chip) | |
445 | { | |
446 | return read_values(chip, chip->pwr_cal_values, | |
447 | E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1, | |
448 | 0); | |
449 | } | |
450 | ||
451 | static int read_pwr_int_values(struct zd_chip *chip) | |
452 | { | |
453 | return read_values(chip, chip->pwr_int_values, | |
454 | E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1, | |
455 | E2P_PWR_INT_GUARD); | |
456 | } | |
457 | ||
458 | static int read_ofdm_cal_values(struct zd_chip *chip) | |
459 | { | |
460 | int r; | |
461 | int i; | |
462 | static const zd_addr_t addresses[] = { | |
463 | E2P_36M_CAL_VALUE1, | |
464 | E2P_48M_CAL_VALUE1, | |
465 | E2P_54M_CAL_VALUE1, | |
466 | }; | |
467 | ||
468 | for (i = 0; i < 3; i++) { | |
469 | r = read_values(chip, chip->ofdm_cal_values[i], | |
470 | E2P_CHANNEL_COUNT, addresses[i], 0); | |
471 | if (r) | |
472 | return r; | |
473 | } | |
474 | return 0; | |
475 | } | |
476 | ||
477 | static int read_cal_int_tables(struct zd_chip *chip) | |
478 | { | |
479 | int r; | |
480 | ||
481 | r = read_pwr_cal_values(chip); | |
482 | if (r) | |
483 | return r; | |
484 | r = read_pwr_int_values(chip); | |
485 | if (r) | |
486 | return r; | |
487 | r = read_ofdm_cal_values(chip); | |
488 | if (r) | |
489 | return r; | |
490 | return 0; | |
491 | } | |
492 | ||
493 | /* phy means physical registers */ | |
494 | int zd_chip_lock_phy_regs(struct zd_chip *chip) | |
495 | { | |
496 | int r; | |
497 | u32 tmp; | |
498 | ||
499 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
500 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); | |
501 | if (r) { | |
502 | dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r); | |
503 | return r; | |
504 | } | |
505 | ||
e85d0918 DD |
506 | tmp &= ~UNLOCK_PHY_REGS; |
507 | ||
508 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); | |
509 | if (r) | |
510 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); | |
511 | return r; | |
512 | } | |
513 | ||
514 | int zd_chip_unlock_phy_regs(struct zd_chip *chip) | |
515 | { | |
516 | int r; | |
517 | u32 tmp; | |
518 | ||
519 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
520 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); | |
521 | if (r) { | |
522 | dev_err(zd_chip_dev(chip), | |
523 | "error ioread32(CR_REG1): %d\n", r); | |
524 | return r; | |
525 | } | |
526 | ||
e85d0918 DD |
527 | tmp |= UNLOCK_PHY_REGS; |
528 | ||
529 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); | |
530 | if (r) | |
531 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); | |
532 | return r; | |
533 | } | |
534 | ||
92b3e2e9 | 535 | /* CR157 can be optionally patched by the EEPROM for original ZD1211 */ |
e85d0918 DD |
536 | static int patch_cr157(struct zd_chip *chip) |
537 | { | |
538 | int r; | |
92b3e2e9 | 539 | u16 value; |
e85d0918 DD |
540 | |
541 | if (!chip->patch_cr157) | |
542 | return 0; | |
543 | ||
92b3e2e9 | 544 | r = zd_ioread16_locked(chip, &value, E2P_PHY_REG); |
e85d0918 DD |
545 | if (r) |
546 | return r; | |
547 | ||
548 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8); | |
549 | return zd_iowrite32_locked(chip, value >> 8, CR157); | |
550 | } | |
551 | ||
552 | /* | |
553 | * 6M band edge can be optionally overwritten for certain RF's | |
554 | * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge | |
555 | * bit (for AL2230, AL2230S) | |
556 | */ | |
72018b22 DD |
557 | static int patch_6m_band_edge(struct zd_chip *chip, u8 channel) |
558 | { | |
559 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
560 | if (!chip->patch_6m_band_edge) | |
561 | return 0; | |
562 | ||
563 | return zd_rf_patch_6m_band_edge(&chip->rf, channel); | |
564 | } | |
565 | ||
566 | /* Generic implementation of 6M band edge patching, used by most RFs via | |
567 | * zd_rf_generic_patch_6m() */ | |
568 | int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel) | |
e85d0918 DD |
569 | { |
570 | struct zd_ioreq16 ioreqs[] = { | |
571 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, | |
572 | { CR47, 0x1e }, | |
573 | }; | |
574 | ||
e85d0918 DD |
575 | /* FIXME: Channel 11 is not the edge for all regulatory domains. */ |
576 | if (channel == 1 || channel == 11) | |
577 | ioreqs[0].value = 0x12; | |
578 | ||
579 | dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel); | |
580 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
581 | } | |
582 | ||
583 | static int zd1211_hw_reset_phy(struct zd_chip *chip) | |
584 | { | |
585 | static const struct zd_ioreq16 ioreqs[] = { | |
586 | { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 }, | |
587 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 }, | |
588 | { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f }, | |
589 | { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d }, | |
590 | { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a }, | |
591 | { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c }, | |
592 | { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 }, | |
593 | { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 }, | |
594 | { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b }, | |
595 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, | |
596 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, | |
597 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, | |
598 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, | |
599 | { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff }, | |
600 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, | |
601 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, | |
602 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, | |
603 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, | |
604 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, | |
605 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, | |
606 | { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 }, | |
607 | { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 }, | |
608 | { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 }, | |
609 | { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 }, | |
610 | { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 }, | |
611 | { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff }, | |
612 | { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 }, | |
613 | { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 }, | |
614 | { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 }, | |
615 | { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a }, | |
616 | { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 }, | |
617 | { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e }, | |
618 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, | |
619 | { }, | |
620 | { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 }, | |
621 | { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 }, | |
622 | { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 }, | |
623 | { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 }, | |
624 | { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C }, | |
625 | { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 }, | |
626 | { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 }, | |
627 | { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 }, | |
628 | { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 }, | |
629 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, | |
630 | { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 }, | |
631 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, | |
632 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, | |
633 | { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f }, | |
dc536a70 DD |
634 | { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 }, |
635 | { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C }, | |
636 | { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 }, | |
637 | { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 }, | |
638 | { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c }, | |
639 | { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 }, | |
640 | { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe }, | |
641 | { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa }, | |
642 | { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe }, | |
643 | { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba }, | |
644 | { CR170, 0xba }, { CR171, 0xba }, | |
e85d0918 DD |
645 | /* Note: CR204 must lead the CR203 */ |
646 | { CR204, 0x7d }, | |
647 | { }, | |
648 | { CR203, 0x30 }, | |
649 | }; | |
650 | ||
651 | int r, t; | |
652 | ||
653 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
654 | ||
655 | r = zd_chip_lock_phy_regs(chip); | |
656 | if (r) | |
657 | goto out; | |
658 | ||
659 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
660 | if (r) | |
661 | goto unlock; | |
662 | ||
663 | r = patch_cr157(chip); | |
664 | unlock: | |
665 | t = zd_chip_unlock_phy_regs(chip); | |
666 | if (t && !r) | |
667 | r = t; | |
668 | out: | |
669 | return r; | |
670 | } | |
671 | ||
672 | static int zd1211b_hw_reset_phy(struct zd_chip *chip) | |
673 | { | |
674 | static const struct zd_ioreq16 ioreqs[] = { | |
675 | { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 }, | |
676 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 }, | |
677 | { CR10, 0x81 }, | |
678 | /* power control { { CR11, 1 << 6 }, */ | |
679 | { CR11, 0x00 }, | |
680 | { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 }, | |
681 | { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e }, | |
682 | { CR18, 0x0a }, { CR19, 0x48 }, | |
683 | { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */ | |
684 | { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 }, | |
685 | { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 }, | |
686 | { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 }, | |
fe7215ca | 687 | { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */ |
e85d0918 DD |
688 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, |
689 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, | |
690 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, | |
691 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, | |
692 | { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff }, | |
693 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, | |
694 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, | |
695 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, | |
696 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, | |
697 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, | |
698 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, | |
699 | { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 }, | |
700 | { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 }, | |
701 | { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 }, | |
702 | { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 }, | |
703 | { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 }, | |
704 | { CR94, 0x01 }, | |
705 | { CR95, 0x20 }, /* ZD1211B */ | |
706 | { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 }, | |
707 | { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 }, | |
708 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, | |
709 | { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 }, | |
710 | { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 }, | |
711 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, | |
712 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, | |
713 | { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e }, | |
714 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, | |
715 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, | |
716 | { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 }, | |
717 | { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 }, | |
718 | { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c }, | |
719 | { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 }, | |
720 | { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */ | |
721 | { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */ | |
722 | { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe }, | |
723 | { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa }, | |
724 | { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe }, | |
725 | { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba }, | |
726 | { CR170, 0xba }, { CR171, 0xba }, | |
727 | /* Note: CR204 must lead the CR203 */ | |
728 | { CR204, 0x7d }, | |
729 | {}, | |
730 | { CR203, 0x30 }, | |
731 | }; | |
732 | ||
733 | int r, t; | |
734 | ||
735 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
736 | ||
737 | r = zd_chip_lock_phy_regs(chip); | |
738 | if (r) | |
739 | goto out; | |
740 | ||
741 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
e85d0918 DD |
742 | t = zd_chip_unlock_phy_regs(chip); |
743 | if (t && !r) | |
744 | r = t; | |
745 | out: | |
746 | return r; | |
747 | } | |
748 | ||
749 | static int hw_reset_phy(struct zd_chip *chip) | |
750 | { | |
74553aed | 751 | return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) : |
e85d0918 DD |
752 | zd1211_hw_reset_phy(chip); |
753 | } | |
754 | ||
755 | static int zd1211_hw_init_hmac(struct zd_chip *chip) | |
756 | { | |
757 | static const struct zd_ioreq32 ioreqs[] = { | |
e85d0918 | 758 | { CR_ZD1211_RETRY_MAX, 0x2 }, |
e85d0918 | 759 | { CR_RX_THRESHOLD, 0x000c0640 }, |
e85d0918 DD |
760 | }; |
761 | ||
e85d0918 DD |
762 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
763 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
34c44912 | 764 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
e85d0918 DD |
765 | } |
766 | ||
767 | static int zd1211b_hw_init_hmac(struct zd_chip *chip) | |
768 | { | |
769 | static const struct zd_ioreq32 ioreqs[] = { | |
e85d0918 DD |
770 | { CR_ZD1211B_RETRY_MAX, 0x02020202 }, |
771 | { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f }, | |
772 | { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f }, | |
773 | { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f }, | |
774 | { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f }, | |
775 | { CR_ZD1211B_AIFS_CTL1, 0x00280028 }, | |
776 | { CR_ZD1211B_AIFS_CTL2, 0x008C003C }, | |
777 | { CR_ZD1211B_TXOP, 0x01800824 }, | |
34c44912 DD |
778 | { CR_RX_THRESHOLD, 0x000c0eff, }, |
779 | }; | |
780 | ||
781 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
782 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
783 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
784 | } | |
785 | ||
786 | static int hw_init_hmac(struct zd_chip *chip) | |
787 | { | |
788 | int r; | |
789 | static const struct zd_ioreq32 ioreqs[] = { | |
790 | { CR_ACK_TIMEOUT_EXT, 0x20 }, | |
791 | { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, | |
e85d0918 | 792 | { CR_SNIFFER_ON, 0 }, |
fde627b5 | 793 | { CR_RX_FILTER, STA_RX_FILTER }, |
e85d0918 DD |
794 | { CR_GROUP_HASH_P1, 0x00 }, |
795 | { CR_GROUP_HASH_P2, 0x80000000 }, | |
796 | { CR_REG1, 0xa4 }, | |
797 | { CR_ADDA_PWR_DWN, 0x7f }, | |
798 | { CR_BCN_PLCP_CFG, 0x00f00401 }, | |
799 | { CR_PHY_DELAY, 0x00 }, | |
800 | { CR_ACK_TIMEOUT_EXT, 0x80 }, | |
801 | { CR_ADDA_PWR_DWN, 0x00 }, | |
802 | { CR_ACK_TIME_80211, 0x100 }, | |
e85d0918 DD |
803 | { CR_RX_PE_DELAY, 0x70 }, |
804 | { CR_PS_CTRL, 0x10000000 }, | |
805 | { CR_RTS_CTS_RATE, 0x02030203 }, | |
e85d0918 DD |
806 | { CR_AFTER_PNP, 0x1 }, |
807 | { CR_WEP_PROTECT, 0x114 }, | |
34c44912 | 808 | { CR_IFS_VALUE, IFS_VALUE_DEFAULT }, |
e85d0918 DD |
809 | }; |
810 | ||
e85d0918 DD |
811 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
812 | r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
34c44912 DD |
813 | if (r) |
814 | return r; | |
e85d0918 | 815 | |
74553aed | 816 | return zd_chip_is_zd1211b(chip) ? |
e85d0918 DD |
817 | zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip); |
818 | } | |
819 | ||
820 | struct aw_pt_bi { | |
821 | u32 atim_wnd_period; | |
822 | u32 pre_tbtt; | |
823 | u32 beacon_interval; | |
824 | }; | |
825 | ||
826 | static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) | |
827 | { | |
828 | int r; | |
829 | static const zd_addr_t aw_pt_bi_addr[] = | |
830 | { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL }; | |
831 | u32 values[3]; | |
832 | ||
833 | r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr, | |
834 | ARRAY_SIZE(aw_pt_bi_addr)); | |
835 | if (r) { | |
836 | memset(s, 0, sizeof(*s)); | |
837 | return r; | |
838 | } | |
839 | ||
840 | s->atim_wnd_period = values[0]; | |
841 | s->pre_tbtt = values[1]; | |
842 | s->beacon_interval = values[2]; | |
e85d0918 DD |
843 | return 0; |
844 | } | |
845 | ||
846 | static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) | |
847 | { | |
848 | struct zd_ioreq32 reqs[3]; | |
849 | ||
850 | if (s->beacon_interval <= 5) | |
851 | s->beacon_interval = 5; | |
852 | if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval) | |
853 | s->pre_tbtt = s->beacon_interval - 1; | |
854 | if (s->atim_wnd_period >= s->pre_tbtt) | |
855 | s->atim_wnd_period = s->pre_tbtt - 1; | |
856 | ||
857 | reqs[0].addr = CR_ATIM_WND_PERIOD; | |
858 | reqs[0].value = s->atim_wnd_period; | |
859 | reqs[1].addr = CR_PRE_TBTT; | |
860 | reqs[1].value = s->pre_tbtt; | |
861 | reqs[2].addr = CR_BCN_INTERVAL; | |
862 | reqs[2].value = s->beacon_interval; | |
863 | ||
e85d0918 DD |
864 | return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); |
865 | } | |
866 | ||
867 | ||
868 | static int set_beacon_interval(struct zd_chip *chip, u32 interval) | |
869 | { | |
870 | int r; | |
871 | struct aw_pt_bi s; | |
872 | ||
873 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
874 | r = get_aw_pt_bi(chip, &s); | |
875 | if (r) | |
876 | return r; | |
877 | s.beacon_interval = interval; | |
878 | return set_aw_pt_bi(chip, &s); | |
879 | } | |
880 | ||
881 | int zd_set_beacon_interval(struct zd_chip *chip, u32 interval) | |
882 | { | |
883 | int r; | |
884 | ||
885 | mutex_lock(&chip->mutex); | |
886 | r = set_beacon_interval(chip, interval); | |
887 | mutex_unlock(&chip->mutex); | |
888 | return r; | |
889 | } | |
890 | ||
891 | static int hw_init(struct zd_chip *chip) | |
892 | { | |
893 | int r; | |
894 | ||
895 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
896 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
897 | r = hw_reset_phy(chip); | |
898 | if (r) | |
899 | return r; | |
900 | ||
901 | r = hw_init_hmac(chip); | |
902 | if (r) | |
903 | return r; | |
98227a90 | 904 | |
98227a90 | 905 | return set_beacon_interval(chip, 100); |
e85d0918 DD |
906 | } |
907 | ||
0ce34bc8 DD |
908 | static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset) |
909 | { | |
910 | return (zd_addr_t)((u16)chip->fw_regs_base + offset); | |
911 | } | |
912 | ||
e85d0918 DD |
913 | #ifdef DEBUG |
914 | static int dump_cr(struct zd_chip *chip, const zd_addr_t addr, | |
915 | const char *addr_string) | |
916 | { | |
917 | int r; | |
918 | u32 value; | |
919 | ||
920 | r = zd_ioread32_locked(chip, &value, addr); | |
921 | if (r) { | |
922 | dev_dbg_f(zd_chip_dev(chip), | |
923 | "error reading %s. Error number %d\n", addr_string, r); | |
924 | return r; | |
925 | } | |
926 | ||
927 | dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n", | |
928 | addr_string, (unsigned int)value); | |
929 | return 0; | |
930 | } | |
931 | ||
932 | static int test_init(struct zd_chip *chip) | |
933 | { | |
934 | int r; | |
935 | ||
936 | r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP"); | |
937 | if (r) | |
938 | return r; | |
939 | r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN"); | |
940 | if (r) | |
941 | return r; | |
942 | return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT"); | |
943 | } | |
944 | ||
945 | static void dump_fw_registers(struct zd_chip *chip) | |
946 | { | |
0ce34bc8 DD |
947 | const zd_addr_t addr[4] = { |
948 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER), | |
949 | fw_reg_addr(chip, FW_REG_USB_SPEED), | |
950 | fw_reg_addr(chip, FW_REG_FIX_TX_RATE), | |
951 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), | |
e85d0918 DD |
952 | }; |
953 | ||
954 | int r; | |
955 | u16 values[4]; | |
956 | ||
957 | r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr, | |
958 | ARRAY_SIZE(addr)); | |
959 | if (r) { | |
960 | dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n", | |
961 | r); | |
962 | return; | |
963 | } | |
964 | ||
965 | dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]); | |
966 | dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]); | |
967 | dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]); | |
968 | dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]); | |
969 | } | |
970 | #endif /* DEBUG */ | |
971 | ||
972 | static int print_fw_version(struct zd_chip *chip) | |
973 | { | |
974 | int r; | |
975 | u16 version; | |
976 | ||
0ce34bc8 DD |
977 | r = zd_ioread16_locked(chip, &version, |
978 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER)); | |
e85d0918 DD |
979 | if (r) |
980 | return r; | |
981 | ||
982 | dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version); | |
983 | return 0; | |
984 | } | |
985 | ||
459c51ad | 986 | static int set_mandatory_rates(struct zd_chip *chip, int mode) |
e85d0918 DD |
987 | { |
988 | u32 rates; | |
989 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
990 | /* This sets the mandatory rates, which only depend from the standard | |
991 | * that the device is supporting. Until further notice we should try | |
992 | * to support 802.11g also for full speed USB. | |
993 | */ | |
459c51ad DD |
994 | switch (mode) { |
995 | case MODE_IEEE80211B: | |
e85d0918 DD |
996 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M; |
997 | break; | |
459c51ad | 998 | case MODE_IEEE80211G: |
e85d0918 DD |
999 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M| |
1000 | CR_RATE_6M|CR_RATE_12M|CR_RATE_24M; | |
1001 | break; | |
1002 | default: | |
1003 | return -EINVAL; | |
1004 | } | |
1005 | return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL); | |
1006 | } | |
1007 | ||
b1382ede | 1008 | int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, |
459c51ad | 1009 | int preamble) |
b1382ede | 1010 | { |
b1382ede DD |
1011 | u32 value = 0; |
1012 | ||
459c51ad | 1013 | dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble); |
b1382ede DD |
1014 | value |= preamble << RTSCTS_SH_RTS_PMB_TYPE; |
1015 | value |= preamble << RTSCTS_SH_CTS_PMB_TYPE; | |
1016 | ||
459c51ad DD |
1017 | /* We always send 11M RTS/self-CTS messages, like the vendor driver. */ |
1018 | value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE; | |
1019 | value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE; | |
64f222cc | 1020 | value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE; |
b1382ede DD |
1021 | value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE; |
1022 | ||
1023 | return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE); | |
1024 | } | |
1025 | ||
e85d0918 DD |
1026 | int zd_chip_enable_hwint(struct zd_chip *chip) |
1027 | { | |
1028 | int r; | |
1029 | ||
1030 | mutex_lock(&chip->mutex); | |
1031 | r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT); | |
1032 | mutex_unlock(&chip->mutex); | |
1033 | return r; | |
1034 | } | |
1035 | ||
1036 | static int disable_hwint(struct zd_chip *chip) | |
1037 | { | |
1038 | return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT); | |
1039 | } | |
1040 | ||
1041 | int zd_chip_disable_hwint(struct zd_chip *chip) | |
1042 | { | |
1043 | int r; | |
1044 | ||
1045 | mutex_lock(&chip->mutex); | |
1046 | r = disable_hwint(chip); | |
1047 | mutex_unlock(&chip->mutex); | |
1048 | return r; | |
1049 | } | |
1050 | ||
0ce34bc8 DD |
1051 | static int read_fw_regs_offset(struct zd_chip *chip) |
1052 | { | |
1053 | int r; | |
1054 | ||
1055 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1056 | r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base, | |
1057 | FWRAW_REGS_ADDR); | |
1058 | if (r) | |
1059 | return r; | |
1060 | dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n", | |
1061 | (u16)chip->fw_regs_base); | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
74553aed DD |
1066 | /* Read mac address using pre-firmware interface */ |
1067 | int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr) | |
1068 | { | |
1069 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
1070 | return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr, | |
1071 | ETH_ALEN); | |
1072 | } | |
0ce34bc8 | 1073 | |
74553aed | 1074 | int zd_chip_init_hw(struct zd_chip *chip) |
e85d0918 DD |
1075 | { |
1076 | int r; | |
1077 | u8 rf_type; | |
1078 | ||
1079 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
1080 | ||
1081 | mutex_lock(&chip->mutex); | |
e85d0918 DD |
1082 | |
1083 | #ifdef DEBUG | |
1084 | r = test_init(chip); | |
1085 | if (r) | |
1086 | goto out; | |
1087 | #endif | |
1088 | r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP); | |
1089 | if (r) | |
1090 | goto out; | |
1091 | ||
0ce34bc8 | 1092 | r = read_fw_regs_offset(chip); |
e85d0918 DD |
1093 | if (r) |
1094 | goto out; | |
1095 | ||
1096 | /* GPI is always disabled, also in the other driver. | |
1097 | */ | |
1098 | r = zd_iowrite32_locked(chip, 0, CR_GPI_EN); | |
1099 | if (r) | |
1100 | goto out; | |
1101 | r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX); | |
1102 | if (r) | |
1103 | goto out; | |
1104 | /* Currently we support IEEE 802.11g for full and high speed USB. | |
1105 | * It might be discussed, whether we should suppport pure b mode for | |
1106 | * full speed USB. | |
1107 | */ | |
459c51ad | 1108 | r = set_mandatory_rates(chip, MODE_IEEE80211G); |
e85d0918 DD |
1109 | if (r) |
1110 | goto out; | |
1111 | /* Disabling interrupts is certainly a smart thing here. | |
1112 | */ | |
1113 | r = disable_hwint(chip); | |
1114 | if (r) | |
1115 | goto out; | |
1116 | r = read_pod(chip, &rf_type); | |
1117 | if (r) | |
1118 | goto out; | |
1119 | r = hw_init(chip); | |
1120 | if (r) | |
1121 | goto out; | |
1122 | r = zd_rf_init_hw(&chip->rf, rf_type); | |
1123 | if (r) | |
1124 | goto out; | |
1125 | ||
1126 | r = print_fw_version(chip); | |
1127 | if (r) | |
1128 | goto out; | |
1129 | ||
1130 | #ifdef DEBUG | |
1131 | dump_fw_registers(chip); | |
1132 | r = test_init(chip); | |
1133 | if (r) | |
1134 | goto out; | |
1135 | #endif /* DEBUG */ | |
1136 | ||
e85d0918 DD |
1137 | r = read_cal_int_tables(chip); |
1138 | if (r) | |
1139 | goto out; | |
1140 | ||
1141 | print_id(chip); | |
1142 | out: | |
1143 | mutex_unlock(&chip->mutex); | |
1144 | return r; | |
1145 | } | |
1146 | ||
1147 | static int update_pwr_int(struct zd_chip *chip, u8 channel) | |
1148 | { | |
1149 | u8 value = chip->pwr_int_values[channel - 1]; | |
cbb5e6bb | 1150 | return zd_iowrite16_locked(chip, value, CR31); |
e85d0918 DD |
1151 | } |
1152 | ||
1153 | static int update_pwr_cal(struct zd_chip *chip, u8 channel) | |
1154 | { | |
1155 | u8 value = chip->pwr_cal_values[channel-1]; | |
cbb5e6bb | 1156 | return zd_iowrite16_locked(chip, value, CR68); |
e85d0918 DD |
1157 | } |
1158 | ||
1159 | static int update_ofdm_cal(struct zd_chip *chip, u8 channel) | |
1160 | { | |
cbb5e6bb | 1161 | struct zd_ioreq16 ioreqs[3]; |
e85d0918 DD |
1162 | |
1163 | ioreqs[0].addr = CR67; | |
1164 | ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1]; | |
1165 | ioreqs[1].addr = CR66; | |
1166 | ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1]; | |
1167 | ioreqs[2].addr = CR65; | |
1168 | ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1]; | |
1169 | ||
cbb5e6bb | 1170 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
e85d0918 DD |
1171 | } |
1172 | ||
1173 | static int update_channel_integration_and_calibration(struct zd_chip *chip, | |
1174 | u8 channel) | |
1175 | { | |
1176 | int r; | |
1177 | ||
9c8fc71d DD |
1178 | if (!zd_rf_should_update_pwr_int(&chip->rf)) |
1179 | return 0; | |
1180 | ||
e85d0918 DD |
1181 | r = update_pwr_int(chip, channel); |
1182 | if (r) | |
1183 | return r; | |
74553aed | 1184 | if (zd_chip_is_zd1211b(chip)) { |
cbb5e6bb | 1185 | static const struct zd_ioreq16 ioreqs[] = { |
e85d0918 DD |
1186 | { CR69, 0x28 }, |
1187 | {}, | |
1188 | { CR69, 0x2a }, | |
1189 | }; | |
1190 | ||
1191 | r = update_ofdm_cal(chip, channel); | |
1192 | if (r) | |
1193 | return r; | |
1194 | r = update_pwr_cal(chip, channel); | |
1195 | if (r) | |
1196 | return r; | |
cbb5e6bb | 1197 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
e85d0918 DD |
1198 | if (r) |
1199 | return r; | |
1200 | } | |
1201 | ||
1202 | return 0; | |
1203 | } | |
1204 | ||
1205 | /* The CCK baseband gain can be optionally patched by the EEPROM */ | |
1206 | static int patch_cck_gain(struct zd_chip *chip) | |
1207 | { | |
1208 | int r; | |
1209 | u32 value; | |
1210 | ||
aaf83d4f | 1211 | if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf)) |
e85d0918 DD |
1212 | return 0; |
1213 | ||
1214 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1215 | r = zd_ioread32_locked(chip, &value, E2P_PHY_REG); | |
1216 | if (r) | |
1217 | return r; | |
1218 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff); | |
cbb5e6bb | 1219 | return zd_iowrite16_locked(chip, value & 0xff, CR47); |
e85d0918 DD |
1220 | } |
1221 | ||
1222 | int zd_chip_set_channel(struct zd_chip *chip, u8 channel) | |
1223 | { | |
1224 | int r, t; | |
1225 | ||
1226 | mutex_lock(&chip->mutex); | |
1227 | r = zd_chip_lock_phy_regs(chip); | |
1228 | if (r) | |
1229 | goto out; | |
1230 | r = zd_rf_set_channel(&chip->rf, channel); | |
1231 | if (r) | |
1232 | goto unlock; | |
1233 | r = update_channel_integration_and_calibration(chip, channel); | |
1234 | if (r) | |
1235 | goto unlock; | |
1236 | r = patch_cck_gain(chip); | |
1237 | if (r) | |
1238 | goto unlock; | |
1239 | r = patch_6m_band_edge(chip, channel); | |
1240 | if (r) | |
1241 | goto unlock; | |
1242 | r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS); | |
1243 | unlock: | |
1244 | t = zd_chip_unlock_phy_regs(chip); | |
1245 | if (t && !r) | |
1246 | r = t; | |
1247 | out: | |
1248 | mutex_unlock(&chip->mutex); | |
1249 | return r; | |
1250 | } | |
1251 | ||
1252 | u8 zd_chip_get_channel(struct zd_chip *chip) | |
1253 | { | |
1254 | u8 channel; | |
1255 | ||
1256 | mutex_lock(&chip->mutex); | |
1257 | channel = chip->rf.channel; | |
1258 | mutex_unlock(&chip->mutex); | |
1259 | return channel; | |
1260 | } | |
1261 | ||
583afd1e | 1262 | int zd_chip_control_leds(struct zd_chip *chip, enum led_status status) |
e85d0918 | 1263 | { |
0ce34bc8 DD |
1264 | const zd_addr_t a[] = { |
1265 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), | |
583afd1e UK |
1266 | CR_LED, |
1267 | }; | |
e85d0918 | 1268 | |
583afd1e UK |
1269 | int r; |
1270 | u16 v[ARRAY_SIZE(a)]; | |
1271 | struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = { | |
0ce34bc8 | 1272 | [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) }, |
583afd1e UK |
1273 | [1] = { CR_LED }, |
1274 | }; | |
1275 | u16 other_led; | |
e85d0918 | 1276 | |
e85d0918 | 1277 | mutex_lock(&chip->mutex); |
583afd1e | 1278 | r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a)); |
e85d0918 | 1279 | if (r) |
583afd1e UK |
1280 | goto out; |
1281 | ||
1282 | other_led = chip->link_led == LED1 ? LED2 : LED1; | |
1283 | ||
e85d0918 | 1284 | switch (status) { |
e85d0918 | 1285 | case LED_OFF: |
583afd1e UK |
1286 | ioreqs[0].value = FW_LINK_OFF; |
1287 | ioreqs[1].value = v[1] & ~(LED1|LED2); | |
e85d0918 | 1288 | break; |
583afd1e UK |
1289 | case LED_SCANNING: |
1290 | ioreqs[0].value = FW_LINK_OFF; | |
1291 | ioreqs[1].value = v[1] & ~other_led; | |
1292 | if (get_seconds() % 3 == 0) { | |
1293 | ioreqs[1].value &= ~chip->link_led; | |
1294 | } else { | |
1295 | ioreqs[1].value |= chip->link_led; | |
1296 | } | |
e85d0918 | 1297 | break; |
583afd1e UK |
1298 | case LED_ASSOCIATED: |
1299 | ioreqs[0].value = FW_LINK_TX; | |
1300 | ioreqs[1].value = v[1] & ~other_led; | |
1301 | ioreqs[1].value |= chip->link_led; | |
e85d0918 DD |
1302 | break; |
1303 | default: | |
583afd1e | 1304 | r = -EINVAL; |
e85d0918 DD |
1305 | goto out; |
1306 | } | |
e85d0918 | 1307 | |
583afd1e UK |
1308 | if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) { |
1309 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
1310 | if (r) | |
e85d0918 | 1311 | goto out; |
e85d0918 | 1312 | } |
583afd1e | 1313 | r = 0; |
e85d0918 | 1314 | out: |
583afd1e | 1315 | mutex_unlock(&chip->mutex); |
e85d0918 DD |
1316 | return r; |
1317 | } | |
1318 | ||
459c51ad | 1319 | int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates) |
e85d0918 | 1320 | { |
459c51ad DD |
1321 | int r; |
1322 | ||
1323 | if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G)) | |
1324 | return -EINVAL; | |
e85d0918 | 1325 | |
459c51ad DD |
1326 | mutex_lock(&chip->mutex); |
1327 | r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL); | |
1328 | mutex_unlock(&chip->mutex); | |
1329 | return r; | |
e85d0918 DD |
1330 | } |
1331 | ||
64f222cc | 1332 | static int ofdm_qual_db(u8 status_quality, u8 zd_rate, unsigned int size) |
e85d0918 DD |
1333 | { |
1334 | static const u16 constants[] = { | |
1335 | 715, 655, 585, 540, 470, 410, 360, 315, | |
1336 | 270, 235, 205, 175, 150, 125, 105, 85, | |
1337 | 65, 50, 40, 25, 15 | |
1338 | }; | |
1339 | ||
1340 | int i; | |
1341 | u32 x; | |
1342 | ||
1343 | /* It seems that their quality parameter is somehow per signal | |
1344 | * and is now transferred per bit. | |
1345 | */ | |
64f222cc | 1346 | switch (zd_rate) { |
e85d0918 DD |
1347 | case ZD_OFDM_RATE_6M: |
1348 | case ZD_OFDM_RATE_12M: | |
1349 | case ZD_OFDM_RATE_24M: | |
1350 | size *= 2; | |
1351 | break; | |
1352 | case ZD_OFDM_RATE_9M: | |
1353 | case ZD_OFDM_RATE_18M: | |
1354 | case ZD_OFDM_RATE_36M: | |
1355 | case ZD_OFDM_RATE_54M: | |
1356 | size *= 4; | |
1357 | size /= 3; | |
1358 | break; | |
1359 | case ZD_OFDM_RATE_48M: | |
1360 | size *= 3; | |
1361 | size /= 2; | |
1362 | break; | |
1363 | default: | |
1364 | return -EINVAL; | |
1365 | } | |
1366 | ||
1367 | x = (10000 * status_quality)/size; | |
1368 | for (i = 0; i < ARRAY_SIZE(constants); i++) { | |
1369 | if (x > constants[i]) | |
1370 | break; | |
1371 | } | |
1372 | ||
64f222cc | 1373 | switch (zd_rate) { |
db888aed UK |
1374 | case ZD_OFDM_RATE_6M: |
1375 | case ZD_OFDM_RATE_9M: | |
1376 | i += 3; | |
1377 | break; | |
1378 | case ZD_OFDM_RATE_12M: | |
1379 | case ZD_OFDM_RATE_18M: | |
1380 | i += 5; | |
1381 | break; | |
1382 | case ZD_OFDM_RATE_24M: | |
1383 | case ZD_OFDM_RATE_36M: | |
1384 | i += 9; | |
1385 | break; | |
1386 | case ZD_OFDM_RATE_48M: | |
1387 | case ZD_OFDM_RATE_54M: | |
1388 | i += 15; | |
1389 | break; | |
1390 | default: | |
1391 | return -EINVAL; | |
1392 | } | |
1393 | ||
e85d0918 DD |
1394 | return i; |
1395 | } | |
1396 | ||
64f222cc | 1397 | static int ofdm_qual_percent(u8 status_quality, u8 zd_rate, unsigned int size) |
db888aed UK |
1398 | { |
1399 | int r; | |
1400 | ||
64f222cc | 1401 | r = ofdm_qual_db(status_quality, zd_rate, size); |
db888aed UK |
1402 | ZD_ASSERT(r >= 0); |
1403 | if (r < 0) | |
1404 | r = 0; | |
1405 | ||
1406 | r = (r * 100)/29; | |
1407 | return r <= 100 ? r : 100; | |
1408 | } | |
1409 | ||
e85d0918 DD |
1410 | static unsigned int log10times100(unsigned int x) |
1411 | { | |
1412 | static const u8 log10[] = { | |
1413 | 0, | |
1414 | 0, 30, 47, 60, 69, 77, 84, 90, 95, 100, | |
1415 | 104, 107, 111, 114, 117, 120, 123, 125, 127, 130, | |
1416 | 132, 134, 136, 138, 139, 141, 143, 144, 146, 147, | |
1417 | 149, 150, 151, 153, 154, 155, 156, 157, 159, 160, | |
1418 | 161, 162, 163, 164, 165, 166, 167, 168, 169, 169, | |
1419 | 170, 171, 172, 173, 174, 174, 175, 176, 177, 177, | |
1420 | 178, 179, 179, 180, 181, 181, 182, 183, 183, 184, | |
1421 | 185, 185, 186, 186, 187, 188, 188, 189, 189, 190, | |
1422 | 190, 191, 191, 192, 192, 193, 193, 194, 194, 195, | |
1423 | 195, 196, 196, 197, 197, 198, 198, 199, 199, 200, | |
1424 | 200, 200, 201, 201, 202, 202, 202, 203, 203, 204, | |
1425 | 204, 204, 205, 205, 206, 206, 206, 207, 207, 207, | |
1426 | 208, 208, 208, 209, 209, 210, 210, 210, 211, 211, | |
1427 | 211, 212, 212, 212, 213, 213, 213, 213, 214, 214, | |
1428 | 214, 215, 215, 215, 216, 216, 216, 217, 217, 217, | |
1429 | 217, 218, 218, 218, 219, 219, 219, 219, 220, 220, | |
1430 | 220, 220, 221, 221, 221, 222, 222, 222, 222, 223, | |
1431 | 223, 223, 223, 224, 224, 224, 224, | |
1432 | }; | |
1433 | ||
1434 | return x < ARRAY_SIZE(log10) ? log10[x] : 225; | |
1435 | } | |
1436 | ||
1437 | enum { | |
1438 | MAX_CCK_EVM_DB = 45, | |
1439 | }; | |
1440 | ||
1441 | static int cck_evm_db(u8 status_quality) | |
1442 | { | |
1443 | return (20 * log10times100(status_quality)) / 100; | |
1444 | } | |
1445 | ||
1446 | static int cck_snr_db(u8 status_quality) | |
1447 | { | |
1448 | int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality); | |
1449 | ZD_ASSERT(r >= 0); | |
1450 | return r; | |
1451 | } | |
1452 | ||
db888aed | 1453 | static int cck_qual_percent(u8 status_quality) |
e85d0918 | 1454 | { |
db888aed UK |
1455 | int r; |
1456 | ||
1457 | r = cck_snr_db(status_quality); | |
1458 | r = (100*r)/17; | |
1459 | return r <= 100 ? r : 100; | |
e85d0918 DD |
1460 | } |
1461 | ||
64f222cc UK |
1462 | static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame) |
1463 | { | |
1464 | return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame); | |
1465 | } | |
1466 | ||
e85d0918 DD |
1467 | u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size, |
1468 | const struct rx_status *status) | |
1469 | { | |
db888aed UK |
1470 | return (status->frame_status&ZD_RX_OFDM) ? |
1471 | ofdm_qual_percent(status->signal_quality_ofdm, | |
459c51ad | 1472 | zd_rate_from_ofdm_plcp_header(rx_frame), |
db888aed UK |
1473 | size) : |
1474 | cck_qual_percent(status->signal_quality_cck); | |
e85d0918 DD |
1475 | } |
1476 | ||
459c51ad DD |
1477 | /** |
1478 | * zd_rx_rate - report zd-rate | |
1479 | * @rx_frame - received frame | |
1480 | * @rx_status - rx_status as given by the device | |
1481 | * | |
1482 | * This function converts the rate as encoded in the received packet to the | |
1483 | * zd-rate, we are using on other places in the driver. | |
1484 | */ | |
1485 | u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status) | |
e85d0918 | 1486 | { |
459c51ad | 1487 | u8 zd_rate; |
e85d0918 | 1488 | if (status->frame_status & ZD_RX_OFDM) { |
459c51ad | 1489 | zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame); |
e85d0918 | 1490 | } else { |
64f222cc UK |
1491 | switch (zd_cck_plcp_header_signal(rx_frame)) { |
1492 | case ZD_CCK_PLCP_SIGNAL_1M: | |
459c51ad | 1493 | zd_rate = ZD_CCK_RATE_1M; |
e85d0918 | 1494 | break; |
64f222cc | 1495 | case ZD_CCK_PLCP_SIGNAL_2M: |
459c51ad | 1496 | zd_rate = ZD_CCK_RATE_2M; |
e85d0918 | 1497 | break; |
64f222cc | 1498 | case ZD_CCK_PLCP_SIGNAL_5M5: |
459c51ad | 1499 | zd_rate = ZD_CCK_RATE_5_5M; |
e85d0918 | 1500 | break; |
64f222cc | 1501 | case ZD_CCK_PLCP_SIGNAL_11M: |
459c51ad | 1502 | zd_rate = ZD_CCK_RATE_11M; |
e85d0918 DD |
1503 | break; |
1504 | default: | |
459c51ad | 1505 | zd_rate = 0; |
e85d0918 DD |
1506 | } |
1507 | } | |
1508 | ||
459c51ad | 1509 | return zd_rate; |
e85d0918 DD |
1510 | } |
1511 | ||
1512 | int zd_chip_switch_radio_on(struct zd_chip *chip) | |
1513 | { | |
1514 | int r; | |
1515 | ||
1516 | mutex_lock(&chip->mutex); | |
1517 | r = zd_switch_radio_on(&chip->rf); | |
1518 | mutex_unlock(&chip->mutex); | |
1519 | return r; | |
1520 | } | |
1521 | ||
1522 | int zd_chip_switch_radio_off(struct zd_chip *chip) | |
1523 | { | |
1524 | int r; | |
1525 | ||
1526 | mutex_lock(&chip->mutex); | |
1527 | r = zd_switch_radio_off(&chip->rf); | |
1528 | mutex_unlock(&chip->mutex); | |
1529 | return r; | |
1530 | } | |
1531 | ||
1532 | int zd_chip_enable_int(struct zd_chip *chip) | |
1533 | { | |
1534 | int r; | |
1535 | ||
1536 | mutex_lock(&chip->mutex); | |
1537 | r = zd_usb_enable_int(&chip->usb); | |
1538 | mutex_unlock(&chip->mutex); | |
1539 | return r; | |
1540 | } | |
1541 | ||
1542 | void zd_chip_disable_int(struct zd_chip *chip) | |
1543 | { | |
1544 | mutex_lock(&chip->mutex); | |
1545 | zd_usb_disable_int(&chip->usb); | |
1546 | mutex_unlock(&chip->mutex); | |
1547 | } | |
1548 | ||
459c51ad | 1549 | int zd_chip_enable_rxtx(struct zd_chip *chip) |
e85d0918 DD |
1550 | { |
1551 | int r; | |
1552 | ||
1553 | mutex_lock(&chip->mutex); | |
459c51ad | 1554 | zd_usb_enable_tx(&chip->usb); |
e85d0918 DD |
1555 | r = zd_usb_enable_rx(&chip->usb); |
1556 | mutex_unlock(&chip->mutex); | |
1557 | return r; | |
1558 | } | |
1559 | ||
459c51ad | 1560 | void zd_chip_disable_rxtx(struct zd_chip *chip) |
e85d0918 DD |
1561 | { |
1562 | mutex_lock(&chip->mutex); | |
1563 | zd_usb_disable_rx(&chip->usb); | |
459c51ad | 1564 | zd_usb_disable_tx(&chip->usb); |
e85d0918 DD |
1565 | mutex_unlock(&chip->mutex); |
1566 | } | |
1567 | ||
1568 | int zd_rfwritev_locked(struct zd_chip *chip, | |
1569 | const u32* values, unsigned int count, u8 bits) | |
1570 | { | |
1571 | int r; | |
1572 | unsigned int i; | |
1573 | ||
1574 | for (i = 0; i < count; i++) { | |
1575 | r = zd_rfwrite_locked(chip, values[i], bits); | |
1576 | if (r) | |
1577 | return r; | |
1578 | } | |
1579 | ||
1580 | return 0; | |
1581 | } | |
20fe2176 DD |
1582 | |
1583 | /* | |
1584 | * We can optionally program the RF directly through CR regs, if supported by | |
1585 | * the hardware. This is much faster than the older method. | |
1586 | */ | |
ec62bd91 | 1587 | int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value) |
20fe2176 DD |
1588 | { |
1589 | struct zd_ioreq16 ioreqs[] = { | |
1590 | { CR244, (value >> 16) & 0xff }, | |
1591 | { CR243, (value >> 8) & 0xff }, | |
1592 | { CR242, value & 0xff }, | |
1593 | }; | |
1594 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1595 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
1596 | } | |
1597 | ||
1598 | int zd_rfwritev_cr_locked(struct zd_chip *chip, | |
1599 | const u32 *values, unsigned int count) | |
1600 | { | |
1601 | int r; | |
1602 | unsigned int i; | |
1603 | ||
1604 | for (i = 0; i < count; i++) { | |
1605 | r = zd_rfwrite_cr_locked(chip, values[i]); | |
1606 | if (r) | |
1607 | return r; | |
1608 | } | |
1609 | ||
1610 | return 0; | |
1611 | } | |
9cdac965 UK |
1612 | |
1613 | int zd_chip_set_multicast_hash(struct zd_chip *chip, | |
1614 | struct zd_mc_hash *hash) | |
1615 | { | |
1616 | struct zd_ioreq32 ioreqs[] = { | |
1617 | { CR_GROUP_HASH_P1, hash->low }, | |
1618 | { CR_GROUP_HASH_P2, hash->high }, | |
1619 | }; | |
1620 | ||
9cdac965 UK |
1621 | return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
1622 | } |