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66bb42fd DD |
1 | /* ZD1211 USB-WLAN driver for Linux |
2 | * | |
3 | * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de> | |
4 | * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org> | |
e85d0918 DD |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | /* This file implements all the hardware specific functions for the ZD1211 | |
22 | * and ZD1211B chips. Support for the ZD1211B was possible after Timothy | |
23 | * Legge sent me a ZD1211B device. Thank you Tim. -- Uli | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/errno.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
e85d0918 DD |
29 | |
30 | #include "zd_def.h" | |
31 | #include "zd_chip.h" | |
e85d0918 DD |
32 | #include "zd_mac.h" |
33 | #include "zd_rf.h" | |
e85d0918 DD |
34 | |
35 | void zd_chip_init(struct zd_chip *chip, | |
459c51ad | 36 | struct ieee80211_hw *hw, |
e85d0918 DD |
37 | struct usb_interface *intf) |
38 | { | |
39 | memset(chip, 0, sizeof(*chip)); | |
40 | mutex_init(&chip->mutex); | |
459c51ad | 41 | zd_usb_init(&chip->usb, hw, intf); |
e85d0918 DD |
42 | zd_rf_init(&chip->rf); |
43 | } | |
44 | ||
45 | void zd_chip_clear(struct zd_chip *chip) | |
46 | { | |
c48cf125 | 47 | ZD_ASSERT(!mutex_is_locked(&chip->mutex)); |
e85d0918 DD |
48 | zd_usb_clear(&chip->usb); |
49 | zd_rf_clear(&chip->rf); | |
e85d0918 | 50 | mutex_destroy(&chip->mutex); |
c48cf125 | 51 | ZD_MEMCLEAR(chip, sizeof(*chip)); |
e85d0918 DD |
52 | } |
53 | ||
74553aed | 54 | static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size) |
e85d0918 | 55 | { |
459c51ad | 56 | u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip)); |
e85d0918 DD |
57 | return scnprintf(buffer, size, "%02x-%02x-%02x", |
58 | addr[0], addr[1], addr[2]); | |
59 | } | |
60 | ||
61 | /* Prints an identifier line, which will support debugging. */ | |
62 | static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size) | |
63 | { | |
64 | int i = 0; | |
65 | ||
66 | i = scnprintf(buffer, size, "zd1211%s chip ", | |
74553aed | 67 | zd_chip_is_zd1211b(chip) ? "b" : ""); |
e85d0918 DD |
68 | i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i); |
69 | i += scnprintf(buffer+i, size-i, " "); | |
74553aed | 70 | i += scnprint_mac_oui(chip, buffer+i, size-i); |
e85d0918 DD |
71 | i += scnprintf(buffer+i, size-i, " "); |
72 | i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i); | |
f2a81a16 | 73 | i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type, |
e85d0918 DD |
74 | chip->patch_cck_gain ? 'g' : '-', |
75 | chip->patch_cr157 ? '7' : '-', | |
20fe2176 | 76 | chip->patch_6m_band_edge ? '6' : '-', |
f2a81a16 DD |
77 | chip->new_phy_layout ? 'N' : '-', |
78 | chip->al2230s_bit ? 'S' : '-'); | |
e85d0918 DD |
79 | return i; |
80 | } | |
81 | ||
82 | static void print_id(struct zd_chip *chip) | |
83 | { | |
84 | char buffer[80]; | |
85 | ||
86 | scnprint_id(chip, buffer, sizeof(buffer)); | |
87 | buffer[sizeof(buffer)-1] = 0; | |
88 | dev_info(zd_chip_dev(chip), "%s\n", buffer); | |
89 | } | |
90 | ||
0ce34bc8 DD |
91 | static zd_addr_t inc_addr(zd_addr_t addr) |
92 | { | |
93 | u16 a = (u16)addr; | |
94 | /* Control registers use byte addressing, but everything else uses word | |
95 | * addressing. */ | |
96 | if ((a & 0xf000) == CR_START) | |
97 | a += 2; | |
98 | else | |
99 | a += 1; | |
100 | return (zd_addr_t)a; | |
101 | } | |
102 | ||
e85d0918 DD |
103 | /* Read a variable number of 32-bit values. Parameter count is not allowed to |
104 | * exceed USB_MAX_IOREAD32_COUNT. | |
105 | */ | |
106 | int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr, | |
107 | unsigned int count) | |
108 | { | |
109 | int r; | |
110 | int i; | |
fa46081c | 111 | zd_addr_t *a16; |
e85d0918 DD |
112 | u16 *v16; |
113 | unsigned int count16; | |
114 | ||
115 | if (count > USB_MAX_IOREAD32_COUNT) | |
116 | return -EINVAL; | |
117 | ||
118 | /* Allocate a single memory block for values and addresses. */ | |
119 | count16 = 2*count; | |
44956855 | 120 | a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)), |
35c3404e | 121 | GFP_KERNEL); |
e85d0918 DD |
122 | if (!a16) { |
123 | dev_dbg_f(zd_chip_dev(chip), | |
124 | "error ENOMEM in allocation of a16\n"); | |
125 | r = -ENOMEM; | |
126 | goto out; | |
127 | } | |
128 | v16 = (u16 *)(a16 + count16); | |
129 | ||
130 | for (i = 0; i < count; i++) { | |
131 | int j = 2*i; | |
132 | /* We read the high word always first. */ | |
0ce34bc8 | 133 | a16[j] = inc_addr(addr[i]); |
e85d0918 DD |
134 | a16[j+1] = addr[i]; |
135 | } | |
136 | ||
137 | r = zd_ioread16v_locked(chip, v16, a16, count16); | |
138 | if (r) { | |
139 | dev_dbg_f(zd_chip_dev(chip), | |
140 | "error: zd_ioread16v_locked. Error number %d\n", r); | |
141 | goto out; | |
142 | } | |
143 | ||
144 | for (i = 0; i < count; i++) { | |
145 | int j = 2*i; | |
146 | values[i] = (v16[j] << 16) | v16[j+1]; | |
147 | } | |
148 | ||
149 | out: | |
150 | kfree((void *)a16); | |
151 | return r; | |
152 | } | |
153 | ||
154 | int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
155 | unsigned int count) | |
156 | { | |
157 | int i, j, r; | |
158 | struct zd_ioreq16 *ioreqs16; | |
159 | unsigned int count16; | |
160 | ||
161 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
162 | ||
163 | if (count == 0) | |
164 | return 0; | |
165 | if (count > USB_MAX_IOWRITE32_COUNT) | |
166 | return -EINVAL; | |
167 | ||
168 | /* Allocate a single memory block for values and addresses. */ | |
169 | count16 = 2*count; | |
35c3404e | 170 | ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL); |
e85d0918 DD |
171 | if (!ioreqs16) { |
172 | r = -ENOMEM; | |
173 | dev_dbg_f(zd_chip_dev(chip), | |
174 | "error %d in ioreqs16 allocation\n", r); | |
175 | goto out; | |
176 | } | |
177 | ||
178 | for (i = 0; i < count; i++) { | |
179 | j = 2*i; | |
180 | /* We write the high word always first. */ | |
181 | ioreqs16[j].value = ioreqs[i].value >> 16; | |
0ce34bc8 | 182 | ioreqs16[j].addr = inc_addr(ioreqs[i].addr); |
e85d0918 DD |
183 | ioreqs16[j+1].value = ioreqs[i].value; |
184 | ioreqs16[j+1].addr = ioreqs[i].addr; | |
185 | } | |
186 | ||
187 | r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16); | |
188 | #ifdef DEBUG | |
189 | if (r) { | |
190 | dev_dbg_f(zd_chip_dev(chip), | |
191 | "error %d in zd_usb_write16v\n", r); | |
192 | } | |
193 | #endif /* DEBUG */ | |
194 | out: | |
195 | kfree(ioreqs16); | |
196 | return r; | |
197 | } | |
198 | ||
199 | int zd_iowrite16a_locked(struct zd_chip *chip, | |
200 | const struct zd_ioreq16 *ioreqs, unsigned int count) | |
201 | { | |
202 | int r; | |
203 | unsigned int i, j, t, max; | |
204 | ||
205 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
206 | for (i = 0; i < count; i += j + t) { | |
207 | t = 0; | |
208 | max = count-i; | |
209 | if (max > USB_MAX_IOWRITE16_COUNT) | |
210 | max = USB_MAX_IOWRITE16_COUNT; | |
211 | for (j = 0; j < max; j++) { | |
212 | if (!ioreqs[i+j].addr) { | |
213 | t = 1; | |
214 | break; | |
215 | } | |
216 | } | |
217 | ||
218 | r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j); | |
219 | if (r) { | |
220 | dev_dbg_f(zd_chip_dev(chip), | |
221 | "error zd_usb_iowrite16v. Error number %d\n", | |
222 | r); | |
223 | return r; | |
224 | } | |
225 | } | |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
230 | /* Writes a variable number of 32 bit registers. The functions will split | |
231 | * that in several USB requests. A split can be forced by inserting an IO | |
232 | * request with an zero address field. | |
233 | */ | |
234 | int zd_iowrite32a_locked(struct zd_chip *chip, | |
235 | const struct zd_ioreq32 *ioreqs, unsigned int count) | |
236 | { | |
237 | int r; | |
238 | unsigned int i, j, t, max; | |
239 | ||
240 | for (i = 0; i < count; i += j + t) { | |
241 | t = 0; | |
242 | max = count-i; | |
243 | if (max > USB_MAX_IOWRITE32_COUNT) | |
244 | max = USB_MAX_IOWRITE32_COUNT; | |
245 | for (j = 0; j < max; j++) { | |
246 | if (!ioreqs[i+j].addr) { | |
247 | t = 1; | |
248 | break; | |
249 | } | |
250 | } | |
251 | ||
252 | r = _zd_iowrite32v_locked(chip, &ioreqs[i], j); | |
253 | if (r) { | |
254 | dev_dbg_f(zd_chip_dev(chip), | |
255 | "error _zd_iowrite32v_locked." | |
256 | " Error number %d\n", r); | |
257 | return r; | |
258 | } | |
259 | } | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value) | |
265 | { | |
266 | int r; | |
267 | ||
e85d0918 DD |
268 | mutex_lock(&chip->mutex); |
269 | r = zd_ioread16_locked(chip, value, addr); | |
270 | mutex_unlock(&chip->mutex); | |
271 | return r; | |
272 | } | |
273 | ||
274 | int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value) | |
275 | { | |
276 | int r; | |
277 | ||
e85d0918 DD |
278 | mutex_lock(&chip->mutex); |
279 | r = zd_ioread32_locked(chip, value, addr); | |
280 | mutex_unlock(&chip->mutex); | |
281 | return r; | |
282 | } | |
283 | ||
284 | int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value) | |
285 | { | |
286 | int r; | |
287 | ||
e85d0918 DD |
288 | mutex_lock(&chip->mutex); |
289 | r = zd_iowrite16_locked(chip, value, addr); | |
290 | mutex_unlock(&chip->mutex); | |
291 | return r; | |
292 | } | |
293 | ||
294 | int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value) | |
295 | { | |
296 | int r; | |
297 | ||
e85d0918 DD |
298 | mutex_lock(&chip->mutex); |
299 | r = zd_iowrite32_locked(chip, value, addr); | |
300 | mutex_unlock(&chip->mutex); | |
301 | return r; | |
302 | } | |
303 | ||
304 | int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, | |
305 | u32 *values, unsigned int count) | |
306 | { | |
307 | int r; | |
308 | ||
e85d0918 DD |
309 | mutex_lock(&chip->mutex); |
310 | r = zd_ioread32v_locked(chip, values, addresses, count); | |
311 | mutex_unlock(&chip->mutex); | |
312 | return r; | |
313 | } | |
314 | ||
315 | int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
316 | unsigned int count) | |
317 | { | |
318 | int r; | |
319 | ||
e85d0918 DD |
320 | mutex_lock(&chip->mutex); |
321 | r = zd_iowrite32a_locked(chip, ioreqs, count); | |
322 | mutex_unlock(&chip->mutex); | |
323 | return r; | |
324 | } | |
325 | ||
326 | static int read_pod(struct zd_chip *chip, u8 *rf_type) | |
327 | { | |
328 | int r; | |
329 | u32 value; | |
330 | ||
331 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
332 | r = zd_ioread32_locked(chip, &value, E2P_POD); | |
333 | if (r) | |
334 | goto error; | |
335 | dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value); | |
336 | ||
337 | /* FIXME: AL2230 handling (Bit 7 in POD) */ | |
338 | *rf_type = value & 0x0f; | |
339 | chip->pa_type = (value >> 16) & 0x0f; | |
340 | chip->patch_cck_gain = (value >> 8) & 0x1; | |
341 | chip->patch_cr157 = (value >> 13) & 0x1; | |
342 | chip->patch_6m_band_edge = (value >> 21) & 0x1; | |
20fe2176 | 343 | chip->new_phy_layout = (value >> 31) & 0x1; |
ae6ead46 | 344 | chip->al2230s_bit = (value >> 7) & 0x1; |
583afd1e UK |
345 | chip->link_led = ((value >> 4) & 1) ? LED1 : LED2; |
346 | chip->supports_tx_led = 1; | |
347 | if (value & (1 << 24)) { /* LED scenario */ | |
348 | if (value & (1 << 29)) | |
349 | chip->supports_tx_led = 0; | |
350 | } | |
e85d0918 DD |
351 | |
352 | dev_dbg_f(zd_chip_dev(chip), | |
353 | "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d " | |
583afd1e | 354 | "patch 6M %d new PHY %d link LED%d tx led %d\n", |
e85d0918 DD |
355 | zd_rf_name(*rf_type), *rf_type, |
356 | chip->pa_type, chip->patch_cck_gain, | |
583afd1e UK |
357 | chip->patch_cr157, chip->patch_6m_band_edge, |
358 | chip->new_phy_layout, | |
359 | chip->link_led == LED1 ? 1 : 2, | |
360 | chip->supports_tx_led); | |
e85d0918 DD |
361 | return 0; |
362 | error: | |
363 | *rf_type = 0; | |
364 | chip->pa_type = 0; | |
365 | chip->patch_cck_gain = 0; | |
366 | chip->patch_cr157 = 0; | |
367 | chip->patch_6m_band_edge = 0; | |
20fe2176 | 368 | chip->new_phy_layout = 0; |
e85d0918 DD |
369 | return r; |
370 | } | |
371 | ||
fd589a8f | 372 | /* MAC address: if custom mac addresses are to be used CR_MAC_ADDR_P1 and |
e85d0918 DD |
373 | * CR_MAC_ADDR_P2 must be overwritten |
374 | */ | |
e85d0918 DD |
375 | int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr) |
376 | { | |
377 | int r; | |
378 | struct zd_ioreq32 reqs[2] = { | |
379 | [0] = { .addr = CR_MAC_ADDR_P1 }, | |
380 | [1] = { .addr = CR_MAC_ADDR_P2 }, | |
381 | }; | |
382 | ||
459c51ad DD |
383 | if (mac_addr) { |
384 | reqs[0].value = (mac_addr[3] << 24) | |
385 | | (mac_addr[2] << 16) | |
386 | | (mac_addr[1] << 8) | |
387 | | mac_addr[0]; | |
388 | reqs[1].value = (mac_addr[5] << 8) | |
389 | | mac_addr[4]; | |
e174961c | 390 | dev_dbg_f(zd_chip_dev(chip), "mac addr %pM\n", mac_addr); |
459c51ad DD |
391 | } else { |
392 | dev_dbg_f(zd_chip_dev(chip), "set NULL mac\n"); | |
393 | } | |
e85d0918 DD |
394 | |
395 | mutex_lock(&chip->mutex); | |
396 | r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); | |
e85d0918 DD |
397 | mutex_unlock(&chip->mutex); |
398 | return r; | |
399 | } | |
400 | ||
401 | int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain) | |
402 | { | |
403 | int r; | |
404 | u32 value; | |
405 | ||
406 | mutex_lock(&chip->mutex); | |
407 | r = zd_ioread32_locked(chip, &value, E2P_SUBID); | |
408 | mutex_unlock(&chip->mutex); | |
409 | if (r) | |
410 | return r; | |
411 | ||
412 | *regdomain = value >> 16; | |
413 | dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain); | |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
418 | static int read_values(struct zd_chip *chip, u8 *values, size_t count, | |
419 | zd_addr_t e2p_addr, u32 guard) | |
420 | { | |
421 | int r; | |
422 | int i; | |
423 | u32 v; | |
424 | ||
425 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
426 | for (i = 0;;) { | |
0ce34bc8 DD |
427 | r = zd_ioread32_locked(chip, &v, |
428 | (zd_addr_t)((u16)e2p_addr+i/2)); | |
e85d0918 DD |
429 | if (r) |
430 | return r; | |
431 | v -= guard; | |
432 | if (i+4 < count) { | |
433 | values[i++] = v; | |
434 | values[i++] = v >> 8; | |
435 | values[i++] = v >> 16; | |
436 | values[i++] = v >> 24; | |
437 | continue; | |
438 | } | |
439 | for (;i < count; i++) | |
440 | values[i] = v >> (8*(i%3)); | |
441 | return 0; | |
442 | } | |
443 | } | |
444 | ||
445 | static int read_pwr_cal_values(struct zd_chip *chip) | |
446 | { | |
447 | return read_values(chip, chip->pwr_cal_values, | |
448 | E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1, | |
449 | 0); | |
450 | } | |
451 | ||
452 | static int read_pwr_int_values(struct zd_chip *chip) | |
453 | { | |
454 | return read_values(chip, chip->pwr_int_values, | |
455 | E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1, | |
456 | E2P_PWR_INT_GUARD); | |
457 | } | |
458 | ||
459 | static int read_ofdm_cal_values(struct zd_chip *chip) | |
460 | { | |
461 | int r; | |
462 | int i; | |
463 | static const zd_addr_t addresses[] = { | |
464 | E2P_36M_CAL_VALUE1, | |
465 | E2P_48M_CAL_VALUE1, | |
466 | E2P_54M_CAL_VALUE1, | |
467 | }; | |
468 | ||
469 | for (i = 0; i < 3; i++) { | |
470 | r = read_values(chip, chip->ofdm_cal_values[i], | |
471 | E2P_CHANNEL_COUNT, addresses[i], 0); | |
472 | if (r) | |
473 | return r; | |
474 | } | |
475 | return 0; | |
476 | } | |
477 | ||
478 | static int read_cal_int_tables(struct zd_chip *chip) | |
479 | { | |
480 | int r; | |
481 | ||
482 | r = read_pwr_cal_values(chip); | |
483 | if (r) | |
484 | return r; | |
485 | r = read_pwr_int_values(chip); | |
486 | if (r) | |
487 | return r; | |
488 | r = read_ofdm_cal_values(chip); | |
489 | if (r) | |
490 | return r; | |
491 | return 0; | |
492 | } | |
493 | ||
494 | /* phy means physical registers */ | |
495 | int zd_chip_lock_phy_regs(struct zd_chip *chip) | |
496 | { | |
497 | int r; | |
498 | u32 tmp; | |
499 | ||
500 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
501 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); | |
502 | if (r) { | |
503 | dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r); | |
504 | return r; | |
505 | } | |
506 | ||
e85d0918 DD |
507 | tmp &= ~UNLOCK_PHY_REGS; |
508 | ||
509 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); | |
510 | if (r) | |
511 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); | |
512 | return r; | |
513 | } | |
514 | ||
515 | int zd_chip_unlock_phy_regs(struct zd_chip *chip) | |
516 | { | |
517 | int r; | |
518 | u32 tmp; | |
519 | ||
520 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
521 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); | |
522 | if (r) { | |
523 | dev_err(zd_chip_dev(chip), | |
524 | "error ioread32(CR_REG1): %d\n", r); | |
525 | return r; | |
526 | } | |
527 | ||
e85d0918 DD |
528 | tmp |= UNLOCK_PHY_REGS; |
529 | ||
530 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); | |
531 | if (r) | |
532 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); | |
533 | return r; | |
534 | } | |
535 | ||
92b3e2e9 | 536 | /* CR157 can be optionally patched by the EEPROM for original ZD1211 */ |
e85d0918 DD |
537 | static int patch_cr157(struct zd_chip *chip) |
538 | { | |
539 | int r; | |
92b3e2e9 | 540 | u16 value; |
e85d0918 DD |
541 | |
542 | if (!chip->patch_cr157) | |
543 | return 0; | |
544 | ||
92b3e2e9 | 545 | r = zd_ioread16_locked(chip, &value, E2P_PHY_REG); |
e85d0918 DD |
546 | if (r) |
547 | return r; | |
548 | ||
549 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8); | |
550 | return zd_iowrite32_locked(chip, value >> 8, CR157); | |
551 | } | |
552 | ||
553 | /* | |
554 | * 6M band edge can be optionally overwritten for certain RF's | |
555 | * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge | |
556 | * bit (for AL2230, AL2230S) | |
557 | */ | |
72018b22 DD |
558 | static int patch_6m_band_edge(struct zd_chip *chip, u8 channel) |
559 | { | |
560 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
561 | if (!chip->patch_6m_band_edge) | |
562 | return 0; | |
563 | ||
564 | return zd_rf_patch_6m_band_edge(&chip->rf, channel); | |
565 | } | |
566 | ||
567 | /* Generic implementation of 6M band edge patching, used by most RFs via | |
568 | * zd_rf_generic_patch_6m() */ | |
569 | int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel) | |
e85d0918 DD |
570 | { |
571 | struct zd_ioreq16 ioreqs[] = { | |
572 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, | |
573 | { CR47, 0x1e }, | |
574 | }; | |
575 | ||
e85d0918 DD |
576 | /* FIXME: Channel 11 is not the edge for all regulatory domains. */ |
577 | if (channel == 1 || channel == 11) | |
578 | ioreqs[0].value = 0x12; | |
579 | ||
580 | dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel); | |
581 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
582 | } | |
583 | ||
584 | static int zd1211_hw_reset_phy(struct zd_chip *chip) | |
585 | { | |
586 | static const struct zd_ioreq16 ioreqs[] = { | |
587 | { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 }, | |
588 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 }, | |
589 | { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f }, | |
590 | { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d }, | |
591 | { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a }, | |
592 | { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c }, | |
593 | { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 }, | |
594 | { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 }, | |
595 | { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b }, | |
596 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, | |
597 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, | |
598 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, | |
599 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, | |
600 | { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff }, | |
601 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, | |
602 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, | |
603 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, | |
604 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, | |
605 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, | |
606 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, | |
607 | { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 }, | |
608 | { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 }, | |
609 | { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 }, | |
610 | { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 }, | |
611 | { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 }, | |
612 | { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff }, | |
613 | { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 }, | |
614 | { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 }, | |
615 | { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 }, | |
616 | { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a }, | |
617 | { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 }, | |
618 | { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e }, | |
619 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, | |
620 | { }, | |
621 | { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 }, | |
622 | { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 }, | |
623 | { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 }, | |
624 | { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 }, | |
625 | { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C }, | |
626 | { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 }, | |
627 | { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 }, | |
628 | { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 }, | |
629 | { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 }, | |
630 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, | |
631 | { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 }, | |
632 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, | |
633 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, | |
634 | { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f }, | |
dc536a70 DD |
635 | { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 }, |
636 | { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C }, | |
637 | { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 }, | |
638 | { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 }, | |
639 | { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c }, | |
640 | { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 }, | |
641 | { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe }, | |
642 | { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa }, | |
643 | { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe }, | |
644 | { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba }, | |
645 | { CR170, 0xba }, { CR171, 0xba }, | |
e85d0918 DD |
646 | /* Note: CR204 must lead the CR203 */ |
647 | { CR204, 0x7d }, | |
648 | { }, | |
649 | { CR203, 0x30 }, | |
650 | }; | |
651 | ||
652 | int r, t; | |
653 | ||
654 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
655 | ||
656 | r = zd_chip_lock_phy_regs(chip); | |
657 | if (r) | |
658 | goto out; | |
659 | ||
660 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
661 | if (r) | |
662 | goto unlock; | |
663 | ||
664 | r = patch_cr157(chip); | |
665 | unlock: | |
666 | t = zd_chip_unlock_phy_regs(chip); | |
667 | if (t && !r) | |
668 | r = t; | |
669 | out: | |
670 | return r; | |
671 | } | |
672 | ||
673 | static int zd1211b_hw_reset_phy(struct zd_chip *chip) | |
674 | { | |
675 | static const struct zd_ioreq16 ioreqs[] = { | |
676 | { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 }, | |
677 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 }, | |
678 | { CR10, 0x81 }, | |
679 | /* power control { { CR11, 1 << 6 }, */ | |
680 | { CR11, 0x00 }, | |
681 | { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 }, | |
682 | { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e }, | |
683 | { CR18, 0x0a }, { CR19, 0x48 }, | |
684 | { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */ | |
685 | { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 }, | |
686 | { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 }, | |
687 | { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 }, | |
fe7215ca | 688 | { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */ |
e85d0918 DD |
689 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, |
690 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, | |
691 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, | |
692 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, | |
693 | { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff }, | |
694 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, | |
695 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, | |
696 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, | |
697 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, | |
698 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, | |
699 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, | |
700 | { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 }, | |
701 | { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 }, | |
702 | { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 }, | |
703 | { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 }, | |
704 | { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 }, | |
705 | { CR94, 0x01 }, | |
706 | { CR95, 0x20 }, /* ZD1211B */ | |
707 | { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 }, | |
708 | { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 }, | |
709 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, | |
710 | { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 }, | |
711 | { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 }, | |
712 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, | |
713 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, | |
714 | { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e }, | |
715 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, | |
716 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, | |
717 | { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 }, | |
718 | { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 }, | |
719 | { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c }, | |
720 | { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 }, | |
721 | { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */ | |
722 | { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */ | |
723 | { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe }, | |
724 | { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa }, | |
725 | { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe }, | |
726 | { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba }, | |
727 | { CR170, 0xba }, { CR171, 0xba }, | |
728 | /* Note: CR204 must lead the CR203 */ | |
729 | { CR204, 0x7d }, | |
730 | {}, | |
731 | { CR203, 0x30 }, | |
732 | }; | |
733 | ||
734 | int r, t; | |
735 | ||
736 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
737 | ||
738 | r = zd_chip_lock_phy_regs(chip); | |
739 | if (r) | |
740 | goto out; | |
741 | ||
742 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
e85d0918 DD |
743 | t = zd_chip_unlock_phy_regs(chip); |
744 | if (t && !r) | |
745 | r = t; | |
746 | out: | |
747 | return r; | |
748 | } | |
749 | ||
750 | static int hw_reset_phy(struct zd_chip *chip) | |
751 | { | |
74553aed | 752 | return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) : |
e85d0918 DD |
753 | zd1211_hw_reset_phy(chip); |
754 | } | |
755 | ||
756 | static int zd1211_hw_init_hmac(struct zd_chip *chip) | |
757 | { | |
758 | static const struct zd_ioreq32 ioreqs[] = { | |
7f4013f0 | 759 | { CR_ZD1211_RETRY_MAX, ZD1211_RETRY_COUNT }, |
e85d0918 | 760 | { CR_RX_THRESHOLD, 0x000c0640 }, |
e85d0918 DD |
761 | }; |
762 | ||
e85d0918 DD |
763 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
764 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
34c44912 | 765 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
e85d0918 DD |
766 | } |
767 | ||
768 | static int zd1211b_hw_init_hmac(struct zd_chip *chip) | |
769 | { | |
770 | static const struct zd_ioreq32 ioreqs[] = { | |
7f4013f0 | 771 | { CR_ZD1211B_RETRY_MAX, ZD1211B_RETRY_COUNT }, |
e51c6837 JC |
772 | { CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f }, |
773 | { CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f }, | |
774 | { CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f }, | |
775 | { CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f }, | |
e85d0918 DD |
776 | { CR_ZD1211B_AIFS_CTL1, 0x00280028 }, |
777 | { CR_ZD1211B_AIFS_CTL2, 0x008C003C }, | |
778 | { CR_ZD1211B_TXOP, 0x01800824 }, | |
34c44912 DD |
779 | { CR_RX_THRESHOLD, 0x000c0eff, }, |
780 | }; | |
781 | ||
782 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
783 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
784 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
785 | } | |
786 | ||
787 | static int hw_init_hmac(struct zd_chip *chip) | |
788 | { | |
789 | int r; | |
790 | static const struct zd_ioreq32 ioreqs[] = { | |
791 | { CR_ACK_TIMEOUT_EXT, 0x20 }, | |
792 | { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, | |
e85d0918 | 793 | { CR_SNIFFER_ON, 0 }, |
fde627b5 | 794 | { CR_RX_FILTER, STA_RX_FILTER }, |
e85d0918 DD |
795 | { CR_GROUP_HASH_P1, 0x00 }, |
796 | { CR_GROUP_HASH_P2, 0x80000000 }, | |
797 | { CR_REG1, 0xa4 }, | |
798 | { CR_ADDA_PWR_DWN, 0x7f }, | |
799 | { CR_BCN_PLCP_CFG, 0x00f00401 }, | |
800 | { CR_PHY_DELAY, 0x00 }, | |
801 | { CR_ACK_TIMEOUT_EXT, 0x80 }, | |
802 | { CR_ADDA_PWR_DWN, 0x00 }, | |
803 | { CR_ACK_TIME_80211, 0x100 }, | |
e85d0918 DD |
804 | { CR_RX_PE_DELAY, 0x70 }, |
805 | { CR_PS_CTRL, 0x10000000 }, | |
806 | { CR_RTS_CTS_RATE, 0x02030203 }, | |
e85d0918 DD |
807 | { CR_AFTER_PNP, 0x1 }, |
808 | { CR_WEP_PROTECT, 0x114 }, | |
34c44912 | 809 | { CR_IFS_VALUE, IFS_VALUE_DEFAULT }, |
72e77a8a | 810 | { CR_CAM_MODE, MODE_AP_WDS}, |
e85d0918 DD |
811 | }; |
812 | ||
e85d0918 DD |
813 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
814 | r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
34c44912 DD |
815 | if (r) |
816 | return r; | |
e85d0918 | 817 | |
74553aed | 818 | return zd_chip_is_zd1211b(chip) ? |
e85d0918 DD |
819 | zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip); |
820 | } | |
821 | ||
822 | struct aw_pt_bi { | |
823 | u32 atim_wnd_period; | |
824 | u32 pre_tbtt; | |
825 | u32 beacon_interval; | |
826 | }; | |
827 | ||
828 | static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) | |
829 | { | |
830 | int r; | |
831 | static const zd_addr_t aw_pt_bi_addr[] = | |
832 | { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL }; | |
833 | u32 values[3]; | |
834 | ||
835 | r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr, | |
836 | ARRAY_SIZE(aw_pt_bi_addr)); | |
837 | if (r) { | |
838 | memset(s, 0, sizeof(*s)); | |
839 | return r; | |
840 | } | |
841 | ||
842 | s->atim_wnd_period = values[0]; | |
843 | s->pre_tbtt = values[1]; | |
844 | s->beacon_interval = values[2]; | |
e85d0918 DD |
845 | return 0; |
846 | } | |
847 | ||
848 | static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) | |
849 | { | |
850 | struct zd_ioreq32 reqs[3]; | |
851 | ||
852 | if (s->beacon_interval <= 5) | |
853 | s->beacon_interval = 5; | |
854 | if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval) | |
855 | s->pre_tbtt = s->beacon_interval - 1; | |
856 | if (s->atim_wnd_period >= s->pre_tbtt) | |
857 | s->atim_wnd_period = s->pre_tbtt - 1; | |
858 | ||
859 | reqs[0].addr = CR_ATIM_WND_PERIOD; | |
860 | reqs[0].value = s->atim_wnd_period; | |
861 | reqs[1].addr = CR_PRE_TBTT; | |
862 | reqs[1].value = s->pre_tbtt; | |
863 | reqs[2].addr = CR_BCN_INTERVAL; | |
864 | reqs[2].value = s->beacon_interval; | |
865 | ||
e85d0918 DD |
866 | return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); |
867 | } | |
868 | ||
869 | ||
870 | static int set_beacon_interval(struct zd_chip *chip, u32 interval) | |
871 | { | |
872 | int r; | |
873 | struct aw_pt_bi s; | |
874 | ||
875 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
876 | r = get_aw_pt_bi(chip, &s); | |
877 | if (r) | |
878 | return r; | |
879 | s.beacon_interval = interval; | |
880 | return set_aw_pt_bi(chip, &s); | |
881 | } | |
882 | ||
883 | int zd_set_beacon_interval(struct zd_chip *chip, u32 interval) | |
884 | { | |
885 | int r; | |
886 | ||
887 | mutex_lock(&chip->mutex); | |
888 | r = set_beacon_interval(chip, interval); | |
889 | mutex_unlock(&chip->mutex); | |
890 | return r; | |
891 | } | |
892 | ||
893 | static int hw_init(struct zd_chip *chip) | |
894 | { | |
895 | int r; | |
896 | ||
897 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
898 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
899 | r = hw_reset_phy(chip); | |
900 | if (r) | |
901 | return r; | |
902 | ||
903 | r = hw_init_hmac(chip); | |
904 | if (r) | |
905 | return r; | |
98227a90 | 906 | |
98227a90 | 907 | return set_beacon_interval(chip, 100); |
e85d0918 DD |
908 | } |
909 | ||
0ce34bc8 DD |
910 | static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset) |
911 | { | |
912 | return (zd_addr_t)((u16)chip->fw_regs_base + offset); | |
913 | } | |
914 | ||
e85d0918 DD |
915 | #ifdef DEBUG |
916 | static int dump_cr(struct zd_chip *chip, const zd_addr_t addr, | |
917 | const char *addr_string) | |
918 | { | |
919 | int r; | |
920 | u32 value; | |
921 | ||
922 | r = zd_ioread32_locked(chip, &value, addr); | |
923 | if (r) { | |
924 | dev_dbg_f(zd_chip_dev(chip), | |
925 | "error reading %s. Error number %d\n", addr_string, r); | |
926 | return r; | |
927 | } | |
928 | ||
929 | dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n", | |
930 | addr_string, (unsigned int)value); | |
931 | return 0; | |
932 | } | |
933 | ||
934 | static int test_init(struct zd_chip *chip) | |
935 | { | |
936 | int r; | |
937 | ||
938 | r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP"); | |
939 | if (r) | |
940 | return r; | |
941 | r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN"); | |
942 | if (r) | |
943 | return r; | |
944 | return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT"); | |
945 | } | |
946 | ||
947 | static void dump_fw_registers(struct zd_chip *chip) | |
948 | { | |
0ce34bc8 DD |
949 | const zd_addr_t addr[4] = { |
950 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER), | |
951 | fw_reg_addr(chip, FW_REG_USB_SPEED), | |
952 | fw_reg_addr(chip, FW_REG_FIX_TX_RATE), | |
953 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), | |
e85d0918 DD |
954 | }; |
955 | ||
956 | int r; | |
957 | u16 values[4]; | |
958 | ||
959 | r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr, | |
960 | ARRAY_SIZE(addr)); | |
961 | if (r) { | |
962 | dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n", | |
963 | r); | |
964 | return; | |
965 | } | |
966 | ||
967 | dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]); | |
968 | dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]); | |
969 | dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]); | |
970 | dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]); | |
971 | } | |
972 | #endif /* DEBUG */ | |
973 | ||
974 | static int print_fw_version(struct zd_chip *chip) | |
975 | { | |
68e887ef | 976 | struct wiphy *wiphy = zd_chip_to_mac(chip)->hw->wiphy; |
e85d0918 DD |
977 | int r; |
978 | u16 version; | |
979 | ||
0ce34bc8 DD |
980 | r = zd_ioread16_locked(chip, &version, |
981 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER)); | |
e85d0918 DD |
982 | if (r) |
983 | return r; | |
984 | ||
985 | dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version); | |
68e887ef JL |
986 | |
987 | snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), | |
988 | "%04hx", version); | |
989 | ||
e85d0918 DD |
990 | return 0; |
991 | } | |
992 | ||
8318d78a | 993 | static int set_mandatory_rates(struct zd_chip *chip, int gmode) |
e85d0918 DD |
994 | { |
995 | u32 rates; | |
996 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
997 | /* This sets the mandatory rates, which only depend from the standard | |
998 | * that the device is supporting. Until further notice we should try | |
999 | * to support 802.11g also for full speed USB. | |
1000 | */ | |
8318d78a | 1001 | if (!gmode) |
e85d0918 | 1002 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M; |
8318d78a | 1003 | else |
e85d0918 DD |
1004 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M| |
1005 | CR_RATE_6M|CR_RATE_12M|CR_RATE_24M; | |
8318d78a | 1006 | |
e85d0918 DD |
1007 | return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL); |
1008 | } | |
1009 | ||
b1382ede | 1010 | int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, |
459c51ad | 1011 | int preamble) |
b1382ede | 1012 | { |
b1382ede DD |
1013 | u32 value = 0; |
1014 | ||
459c51ad | 1015 | dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble); |
b1382ede DD |
1016 | value |= preamble << RTSCTS_SH_RTS_PMB_TYPE; |
1017 | value |= preamble << RTSCTS_SH_CTS_PMB_TYPE; | |
1018 | ||
459c51ad DD |
1019 | /* We always send 11M RTS/self-CTS messages, like the vendor driver. */ |
1020 | value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE; | |
1021 | value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE; | |
64f222cc | 1022 | value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE; |
b1382ede DD |
1023 | value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE; |
1024 | ||
1025 | return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE); | |
1026 | } | |
1027 | ||
e85d0918 DD |
1028 | int zd_chip_enable_hwint(struct zd_chip *chip) |
1029 | { | |
1030 | int r; | |
1031 | ||
1032 | mutex_lock(&chip->mutex); | |
1033 | r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT); | |
1034 | mutex_unlock(&chip->mutex); | |
1035 | return r; | |
1036 | } | |
1037 | ||
1038 | static int disable_hwint(struct zd_chip *chip) | |
1039 | { | |
1040 | return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT); | |
1041 | } | |
1042 | ||
1043 | int zd_chip_disable_hwint(struct zd_chip *chip) | |
1044 | { | |
1045 | int r; | |
1046 | ||
1047 | mutex_lock(&chip->mutex); | |
1048 | r = disable_hwint(chip); | |
1049 | mutex_unlock(&chip->mutex); | |
1050 | return r; | |
1051 | } | |
1052 | ||
0ce34bc8 DD |
1053 | static int read_fw_regs_offset(struct zd_chip *chip) |
1054 | { | |
1055 | int r; | |
1056 | ||
1057 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1058 | r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base, | |
1059 | FWRAW_REGS_ADDR); | |
1060 | if (r) | |
1061 | return r; | |
1062 | dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n", | |
1063 | (u16)chip->fw_regs_base); | |
1064 | ||
1065 | return 0; | |
1066 | } | |
1067 | ||
74553aed DD |
1068 | /* Read mac address using pre-firmware interface */ |
1069 | int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr) | |
1070 | { | |
1071 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
1072 | return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr, | |
1073 | ETH_ALEN); | |
1074 | } | |
0ce34bc8 | 1075 | |
74553aed | 1076 | int zd_chip_init_hw(struct zd_chip *chip) |
e85d0918 DD |
1077 | { |
1078 | int r; | |
1079 | u8 rf_type; | |
1080 | ||
1081 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
1082 | ||
1083 | mutex_lock(&chip->mutex); | |
e85d0918 DD |
1084 | |
1085 | #ifdef DEBUG | |
1086 | r = test_init(chip); | |
1087 | if (r) | |
1088 | goto out; | |
1089 | #endif | |
1090 | r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP); | |
1091 | if (r) | |
1092 | goto out; | |
1093 | ||
0ce34bc8 | 1094 | r = read_fw_regs_offset(chip); |
e85d0918 DD |
1095 | if (r) |
1096 | goto out; | |
1097 | ||
1098 | /* GPI is always disabled, also in the other driver. | |
1099 | */ | |
1100 | r = zd_iowrite32_locked(chip, 0, CR_GPI_EN); | |
1101 | if (r) | |
1102 | goto out; | |
1103 | r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX); | |
1104 | if (r) | |
1105 | goto out; | |
1106 | /* Currently we support IEEE 802.11g for full and high speed USB. | |
1107 | * It might be discussed, whether we should suppport pure b mode for | |
1108 | * full speed USB. | |
1109 | */ | |
8318d78a | 1110 | r = set_mandatory_rates(chip, 1); |
e85d0918 DD |
1111 | if (r) |
1112 | goto out; | |
1113 | /* Disabling interrupts is certainly a smart thing here. | |
1114 | */ | |
1115 | r = disable_hwint(chip); | |
1116 | if (r) | |
1117 | goto out; | |
1118 | r = read_pod(chip, &rf_type); | |
1119 | if (r) | |
1120 | goto out; | |
1121 | r = hw_init(chip); | |
1122 | if (r) | |
1123 | goto out; | |
1124 | r = zd_rf_init_hw(&chip->rf, rf_type); | |
1125 | if (r) | |
1126 | goto out; | |
1127 | ||
1128 | r = print_fw_version(chip); | |
1129 | if (r) | |
1130 | goto out; | |
1131 | ||
1132 | #ifdef DEBUG | |
1133 | dump_fw_registers(chip); | |
1134 | r = test_init(chip); | |
1135 | if (r) | |
1136 | goto out; | |
1137 | #endif /* DEBUG */ | |
1138 | ||
e85d0918 DD |
1139 | r = read_cal_int_tables(chip); |
1140 | if (r) | |
1141 | goto out; | |
1142 | ||
1143 | print_id(chip); | |
1144 | out: | |
1145 | mutex_unlock(&chip->mutex); | |
1146 | return r; | |
1147 | } | |
1148 | ||
1149 | static int update_pwr_int(struct zd_chip *chip, u8 channel) | |
1150 | { | |
1151 | u8 value = chip->pwr_int_values[channel - 1]; | |
cbb5e6bb | 1152 | return zd_iowrite16_locked(chip, value, CR31); |
e85d0918 DD |
1153 | } |
1154 | ||
1155 | static int update_pwr_cal(struct zd_chip *chip, u8 channel) | |
1156 | { | |
1157 | u8 value = chip->pwr_cal_values[channel-1]; | |
cbb5e6bb | 1158 | return zd_iowrite16_locked(chip, value, CR68); |
e85d0918 DD |
1159 | } |
1160 | ||
1161 | static int update_ofdm_cal(struct zd_chip *chip, u8 channel) | |
1162 | { | |
cbb5e6bb | 1163 | struct zd_ioreq16 ioreqs[3]; |
e85d0918 DD |
1164 | |
1165 | ioreqs[0].addr = CR67; | |
1166 | ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1]; | |
1167 | ioreqs[1].addr = CR66; | |
1168 | ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1]; | |
1169 | ioreqs[2].addr = CR65; | |
1170 | ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1]; | |
1171 | ||
cbb5e6bb | 1172 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
e85d0918 DD |
1173 | } |
1174 | ||
1175 | static int update_channel_integration_and_calibration(struct zd_chip *chip, | |
1176 | u8 channel) | |
1177 | { | |
1178 | int r; | |
1179 | ||
9c8fc71d DD |
1180 | if (!zd_rf_should_update_pwr_int(&chip->rf)) |
1181 | return 0; | |
1182 | ||
e85d0918 DD |
1183 | r = update_pwr_int(chip, channel); |
1184 | if (r) | |
1185 | return r; | |
74553aed | 1186 | if (zd_chip_is_zd1211b(chip)) { |
cbb5e6bb | 1187 | static const struct zd_ioreq16 ioreqs[] = { |
e85d0918 DD |
1188 | { CR69, 0x28 }, |
1189 | {}, | |
1190 | { CR69, 0x2a }, | |
1191 | }; | |
1192 | ||
1193 | r = update_ofdm_cal(chip, channel); | |
1194 | if (r) | |
1195 | return r; | |
1196 | r = update_pwr_cal(chip, channel); | |
1197 | if (r) | |
1198 | return r; | |
cbb5e6bb | 1199 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
e85d0918 DD |
1200 | if (r) |
1201 | return r; | |
1202 | } | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | /* The CCK baseband gain can be optionally patched by the EEPROM */ | |
1208 | static int patch_cck_gain(struct zd_chip *chip) | |
1209 | { | |
1210 | int r; | |
1211 | u32 value; | |
1212 | ||
aaf83d4f | 1213 | if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf)) |
e85d0918 DD |
1214 | return 0; |
1215 | ||
1216 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1217 | r = zd_ioread32_locked(chip, &value, E2P_PHY_REG); | |
1218 | if (r) | |
1219 | return r; | |
1220 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff); | |
cbb5e6bb | 1221 | return zd_iowrite16_locked(chip, value & 0xff, CR47); |
e85d0918 DD |
1222 | } |
1223 | ||
1224 | int zd_chip_set_channel(struct zd_chip *chip, u8 channel) | |
1225 | { | |
1226 | int r, t; | |
1227 | ||
1228 | mutex_lock(&chip->mutex); | |
1229 | r = zd_chip_lock_phy_regs(chip); | |
1230 | if (r) | |
1231 | goto out; | |
1232 | r = zd_rf_set_channel(&chip->rf, channel); | |
1233 | if (r) | |
1234 | goto unlock; | |
1235 | r = update_channel_integration_and_calibration(chip, channel); | |
1236 | if (r) | |
1237 | goto unlock; | |
1238 | r = patch_cck_gain(chip); | |
1239 | if (r) | |
1240 | goto unlock; | |
1241 | r = patch_6m_band_edge(chip, channel); | |
1242 | if (r) | |
1243 | goto unlock; | |
1244 | r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS); | |
1245 | unlock: | |
1246 | t = zd_chip_unlock_phy_regs(chip); | |
1247 | if (t && !r) | |
1248 | r = t; | |
1249 | out: | |
1250 | mutex_unlock(&chip->mutex); | |
1251 | return r; | |
1252 | } | |
1253 | ||
1254 | u8 zd_chip_get_channel(struct zd_chip *chip) | |
1255 | { | |
1256 | u8 channel; | |
1257 | ||
1258 | mutex_lock(&chip->mutex); | |
1259 | channel = chip->rf.channel; | |
1260 | mutex_unlock(&chip->mutex); | |
1261 | return channel; | |
1262 | } | |
1263 | ||
583afd1e | 1264 | int zd_chip_control_leds(struct zd_chip *chip, enum led_status status) |
e85d0918 | 1265 | { |
0ce34bc8 DD |
1266 | const zd_addr_t a[] = { |
1267 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), | |
583afd1e UK |
1268 | CR_LED, |
1269 | }; | |
e85d0918 | 1270 | |
583afd1e UK |
1271 | int r; |
1272 | u16 v[ARRAY_SIZE(a)]; | |
1273 | struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = { | |
0ce34bc8 | 1274 | [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) }, |
583afd1e UK |
1275 | [1] = { CR_LED }, |
1276 | }; | |
1277 | u16 other_led; | |
e85d0918 | 1278 | |
e85d0918 | 1279 | mutex_lock(&chip->mutex); |
583afd1e | 1280 | r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a)); |
e85d0918 | 1281 | if (r) |
583afd1e UK |
1282 | goto out; |
1283 | ||
1284 | other_led = chip->link_led == LED1 ? LED2 : LED1; | |
1285 | ||
e85d0918 | 1286 | switch (status) { |
14b46c8a | 1287 | case ZD_LED_OFF: |
583afd1e UK |
1288 | ioreqs[0].value = FW_LINK_OFF; |
1289 | ioreqs[1].value = v[1] & ~(LED1|LED2); | |
e85d0918 | 1290 | break; |
14b46c8a | 1291 | case ZD_LED_SCANNING: |
583afd1e UK |
1292 | ioreqs[0].value = FW_LINK_OFF; |
1293 | ioreqs[1].value = v[1] & ~other_led; | |
1294 | if (get_seconds() % 3 == 0) { | |
1295 | ioreqs[1].value &= ~chip->link_led; | |
1296 | } else { | |
1297 | ioreqs[1].value |= chip->link_led; | |
1298 | } | |
e85d0918 | 1299 | break; |
14b46c8a | 1300 | case ZD_LED_ASSOCIATED: |
583afd1e UK |
1301 | ioreqs[0].value = FW_LINK_TX; |
1302 | ioreqs[1].value = v[1] & ~other_led; | |
1303 | ioreqs[1].value |= chip->link_led; | |
e85d0918 DD |
1304 | break; |
1305 | default: | |
583afd1e | 1306 | r = -EINVAL; |
e85d0918 DD |
1307 | goto out; |
1308 | } | |
e85d0918 | 1309 | |
583afd1e UK |
1310 | if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) { |
1311 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
1312 | if (r) | |
e85d0918 | 1313 | goto out; |
e85d0918 | 1314 | } |
583afd1e | 1315 | r = 0; |
e85d0918 | 1316 | out: |
583afd1e | 1317 | mutex_unlock(&chip->mutex); |
e85d0918 DD |
1318 | return r; |
1319 | } | |
1320 | ||
459c51ad | 1321 | int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates) |
e85d0918 | 1322 | { |
459c51ad DD |
1323 | int r; |
1324 | ||
1325 | if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G)) | |
1326 | return -EINVAL; | |
e85d0918 | 1327 | |
459c51ad DD |
1328 | mutex_lock(&chip->mutex); |
1329 | r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL); | |
1330 | mutex_unlock(&chip->mutex); | |
1331 | return r; | |
e85d0918 DD |
1332 | } |
1333 | ||
64f222cc UK |
1334 | static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame) |
1335 | { | |
1336 | return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame); | |
1337 | } | |
1338 | ||
459c51ad DD |
1339 | /** |
1340 | * zd_rx_rate - report zd-rate | |
1341 | * @rx_frame - received frame | |
1342 | * @rx_status - rx_status as given by the device | |
1343 | * | |
1344 | * This function converts the rate as encoded in the received packet to the | |
1345 | * zd-rate, we are using on other places in the driver. | |
1346 | */ | |
1347 | u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status) | |
e85d0918 | 1348 | { |
459c51ad | 1349 | u8 zd_rate; |
e85d0918 | 1350 | if (status->frame_status & ZD_RX_OFDM) { |
459c51ad | 1351 | zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame); |
e85d0918 | 1352 | } else { |
64f222cc UK |
1353 | switch (zd_cck_plcp_header_signal(rx_frame)) { |
1354 | case ZD_CCK_PLCP_SIGNAL_1M: | |
459c51ad | 1355 | zd_rate = ZD_CCK_RATE_1M; |
e85d0918 | 1356 | break; |
64f222cc | 1357 | case ZD_CCK_PLCP_SIGNAL_2M: |
459c51ad | 1358 | zd_rate = ZD_CCK_RATE_2M; |
e85d0918 | 1359 | break; |
64f222cc | 1360 | case ZD_CCK_PLCP_SIGNAL_5M5: |
459c51ad | 1361 | zd_rate = ZD_CCK_RATE_5_5M; |
e85d0918 | 1362 | break; |
64f222cc | 1363 | case ZD_CCK_PLCP_SIGNAL_11M: |
459c51ad | 1364 | zd_rate = ZD_CCK_RATE_11M; |
e85d0918 DD |
1365 | break; |
1366 | default: | |
459c51ad | 1367 | zd_rate = 0; |
e85d0918 DD |
1368 | } |
1369 | } | |
1370 | ||
459c51ad | 1371 | return zd_rate; |
e85d0918 DD |
1372 | } |
1373 | ||
1374 | int zd_chip_switch_radio_on(struct zd_chip *chip) | |
1375 | { | |
1376 | int r; | |
1377 | ||
1378 | mutex_lock(&chip->mutex); | |
1379 | r = zd_switch_radio_on(&chip->rf); | |
1380 | mutex_unlock(&chip->mutex); | |
1381 | return r; | |
1382 | } | |
1383 | ||
1384 | int zd_chip_switch_radio_off(struct zd_chip *chip) | |
1385 | { | |
1386 | int r; | |
1387 | ||
1388 | mutex_lock(&chip->mutex); | |
1389 | r = zd_switch_radio_off(&chip->rf); | |
1390 | mutex_unlock(&chip->mutex); | |
1391 | return r; | |
1392 | } | |
1393 | ||
1394 | int zd_chip_enable_int(struct zd_chip *chip) | |
1395 | { | |
1396 | int r; | |
1397 | ||
1398 | mutex_lock(&chip->mutex); | |
1399 | r = zd_usb_enable_int(&chip->usb); | |
1400 | mutex_unlock(&chip->mutex); | |
1401 | return r; | |
1402 | } | |
1403 | ||
1404 | void zd_chip_disable_int(struct zd_chip *chip) | |
1405 | { | |
1406 | mutex_lock(&chip->mutex); | |
1407 | zd_usb_disable_int(&chip->usb); | |
1408 | mutex_unlock(&chip->mutex); | |
1409 | } | |
1410 | ||
459c51ad | 1411 | int zd_chip_enable_rxtx(struct zd_chip *chip) |
e85d0918 DD |
1412 | { |
1413 | int r; | |
1414 | ||
1415 | mutex_lock(&chip->mutex); | |
459c51ad | 1416 | zd_usb_enable_tx(&chip->usb); |
e85d0918 DD |
1417 | r = zd_usb_enable_rx(&chip->usb); |
1418 | mutex_unlock(&chip->mutex); | |
1419 | return r; | |
1420 | } | |
1421 | ||
459c51ad | 1422 | void zd_chip_disable_rxtx(struct zd_chip *chip) |
e85d0918 DD |
1423 | { |
1424 | mutex_lock(&chip->mutex); | |
1425 | zd_usb_disable_rx(&chip->usb); | |
459c51ad | 1426 | zd_usb_disable_tx(&chip->usb); |
e85d0918 DD |
1427 | mutex_unlock(&chip->mutex); |
1428 | } | |
1429 | ||
1430 | int zd_rfwritev_locked(struct zd_chip *chip, | |
1431 | const u32* values, unsigned int count, u8 bits) | |
1432 | { | |
1433 | int r; | |
1434 | unsigned int i; | |
1435 | ||
1436 | for (i = 0; i < count; i++) { | |
1437 | r = zd_rfwrite_locked(chip, values[i], bits); | |
1438 | if (r) | |
1439 | return r; | |
1440 | } | |
1441 | ||
1442 | return 0; | |
1443 | } | |
20fe2176 DD |
1444 | |
1445 | /* | |
1446 | * We can optionally program the RF directly through CR regs, if supported by | |
1447 | * the hardware. This is much faster than the older method. | |
1448 | */ | |
ec62bd91 | 1449 | int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value) |
20fe2176 | 1450 | { |
7253965a | 1451 | const struct zd_ioreq16 ioreqs[] = { |
20fe2176 DD |
1452 | { CR244, (value >> 16) & 0xff }, |
1453 | { CR243, (value >> 8) & 0xff }, | |
1454 | { CR242, value & 0xff }, | |
1455 | }; | |
1456 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1457 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
1458 | } | |
1459 | ||
1460 | int zd_rfwritev_cr_locked(struct zd_chip *chip, | |
1461 | const u32 *values, unsigned int count) | |
1462 | { | |
1463 | int r; | |
1464 | unsigned int i; | |
1465 | ||
1466 | for (i = 0; i < count; i++) { | |
1467 | r = zd_rfwrite_cr_locked(chip, values[i]); | |
1468 | if (r) | |
1469 | return r; | |
1470 | } | |
1471 | ||
1472 | return 0; | |
1473 | } | |
9cdac965 UK |
1474 | |
1475 | int zd_chip_set_multicast_hash(struct zd_chip *chip, | |
1476 | struct zd_mc_hash *hash) | |
1477 | { | |
7253965a | 1478 | const struct zd_ioreq32 ioreqs[] = { |
9cdac965 UK |
1479 | { CR_GROUP_HASH_P1, hash->low }, |
1480 | { CR_GROUP_HASH_P2, hash->high }, | |
1481 | }; | |
1482 | ||
9cdac965 UK |
1483 | return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
1484 | } | |
5fe73197 AF |
1485 | |
1486 | u64 zd_chip_get_tsf(struct zd_chip *chip) | |
1487 | { | |
1488 | int r; | |
1489 | static const zd_addr_t aw_pt_bi_addr[] = | |
1490 | { CR_TSF_LOW_PART, CR_TSF_HIGH_PART }; | |
1491 | u32 values[2]; | |
1492 | u64 tsf; | |
1493 | ||
1494 | mutex_lock(&chip->mutex); | |
1495 | r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr, | |
1496 | ARRAY_SIZE(aw_pt_bi_addr)); | |
1497 | mutex_unlock(&chip->mutex); | |
1498 | if (r) | |
1499 | return 0; | |
1500 | ||
1501 | tsf = values[1]; | |
1502 | tsf = (tsf << 32) | values[0]; | |
1503 | ||
1504 | return tsf; | |
1505 | } |