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e85d0918 DD |
1 | /* zd_chip.c |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License as published by | |
5 | * the Free Software Foundation; either version 2 of the License, or | |
6 | * (at your option) any later version. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
16 | */ | |
17 | ||
18 | /* This file implements all the hardware specific functions for the ZD1211 | |
19 | * and ZD1211B chips. Support for the ZD1211B was possible after Timothy | |
20 | * Legge sent me a ZD1211B device. Thank you Tim. -- Uli | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/errno.h> | |
25 | ||
26 | #include "zd_def.h" | |
27 | #include "zd_chip.h" | |
28 | #include "zd_ieee80211.h" | |
29 | #include "zd_mac.h" | |
30 | #include "zd_rf.h" | |
31 | #include "zd_util.h" | |
32 | ||
33 | void zd_chip_init(struct zd_chip *chip, | |
34 | struct net_device *netdev, | |
35 | struct usb_interface *intf) | |
36 | { | |
37 | memset(chip, 0, sizeof(*chip)); | |
38 | mutex_init(&chip->mutex); | |
39 | zd_usb_init(&chip->usb, netdev, intf); | |
40 | zd_rf_init(&chip->rf); | |
41 | } | |
42 | ||
43 | void zd_chip_clear(struct zd_chip *chip) | |
44 | { | |
c48cf125 | 45 | ZD_ASSERT(!mutex_is_locked(&chip->mutex)); |
e85d0918 DD |
46 | zd_usb_clear(&chip->usb); |
47 | zd_rf_clear(&chip->rf); | |
e85d0918 | 48 | mutex_destroy(&chip->mutex); |
c48cf125 | 49 | ZD_MEMCLEAR(chip, sizeof(*chip)); |
e85d0918 DD |
50 | } |
51 | ||
52 | static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size) | |
53 | { | |
54 | return scnprintf(buffer, size, "%02x-%02x-%02x", | |
55 | addr[0], addr[1], addr[2]); | |
56 | } | |
57 | ||
58 | /* Prints an identifier line, which will support debugging. */ | |
59 | static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size) | |
60 | { | |
61 | int i = 0; | |
62 | ||
63 | i = scnprintf(buffer, size, "zd1211%s chip ", | |
64 | chip->is_zd1211b ? "b" : ""); | |
65 | i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i); | |
66 | i += scnprintf(buffer+i, size-i, " "); | |
67 | i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i); | |
68 | i += scnprintf(buffer+i, size-i, " "); | |
69 | i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i); | |
20fe2176 | 70 | i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c", chip->pa_type, |
e85d0918 DD |
71 | chip->patch_cck_gain ? 'g' : '-', |
72 | chip->patch_cr157 ? '7' : '-', | |
20fe2176 DD |
73 | chip->patch_6m_band_edge ? '6' : '-', |
74 | chip->new_phy_layout ? 'N' : '-'); | |
e85d0918 DD |
75 | return i; |
76 | } | |
77 | ||
78 | static void print_id(struct zd_chip *chip) | |
79 | { | |
80 | char buffer[80]; | |
81 | ||
82 | scnprint_id(chip, buffer, sizeof(buffer)); | |
83 | buffer[sizeof(buffer)-1] = 0; | |
84 | dev_info(zd_chip_dev(chip), "%s\n", buffer); | |
85 | } | |
86 | ||
0ce34bc8 DD |
87 | static zd_addr_t inc_addr(zd_addr_t addr) |
88 | { | |
89 | u16 a = (u16)addr; | |
90 | /* Control registers use byte addressing, but everything else uses word | |
91 | * addressing. */ | |
92 | if ((a & 0xf000) == CR_START) | |
93 | a += 2; | |
94 | else | |
95 | a += 1; | |
96 | return (zd_addr_t)a; | |
97 | } | |
98 | ||
e85d0918 DD |
99 | /* Read a variable number of 32-bit values. Parameter count is not allowed to |
100 | * exceed USB_MAX_IOREAD32_COUNT. | |
101 | */ | |
102 | int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr, | |
103 | unsigned int count) | |
104 | { | |
105 | int r; | |
106 | int i; | |
107 | zd_addr_t *a16 = (zd_addr_t *)NULL; | |
108 | u16 *v16; | |
109 | unsigned int count16; | |
110 | ||
111 | if (count > USB_MAX_IOREAD32_COUNT) | |
112 | return -EINVAL; | |
113 | ||
114 | /* Allocate a single memory block for values and addresses. */ | |
115 | count16 = 2*count; | |
44956855 | 116 | a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)), |
35c3404e | 117 | GFP_KERNEL); |
e85d0918 DD |
118 | if (!a16) { |
119 | dev_dbg_f(zd_chip_dev(chip), | |
120 | "error ENOMEM in allocation of a16\n"); | |
121 | r = -ENOMEM; | |
122 | goto out; | |
123 | } | |
124 | v16 = (u16 *)(a16 + count16); | |
125 | ||
126 | for (i = 0; i < count; i++) { | |
127 | int j = 2*i; | |
128 | /* We read the high word always first. */ | |
0ce34bc8 | 129 | a16[j] = inc_addr(addr[i]); |
e85d0918 DD |
130 | a16[j+1] = addr[i]; |
131 | } | |
132 | ||
133 | r = zd_ioread16v_locked(chip, v16, a16, count16); | |
134 | if (r) { | |
135 | dev_dbg_f(zd_chip_dev(chip), | |
136 | "error: zd_ioread16v_locked. Error number %d\n", r); | |
137 | goto out; | |
138 | } | |
139 | ||
140 | for (i = 0; i < count; i++) { | |
141 | int j = 2*i; | |
142 | values[i] = (v16[j] << 16) | v16[j+1]; | |
143 | } | |
144 | ||
145 | out: | |
146 | kfree((void *)a16); | |
147 | return r; | |
148 | } | |
149 | ||
150 | int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
151 | unsigned int count) | |
152 | { | |
153 | int i, j, r; | |
154 | struct zd_ioreq16 *ioreqs16; | |
155 | unsigned int count16; | |
156 | ||
157 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
158 | ||
159 | if (count == 0) | |
160 | return 0; | |
161 | if (count > USB_MAX_IOWRITE32_COUNT) | |
162 | return -EINVAL; | |
163 | ||
164 | /* Allocate a single memory block for values and addresses. */ | |
165 | count16 = 2*count; | |
35c3404e | 166 | ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL); |
e85d0918 DD |
167 | if (!ioreqs16) { |
168 | r = -ENOMEM; | |
169 | dev_dbg_f(zd_chip_dev(chip), | |
170 | "error %d in ioreqs16 allocation\n", r); | |
171 | goto out; | |
172 | } | |
173 | ||
174 | for (i = 0; i < count; i++) { | |
175 | j = 2*i; | |
176 | /* We write the high word always first. */ | |
177 | ioreqs16[j].value = ioreqs[i].value >> 16; | |
0ce34bc8 | 178 | ioreqs16[j].addr = inc_addr(ioreqs[i].addr); |
e85d0918 DD |
179 | ioreqs16[j+1].value = ioreqs[i].value; |
180 | ioreqs16[j+1].addr = ioreqs[i].addr; | |
181 | } | |
182 | ||
183 | r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16); | |
184 | #ifdef DEBUG | |
185 | if (r) { | |
186 | dev_dbg_f(zd_chip_dev(chip), | |
187 | "error %d in zd_usb_write16v\n", r); | |
188 | } | |
189 | #endif /* DEBUG */ | |
190 | out: | |
191 | kfree(ioreqs16); | |
192 | return r; | |
193 | } | |
194 | ||
195 | int zd_iowrite16a_locked(struct zd_chip *chip, | |
196 | const struct zd_ioreq16 *ioreqs, unsigned int count) | |
197 | { | |
198 | int r; | |
199 | unsigned int i, j, t, max; | |
200 | ||
201 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
202 | for (i = 0; i < count; i += j + t) { | |
203 | t = 0; | |
204 | max = count-i; | |
205 | if (max > USB_MAX_IOWRITE16_COUNT) | |
206 | max = USB_MAX_IOWRITE16_COUNT; | |
207 | for (j = 0; j < max; j++) { | |
208 | if (!ioreqs[i+j].addr) { | |
209 | t = 1; | |
210 | break; | |
211 | } | |
212 | } | |
213 | ||
214 | r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j); | |
215 | if (r) { | |
216 | dev_dbg_f(zd_chip_dev(chip), | |
217 | "error zd_usb_iowrite16v. Error number %d\n", | |
218 | r); | |
219 | return r; | |
220 | } | |
221 | } | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | /* Writes a variable number of 32 bit registers. The functions will split | |
227 | * that in several USB requests. A split can be forced by inserting an IO | |
228 | * request with an zero address field. | |
229 | */ | |
230 | int zd_iowrite32a_locked(struct zd_chip *chip, | |
231 | const struct zd_ioreq32 *ioreqs, unsigned int count) | |
232 | { | |
233 | int r; | |
234 | unsigned int i, j, t, max; | |
235 | ||
236 | for (i = 0; i < count; i += j + t) { | |
237 | t = 0; | |
238 | max = count-i; | |
239 | if (max > USB_MAX_IOWRITE32_COUNT) | |
240 | max = USB_MAX_IOWRITE32_COUNT; | |
241 | for (j = 0; j < max; j++) { | |
242 | if (!ioreqs[i+j].addr) { | |
243 | t = 1; | |
244 | break; | |
245 | } | |
246 | } | |
247 | ||
248 | r = _zd_iowrite32v_locked(chip, &ioreqs[i], j); | |
249 | if (r) { | |
250 | dev_dbg_f(zd_chip_dev(chip), | |
251 | "error _zd_iowrite32v_locked." | |
252 | " Error number %d\n", r); | |
253 | return r; | |
254 | } | |
255 | } | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
260 | int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value) | |
261 | { | |
262 | int r; | |
263 | ||
e85d0918 DD |
264 | mutex_lock(&chip->mutex); |
265 | r = zd_ioread16_locked(chip, value, addr); | |
266 | mutex_unlock(&chip->mutex); | |
267 | return r; | |
268 | } | |
269 | ||
270 | int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value) | |
271 | { | |
272 | int r; | |
273 | ||
e85d0918 DD |
274 | mutex_lock(&chip->mutex); |
275 | r = zd_ioread32_locked(chip, value, addr); | |
276 | mutex_unlock(&chip->mutex); | |
277 | return r; | |
278 | } | |
279 | ||
280 | int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value) | |
281 | { | |
282 | int r; | |
283 | ||
e85d0918 DD |
284 | mutex_lock(&chip->mutex); |
285 | r = zd_iowrite16_locked(chip, value, addr); | |
286 | mutex_unlock(&chip->mutex); | |
287 | return r; | |
288 | } | |
289 | ||
290 | int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value) | |
291 | { | |
292 | int r; | |
293 | ||
e85d0918 DD |
294 | mutex_lock(&chip->mutex); |
295 | r = zd_iowrite32_locked(chip, value, addr); | |
296 | mutex_unlock(&chip->mutex); | |
297 | return r; | |
298 | } | |
299 | ||
300 | int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, | |
301 | u32 *values, unsigned int count) | |
302 | { | |
303 | int r; | |
304 | ||
e85d0918 DD |
305 | mutex_lock(&chip->mutex); |
306 | r = zd_ioread32v_locked(chip, values, addresses, count); | |
307 | mutex_unlock(&chip->mutex); | |
308 | return r; | |
309 | } | |
310 | ||
311 | int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
312 | unsigned int count) | |
313 | { | |
314 | int r; | |
315 | ||
e85d0918 DD |
316 | mutex_lock(&chip->mutex); |
317 | r = zd_iowrite32a_locked(chip, ioreqs, count); | |
318 | mutex_unlock(&chip->mutex); | |
319 | return r; | |
320 | } | |
321 | ||
322 | static int read_pod(struct zd_chip *chip, u8 *rf_type) | |
323 | { | |
324 | int r; | |
325 | u32 value; | |
326 | ||
327 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
328 | r = zd_ioread32_locked(chip, &value, E2P_POD); | |
329 | if (r) | |
330 | goto error; | |
331 | dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value); | |
332 | ||
333 | /* FIXME: AL2230 handling (Bit 7 in POD) */ | |
334 | *rf_type = value & 0x0f; | |
335 | chip->pa_type = (value >> 16) & 0x0f; | |
336 | chip->patch_cck_gain = (value >> 8) & 0x1; | |
337 | chip->patch_cr157 = (value >> 13) & 0x1; | |
338 | chip->patch_6m_band_edge = (value >> 21) & 0x1; | |
20fe2176 | 339 | chip->new_phy_layout = (value >> 31) & 0x1; |
ae6ead46 | 340 | chip->al2230s_bit = (value >> 7) & 0x1; |
583afd1e UK |
341 | chip->link_led = ((value >> 4) & 1) ? LED1 : LED2; |
342 | chip->supports_tx_led = 1; | |
343 | if (value & (1 << 24)) { /* LED scenario */ | |
344 | if (value & (1 << 29)) | |
345 | chip->supports_tx_led = 0; | |
346 | } | |
e85d0918 DD |
347 | |
348 | dev_dbg_f(zd_chip_dev(chip), | |
349 | "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d " | |
583afd1e | 350 | "patch 6M %d new PHY %d link LED%d tx led %d\n", |
e85d0918 DD |
351 | zd_rf_name(*rf_type), *rf_type, |
352 | chip->pa_type, chip->patch_cck_gain, | |
583afd1e UK |
353 | chip->patch_cr157, chip->patch_6m_band_edge, |
354 | chip->new_phy_layout, | |
355 | chip->link_led == LED1 ? 1 : 2, | |
356 | chip->supports_tx_led); | |
e85d0918 DD |
357 | return 0; |
358 | error: | |
359 | *rf_type = 0; | |
360 | chip->pa_type = 0; | |
361 | chip->patch_cck_gain = 0; | |
362 | chip->patch_cr157 = 0; | |
363 | chip->patch_6m_band_edge = 0; | |
20fe2176 | 364 | chip->new_phy_layout = 0; |
e85d0918 DD |
365 | return r; |
366 | } | |
367 | ||
368 | static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr, | |
369 | const zd_addr_t *addr) | |
370 | { | |
371 | int r; | |
372 | u32 parts[2]; | |
373 | ||
374 | r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2); | |
375 | if (r) { | |
376 | dev_dbg_f(zd_chip_dev(chip), | |
377 | "error: couldn't read e2p macs. Error number %d\n", r); | |
378 | return r; | |
379 | } | |
380 | ||
381 | mac_addr[0] = parts[0]; | |
382 | mac_addr[1] = parts[0] >> 8; | |
383 | mac_addr[2] = parts[0] >> 16; | |
384 | mac_addr[3] = parts[0] >> 24; | |
385 | mac_addr[4] = parts[1]; | |
386 | mac_addr[5] = parts[1] >> 8; | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
391 | static int read_e2p_mac_addr(struct zd_chip *chip) | |
392 | { | |
393 | static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 }; | |
394 | ||
395 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
396 | return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr); | |
397 | } | |
398 | ||
399 | /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and | |
400 | * CR_MAC_ADDR_P2 must be overwritten | |
401 | */ | |
402 | void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr) | |
403 | { | |
404 | mutex_lock(&chip->mutex); | |
405 | memcpy(mac_addr, chip->e2p_mac, ETH_ALEN); | |
406 | mutex_unlock(&chip->mutex); | |
407 | } | |
408 | ||
409 | static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr) | |
410 | { | |
411 | static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 }; | |
412 | return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr); | |
413 | } | |
414 | ||
415 | int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr) | |
416 | { | |
417 | int r; | |
418 | ||
419 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
420 | mutex_lock(&chip->mutex); | |
421 | r = read_mac_addr(chip, mac_addr); | |
422 | mutex_unlock(&chip->mutex); | |
423 | return r; | |
424 | } | |
425 | ||
426 | int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr) | |
427 | { | |
428 | int r; | |
429 | struct zd_ioreq32 reqs[2] = { | |
430 | [0] = { .addr = CR_MAC_ADDR_P1 }, | |
431 | [1] = { .addr = CR_MAC_ADDR_P2 }, | |
432 | }; | |
433 | ||
434 | reqs[0].value = (mac_addr[3] << 24) | |
435 | | (mac_addr[2] << 16) | |
436 | | (mac_addr[1] << 8) | |
437 | | mac_addr[0]; | |
438 | reqs[1].value = (mac_addr[5] << 8) | |
439 | | mac_addr[4]; | |
440 | ||
441 | dev_dbg_f(zd_chip_dev(chip), | |
442 | "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr)); | |
443 | ||
444 | mutex_lock(&chip->mutex); | |
445 | r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); | |
446 | #ifdef DEBUG | |
447 | { | |
448 | u8 tmp[ETH_ALEN]; | |
449 | read_mac_addr(chip, tmp); | |
450 | } | |
451 | #endif /* DEBUG */ | |
452 | mutex_unlock(&chip->mutex); | |
453 | return r; | |
454 | } | |
455 | ||
456 | int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain) | |
457 | { | |
458 | int r; | |
459 | u32 value; | |
460 | ||
461 | mutex_lock(&chip->mutex); | |
462 | r = zd_ioread32_locked(chip, &value, E2P_SUBID); | |
463 | mutex_unlock(&chip->mutex); | |
464 | if (r) | |
465 | return r; | |
466 | ||
467 | *regdomain = value >> 16; | |
468 | dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain); | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
473 | static int read_values(struct zd_chip *chip, u8 *values, size_t count, | |
474 | zd_addr_t e2p_addr, u32 guard) | |
475 | { | |
476 | int r; | |
477 | int i; | |
478 | u32 v; | |
479 | ||
480 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
481 | for (i = 0;;) { | |
0ce34bc8 DD |
482 | r = zd_ioread32_locked(chip, &v, |
483 | (zd_addr_t)((u16)e2p_addr+i/2)); | |
e85d0918 DD |
484 | if (r) |
485 | return r; | |
486 | v -= guard; | |
487 | if (i+4 < count) { | |
488 | values[i++] = v; | |
489 | values[i++] = v >> 8; | |
490 | values[i++] = v >> 16; | |
491 | values[i++] = v >> 24; | |
492 | continue; | |
493 | } | |
494 | for (;i < count; i++) | |
495 | values[i] = v >> (8*(i%3)); | |
496 | return 0; | |
497 | } | |
498 | } | |
499 | ||
500 | static int read_pwr_cal_values(struct zd_chip *chip) | |
501 | { | |
502 | return read_values(chip, chip->pwr_cal_values, | |
503 | E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1, | |
504 | 0); | |
505 | } | |
506 | ||
507 | static int read_pwr_int_values(struct zd_chip *chip) | |
508 | { | |
509 | return read_values(chip, chip->pwr_int_values, | |
510 | E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1, | |
511 | E2P_PWR_INT_GUARD); | |
512 | } | |
513 | ||
514 | static int read_ofdm_cal_values(struct zd_chip *chip) | |
515 | { | |
516 | int r; | |
517 | int i; | |
518 | static const zd_addr_t addresses[] = { | |
519 | E2P_36M_CAL_VALUE1, | |
520 | E2P_48M_CAL_VALUE1, | |
521 | E2P_54M_CAL_VALUE1, | |
522 | }; | |
523 | ||
524 | for (i = 0; i < 3; i++) { | |
525 | r = read_values(chip, chip->ofdm_cal_values[i], | |
526 | E2P_CHANNEL_COUNT, addresses[i], 0); | |
527 | if (r) | |
528 | return r; | |
529 | } | |
530 | return 0; | |
531 | } | |
532 | ||
533 | static int read_cal_int_tables(struct zd_chip *chip) | |
534 | { | |
535 | int r; | |
536 | ||
537 | r = read_pwr_cal_values(chip); | |
538 | if (r) | |
539 | return r; | |
540 | r = read_pwr_int_values(chip); | |
541 | if (r) | |
542 | return r; | |
543 | r = read_ofdm_cal_values(chip); | |
544 | if (r) | |
545 | return r; | |
546 | return 0; | |
547 | } | |
548 | ||
549 | /* phy means physical registers */ | |
550 | int zd_chip_lock_phy_regs(struct zd_chip *chip) | |
551 | { | |
552 | int r; | |
553 | u32 tmp; | |
554 | ||
555 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
556 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); | |
557 | if (r) { | |
558 | dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r); | |
559 | return r; | |
560 | } | |
561 | ||
562 | dev_dbg_f(zd_chip_dev(chip), | |
563 | "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS); | |
564 | tmp &= ~UNLOCK_PHY_REGS; | |
565 | ||
566 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); | |
567 | if (r) | |
568 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); | |
569 | return r; | |
570 | } | |
571 | ||
572 | int zd_chip_unlock_phy_regs(struct zd_chip *chip) | |
573 | { | |
574 | int r; | |
575 | u32 tmp; | |
576 | ||
577 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
578 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); | |
579 | if (r) { | |
580 | dev_err(zd_chip_dev(chip), | |
581 | "error ioread32(CR_REG1): %d\n", r); | |
582 | return r; | |
583 | } | |
584 | ||
585 | dev_dbg_f(zd_chip_dev(chip), | |
586 | "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS); | |
587 | tmp |= UNLOCK_PHY_REGS; | |
588 | ||
589 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); | |
590 | if (r) | |
591 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); | |
592 | return r; | |
593 | } | |
594 | ||
92b3e2e9 | 595 | /* CR157 can be optionally patched by the EEPROM for original ZD1211 */ |
e85d0918 DD |
596 | static int patch_cr157(struct zd_chip *chip) |
597 | { | |
598 | int r; | |
92b3e2e9 | 599 | u16 value; |
e85d0918 DD |
600 | |
601 | if (!chip->patch_cr157) | |
602 | return 0; | |
603 | ||
92b3e2e9 | 604 | r = zd_ioread16_locked(chip, &value, E2P_PHY_REG); |
e85d0918 DD |
605 | if (r) |
606 | return r; | |
607 | ||
608 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8); | |
609 | return zd_iowrite32_locked(chip, value >> 8, CR157); | |
610 | } | |
611 | ||
612 | /* | |
613 | * 6M band edge can be optionally overwritten for certain RF's | |
614 | * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge | |
615 | * bit (for AL2230, AL2230S) | |
616 | */ | |
617 | static int patch_6m_band_edge(struct zd_chip *chip, int channel) | |
618 | { | |
619 | struct zd_ioreq16 ioreqs[] = { | |
620 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, | |
621 | { CR47, 0x1e }, | |
622 | }; | |
623 | ||
624 | if (!chip->patch_6m_band_edge || !chip->rf.patch_6m_band_edge) | |
625 | return 0; | |
626 | ||
627 | /* FIXME: Channel 11 is not the edge for all regulatory domains. */ | |
628 | if (channel == 1 || channel == 11) | |
629 | ioreqs[0].value = 0x12; | |
630 | ||
631 | dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel); | |
632 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
633 | } | |
634 | ||
635 | static int zd1211_hw_reset_phy(struct zd_chip *chip) | |
636 | { | |
637 | static const struct zd_ioreq16 ioreqs[] = { | |
638 | { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 }, | |
639 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 }, | |
640 | { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f }, | |
641 | { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d }, | |
642 | { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a }, | |
643 | { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c }, | |
644 | { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 }, | |
645 | { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 }, | |
646 | { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b }, | |
647 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, | |
648 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, | |
649 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, | |
650 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, | |
651 | { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff }, | |
652 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, | |
653 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, | |
654 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, | |
655 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, | |
656 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, | |
657 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, | |
658 | { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 }, | |
659 | { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 }, | |
660 | { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 }, | |
661 | { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 }, | |
662 | { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 }, | |
663 | { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff }, | |
664 | { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 }, | |
665 | { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 }, | |
666 | { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 }, | |
667 | { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a }, | |
668 | { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 }, | |
669 | { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e }, | |
670 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, | |
671 | { }, | |
672 | { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 }, | |
673 | { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 }, | |
674 | { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 }, | |
675 | { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 }, | |
676 | { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C }, | |
677 | { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 }, | |
678 | { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 }, | |
679 | { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 }, | |
680 | { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 }, | |
681 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, | |
682 | { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 }, | |
683 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, | |
684 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, | |
685 | { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f }, | |
686 | { CR123, 0x27 }, { CR125, 0xaa }, { CR127, 0x03 }, | |
687 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, | |
688 | { CR131, 0x0C }, { CR136, 0xdf }, { CR137, 0x40 }, | |
689 | { CR138, 0xa0 }, { CR139, 0xb0 }, { CR140, 0x99 }, | |
690 | { CR141, 0x82 }, { CR142, 0x54 }, { CR143, 0x1c }, | |
691 | { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x4c }, | |
692 | { CR149, 0x50 }, { CR150, 0x0e }, { CR151, 0x18 }, | |
693 | { CR160, 0xfe }, { CR161, 0xee }, { CR162, 0xaa }, | |
694 | { CR163, 0xfa }, { CR164, 0xfa }, { CR165, 0xea }, | |
695 | { CR166, 0xbe }, { CR167, 0xbe }, { CR168, 0x6a }, | |
696 | { CR169, 0xba }, { CR170, 0xba }, { CR171, 0xba }, | |
697 | /* Note: CR204 must lead the CR203 */ | |
698 | { CR204, 0x7d }, | |
699 | { }, | |
700 | { CR203, 0x30 }, | |
701 | }; | |
702 | ||
703 | int r, t; | |
704 | ||
705 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
706 | ||
707 | r = zd_chip_lock_phy_regs(chip); | |
708 | if (r) | |
709 | goto out; | |
710 | ||
711 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
712 | if (r) | |
713 | goto unlock; | |
714 | ||
715 | r = patch_cr157(chip); | |
716 | unlock: | |
717 | t = zd_chip_unlock_phy_regs(chip); | |
718 | if (t && !r) | |
719 | r = t; | |
720 | out: | |
721 | return r; | |
722 | } | |
723 | ||
724 | static int zd1211b_hw_reset_phy(struct zd_chip *chip) | |
725 | { | |
726 | static const struct zd_ioreq16 ioreqs[] = { | |
727 | { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 }, | |
728 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 }, | |
729 | { CR10, 0x81 }, | |
730 | /* power control { { CR11, 1 << 6 }, */ | |
731 | { CR11, 0x00 }, | |
732 | { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 }, | |
733 | { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e }, | |
734 | { CR18, 0x0a }, { CR19, 0x48 }, | |
735 | { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */ | |
736 | { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 }, | |
737 | { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 }, | |
738 | { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 }, | |
fe7215ca | 739 | { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */ |
e85d0918 DD |
740 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, |
741 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, | |
742 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, | |
743 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, | |
744 | { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff }, | |
745 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, | |
746 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, | |
747 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, | |
748 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, | |
749 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, | |
750 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, | |
751 | { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 }, | |
752 | { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 }, | |
753 | { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 }, | |
754 | { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 }, | |
755 | { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 }, | |
756 | { CR94, 0x01 }, | |
757 | { CR95, 0x20 }, /* ZD1211B */ | |
758 | { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 }, | |
759 | { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 }, | |
760 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, | |
761 | { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 }, | |
762 | { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 }, | |
763 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, | |
764 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, | |
765 | { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e }, | |
766 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, | |
767 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, | |
768 | { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 }, | |
769 | { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 }, | |
770 | { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c }, | |
771 | { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 }, | |
772 | { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */ | |
773 | { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */ | |
774 | { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe }, | |
775 | { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa }, | |
776 | { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe }, | |
777 | { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba }, | |
778 | { CR170, 0xba }, { CR171, 0xba }, | |
779 | /* Note: CR204 must lead the CR203 */ | |
780 | { CR204, 0x7d }, | |
781 | {}, | |
782 | { CR203, 0x30 }, | |
783 | }; | |
784 | ||
785 | int r, t; | |
786 | ||
787 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
788 | ||
789 | r = zd_chip_lock_phy_regs(chip); | |
790 | if (r) | |
791 | goto out; | |
792 | ||
793 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
e85d0918 DD |
794 | t = zd_chip_unlock_phy_regs(chip); |
795 | if (t && !r) | |
796 | r = t; | |
797 | out: | |
798 | return r; | |
799 | } | |
800 | ||
801 | static int hw_reset_phy(struct zd_chip *chip) | |
802 | { | |
803 | return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) : | |
804 | zd1211_hw_reset_phy(chip); | |
805 | } | |
806 | ||
807 | static int zd1211_hw_init_hmac(struct zd_chip *chip) | |
808 | { | |
809 | static const struct zd_ioreq32 ioreqs[] = { | |
e85d0918 | 810 | { CR_ZD1211_RETRY_MAX, 0x2 }, |
e85d0918 | 811 | { CR_RX_THRESHOLD, 0x000c0640 }, |
e85d0918 DD |
812 | }; |
813 | ||
e85d0918 DD |
814 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
815 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
34c44912 | 816 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
e85d0918 DD |
817 | } |
818 | ||
819 | static int zd1211b_hw_init_hmac(struct zd_chip *chip) | |
820 | { | |
821 | static const struct zd_ioreq32 ioreqs[] = { | |
e85d0918 DD |
822 | { CR_ZD1211B_RETRY_MAX, 0x02020202 }, |
823 | { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f }, | |
824 | { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f }, | |
825 | { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f }, | |
826 | { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f }, | |
827 | { CR_ZD1211B_AIFS_CTL1, 0x00280028 }, | |
828 | { CR_ZD1211B_AIFS_CTL2, 0x008C003C }, | |
829 | { CR_ZD1211B_TXOP, 0x01800824 }, | |
34c44912 DD |
830 | { CR_RX_THRESHOLD, 0x000c0eff, }, |
831 | }; | |
832 | ||
833 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
834 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
835 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
836 | } | |
837 | ||
838 | static int hw_init_hmac(struct zd_chip *chip) | |
839 | { | |
840 | int r; | |
841 | static const struct zd_ioreq32 ioreqs[] = { | |
842 | { CR_ACK_TIMEOUT_EXT, 0x20 }, | |
843 | { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, | |
e85d0918 | 844 | { CR_SNIFFER_ON, 0 }, |
fde627b5 | 845 | { CR_RX_FILTER, STA_RX_FILTER }, |
e85d0918 DD |
846 | { CR_GROUP_HASH_P1, 0x00 }, |
847 | { CR_GROUP_HASH_P2, 0x80000000 }, | |
848 | { CR_REG1, 0xa4 }, | |
849 | { CR_ADDA_PWR_DWN, 0x7f }, | |
850 | { CR_BCN_PLCP_CFG, 0x00f00401 }, | |
851 | { CR_PHY_DELAY, 0x00 }, | |
852 | { CR_ACK_TIMEOUT_EXT, 0x80 }, | |
853 | { CR_ADDA_PWR_DWN, 0x00 }, | |
854 | { CR_ACK_TIME_80211, 0x100 }, | |
e85d0918 DD |
855 | { CR_RX_PE_DELAY, 0x70 }, |
856 | { CR_PS_CTRL, 0x10000000 }, | |
857 | { CR_RTS_CTS_RATE, 0x02030203 }, | |
e85d0918 DD |
858 | { CR_AFTER_PNP, 0x1 }, |
859 | { CR_WEP_PROTECT, 0x114 }, | |
34c44912 | 860 | { CR_IFS_VALUE, IFS_VALUE_DEFAULT }, |
e85d0918 DD |
861 | }; |
862 | ||
e85d0918 DD |
863 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
864 | r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
34c44912 DD |
865 | if (r) |
866 | return r; | |
e85d0918 | 867 | |
e85d0918 DD |
868 | return chip->is_zd1211b ? |
869 | zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip); | |
870 | } | |
871 | ||
872 | struct aw_pt_bi { | |
873 | u32 atim_wnd_period; | |
874 | u32 pre_tbtt; | |
875 | u32 beacon_interval; | |
876 | }; | |
877 | ||
878 | static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) | |
879 | { | |
880 | int r; | |
881 | static const zd_addr_t aw_pt_bi_addr[] = | |
882 | { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL }; | |
883 | u32 values[3]; | |
884 | ||
885 | r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr, | |
886 | ARRAY_SIZE(aw_pt_bi_addr)); | |
887 | if (r) { | |
888 | memset(s, 0, sizeof(*s)); | |
889 | return r; | |
890 | } | |
891 | ||
892 | s->atim_wnd_period = values[0]; | |
893 | s->pre_tbtt = values[1]; | |
894 | s->beacon_interval = values[2]; | |
895 | dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n", | |
896 | s->atim_wnd_period, s->pre_tbtt, s->beacon_interval); | |
897 | return 0; | |
898 | } | |
899 | ||
900 | static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) | |
901 | { | |
902 | struct zd_ioreq32 reqs[3]; | |
903 | ||
904 | if (s->beacon_interval <= 5) | |
905 | s->beacon_interval = 5; | |
906 | if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval) | |
907 | s->pre_tbtt = s->beacon_interval - 1; | |
908 | if (s->atim_wnd_period >= s->pre_tbtt) | |
909 | s->atim_wnd_period = s->pre_tbtt - 1; | |
910 | ||
911 | reqs[0].addr = CR_ATIM_WND_PERIOD; | |
912 | reqs[0].value = s->atim_wnd_period; | |
913 | reqs[1].addr = CR_PRE_TBTT; | |
914 | reqs[1].value = s->pre_tbtt; | |
915 | reqs[2].addr = CR_BCN_INTERVAL; | |
916 | reqs[2].value = s->beacon_interval; | |
917 | ||
918 | dev_dbg_f(zd_chip_dev(chip), | |
919 | "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt, | |
920 | s->beacon_interval); | |
921 | return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); | |
922 | } | |
923 | ||
924 | ||
925 | static int set_beacon_interval(struct zd_chip *chip, u32 interval) | |
926 | { | |
927 | int r; | |
928 | struct aw_pt_bi s; | |
929 | ||
930 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
931 | r = get_aw_pt_bi(chip, &s); | |
932 | if (r) | |
933 | return r; | |
934 | s.beacon_interval = interval; | |
935 | return set_aw_pt_bi(chip, &s); | |
936 | } | |
937 | ||
938 | int zd_set_beacon_interval(struct zd_chip *chip, u32 interval) | |
939 | { | |
940 | int r; | |
941 | ||
942 | mutex_lock(&chip->mutex); | |
943 | r = set_beacon_interval(chip, interval); | |
944 | mutex_unlock(&chip->mutex); | |
945 | return r; | |
946 | } | |
947 | ||
948 | static int hw_init(struct zd_chip *chip) | |
949 | { | |
950 | int r; | |
951 | ||
952 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
953 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
954 | r = hw_reset_phy(chip); | |
955 | if (r) | |
956 | return r; | |
957 | ||
958 | r = hw_init_hmac(chip); | |
959 | if (r) | |
960 | return r; | |
98227a90 | 961 | |
98227a90 | 962 | return set_beacon_interval(chip, 100); |
e85d0918 DD |
963 | } |
964 | ||
0ce34bc8 DD |
965 | static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset) |
966 | { | |
967 | return (zd_addr_t)((u16)chip->fw_regs_base + offset); | |
968 | } | |
969 | ||
e85d0918 DD |
970 | #ifdef DEBUG |
971 | static int dump_cr(struct zd_chip *chip, const zd_addr_t addr, | |
972 | const char *addr_string) | |
973 | { | |
974 | int r; | |
975 | u32 value; | |
976 | ||
977 | r = zd_ioread32_locked(chip, &value, addr); | |
978 | if (r) { | |
979 | dev_dbg_f(zd_chip_dev(chip), | |
980 | "error reading %s. Error number %d\n", addr_string, r); | |
981 | return r; | |
982 | } | |
983 | ||
984 | dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n", | |
985 | addr_string, (unsigned int)value); | |
986 | return 0; | |
987 | } | |
988 | ||
989 | static int test_init(struct zd_chip *chip) | |
990 | { | |
991 | int r; | |
992 | ||
993 | r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP"); | |
994 | if (r) | |
995 | return r; | |
996 | r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN"); | |
997 | if (r) | |
998 | return r; | |
999 | return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT"); | |
1000 | } | |
1001 | ||
1002 | static void dump_fw_registers(struct zd_chip *chip) | |
1003 | { | |
0ce34bc8 DD |
1004 | const zd_addr_t addr[4] = { |
1005 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER), | |
1006 | fw_reg_addr(chip, FW_REG_USB_SPEED), | |
1007 | fw_reg_addr(chip, FW_REG_FIX_TX_RATE), | |
1008 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), | |
e85d0918 DD |
1009 | }; |
1010 | ||
1011 | int r; | |
1012 | u16 values[4]; | |
1013 | ||
1014 | r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr, | |
1015 | ARRAY_SIZE(addr)); | |
1016 | if (r) { | |
1017 | dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n", | |
1018 | r); | |
1019 | return; | |
1020 | } | |
1021 | ||
1022 | dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]); | |
1023 | dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]); | |
1024 | dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]); | |
1025 | dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]); | |
1026 | } | |
1027 | #endif /* DEBUG */ | |
1028 | ||
1029 | static int print_fw_version(struct zd_chip *chip) | |
1030 | { | |
1031 | int r; | |
1032 | u16 version; | |
1033 | ||
0ce34bc8 DD |
1034 | r = zd_ioread16_locked(chip, &version, |
1035 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER)); | |
e85d0918 DD |
1036 | if (r) |
1037 | return r; | |
1038 | ||
1039 | dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version); | |
1040 | return 0; | |
1041 | } | |
1042 | ||
1043 | static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std) | |
1044 | { | |
1045 | u32 rates; | |
1046 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1047 | /* This sets the mandatory rates, which only depend from the standard | |
1048 | * that the device is supporting. Until further notice we should try | |
1049 | * to support 802.11g also for full speed USB. | |
1050 | */ | |
1051 | switch (std) { | |
1052 | case IEEE80211B: | |
1053 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M; | |
1054 | break; | |
1055 | case IEEE80211G: | |
1056 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M| | |
1057 | CR_RATE_6M|CR_RATE_12M|CR_RATE_24M; | |
1058 | break; | |
1059 | default: | |
1060 | return -EINVAL; | |
1061 | } | |
1062 | return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL); | |
1063 | } | |
1064 | ||
b1382ede DD |
1065 | int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, |
1066 | u8 rts_rate, int preamble) | |
1067 | { | |
1068 | int rts_mod = ZD_RX_CCK; | |
1069 | u32 value = 0; | |
1070 | ||
1071 | /* Modulation bit */ | |
1072 | if (ZD_CS_TYPE(rts_rate) == ZD_CS_OFDM) | |
1073 | rts_mod = ZD_RX_OFDM; | |
1074 | ||
1075 | dev_dbg_f(zd_chip_dev(chip), "rts_rate=%x preamble=%x\n", | |
1076 | rts_rate, preamble); | |
1077 | ||
1078 | value |= rts_rate << RTSCTS_SH_RTS_RATE; | |
1079 | value |= rts_mod << RTSCTS_SH_RTS_MOD_TYPE; | |
1080 | value |= preamble << RTSCTS_SH_RTS_PMB_TYPE; | |
1081 | value |= preamble << RTSCTS_SH_CTS_PMB_TYPE; | |
1082 | ||
1083 | /* We always send 11M self-CTS messages, like the vendor driver. */ | |
1084 | value |= ZD_CCK_RATE_11M << RTSCTS_SH_CTS_RATE; | |
1085 | value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE; | |
1086 | ||
1087 | return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE); | |
1088 | } | |
1089 | ||
e85d0918 DD |
1090 | int zd_chip_enable_hwint(struct zd_chip *chip) |
1091 | { | |
1092 | int r; | |
1093 | ||
1094 | mutex_lock(&chip->mutex); | |
1095 | r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT); | |
1096 | mutex_unlock(&chip->mutex); | |
1097 | return r; | |
1098 | } | |
1099 | ||
1100 | static int disable_hwint(struct zd_chip *chip) | |
1101 | { | |
1102 | return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT); | |
1103 | } | |
1104 | ||
1105 | int zd_chip_disable_hwint(struct zd_chip *chip) | |
1106 | { | |
1107 | int r; | |
1108 | ||
1109 | mutex_lock(&chip->mutex); | |
1110 | r = disable_hwint(chip); | |
1111 | mutex_unlock(&chip->mutex); | |
1112 | return r; | |
1113 | } | |
1114 | ||
0ce34bc8 DD |
1115 | static int read_fw_regs_offset(struct zd_chip *chip) |
1116 | { | |
1117 | int r; | |
1118 | ||
1119 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1120 | r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base, | |
1121 | FWRAW_REGS_ADDR); | |
1122 | if (r) | |
1123 | return r; | |
1124 | dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n", | |
1125 | (u16)chip->fw_regs_base); | |
1126 | ||
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | ||
e85d0918 DD |
1131 | int zd_chip_init_hw(struct zd_chip *chip, u8 device_type) |
1132 | { | |
1133 | int r; | |
1134 | u8 rf_type; | |
1135 | ||
1136 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
1137 | ||
1138 | mutex_lock(&chip->mutex); | |
1139 | chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0; | |
1140 | ||
1141 | #ifdef DEBUG | |
1142 | r = test_init(chip); | |
1143 | if (r) | |
1144 | goto out; | |
1145 | #endif | |
1146 | r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP); | |
1147 | if (r) | |
1148 | goto out; | |
1149 | ||
0ce34bc8 | 1150 | r = read_fw_regs_offset(chip); |
e85d0918 DD |
1151 | if (r) |
1152 | goto out; | |
1153 | ||
1154 | /* GPI is always disabled, also in the other driver. | |
1155 | */ | |
1156 | r = zd_iowrite32_locked(chip, 0, CR_GPI_EN); | |
1157 | if (r) | |
1158 | goto out; | |
1159 | r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX); | |
1160 | if (r) | |
1161 | goto out; | |
1162 | /* Currently we support IEEE 802.11g for full and high speed USB. | |
1163 | * It might be discussed, whether we should suppport pure b mode for | |
1164 | * full speed USB. | |
1165 | */ | |
1166 | r = set_mandatory_rates(chip, IEEE80211G); | |
1167 | if (r) | |
1168 | goto out; | |
1169 | /* Disabling interrupts is certainly a smart thing here. | |
1170 | */ | |
1171 | r = disable_hwint(chip); | |
1172 | if (r) | |
1173 | goto out; | |
1174 | r = read_pod(chip, &rf_type); | |
1175 | if (r) | |
1176 | goto out; | |
1177 | r = hw_init(chip); | |
1178 | if (r) | |
1179 | goto out; | |
1180 | r = zd_rf_init_hw(&chip->rf, rf_type); | |
1181 | if (r) | |
1182 | goto out; | |
1183 | ||
1184 | r = print_fw_version(chip); | |
1185 | if (r) | |
1186 | goto out; | |
1187 | ||
1188 | #ifdef DEBUG | |
1189 | dump_fw_registers(chip); | |
1190 | r = test_init(chip); | |
1191 | if (r) | |
1192 | goto out; | |
1193 | #endif /* DEBUG */ | |
1194 | ||
1195 | r = read_e2p_mac_addr(chip); | |
1196 | if (r) | |
1197 | goto out; | |
1198 | ||
1199 | r = read_cal_int_tables(chip); | |
1200 | if (r) | |
1201 | goto out; | |
1202 | ||
1203 | print_id(chip); | |
1204 | out: | |
1205 | mutex_unlock(&chip->mutex); | |
1206 | return r; | |
1207 | } | |
1208 | ||
1209 | static int update_pwr_int(struct zd_chip *chip, u8 channel) | |
1210 | { | |
1211 | u8 value = chip->pwr_int_values[channel - 1]; | |
1212 | dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n", | |
1213 | channel, value); | |
cbb5e6bb | 1214 | return zd_iowrite16_locked(chip, value, CR31); |
e85d0918 DD |
1215 | } |
1216 | ||
1217 | static int update_pwr_cal(struct zd_chip *chip, u8 channel) | |
1218 | { | |
1219 | u8 value = chip->pwr_cal_values[channel-1]; | |
1220 | dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n", | |
1221 | channel, value); | |
cbb5e6bb | 1222 | return zd_iowrite16_locked(chip, value, CR68); |
e85d0918 DD |
1223 | } |
1224 | ||
1225 | static int update_ofdm_cal(struct zd_chip *chip, u8 channel) | |
1226 | { | |
cbb5e6bb | 1227 | struct zd_ioreq16 ioreqs[3]; |
e85d0918 DD |
1228 | |
1229 | ioreqs[0].addr = CR67; | |
1230 | ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1]; | |
1231 | ioreqs[1].addr = CR66; | |
1232 | ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1]; | |
1233 | ioreqs[2].addr = CR65; | |
1234 | ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1]; | |
1235 | ||
1236 | dev_dbg_f(zd_chip_dev(chip), | |
1237 | "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n", | |
1238 | channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value); | |
cbb5e6bb | 1239 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
e85d0918 DD |
1240 | } |
1241 | ||
1242 | static int update_channel_integration_and_calibration(struct zd_chip *chip, | |
1243 | u8 channel) | |
1244 | { | |
1245 | int r; | |
1246 | ||
1247 | r = update_pwr_int(chip, channel); | |
1248 | if (r) | |
1249 | return r; | |
1250 | if (chip->is_zd1211b) { | |
cbb5e6bb | 1251 | static const struct zd_ioreq16 ioreqs[] = { |
e85d0918 DD |
1252 | { CR69, 0x28 }, |
1253 | {}, | |
1254 | { CR69, 0x2a }, | |
1255 | }; | |
1256 | ||
1257 | r = update_ofdm_cal(chip, channel); | |
1258 | if (r) | |
1259 | return r; | |
1260 | r = update_pwr_cal(chip, channel); | |
1261 | if (r) | |
1262 | return r; | |
cbb5e6bb | 1263 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
e85d0918 DD |
1264 | if (r) |
1265 | return r; | |
1266 | } | |
1267 | ||
1268 | return 0; | |
1269 | } | |
1270 | ||
1271 | /* The CCK baseband gain can be optionally patched by the EEPROM */ | |
1272 | static int patch_cck_gain(struct zd_chip *chip) | |
1273 | { | |
1274 | int r; | |
1275 | u32 value; | |
1276 | ||
1277 | if (!chip->patch_cck_gain) | |
1278 | return 0; | |
1279 | ||
1280 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1281 | r = zd_ioread32_locked(chip, &value, E2P_PHY_REG); | |
1282 | if (r) | |
1283 | return r; | |
1284 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff); | |
cbb5e6bb | 1285 | return zd_iowrite16_locked(chip, value & 0xff, CR47); |
e85d0918 DD |
1286 | } |
1287 | ||
1288 | int zd_chip_set_channel(struct zd_chip *chip, u8 channel) | |
1289 | { | |
1290 | int r, t; | |
1291 | ||
1292 | mutex_lock(&chip->mutex); | |
1293 | r = zd_chip_lock_phy_regs(chip); | |
1294 | if (r) | |
1295 | goto out; | |
1296 | r = zd_rf_set_channel(&chip->rf, channel); | |
1297 | if (r) | |
1298 | goto unlock; | |
1299 | r = update_channel_integration_and_calibration(chip, channel); | |
1300 | if (r) | |
1301 | goto unlock; | |
1302 | r = patch_cck_gain(chip); | |
1303 | if (r) | |
1304 | goto unlock; | |
1305 | r = patch_6m_band_edge(chip, channel); | |
1306 | if (r) | |
1307 | goto unlock; | |
1308 | r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS); | |
1309 | unlock: | |
1310 | t = zd_chip_unlock_phy_regs(chip); | |
1311 | if (t && !r) | |
1312 | r = t; | |
1313 | out: | |
1314 | mutex_unlock(&chip->mutex); | |
1315 | return r; | |
1316 | } | |
1317 | ||
1318 | u8 zd_chip_get_channel(struct zd_chip *chip) | |
1319 | { | |
1320 | u8 channel; | |
1321 | ||
1322 | mutex_lock(&chip->mutex); | |
1323 | channel = chip->rf.channel; | |
1324 | mutex_unlock(&chip->mutex); | |
1325 | return channel; | |
1326 | } | |
1327 | ||
583afd1e | 1328 | int zd_chip_control_leds(struct zd_chip *chip, enum led_status status) |
e85d0918 | 1329 | { |
0ce34bc8 DD |
1330 | const zd_addr_t a[] = { |
1331 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), | |
583afd1e UK |
1332 | CR_LED, |
1333 | }; | |
e85d0918 | 1334 | |
583afd1e UK |
1335 | int r; |
1336 | u16 v[ARRAY_SIZE(a)]; | |
1337 | struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = { | |
0ce34bc8 | 1338 | [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) }, |
583afd1e UK |
1339 | [1] = { CR_LED }, |
1340 | }; | |
1341 | u16 other_led; | |
e85d0918 | 1342 | |
e85d0918 | 1343 | mutex_lock(&chip->mutex); |
583afd1e | 1344 | r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a)); |
e85d0918 | 1345 | if (r) |
583afd1e UK |
1346 | goto out; |
1347 | ||
1348 | other_led = chip->link_led == LED1 ? LED2 : LED1; | |
1349 | ||
e85d0918 | 1350 | switch (status) { |
e85d0918 | 1351 | case LED_OFF: |
583afd1e UK |
1352 | ioreqs[0].value = FW_LINK_OFF; |
1353 | ioreqs[1].value = v[1] & ~(LED1|LED2); | |
e85d0918 | 1354 | break; |
583afd1e UK |
1355 | case LED_SCANNING: |
1356 | ioreqs[0].value = FW_LINK_OFF; | |
1357 | ioreqs[1].value = v[1] & ~other_led; | |
1358 | if (get_seconds() % 3 == 0) { | |
1359 | ioreqs[1].value &= ~chip->link_led; | |
1360 | } else { | |
1361 | ioreqs[1].value |= chip->link_led; | |
1362 | } | |
e85d0918 | 1363 | break; |
583afd1e UK |
1364 | case LED_ASSOCIATED: |
1365 | ioreqs[0].value = FW_LINK_TX; | |
1366 | ioreqs[1].value = v[1] & ~other_led; | |
1367 | ioreqs[1].value |= chip->link_led; | |
e85d0918 DD |
1368 | break; |
1369 | default: | |
583afd1e | 1370 | r = -EINVAL; |
e85d0918 DD |
1371 | goto out; |
1372 | } | |
e85d0918 | 1373 | |
583afd1e UK |
1374 | if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) { |
1375 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
1376 | if (r) | |
e85d0918 | 1377 | goto out; |
e85d0918 | 1378 | } |
583afd1e | 1379 | r = 0; |
e85d0918 | 1380 | out: |
583afd1e | 1381 | mutex_unlock(&chip->mutex); |
e85d0918 DD |
1382 | return r; |
1383 | } | |
1384 | ||
b1382ede | 1385 | int zd_chip_set_basic_rates_locked(struct zd_chip *chip, u16 cr_rates) |
e85d0918 | 1386 | { |
b1382ede DD |
1387 | ZD_ASSERT((cr_rates & ~(CR_RATES_80211B | CR_RATES_80211G)) == 0); |
1388 | dev_dbg_f(zd_chip_dev(chip), "%x\n", cr_rates); | |
e85d0918 | 1389 | |
b1382ede | 1390 | return zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL); |
e85d0918 DD |
1391 | } |
1392 | ||
1393 | static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size) | |
1394 | { | |
1395 | static const u16 constants[] = { | |
1396 | 715, 655, 585, 540, 470, 410, 360, 315, | |
1397 | 270, 235, 205, 175, 150, 125, 105, 85, | |
1398 | 65, 50, 40, 25, 15 | |
1399 | }; | |
1400 | ||
1401 | int i; | |
1402 | u32 x; | |
1403 | ||
1404 | /* It seems that their quality parameter is somehow per signal | |
1405 | * and is now transferred per bit. | |
1406 | */ | |
1407 | switch (rate) { | |
1408 | case ZD_OFDM_RATE_6M: | |
1409 | case ZD_OFDM_RATE_12M: | |
1410 | case ZD_OFDM_RATE_24M: | |
1411 | size *= 2; | |
1412 | break; | |
1413 | case ZD_OFDM_RATE_9M: | |
1414 | case ZD_OFDM_RATE_18M: | |
1415 | case ZD_OFDM_RATE_36M: | |
1416 | case ZD_OFDM_RATE_54M: | |
1417 | size *= 4; | |
1418 | size /= 3; | |
1419 | break; | |
1420 | case ZD_OFDM_RATE_48M: | |
1421 | size *= 3; | |
1422 | size /= 2; | |
1423 | break; | |
1424 | default: | |
1425 | return -EINVAL; | |
1426 | } | |
1427 | ||
1428 | x = (10000 * status_quality)/size; | |
1429 | for (i = 0; i < ARRAY_SIZE(constants); i++) { | |
1430 | if (x > constants[i]) | |
1431 | break; | |
1432 | } | |
1433 | ||
db888aed UK |
1434 | switch (rate) { |
1435 | case ZD_OFDM_RATE_6M: | |
1436 | case ZD_OFDM_RATE_9M: | |
1437 | i += 3; | |
1438 | break; | |
1439 | case ZD_OFDM_RATE_12M: | |
1440 | case ZD_OFDM_RATE_18M: | |
1441 | i += 5; | |
1442 | break; | |
1443 | case ZD_OFDM_RATE_24M: | |
1444 | case ZD_OFDM_RATE_36M: | |
1445 | i += 9; | |
1446 | break; | |
1447 | case ZD_OFDM_RATE_48M: | |
1448 | case ZD_OFDM_RATE_54M: | |
1449 | i += 15; | |
1450 | break; | |
1451 | default: | |
1452 | return -EINVAL; | |
1453 | } | |
1454 | ||
e85d0918 DD |
1455 | return i; |
1456 | } | |
1457 | ||
db888aed UK |
1458 | static int ofdm_qual_percent(u8 status_quality, u8 rate, unsigned int size) |
1459 | { | |
1460 | int r; | |
1461 | ||
1462 | r = ofdm_qual_db(status_quality, rate, size); | |
1463 | ZD_ASSERT(r >= 0); | |
1464 | if (r < 0) | |
1465 | r = 0; | |
1466 | ||
1467 | r = (r * 100)/29; | |
1468 | return r <= 100 ? r : 100; | |
1469 | } | |
1470 | ||
e85d0918 DD |
1471 | static unsigned int log10times100(unsigned int x) |
1472 | { | |
1473 | static const u8 log10[] = { | |
1474 | 0, | |
1475 | 0, 30, 47, 60, 69, 77, 84, 90, 95, 100, | |
1476 | 104, 107, 111, 114, 117, 120, 123, 125, 127, 130, | |
1477 | 132, 134, 136, 138, 139, 141, 143, 144, 146, 147, | |
1478 | 149, 150, 151, 153, 154, 155, 156, 157, 159, 160, | |
1479 | 161, 162, 163, 164, 165, 166, 167, 168, 169, 169, | |
1480 | 170, 171, 172, 173, 174, 174, 175, 176, 177, 177, | |
1481 | 178, 179, 179, 180, 181, 181, 182, 183, 183, 184, | |
1482 | 185, 185, 186, 186, 187, 188, 188, 189, 189, 190, | |
1483 | 190, 191, 191, 192, 192, 193, 193, 194, 194, 195, | |
1484 | 195, 196, 196, 197, 197, 198, 198, 199, 199, 200, | |
1485 | 200, 200, 201, 201, 202, 202, 202, 203, 203, 204, | |
1486 | 204, 204, 205, 205, 206, 206, 206, 207, 207, 207, | |
1487 | 208, 208, 208, 209, 209, 210, 210, 210, 211, 211, | |
1488 | 211, 212, 212, 212, 213, 213, 213, 213, 214, 214, | |
1489 | 214, 215, 215, 215, 216, 216, 216, 217, 217, 217, | |
1490 | 217, 218, 218, 218, 219, 219, 219, 219, 220, 220, | |
1491 | 220, 220, 221, 221, 221, 222, 222, 222, 222, 223, | |
1492 | 223, 223, 223, 224, 224, 224, 224, | |
1493 | }; | |
1494 | ||
1495 | return x < ARRAY_SIZE(log10) ? log10[x] : 225; | |
1496 | } | |
1497 | ||
1498 | enum { | |
1499 | MAX_CCK_EVM_DB = 45, | |
1500 | }; | |
1501 | ||
1502 | static int cck_evm_db(u8 status_quality) | |
1503 | { | |
1504 | return (20 * log10times100(status_quality)) / 100; | |
1505 | } | |
1506 | ||
1507 | static int cck_snr_db(u8 status_quality) | |
1508 | { | |
1509 | int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality); | |
1510 | ZD_ASSERT(r >= 0); | |
1511 | return r; | |
1512 | } | |
1513 | ||
db888aed | 1514 | static int cck_qual_percent(u8 status_quality) |
e85d0918 | 1515 | { |
db888aed UK |
1516 | int r; |
1517 | ||
1518 | r = cck_snr_db(status_quality); | |
1519 | r = (100*r)/17; | |
1520 | return r <= 100 ? r : 100; | |
e85d0918 DD |
1521 | } |
1522 | ||
1523 | u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size, | |
1524 | const struct rx_status *status) | |
1525 | { | |
db888aed UK |
1526 | return (status->frame_status&ZD_RX_OFDM) ? |
1527 | ofdm_qual_percent(status->signal_quality_ofdm, | |
1528 | zd_ofdm_plcp_header_rate(rx_frame), | |
1529 | size) : | |
1530 | cck_qual_percent(status->signal_quality_cck); | |
e85d0918 DD |
1531 | } |
1532 | ||
1533 | u8 zd_rx_strength_percent(u8 rssi) | |
1534 | { | |
db888aed | 1535 | int r = (rssi*100) / 41; |
e85d0918 DD |
1536 | if (r > 100) |
1537 | r = 100; | |
1538 | return (u8) r; | |
1539 | } | |
1540 | ||
1541 | u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status) | |
1542 | { | |
1543 | static const u16 ofdm_rates[] = { | |
1544 | [ZD_OFDM_RATE_6M] = 60, | |
1545 | [ZD_OFDM_RATE_9M] = 90, | |
1546 | [ZD_OFDM_RATE_12M] = 120, | |
1547 | [ZD_OFDM_RATE_18M] = 180, | |
1548 | [ZD_OFDM_RATE_24M] = 240, | |
1549 | [ZD_OFDM_RATE_36M] = 360, | |
1550 | [ZD_OFDM_RATE_48M] = 480, | |
1551 | [ZD_OFDM_RATE_54M] = 540, | |
1552 | }; | |
1553 | u16 rate; | |
1554 | if (status->frame_status & ZD_RX_OFDM) { | |
1555 | u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame); | |
1556 | rate = ofdm_rates[ofdm_rate & 0xf]; | |
1557 | } else { | |
1558 | u8 cck_rate = zd_cck_plcp_header_rate(rx_frame); | |
1559 | switch (cck_rate) { | |
1560 | case ZD_CCK_SIGNAL_1M: | |
1561 | rate = 10; | |
1562 | break; | |
1563 | case ZD_CCK_SIGNAL_2M: | |
1564 | rate = 20; | |
1565 | break; | |
1566 | case ZD_CCK_SIGNAL_5M5: | |
1567 | rate = 55; | |
1568 | break; | |
1569 | case ZD_CCK_SIGNAL_11M: | |
1570 | rate = 110; | |
1571 | break; | |
1572 | default: | |
1573 | rate = 0; | |
1574 | } | |
1575 | } | |
1576 | ||
1577 | return rate; | |
1578 | } | |
1579 | ||
1580 | int zd_chip_switch_radio_on(struct zd_chip *chip) | |
1581 | { | |
1582 | int r; | |
1583 | ||
1584 | mutex_lock(&chip->mutex); | |
1585 | r = zd_switch_radio_on(&chip->rf); | |
1586 | mutex_unlock(&chip->mutex); | |
1587 | return r; | |
1588 | } | |
1589 | ||
1590 | int zd_chip_switch_radio_off(struct zd_chip *chip) | |
1591 | { | |
1592 | int r; | |
1593 | ||
1594 | mutex_lock(&chip->mutex); | |
1595 | r = zd_switch_radio_off(&chip->rf); | |
1596 | mutex_unlock(&chip->mutex); | |
1597 | return r; | |
1598 | } | |
1599 | ||
1600 | int zd_chip_enable_int(struct zd_chip *chip) | |
1601 | { | |
1602 | int r; | |
1603 | ||
1604 | mutex_lock(&chip->mutex); | |
1605 | r = zd_usb_enable_int(&chip->usb); | |
1606 | mutex_unlock(&chip->mutex); | |
1607 | return r; | |
1608 | } | |
1609 | ||
1610 | void zd_chip_disable_int(struct zd_chip *chip) | |
1611 | { | |
1612 | mutex_lock(&chip->mutex); | |
1613 | zd_usb_disable_int(&chip->usb); | |
1614 | mutex_unlock(&chip->mutex); | |
1615 | } | |
1616 | ||
1617 | int zd_chip_enable_rx(struct zd_chip *chip) | |
1618 | { | |
1619 | int r; | |
1620 | ||
1621 | mutex_lock(&chip->mutex); | |
1622 | r = zd_usb_enable_rx(&chip->usb); | |
1623 | mutex_unlock(&chip->mutex); | |
1624 | return r; | |
1625 | } | |
1626 | ||
1627 | void zd_chip_disable_rx(struct zd_chip *chip) | |
1628 | { | |
1629 | mutex_lock(&chip->mutex); | |
1630 | zd_usb_disable_rx(&chip->usb); | |
1631 | mutex_unlock(&chip->mutex); | |
1632 | } | |
1633 | ||
1634 | int zd_rfwritev_locked(struct zd_chip *chip, | |
1635 | const u32* values, unsigned int count, u8 bits) | |
1636 | { | |
1637 | int r; | |
1638 | unsigned int i; | |
1639 | ||
1640 | for (i = 0; i < count; i++) { | |
1641 | r = zd_rfwrite_locked(chip, values[i], bits); | |
1642 | if (r) | |
1643 | return r; | |
1644 | } | |
1645 | ||
1646 | return 0; | |
1647 | } | |
20fe2176 DD |
1648 | |
1649 | /* | |
1650 | * We can optionally program the RF directly through CR regs, if supported by | |
1651 | * the hardware. This is much faster than the older method. | |
1652 | */ | |
ec62bd91 | 1653 | int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value) |
20fe2176 DD |
1654 | { |
1655 | struct zd_ioreq16 ioreqs[] = { | |
1656 | { CR244, (value >> 16) & 0xff }, | |
1657 | { CR243, (value >> 8) & 0xff }, | |
1658 | { CR242, value & 0xff }, | |
1659 | }; | |
1660 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1661 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
1662 | } | |
1663 | ||
1664 | int zd_rfwritev_cr_locked(struct zd_chip *chip, | |
1665 | const u32 *values, unsigned int count) | |
1666 | { | |
1667 | int r; | |
1668 | unsigned int i; | |
1669 | ||
1670 | for (i = 0; i < count; i++) { | |
1671 | r = zd_rfwrite_cr_locked(chip, values[i]); | |
1672 | if (r) | |
1673 | return r; | |
1674 | } | |
1675 | ||
1676 | return 0; | |
1677 | } | |
9cdac965 UK |
1678 | |
1679 | int zd_chip_set_multicast_hash(struct zd_chip *chip, | |
1680 | struct zd_mc_hash *hash) | |
1681 | { | |
1682 | struct zd_ioreq32 ioreqs[] = { | |
1683 | { CR_GROUP_HASH_P1, hash->low }, | |
1684 | { CR_GROUP_HASH_P2, hash->high }, | |
1685 | }; | |
1686 | ||
1687 | dev_dbg_f(zd_chip_dev(chip), "hash l 0x%08x h 0x%08x\n", | |
1688 | ioreqs[0].value, ioreqs[1].value); | |
1689 | return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
1690 | } |