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e85d0918 DD |
1 | /* zd_chip.c |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License as published by | |
5 | * the Free Software Foundation; either version 2 of the License, or | |
6 | * (at your option) any later version. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
16 | */ | |
17 | ||
18 | /* This file implements all the hardware specific functions for the ZD1211 | |
19 | * and ZD1211B chips. Support for the ZD1211B was possible after Timothy | |
20 | * Legge sent me a ZD1211B device. Thank you Tim. -- Uli | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/errno.h> | |
25 | ||
26 | #include "zd_def.h" | |
27 | #include "zd_chip.h" | |
28 | #include "zd_ieee80211.h" | |
29 | #include "zd_mac.h" | |
30 | #include "zd_rf.h" | |
31 | #include "zd_util.h" | |
32 | ||
33 | void zd_chip_init(struct zd_chip *chip, | |
34 | struct net_device *netdev, | |
35 | struct usb_interface *intf) | |
36 | { | |
37 | memset(chip, 0, sizeof(*chip)); | |
38 | mutex_init(&chip->mutex); | |
39 | zd_usb_init(&chip->usb, netdev, intf); | |
40 | zd_rf_init(&chip->rf); | |
41 | } | |
42 | ||
43 | void zd_chip_clear(struct zd_chip *chip) | |
44 | { | |
c48cf125 | 45 | ZD_ASSERT(!mutex_is_locked(&chip->mutex)); |
e85d0918 DD |
46 | zd_usb_clear(&chip->usb); |
47 | zd_rf_clear(&chip->rf); | |
e85d0918 | 48 | mutex_destroy(&chip->mutex); |
c48cf125 | 49 | ZD_MEMCLEAR(chip, sizeof(*chip)); |
e85d0918 DD |
50 | } |
51 | ||
52 | static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size) | |
53 | { | |
54 | return scnprintf(buffer, size, "%02x-%02x-%02x", | |
55 | addr[0], addr[1], addr[2]); | |
56 | } | |
57 | ||
58 | /* Prints an identifier line, which will support debugging. */ | |
59 | static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size) | |
60 | { | |
61 | int i = 0; | |
62 | ||
63 | i = scnprintf(buffer, size, "zd1211%s chip ", | |
64 | chip->is_zd1211b ? "b" : ""); | |
65 | i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i); | |
66 | i += scnprintf(buffer+i, size-i, " "); | |
67 | i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i); | |
68 | i += scnprintf(buffer+i, size-i, " "); | |
69 | i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i); | |
f2a81a16 | 70 | i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type, |
e85d0918 DD |
71 | chip->patch_cck_gain ? 'g' : '-', |
72 | chip->patch_cr157 ? '7' : '-', | |
20fe2176 | 73 | chip->patch_6m_band_edge ? '6' : '-', |
f2a81a16 DD |
74 | chip->new_phy_layout ? 'N' : '-', |
75 | chip->al2230s_bit ? 'S' : '-'); | |
e85d0918 DD |
76 | return i; |
77 | } | |
78 | ||
79 | static void print_id(struct zd_chip *chip) | |
80 | { | |
81 | char buffer[80]; | |
82 | ||
83 | scnprint_id(chip, buffer, sizeof(buffer)); | |
84 | buffer[sizeof(buffer)-1] = 0; | |
85 | dev_info(zd_chip_dev(chip), "%s\n", buffer); | |
86 | } | |
87 | ||
0ce34bc8 DD |
88 | static zd_addr_t inc_addr(zd_addr_t addr) |
89 | { | |
90 | u16 a = (u16)addr; | |
91 | /* Control registers use byte addressing, but everything else uses word | |
92 | * addressing. */ | |
93 | if ((a & 0xf000) == CR_START) | |
94 | a += 2; | |
95 | else | |
96 | a += 1; | |
97 | return (zd_addr_t)a; | |
98 | } | |
99 | ||
e85d0918 DD |
100 | /* Read a variable number of 32-bit values. Parameter count is not allowed to |
101 | * exceed USB_MAX_IOREAD32_COUNT. | |
102 | */ | |
103 | int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr, | |
104 | unsigned int count) | |
105 | { | |
106 | int r; | |
107 | int i; | |
108 | zd_addr_t *a16 = (zd_addr_t *)NULL; | |
109 | u16 *v16; | |
110 | unsigned int count16; | |
111 | ||
112 | if (count > USB_MAX_IOREAD32_COUNT) | |
113 | return -EINVAL; | |
114 | ||
115 | /* Allocate a single memory block for values and addresses. */ | |
116 | count16 = 2*count; | |
44956855 | 117 | a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)), |
35c3404e | 118 | GFP_KERNEL); |
e85d0918 DD |
119 | if (!a16) { |
120 | dev_dbg_f(zd_chip_dev(chip), | |
121 | "error ENOMEM in allocation of a16\n"); | |
122 | r = -ENOMEM; | |
123 | goto out; | |
124 | } | |
125 | v16 = (u16 *)(a16 + count16); | |
126 | ||
127 | for (i = 0; i < count; i++) { | |
128 | int j = 2*i; | |
129 | /* We read the high word always first. */ | |
0ce34bc8 | 130 | a16[j] = inc_addr(addr[i]); |
e85d0918 DD |
131 | a16[j+1] = addr[i]; |
132 | } | |
133 | ||
134 | r = zd_ioread16v_locked(chip, v16, a16, count16); | |
135 | if (r) { | |
136 | dev_dbg_f(zd_chip_dev(chip), | |
137 | "error: zd_ioread16v_locked. Error number %d\n", r); | |
138 | goto out; | |
139 | } | |
140 | ||
141 | for (i = 0; i < count; i++) { | |
142 | int j = 2*i; | |
143 | values[i] = (v16[j] << 16) | v16[j+1]; | |
144 | } | |
145 | ||
146 | out: | |
147 | kfree((void *)a16); | |
148 | return r; | |
149 | } | |
150 | ||
151 | int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
152 | unsigned int count) | |
153 | { | |
154 | int i, j, r; | |
155 | struct zd_ioreq16 *ioreqs16; | |
156 | unsigned int count16; | |
157 | ||
158 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
159 | ||
160 | if (count == 0) | |
161 | return 0; | |
162 | if (count > USB_MAX_IOWRITE32_COUNT) | |
163 | return -EINVAL; | |
164 | ||
165 | /* Allocate a single memory block for values and addresses. */ | |
166 | count16 = 2*count; | |
35c3404e | 167 | ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL); |
e85d0918 DD |
168 | if (!ioreqs16) { |
169 | r = -ENOMEM; | |
170 | dev_dbg_f(zd_chip_dev(chip), | |
171 | "error %d in ioreqs16 allocation\n", r); | |
172 | goto out; | |
173 | } | |
174 | ||
175 | for (i = 0; i < count; i++) { | |
176 | j = 2*i; | |
177 | /* We write the high word always first. */ | |
178 | ioreqs16[j].value = ioreqs[i].value >> 16; | |
0ce34bc8 | 179 | ioreqs16[j].addr = inc_addr(ioreqs[i].addr); |
e85d0918 DD |
180 | ioreqs16[j+1].value = ioreqs[i].value; |
181 | ioreqs16[j+1].addr = ioreqs[i].addr; | |
182 | } | |
183 | ||
184 | r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16); | |
185 | #ifdef DEBUG | |
186 | if (r) { | |
187 | dev_dbg_f(zd_chip_dev(chip), | |
188 | "error %d in zd_usb_write16v\n", r); | |
189 | } | |
190 | #endif /* DEBUG */ | |
191 | out: | |
192 | kfree(ioreqs16); | |
193 | return r; | |
194 | } | |
195 | ||
196 | int zd_iowrite16a_locked(struct zd_chip *chip, | |
197 | const struct zd_ioreq16 *ioreqs, unsigned int count) | |
198 | { | |
199 | int r; | |
200 | unsigned int i, j, t, max; | |
201 | ||
202 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
203 | for (i = 0; i < count; i += j + t) { | |
204 | t = 0; | |
205 | max = count-i; | |
206 | if (max > USB_MAX_IOWRITE16_COUNT) | |
207 | max = USB_MAX_IOWRITE16_COUNT; | |
208 | for (j = 0; j < max; j++) { | |
209 | if (!ioreqs[i+j].addr) { | |
210 | t = 1; | |
211 | break; | |
212 | } | |
213 | } | |
214 | ||
215 | r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j); | |
216 | if (r) { | |
217 | dev_dbg_f(zd_chip_dev(chip), | |
218 | "error zd_usb_iowrite16v. Error number %d\n", | |
219 | r); | |
220 | return r; | |
221 | } | |
222 | } | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | /* Writes a variable number of 32 bit registers. The functions will split | |
228 | * that in several USB requests. A split can be forced by inserting an IO | |
229 | * request with an zero address field. | |
230 | */ | |
231 | int zd_iowrite32a_locked(struct zd_chip *chip, | |
232 | const struct zd_ioreq32 *ioreqs, unsigned int count) | |
233 | { | |
234 | int r; | |
235 | unsigned int i, j, t, max; | |
236 | ||
237 | for (i = 0; i < count; i += j + t) { | |
238 | t = 0; | |
239 | max = count-i; | |
240 | if (max > USB_MAX_IOWRITE32_COUNT) | |
241 | max = USB_MAX_IOWRITE32_COUNT; | |
242 | for (j = 0; j < max; j++) { | |
243 | if (!ioreqs[i+j].addr) { | |
244 | t = 1; | |
245 | break; | |
246 | } | |
247 | } | |
248 | ||
249 | r = _zd_iowrite32v_locked(chip, &ioreqs[i], j); | |
250 | if (r) { | |
251 | dev_dbg_f(zd_chip_dev(chip), | |
252 | "error _zd_iowrite32v_locked." | |
253 | " Error number %d\n", r); | |
254 | return r; | |
255 | } | |
256 | } | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value) | |
262 | { | |
263 | int r; | |
264 | ||
e85d0918 DD |
265 | mutex_lock(&chip->mutex); |
266 | r = zd_ioread16_locked(chip, value, addr); | |
267 | mutex_unlock(&chip->mutex); | |
268 | return r; | |
269 | } | |
270 | ||
271 | int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value) | |
272 | { | |
273 | int r; | |
274 | ||
e85d0918 DD |
275 | mutex_lock(&chip->mutex); |
276 | r = zd_ioread32_locked(chip, value, addr); | |
277 | mutex_unlock(&chip->mutex); | |
278 | return r; | |
279 | } | |
280 | ||
281 | int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value) | |
282 | { | |
283 | int r; | |
284 | ||
e85d0918 DD |
285 | mutex_lock(&chip->mutex); |
286 | r = zd_iowrite16_locked(chip, value, addr); | |
287 | mutex_unlock(&chip->mutex); | |
288 | return r; | |
289 | } | |
290 | ||
291 | int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value) | |
292 | { | |
293 | int r; | |
294 | ||
e85d0918 DD |
295 | mutex_lock(&chip->mutex); |
296 | r = zd_iowrite32_locked(chip, value, addr); | |
297 | mutex_unlock(&chip->mutex); | |
298 | return r; | |
299 | } | |
300 | ||
301 | int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, | |
302 | u32 *values, unsigned int count) | |
303 | { | |
304 | int r; | |
305 | ||
e85d0918 DD |
306 | mutex_lock(&chip->mutex); |
307 | r = zd_ioread32v_locked(chip, values, addresses, count); | |
308 | mutex_unlock(&chip->mutex); | |
309 | return r; | |
310 | } | |
311 | ||
312 | int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
313 | unsigned int count) | |
314 | { | |
315 | int r; | |
316 | ||
e85d0918 DD |
317 | mutex_lock(&chip->mutex); |
318 | r = zd_iowrite32a_locked(chip, ioreqs, count); | |
319 | mutex_unlock(&chip->mutex); | |
320 | return r; | |
321 | } | |
322 | ||
323 | static int read_pod(struct zd_chip *chip, u8 *rf_type) | |
324 | { | |
325 | int r; | |
326 | u32 value; | |
327 | ||
328 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
329 | r = zd_ioread32_locked(chip, &value, E2P_POD); | |
330 | if (r) | |
331 | goto error; | |
332 | dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value); | |
333 | ||
334 | /* FIXME: AL2230 handling (Bit 7 in POD) */ | |
335 | *rf_type = value & 0x0f; | |
336 | chip->pa_type = (value >> 16) & 0x0f; | |
337 | chip->patch_cck_gain = (value >> 8) & 0x1; | |
338 | chip->patch_cr157 = (value >> 13) & 0x1; | |
339 | chip->patch_6m_band_edge = (value >> 21) & 0x1; | |
20fe2176 | 340 | chip->new_phy_layout = (value >> 31) & 0x1; |
ae6ead46 | 341 | chip->al2230s_bit = (value >> 7) & 0x1; |
583afd1e UK |
342 | chip->link_led = ((value >> 4) & 1) ? LED1 : LED2; |
343 | chip->supports_tx_led = 1; | |
344 | if (value & (1 << 24)) { /* LED scenario */ | |
345 | if (value & (1 << 29)) | |
346 | chip->supports_tx_led = 0; | |
347 | } | |
e85d0918 DD |
348 | |
349 | dev_dbg_f(zd_chip_dev(chip), | |
350 | "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d " | |
583afd1e | 351 | "patch 6M %d new PHY %d link LED%d tx led %d\n", |
e85d0918 DD |
352 | zd_rf_name(*rf_type), *rf_type, |
353 | chip->pa_type, chip->patch_cck_gain, | |
583afd1e UK |
354 | chip->patch_cr157, chip->patch_6m_band_edge, |
355 | chip->new_phy_layout, | |
356 | chip->link_led == LED1 ? 1 : 2, | |
357 | chip->supports_tx_led); | |
e85d0918 DD |
358 | return 0; |
359 | error: | |
360 | *rf_type = 0; | |
361 | chip->pa_type = 0; | |
362 | chip->patch_cck_gain = 0; | |
363 | chip->patch_cr157 = 0; | |
364 | chip->patch_6m_band_edge = 0; | |
20fe2176 | 365 | chip->new_phy_layout = 0; |
e85d0918 DD |
366 | return r; |
367 | } | |
368 | ||
369 | static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr, | |
370 | const zd_addr_t *addr) | |
371 | { | |
372 | int r; | |
373 | u32 parts[2]; | |
374 | ||
375 | r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2); | |
376 | if (r) { | |
377 | dev_dbg_f(zd_chip_dev(chip), | |
378 | "error: couldn't read e2p macs. Error number %d\n", r); | |
379 | return r; | |
380 | } | |
381 | ||
382 | mac_addr[0] = parts[0]; | |
383 | mac_addr[1] = parts[0] >> 8; | |
384 | mac_addr[2] = parts[0] >> 16; | |
385 | mac_addr[3] = parts[0] >> 24; | |
386 | mac_addr[4] = parts[1]; | |
387 | mac_addr[5] = parts[1] >> 8; | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
392 | static int read_e2p_mac_addr(struct zd_chip *chip) | |
393 | { | |
394 | static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 }; | |
395 | ||
396 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
397 | return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr); | |
398 | } | |
399 | ||
400 | /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and | |
401 | * CR_MAC_ADDR_P2 must be overwritten | |
402 | */ | |
403 | void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr) | |
404 | { | |
405 | mutex_lock(&chip->mutex); | |
406 | memcpy(mac_addr, chip->e2p_mac, ETH_ALEN); | |
407 | mutex_unlock(&chip->mutex); | |
408 | } | |
409 | ||
410 | static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr) | |
411 | { | |
412 | static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 }; | |
413 | return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr); | |
414 | } | |
415 | ||
416 | int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr) | |
417 | { | |
418 | int r; | |
419 | ||
420 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
421 | mutex_lock(&chip->mutex); | |
422 | r = read_mac_addr(chip, mac_addr); | |
423 | mutex_unlock(&chip->mutex); | |
424 | return r; | |
425 | } | |
426 | ||
427 | int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr) | |
428 | { | |
429 | int r; | |
430 | struct zd_ioreq32 reqs[2] = { | |
431 | [0] = { .addr = CR_MAC_ADDR_P1 }, | |
432 | [1] = { .addr = CR_MAC_ADDR_P2 }, | |
433 | }; | |
434 | ||
435 | reqs[0].value = (mac_addr[3] << 24) | |
436 | | (mac_addr[2] << 16) | |
437 | | (mac_addr[1] << 8) | |
438 | | mac_addr[0]; | |
439 | reqs[1].value = (mac_addr[5] << 8) | |
440 | | mac_addr[4]; | |
441 | ||
442 | dev_dbg_f(zd_chip_dev(chip), | |
443 | "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr)); | |
444 | ||
445 | mutex_lock(&chip->mutex); | |
446 | r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); | |
447 | #ifdef DEBUG | |
448 | { | |
449 | u8 tmp[ETH_ALEN]; | |
450 | read_mac_addr(chip, tmp); | |
451 | } | |
452 | #endif /* DEBUG */ | |
453 | mutex_unlock(&chip->mutex); | |
454 | return r; | |
455 | } | |
456 | ||
457 | int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain) | |
458 | { | |
459 | int r; | |
460 | u32 value; | |
461 | ||
462 | mutex_lock(&chip->mutex); | |
463 | r = zd_ioread32_locked(chip, &value, E2P_SUBID); | |
464 | mutex_unlock(&chip->mutex); | |
465 | if (r) | |
466 | return r; | |
467 | ||
468 | *regdomain = value >> 16; | |
469 | dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain); | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
474 | static int read_values(struct zd_chip *chip, u8 *values, size_t count, | |
475 | zd_addr_t e2p_addr, u32 guard) | |
476 | { | |
477 | int r; | |
478 | int i; | |
479 | u32 v; | |
480 | ||
481 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
482 | for (i = 0;;) { | |
0ce34bc8 DD |
483 | r = zd_ioread32_locked(chip, &v, |
484 | (zd_addr_t)((u16)e2p_addr+i/2)); | |
e85d0918 DD |
485 | if (r) |
486 | return r; | |
487 | v -= guard; | |
488 | if (i+4 < count) { | |
489 | values[i++] = v; | |
490 | values[i++] = v >> 8; | |
491 | values[i++] = v >> 16; | |
492 | values[i++] = v >> 24; | |
493 | continue; | |
494 | } | |
495 | for (;i < count; i++) | |
496 | values[i] = v >> (8*(i%3)); | |
497 | return 0; | |
498 | } | |
499 | } | |
500 | ||
501 | static int read_pwr_cal_values(struct zd_chip *chip) | |
502 | { | |
503 | return read_values(chip, chip->pwr_cal_values, | |
504 | E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1, | |
505 | 0); | |
506 | } | |
507 | ||
508 | static int read_pwr_int_values(struct zd_chip *chip) | |
509 | { | |
510 | return read_values(chip, chip->pwr_int_values, | |
511 | E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1, | |
512 | E2P_PWR_INT_GUARD); | |
513 | } | |
514 | ||
515 | static int read_ofdm_cal_values(struct zd_chip *chip) | |
516 | { | |
517 | int r; | |
518 | int i; | |
519 | static const zd_addr_t addresses[] = { | |
520 | E2P_36M_CAL_VALUE1, | |
521 | E2P_48M_CAL_VALUE1, | |
522 | E2P_54M_CAL_VALUE1, | |
523 | }; | |
524 | ||
525 | for (i = 0; i < 3; i++) { | |
526 | r = read_values(chip, chip->ofdm_cal_values[i], | |
527 | E2P_CHANNEL_COUNT, addresses[i], 0); | |
528 | if (r) | |
529 | return r; | |
530 | } | |
531 | return 0; | |
532 | } | |
533 | ||
534 | static int read_cal_int_tables(struct zd_chip *chip) | |
535 | { | |
536 | int r; | |
537 | ||
538 | r = read_pwr_cal_values(chip); | |
539 | if (r) | |
540 | return r; | |
541 | r = read_pwr_int_values(chip); | |
542 | if (r) | |
543 | return r; | |
544 | r = read_ofdm_cal_values(chip); | |
545 | if (r) | |
546 | return r; | |
547 | return 0; | |
548 | } | |
549 | ||
550 | /* phy means physical registers */ | |
551 | int zd_chip_lock_phy_regs(struct zd_chip *chip) | |
552 | { | |
553 | int r; | |
554 | u32 tmp; | |
555 | ||
556 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
557 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); | |
558 | if (r) { | |
559 | dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r); | |
560 | return r; | |
561 | } | |
562 | ||
563 | dev_dbg_f(zd_chip_dev(chip), | |
564 | "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS); | |
565 | tmp &= ~UNLOCK_PHY_REGS; | |
566 | ||
567 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); | |
568 | if (r) | |
569 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); | |
570 | return r; | |
571 | } | |
572 | ||
573 | int zd_chip_unlock_phy_regs(struct zd_chip *chip) | |
574 | { | |
575 | int r; | |
576 | u32 tmp; | |
577 | ||
578 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
579 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); | |
580 | if (r) { | |
581 | dev_err(zd_chip_dev(chip), | |
582 | "error ioread32(CR_REG1): %d\n", r); | |
583 | return r; | |
584 | } | |
585 | ||
586 | dev_dbg_f(zd_chip_dev(chip), | |
587 | "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS); | |
588 | tmp |= UNLOCK_PHY_REGS; | |
589 | ||
590 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); | |
591 | if (r) | |
592 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); | |
593 | return r; | |
594 | } | |
595 | ||
92b3e2e9 | 596 | /* CR157 can be optionally patched by the EEPROM for original ZD1211 */ |
e85d0918 DD |
597 | static int patch_cr157(struct zd_chip *chip) |
598 | { | |
599 | int r; | |
92b3e2e9 | 600 | u16 value; |
e85d0918 DD |
601 | |
602 | if (!chip->patch_cr157) | |
603 | return 0; | |
604 | ||
92b3e2e9 | 605 | r = zd_ioread16_locked(chip, &value, E2P_PHY_REG); |
e85d0918 DD |
606 | if (r) |
607 | return r; | |
608 | ||
609 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8); | |
610 | return zd_iowrite32_locked(chip, value >> 8, CR157); | |
611 | } | |
612 | ||
613 | /* | |
614 | * 6M band edge can be optionally overwritten for certain RF's | |
615 | * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge | |
616 | * bit (for AL2230, AL2230S) | |
617 | */ | |
72018b22 DD |
618 | static int patch_6m_band_edge(struct zd_chip *chip, u8 channel) |
619 | { | |
620 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
621 | if (!chip->patch_6m_band_edge) | |
622 | return 0; | |
623 | ||
624 | return zd_rf_patch_6m_band_edge(&chip->rf, channel); | |
625 | } | |
626 | ||
627 | /* Generic implementation of 6M band edge patching, used by most RFs via | |
628 | * zd_rf_generic_patch_6m() */ | |
629 | int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel) | |
e85d0918 DD |
630 | { |
631 | struct zd_ioreq16 ioreqs[] = { | |
632 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, | |
633 | { CR47, 0x1e }, | |
634 | }; | |
635 | ||
e85d0918 DD |
636 | /* FIXME: Channel 11 is not the edge for all regulatory domains. */ |
637 | if (channel == 1 || channel == 11) | |
638 | ioreqs[0].value = 0x12; | |
639 | ||
640 | dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel); | |
641 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
642 | } | |
643 | ||
644 | static int zd1211_hw_reset_phy(struct zd_chip *chip) | |
645 | { | |
646 | static const struct zd_ioreq16 ioreqs[] = { | |
647 | { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 }, | |
648 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 }, | |
649 | { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f }, | |
650 | { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d }, | |
651 | { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a }, | |
652 | { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c }, | |
653 | { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 }, | |
654 | { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 }, | |
655 | { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b }, | |
656 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, | |
657 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, | |
658 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, | |
659 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, | |
660 | { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff }, | |
661 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, | |
662 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, | |
663 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, | |
664 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, | |
665 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, | |
666 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, | |
667 | { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 }, | |
668 | { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 }, | |
669 | { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 }, | |
670 | { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 }, | |
671 | { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 }, | |
672 | { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff }, | |
673 | { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 }, | |
674 | { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 }, | |
675 | { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 }, | |
676 | { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a }, | |
677 | { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 }, | |
678 | { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e }, | |
679 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, | |
680 | { }, | |
681 | { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 }, | |
682 | { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 }, | |
683 | { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 }, | |
684 | { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 }, | |
685 | { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C }, | |
686 | { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 }, | |
687 | { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 }, | |
688 | { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 }, | |
689 | { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 }, | |
690 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, | |
691 | { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 }, | |
692 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, | |
693 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, | |
694 | { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f }, | |
dc536a70 DD |
695 | { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 }, |
696 | { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C }, | |
697 | { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 }, | |
698 | { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 }, | |
699 | { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c }, | |
700 | { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 }, | |
701 | { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe }, | |
702 | { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa }, | |
703 | { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe }, | |
704 | { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba }, | |
705 | { CR170, 0xba }, { CR171, 0xba }, | |
e85d0918 DD |
706 | /* Note: CR204 must lead the CR203 */ |
707 | { CR204, 0x7d }, | |
708 | { }, | |
709 | { CR203, 0x30 }, | |
710 | }; | |
711 | ||
712 | int r, t; | |
713 | ||
714 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
715 | ||
716 | r = zd_chip_lock_phy_regs(chip); | |
717 | if (r) | |
718 | goto out; | |
719 | ||
720 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
721 | if (r) | |
722 | goto unlock; | |
723 | ||
724 | r = patch_cr157(chip); | |
725 | unlock: | |
726 | t = zd_chip_unlock_phy_regs(chip); | |
727 | if (t && !r) | |
728 | r = t; | |
729 | out: | |
730 | return r; | |
731 | } | |
732 | ||
733 | static int zd1211b_hw_reset_phy(struct zd_chip *chip) | |
734 | { | |
735 | static const struct zd_ioreq16 ioreqs[] = { | |
736 | { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 }, | |
737 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 }, | |
738 | { CR10, 0x81 }, | |
739 | /* power control { { CR11, 1 << 6 }, */ | |
740 | { CR11, 0x00 }, | |
741 | { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 }, | |
742 | { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e }, | |
743 | { CR18, 0x0a }, { CR19, 0x48 }, | |
744 | { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */ | |
745 | { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 }, | |
746 | { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 }, | |
747 | { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 }, | |
fe7215ca | 748 | { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */ |
e85d0918 DD |
749 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, |
750 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, | |
751 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, | |
752 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, | |
753 | { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff }, | |
754 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, | |
755 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, | |
756 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, | |
757 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, | |
758 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, | |
759 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, | |
760 | { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 }, | |
761 | { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 }, | |
762 | { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 }, | |
763 | { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 }, | |
764 | { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 }, | |
765 | { CR94, 0x01 }, | |
766 | { CR95, 0x20 }, /* ZD1211B */ | |
767 | { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 }, | |
768 | { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 }, | |
769 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, | |
770 | { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 }, | |
771 | { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 }, | |
772 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, | |
773 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, | |
774 | { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e }, | |
775 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, | |
776 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, | |
777 | { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 }, | |
778 | { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 }, | |
779 | { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c }, | |
780 | { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 }, | |
781 | { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */ | |
782 | { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */ | |
783 | { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe }, | |
784 | { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa }, | |
785 | { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe }, | |
786 | { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba }, | |
787 | { CR170, 0xba }, { CR171, 0xba }, | |
788 | /* Note: CR204 must lead the CR203 */ | |
789 | { CR204, 0x7d }, | |
790 | {}, | |
791 | { CR203, 0x30 }, | |
792 | }; | |
793 | ||
794 | int r, t; | |
795 | ||
796 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
797 | ||
798 | r = zd_chip_lock_phy_regs(chip); | |
799 | if (r) | |
800 | goto out; | |
801 | ||
802 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
e85d0918 DD |
803 | t = zd_chip_unlock_phy_regs(chip); |
804 | if (t && !r) | |
805 | r = t; | |
806 | out: | |
807 | return r; | |
808 | } | |
809 | ||
810 | static int hw_reset_phy(struct zd_chip *chip) | |
811 | { | |
812 | return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) : | |
813 | zd1211_hw_reset_phy(chip); | |
814 | } | |
815 | ||
816 | static int zd1211_hw_init_hmac(struct zd_chip *chip) | |
817 | { | |
818 | static const struct zd_ioreq32 ioreqs[] = { | |
e85d0918 | 819 | { CR_ZD1211_RETRY_MAX, 0x2 }, |
e85d0918 | 820 | { CR_RX_THRESHOLD, 0x000c0640 }, |
e85d0918 DD |
821 | }; |
822 | ||
e85d0918 DD |
823 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
824 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
34c44912 | 825 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
e85d0918 DD |
826 | } |
827 | ||
828 | static int zd1211b_hw_init_hmac(struct zd_chip *chip) | |
829 | { | |
830 | static const struct zd_ioreq32 ioreqs[] = { | |
e85d0918 DD |
831 | { CR_ZD1211B_RETRY_MAX, 0x02020202 }, |
832 | { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f }, | |
833 | { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f }, | |
834 | { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f }, | |
835 | { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f }, | |
836 | { CR_ZD1211B_AIFS_CTL1, 0x00280028 }, | |
837 | { CR_ZD1211B_AIFS_CTL2, 0x008C003C }, | |
838 | { CR_ZD1211B_TXOP, 0x01800824 }, | |
34c44912 DD |
839 | { CR_RX_THRESHOLD, 0x000c0eff, }, |
840 | }; | |
841 | ||
842 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
843 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
844 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
845 | } | |
846 | ||
847 | static int hw_init_hmac(struct zd_chip *chip) | |
848 | { | |
849 | int r; | |
850 | static const struct zd_ioreq32 ioreqs[] = { | |
851 | { CR_ACK_TIMEOUT_EXT, 0x20 }, | |
852 | { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, | |
e85d0918 | 853 | { CR_SNIFFER_ON, 0 }, |
fde627b5 | 854 | { CR_RX_FILTER, STA_RX_FILTER }, |
e85d0918 DD |
855 | { CR_GROUP_HASH_P1, 0x00 }, |
856 | { CR_GROUP_HASH_P2, 0x80000000 }, | |
857 | { CR_REG1, 0xa4 }, | |
858 | { CR_ADDA_PWR_DWN, 0x7f }, | |
859 | { CR_BCN_PLCP_CFG, 0x00f00401 }, | |
860 | { CR_PHY_DELAY, 0x00 }, | |
861 | { CR_ACK_TIMEOUT_EXT, 0x80 }, | |
862 | { CR_ADDA_PWR_DWN, 0x00 }, | |
863 | { CR_ACK_TIME_80211, 0x100 }, | |
e85d0918 DD |
864 | { CR_RX_PE_DELAY, 0x70 }, |
865 | { CR_PS_CTRL, 0x10000000 }, | |
866 | { CR_RTS_CTS_RATE, 0x02030203 }, | |
e85d0918 DD |
867 | { CR_AFTER_PNP, 0x1 }, |
868 | { CR_WEP_PROTECT, 0x114 }, | |
34c44912 | 869 | { CR_IFS_VALUE, IFS_VALUE_DEFAULT }, |
e85d0918 DD |
870 | }; |
871 | ||
e85d0918 DD |
872 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
873 | r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
34c44912 DD |
874 | if (r) |
875 | return r; | |
e85d0918 | 876 | |
e85d0918 DD |
877 | return chip->is_zd1211b ? |
878 | zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip); | |
879 | } | |
880 | ||
881 | struct aw_pt_bi { | |
882 | u32 atim_wnd_period; | |
883 | u32 pre_tbtt; | |
884 | u32 beacon_interval; | |
885 | }; | |
886 | ||
887 | static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) | |
888 | { | |
889 | int r; | |
890 | static const zd_addr_t aw_pt_bi_addr[] = | |
891 | { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL }; | |
892 | u32 values[3]; | |
893 | ||
894 | r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr, | |
895 | ARRAY_SIZE(aw_pt_bi_addr)); | |
896 | if (r) { | |
897 | memset(s, 0, sizeof(*s)); | |
898 | return r; | |
899 | } | |
900 | ||
901 | s->atim_wnd_period = values[0]; | |
902 | s->pre_tbtt = values[1]; | |
903 | s->beacon_interval = values[2]; | |
904 | dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n", | |
905 | s->atim_wnd_period, s->pre_tbtt, s->beacon_interval); | |
906 | return 0; | |
907 | } | |
908 | ||
909 | static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) | |
910 | { | |
911 | struct zd_ioreq32 reqs[3]; | |
912 | ||
913 | if (s->beacon_interval <= 5) | |
914 | s->beacon_interval = 5; | |
915 | if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval) | |
916 | s->pre_tbtt = s->beacon_interval - 1; | |
917 | if (s->atim_wnd_period >= s->pre_tbtt) | |
918 | s->atim_wnd_period = s->pre_tbtt - 1; | |
919 | ||
920 | reqs[0].addr = CR_ATIM_WND_PERIOD; | |
921 | reqs[0].value = s->atim_wnd_period; | |
922 | reqs[1].addr = CR_PRE_TBTT; | |
923 | reqs[1].value = s->pre_tbtt; | |
924 | reqs[2].addr = CR_BCN_INTERVAL; | |
925 | reqs[2].value = s->beacon_interval; | |
926 | ||
927 | dev_dbg_f(zd_chip_dev(chip), | |
928 | "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt, | |
929 | s->beacon_interval); | |
930 | return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); | |
931 | } | |
932 | ||
933 | ||
934 | static int set_beacon_interval(struct zd_chip *chip, u32 interval) | |
935 | { | |
936 | int r; | |
937 | struct aw_pt_bi s; | |
938 | ||
939 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
940 | r = get_aw_pt_bi(chip, &s); | |
941 | if (r) | |
942 | return r; | |
943 | s.beacon_interval = interval; | |
944 | return set_aw_pt_bi(chip, &s); | |
945 | } | |
946 | ||
947 | int zd_set_beacon_interval(struct zd_chip *chip, u32 interval) | |
948 | { | |
949 | int r; | |
950 | ||
951 | mutex_lock(&chip->mutex); | |
952 | r = set_beacon_interval(chip, interval); | |
953 | mutex_unlock(&chip->mutex); | |
954 | return r; | |
955 | } | |
956 | ||
957 | static int hw_init(struct zd_chip *chip) | |
958 | { | |
959 | int r; | |
960 | ||
961 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
962 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
963 | r = hw_reset_phy(chip); | |
964 | if (r) | |
965 | return r; | |
966 | ||
967 | r = hw_init_hmac(chip); | |
968 | if (r) | |
969 | return r; | |
98227a90 | 970 | |
98227a90 | 971 | return set_beacon_interval(chip, 100); |
e85d0918 DD |
972 | } |
973 | ||
0ce34bc8 DD |
974 | static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset) |
975 | { | |
976 | return (zd_addr_t)((u16)chip->fw_regs_base + offset); | |
977 | } | |
978 | ||
e85d0918 DD |
979 | #ifdef DEBUG |
980 | static int dump_cr(struct zd_chip *chip, const zd_addr_t addr, | |
981 | const char *addr_string) | |
982 | { | |
983 | int r; | |
984 | u32 value; | |
985 | ||
986 | r = zd_ioread32_locked(chip, &value, addr); | |
987 | if (r) { | |
988 | dev_dbg_f(zd_chip_dev(chip), | |
989 | "error reading %s. Error number %d\n", addr_string, r); | |
990 | return r; | |
991 | } | |
992 | ||
993 | dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n", | |
994 | addr_string, (unsigned int)value); | |
995 | return 0; | |
996 | } | |
997 | ||
998 | static int test_init(struct zd_chip *chip) | |
999 | { | |
1000 | int r; | |
1001 | ||
1002 | r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP"); | |
1003 | if (r) | |
1004 | return r; | |
1005 | r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN"); | |
1006 | if (r) | |
1007 | return r; | |
1008 | return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT"); | |
1009 | } | |
1010 | ||
1011 | static void dump_fw_registers(struct zd_chip *chip) | |
1012 | { | |
0ce34bc8 DD |
1013 | const zd_addr_t addr[4] = { |
1014 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER), | |
1015 | fw_reg_addr(chip, FW_REG_USB_SPEED), | |
1016 | fw_reg_addr(chip, FW_REG_FIX_TX_RATE), | |
1017 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), | |
e85d0918 DD |
1018 | }; |
1019 | ||
1020 | int r; | |
1021 | u16 values[4]; | |
1022 | ||
1023 | r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr, | |
1024 | ARRAY_SIZE(addr)); | |
1025 | if (r) { | |
1026 | dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n", | |
1027 | r); | |
1028 | return; | |
1029 | } | |
1030 | ||
1031 | dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]); | |
1032 | dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]); | |
1033 | dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]); | |
1034 | dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]); | |
1035 | } | |
1036 | #endif /* DEBUG */ | |
1037 | ||
1038 | static int print_fw_version(struct zd_chip *chip) | |
1039 | { | |
1040 | int r; | |
1041 | u16 version; | |
1042 | ||
0ce34bc8 DD |
1043 | r = zd_ioread16_locked(chip, &version, |
1044 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER)); | |
e85d0918 DD |
1045 | if (r) |
1046 | return r; | |
1047 | ||
1048 | dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version); | |
1049 | return 0; | |
1050 | } | |
1051 | ||
1052 | static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std) | |
1053 | { | |
1054 | u32 rates; | |
1055 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1056 | /* This sets the mandatory rates, which only depend from the standard | |
1057 | * that the device is supporting. Until further notice we should try | |
1058 | * to support 802.11g also for full speed USB. | |
1059 | */ | |
1060 | switch (std) { | |
1061 | case IEEE80211B: | |
1062 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M; | |
1063 | break; | |
1064 | case IEEE80211G: | |
1065 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M| | |
1066 | CR_RATE_6M|CR_RATE_12M|CR_RATE_24M; | |
1067 | break; | |
1068 | default: | |
1069 | return -EINVAL; | |
1070 | } | |
1071 | return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL); | |
1072 | } | |
1073 | ||
b1382ede DD |
1074 | int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, |
1075 | u8 rts_rate, int preamble) | |
1076 | { | |
1077 | int rts_mod = ZD_RX_CCK; | |
1078 | u32 value = 0; | |
1079 | ||
1080 | /* Modulation bit */ | |
1081 | if (ZD_CS_TYPE(rts_rate) == ZD_CS_OFDM) | |
1082 | rts_mod = ZD_RX_OFDM; | |
1083 | ||
1084 | dev_dbg_f(zd_chip_dev(chip), "rts_rate=%x preamble=%x\n", | |
1085 | rts_rate, preamble); | |
1086 | ||
1087 | value |= rts_rate << RTSCTS_SH_RTS_RATE; | |
1088 | value |= rts_mod << RTSCTS_SH_RTS_MOD_TYPE; | |
1089 | value |= preamble << RTSCTS_SH_RTS_PMB_TYPE; | |
1090 | value |= preamble << RTSCTS_SH_CTS_PMB_TYPE; | |
1091 | ||
1092 | /* We always send 11M self-CTS messages, like the vendor driver. */ | |
1093 | value |= ZD_CCK_RATE_11M << RTSCTS_SH_CTS_RATE; | |
1094 | value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE; | |
1095 | ||
1096 | return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE); | |
1097 | } | |
1098 | ||
e85d0918 DD |
1099 | int zd_chip_enable_hwint(struct zd_chip *chip) |
1100 | { | |
1101 | int r; | |
1102 | ||
1103 | mutex_lock(&chip->mutex); | |
1104 | r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT); | |
1105 | mutex_unlock(&chip->mutex); | |
1106 | return r; | |
1107 | } | |
1108 | ||
1109 | static int disable_hwint(struct zd_chip *chip) | |
1110 | { | |
1111 | return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT); | |
1112 | } | |
1113 | ||
1114 | int zd_chip_disable_hwint(struct zd_chip *chip) | |
1115 | { | |
1116 | int r; | |
1117 | ||
1118 | mutex_lock(&chip->mutex); | |
1119 | r = disable_hwint(chip); | |
1120 | mutex_unlock(&chip->mutex); | |
1121 | return r; | |
1122 | } | |
1123 | ||
0ce34bc8 DD |
1124 | static int read_fw_regs_offset(struct zd_chip *chip) |
1125 | { | |
1126 | int r; | |
1127 | ||
1128 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1129 | r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base, | |
1130 | FWRAW_REGS_ADDR); | |
1131 | if (r) | |
1132 | return r; | |
1133 | dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n", | |
1134 | (u16)chip->fw_regs_base); | |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | ||
e85d0918 DD |
1140 | int zd_chip_init_hw(struct zd_chip *chip, u8 device_type) |
1141 | { | |
1142 | int r; | |
1143 | u8 rf_type; | |
1144 | ||
1145 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
1146 | ||
1147 | mutex_lock(&chip->mutex); | |
1148 | chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0; | |
1149 | ||
1150 | #ifdef DEBUG | |
1151 | r = test_init(chip); | |
1152 | if (r) | |
1153 | goto out; | |
1154 | #endif | |
1155 | r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP); | |
1156 | if (r) | |
1157 | goto out; | |
1158 | ||
0ce34bc8 | 1159 | r = read_fw_regs_offset(chip); |
e85d0918 DD |
1160 | if (r) |
1161 | goto out; | |
1162 | ||
1163 | /* GPI is always disabled, also in the other driver. | |
1164 | */ | |
1165 | r = zd_iowrite32_locked(chip, 0, CR_GPI_EN); | |
1166 | if (r) | |
1167 | goto out; | |
1168 | r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX); | |
1169 | if (r) | |
1170 | goto out; | |
1171 | /* Currently we support IEEE 802.11g for full and high speed USB. | |
1172 | * It might be discussed, whether we should suppport pure b mode for | |
1173 | * full speed USB. | |
1174 | */ | |
1175 | r = set_mandatory_rates(chip, IEEE80211G); | |
1176 | if (r) | |
1177 | goto out; | |
1178 | /* Disabling interrupts is certainly a smart thing here. | |
1179 | */ | |
1180 | r = disable_hwint(chip); | |
1181 | if (r) | |
1182 | goto out; | |
1183 | r = read_pod(chip, &rf_type); | |
1184 | if (r) | |
1185 | goto out; | |
1186 | r = hw_init(chip); | |
1187 | if (r) | |
1188 | goto out; | |
1189 | r = zd_rf_init_hw(&chip->rf, rf_type); | |
1190 | if (r) | |
1191 | goto out; | |
1192 | ||
1193 | r = print_fw_version(chip); | |
1194 | if (r) | |
1195 | goto out; | |
1196 | ||
1197 | #ifdef DEBUG | |
1198 | dump_fw_registers(chip); | |
1199 | r = test_init(chip); | |
1200 | if (r) | |
1201 | goto out; | |
1202 | #endif /* DEBUG */ | |
1203 | ||
1204 | r = read_e2p_mac_addr(chip); | |
1205 | if (r) | |
1206 | goto out; | |
1207 | ||
1208 | r = read_cal_int_tables(chip); | |
1209 | if (r) | |
1210 | goto out; | |
1211 | ||
1212 | print_id(chip); | |
1213 | out: | |
1214 | mutex_unlock(&chip->mutex); | |
1215 | return r; | |
1216 | } | |
1217 | ||
1218 | static int update_pwr_int(struct zd_chip *chip, u8 channel) | |
1219 | { | |
1220 | u8 value = chip->pwr_int_values[channel - 1]; | |
1221 | dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n", | |
1222 | channel, value); | |
cbb5e6bb | 1223 | return zd_iowrite16_locked(chip, value, CR31); |
e85d0918 DD |
1224 | } |
1225 | ||
1226 | static int update_pwr_cal(struct zd_chip *chip, u8 channel) | |
1227 | { | |
1228 | u8 value = chip->pwr_cal_values[channel-1]; | |
1229 | dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n", | |
1230 | channel, value); | |
cbb5e6bb | 1231 | return zd_iowrite16_locked(chip, value, CR68); |
e85d0918 DD |
1232 | } |
1233 | ||
1234 | static int update_ofdm_cal(struct zd_chip *chip, u8 channel) | |
1235 | { | |
cbb5e6bb | 1236 | struct zd_ioreq16 ioreqs[3]; |
e85d0918 DD |
1237 | |
1238 | ioreqs[0].addr = CR67; | |
1239 | ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1]; | |
1240 | ioreqs[1].addr = CR66; | |
1241 | ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1]; | |
1242 | ioreqs[2].addr = CR65; | |
1243 | ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1]; | |
1244 | ||
1245 | dev_dbg_f(zd_chip_dev(chip), | |
1246 | "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n", | |
1247 | channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value); | |
cbb5e6bb | 1248 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
e85d0918 DD |
1249 | } |
1250 | ||
1251 | static int update_channel_integration_and_calibration(struct zd_chip *chip, | |
1252 | u8 channel) | |
1253 | { | |
1254 | int r; | |
1255 | ||
9c8fc71d DD |
1256 | if (!zd_rf_should_update_pwr_int(&chip->rf)) |
1257 | return 0; | |
1258 | ||
e85d0918 DD |
1259 | r = update_pwr_int(chip, channel); |
1260 | if (r) | |
1261 | return r; | |
1262 | if (chip->is_zd1211b) { | |
cbb5e6bb | 1263 | static const struct zd_ioreq16 ioreqs[] = { |
e85d0918 DD |
1264 | { CR69, 0x28 }, |
1265 | {}, | |
1266 | { CR69, 0x2a }, | |
1267 | }; | |
1268 | ||
1269 | r = update_ofdm_cal(chip, channel); | |
1270 | if (r) | |
1271 | return r; | |
1272 | r = update_pwr_cal(chip, channel); | |
1273 | if (r) | |
1274 | return r; | |
cbb5e6bb | 1275 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
e85d0918 DD |
1276 | if (r) |
1277 | return r; | |
1278 | } | |
1279 | ||
1280 | return 0; | |
1281 | } | |
1282 | ||
1283 | /* The CCK baseband gain can be optionally patched by the EEPROM */ | |
1284 | static int patch_cck_gain(struct zd_chip *chip) | |
1285 | { | |
1286 | int r; | |
1287 | u32 value; | |
1288 | ||
aaf83d4f | 1289 | if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf)) |
e85d0918 DD |
1290 | return 0; |
1291 | ||
1292 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1293 | r = zd_ioread32_locked(chip, &value, E2P_PHY_REG); | |
1294 | if (r) | |
1295 | return r; | |
1296 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff); | |
cbb5e6bb | 1297 | return zd_iowrite16_locked(chip, value & 0xff, CR47); |
e85d0918 DD |
1298 | } |
1299 | ||
1300 | int zd_chip_set_channel(struct zd_chip *chip, u8 channel) | |
1301 | { | |
1302 | int r, t; | |
1303 | ||
1304 | mutex_lock(&chip->mutex); | |
1305 | r = zd_chip_lock_phy_regs(chip); | |
1306 | if (r) | |
1307 | goto out; | |
1308 | r = zd_rf_set_channel(&chip->rf, channel); | |
1309 | if (r) | |
1310 | goto unlock; | |
1311 | r = update_channel_integration_and_calibration(chip, channel); | |
1312 | if (r) | |
1313 | goto unlock; | |
1314 | r = patch_cck_gain(chip); | |
1315 | if (r) | |
1316 | goto unlock; | |
1317 | r = patch_6m_band_edge(chip, channel); | |
1318 | if (r) | |
1319 | goto unlock; | |
1320 | r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS); | |
1321 | unlock: | |
1322 | t = zd_chip_unlock_phy_regs(chip); | |
1323 | if (t && !r) | |
1324 | r = t; | |
1325 | out: | |
1326 | mutex_unlock(&chip->mutex); | |
1327 | return r; | |
1328 | } | |
1329 | ||
1330 | u8 zd_chip_get_channel(struct zd_chip *chip) | |
1331 | { | |
1332 | u8 channel; | |
1333 | ||
1334 | mutex_lock(&chip->mutex); | |
1335 | channel = chip->rf.channel; | |
1336 | mutex_unlock(&chip->mutex); | |
1337 | return channel; | |
1338 | } | |
1339 | ||
583afd1e | 1340 | int zd_chip_control_leds(struct zd_chip *chip, enum led_status status) |
e85d0918 | 1341 | { |
0ce34bc8 DD |
1342 | const zd_addr_t a[] = { |
1343 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), | |
583afd1e UK |
1344 | CR_LED, |
1345 | }; | |
e85d0918 | 1346 | |
583afd1e UK |
1347 | int r; |
1348 | u16 v[ARRAY_SIZE(a)]; | |
1349 | struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = { | |
0ce34bc8 | 1350 | [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) }, |
583afd1e UK |
1351 | [1] = { CR_LED }, |
1352 | }; | |
1353 | u16 other_led; | |
e85d0918 | 1354 | |
e85d0918 | 1355 | mutex_lock(&chip->mutex); |
583afd1e | 1356 | r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a)); |
e85d0918 | 1357 | if (r) |
583afd1e UK |
1358 | goto out; |
1359 | ||
1360 | other_led = chip->link_led == LED1 ? LED2 : LED1; | |
1361 | ||
e85d0918 | 1362 | switch (status) { |
e85d0918 | 1363 | case LED_OFF: |
583afd1e UK |
1364 | ioreqs[0].value = FW_LINK_OFF; |
1365 | ioreqs[1].value = v[1] & ~(LED1|LED2); | |
e85d0918 | 1366 | break; |
583afd1e UK |
1367 | case LED_SCANNING: |
1368 | ioreqs[0].value = FW_LINK_OFF; | |
1369 | ioreqs[1].value = v[1] & ~other_led; | |
1370 | if (get_seconds() % 3 == 0) { | |
1371 | ioreqs[1].value &= ~chip->link_led; | |
1372 | } else { | |
1373 | ioreqs[1].value |= chip->link_led; | |
1374 | } | |
e85d0918 | 1375 | break; |
583afd1e UK |
1376 | case LED_ASSOCIATED: |
1377 | ioreqs[0].value = FW_LINK_TX; | |
1378 | ioreqs[1].value = v[1] & ~other_led; | |
1379 | ioreqs[1].value |= chip->link_led; | |
e85d0918 DD |
1380 | break; |
1381 | default: | |
583afd1e | 1382 | r = -EINVAL; |
e85d0918 DD |
1383 | goto out; |
1384 | } | |
e85d0918 | 1385 | |
583afd1e UK |
1386 | if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) { |
1387 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
1388 | if (r) | |
e85d0918 | 1389 | goto out; |
e85d0918 | 1390 | } |
583afd1e | 1391 | r = 0; |
e85d0918 | 1392 | out: |
583afd1e | 1393 | mutex_unlock(&chip->mutex); |
e85d0918 DD |
1394 | return r; |
1395 | } | |
1396 | ||
b1382ede | 1397 | int zd_chip_set_basic_rates_locked(struct zd_chip *chip, u16 cr_rates) |
e85d0918 | 1398 | { |
b1382ede DD |
1399 | ZD_ASSERT((cr_rates & ~(CR_RATES_80211B | CR_RATES_80211G)) == 0); |
1400 | dev_dbg_f(zd_chip_dev(chip), "%x\n", cr_rates); | |
e85d0918 | 1401 | |
b1382ede | 1402 | return zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL); |
e85d0918 DD |
1403 | } |
1404 | ||
1405 | static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size) | |
1406 | { | |
1407 | static const u16 constants[] = { | |
1408 | 715, 655, 585, 540, 470, 410, 360, 315, | |
1409 | 270, 235, 205, 175, 150, 125, 105, 85, | |
1410 | 65, 50, 40, 25, 15 | |
1411 | }; | |
1412 | ||
1413 | int i; | |
1414 | u32 x; | |
1415 | ||
1416 | /* It seems that their quality parameter is somehow per signal | |
1417 | * and is now transferred per bit. | |
1418 | */ | |
1419 | switch (rate) { | |
1420 | case ZD_OFDM_RATE_6M: | |
1421 | case ZD_OFDM_RATE_12M: | |
1422 | case ZD_OFDM_RATE_24M: | |
1423 | size *= 2; | |
1424 | break; | |
1425 | case ZD_OFDM_RATE_9M: | |
1426 | case ZD_OFDM_RATE_18M: | |
1427 | case ZD_OFDM_RATE_36M: | |
1428 | case ZD_OFDM_RATE_54M: | |
1429 | size *= 4; | |
1430 | size /= 3; | |
1431 | break; | |
1432 | case ZD_OFDM_RATE_48M: | |
1433 | size *= 3; | |
1434 | size /= 2; | |
1435 | break; | |
1436 | default: | |
1437 | return -EINVAL; | |
1438 | } | |
1439 | ||
1440 | x = (10000 * status_quality)/size; | |
1441 | for (i = 0; i < ARRAY_SIZE(constants); i++) { | |
1442 | if (x > constants[i]) | |
1443 | break; | |
1444 | } | |
1445 | ||
db888aed UK |
1446 | switch (rate) { |
1447 | case ZD_OFDM_RATE_6M: | |
1448 | case ZD_OFDM_RATE_9M: | |
1449 | i += 3; | |
1450 | break; | |
1451 | case ZD_OFDM_RATE_12M: | |
1452 | case ZD_OFDM_RATE_18M: | |
1453 | i += 5; | |
1454 | break; | |
1455 | case ZD_OFDM_RATE_24M: | |
1456 | case ZD_OFDM_RATE_36M: | |
1457 | i += 9; | |
1458 | break; | |
1459 | case ZD_OFDM_RATE_48M: | |
1460 | case ZD_OFDM_RATE_54M: | |
1461 | i += 15; | |
1462 | break; | |
1463 | default: | |
1464 | return -EINVAL; | |
1465 | } | |
1466 | ||
e85d0918 DD |
1467 | return i; |
1468 | } | |
1469 | ||
db888aed UK |
1470 | static int ofdm_qual_percent(u8 status_quality, u8 rate, unsigned int size) |
1471 | { | |
1472 | int r; | |
1473 | ||
1474 | r = ofdm_qual_db(status_quality, rate, size); | |
1475 | ZD_ASSERT(r >= 0); | |
1476 | if (r < 0) | |
1477 | r = 0; | |
1478 | ||
1479 | r = (r * 100)/29; | |
1480 | return r <= 100 ? r : 100; | |
1481 | } | |
1482 | ||
e85d0918 DD |
1483 | static unsigned int log10times100(unsigned int x) |
1484 | { | |
1485 | static const u8 log10[] = { | |
1486 | 0, | |
1487 | 0, 30, 47, 60, 69, 77, 84, 90, 95, 100, | |
1488 | 104, 107, 111, 114, 117, 120, 123, 125, 127, 130, | |
1489 | 132, 134, 136, 138, 139, 141, 143, 144, 146, 147, | |
1490 | 149, 150, 151, 153, 154, 155, 156, 157, 159, 160, | |
1491 | 161, 162, 163, 164, 165, 166, 167, 168, 169, 169, | |
1492 | 170, 171, 172, 173, 174, 174, 175, 176, 177, 177, | |
1493 | 178, 179, 179, 180, 181, 181, 182, 183, 183, 184, | |
1494 | 185, 185, 186, 186, 187, 188, 188, 189, 189, 190, | |
1495 | 190, 191, 191, 192, 192, 193, 193, 194, 194, 195, | |
1496 | 195, 196, 196, 197, 197, 198, 198, 199, 199, 200, | |
1497 | 200, 200, 201, 201, 202, 202, 202, 203, 203, 204, | |
1498 | 204, 204, 205, 205, 206, 206, 206, 207, 207, 207, | |
1499 | 208, 208, 208, 209, 209, 210, 210, 210, 211, 211, | |
1500 | 211, 212, 212, 212, 213, 213, 213, 213, 214, 214, | |
1501 | 214, 215, 215, 215, 216, 216, 216, 217, 217, 217, | |
1502 | 217, 218, 218, 218, 219, 219, 219, 219, 220, 220, | |
1503 | 220, 220, 221, 221, 221, 222, 222, 222, 222, 223, | |
1504 | 223, 223, 223, 224, 224, 224, 224, | |
1505 | }; | |
1506 | ||
1507 | return x < ARRAY_SIZE(log10) ? log10[x] : 225; | |
1508 | } | |
1509 | ||
1510 | enum { | |
1511 | MAX_CCK_EVM_DB = 45, | |
1512 | }; | |
1513 | ||
1514 | static int cck_evm_db(u8 status_quality) | |
1515 | { | |
1516 | return (20 * log10times100(status_quality)) / 100; | |
1517 | } | |
1518 | ||
1519 | static int cck_snr_db(u8 status_quality) | |
1520 | { | |
1521 | int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality); | |
1522 | ZD_ASSERT(r >= 0); | |
1523 | return r; | |
1524 | } | |
1525 | ||
db888aed | 1526 | static int cck_qual_percent(u8 status_quality) |
e85d0918 | 1527 | { |
db888aed UK |
1528 | int r; |
1529 | ||
1530 | r = cck_snr_db(status_quality); | |
1531 | r = (100*r)/17; | |
1532 | return r <= 100 ? r : 100; | |
e85d0918 DD |
1533 | } |
1534 | ||
1535 | u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size, | |
1536 | const struct rx_status *status) | |
1537 | { | |
db888aed UK |
1538 | return (status->frame_status&ZD_RX_OFDM) ? |
1539 | ofdm_qual_percent(status->signal_quality_ofdm, | |
1540 | zd_ofdm_plcp_header_rate(rx_frame), | |
1541 | size) : | |
1542 | cck_qual_percent(status->signal_quality_cck); | |
e85d0918 DD |
1543 | } |
1544 | ||
1545 | u8 zd_rx_strength_percent(u8 rssi) | |
1546 | { | |
db888aed | 1547 | int r = (rssi*100) / 41; |
e85d0918 DD |
1548 | if (r > 100) |
1549 | r = 100; | |
1550 | return (u8) r; | |
1551 | } | |
1552 | ||
1553 | u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status) | |
1554 | { | |
1555 | static const u16 ofdm_rates[] = { | |
1556 | [ZD_OFDM_RATE_6M] = 60, | |
1557 | [ZD_OFDM_RATE_9M] = 90, | |
1558 | [ZD_OFDM_RATE_12M] = 120, | |
1559 | [ZD_OFDM_RATE_18M] = 180, | |
1560 | [ZD_OFDM_RATE_24M] = 240, | |
1561 | [ZD_OFDM_RATE_36M] = 360, | |
1562 | [ZD_OFDM_RATE_48M] = 480, | |
1563 | [ZD_OFDM_RATE_54M] = 540, | |
1564 | }; | |
1565 | u16 rate; | |
1566 | if (status->frame_status & ZD_RX_OFDM) { | |
1567 | u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame); | |
1568 | rate = ofdm_rates[ofdm_rate & 0xf]; | |
1569 | } else { | |
1570 | u8 cck_rate = zd_cck_plcp_header_rate(rx_frame); | |
1571 | switch (cck_rate) { | |
1572 | case ZD_CCK_SIGNAL_1M: | |
1573 | rate = 10; | |
1574 | break; | |
1575 | case ZD_CCK_SIGNAL_2M: | |
1576 | rate = 20; | |
1577 | break; | |
1578 | case ZD_CCK_SIGNAL_5M5: | |
1579 | rate = 55; | |
1580 | break; | |
1581 | case ZD_CCK_SIGNAL_11M: | |
1582 | rate = 110; | |
1583 | break; | |
1584 | default: | |
1585 | rate = 0; | |
1586 | } | |
1587 | } | |
1588 | ||
1589 | return rate; | |
1590 | } | |
1591 | ||
1592 | int zd_chip_switch_radio_on(struct zd_chip *chip) | |
1593 | { | |
1594 | int r; | |
1595 | ||
1596 | mutex_lock(&chip->mutex); | |
1597 | r = zd_switch_radio_on(&chip->rf); | |
1598 | mutex_unlock(&chip->mutex); | |
1599 | return r; | |
1600 | } | |
1601 | ||
1602 | int zd_chip_switch_radio_off(struct zd_chip *chip) | |
1603 | { | |
1604 | int r; | |
1605 | ||
1606 | mutex_lock(&chip->mutex); | |
1607 | r = zd_switch_radio_off(&chip->rf); | |
1608 | mutex_unlock(&chip->mutex); | |
1609 | return r; | |
1610 | } | |
1611 | ||
1612 | int zd_chip_enable_int(struct zd_chip *chip) | |
1613 | { | |
1614 | int r; | |
1615 | ||
1616 | mutex_lock(&chip->mutex); | |
1617 | r = zd_usb_enable_int(&chip->usb); | |
1618 | mutex_unlock(&chip->mutex); | |
1619 | return r; | |
1620 | } | |
1621 | ||
1622 | void zd_chip_disable_int(struct zd_chip *chip) | |
1623 | { | |
1624 | mutex_lock(&chip->mutex); | |
1625 | zd_usb_disable_int(&chip->usb); | |
1626 | mutex_unlock(&chip->mutex); | |
1627 | } | |
1628 | ||
1629 | int zd_chip_enable_rx(struct zd_chip *chip) | |
1630 | { | |
1631 | int r; | |
1632 | ||
1633 | mutex_lock(&chip->mutex); | |
1634 | r = zd_usb_enable_rx(&chip->usb); | |
1635 | mutex_unlock(&chip->mutex); | |
1636 | return r; | |
1637 | } | |
1638 | ||
1639 | void zd_chip_disable_rx(struct zd_chip *chip) | |
1640 | { | |
1641 | mutex_lock(&chip->mutex); | |
1642 | zd_usb_disable_rx(&chip->usb); | |
1643 | mutex_unlock(&chip->mutex); | |
1644 | } | |
1645 | ||
1646 | int zd_rfwritev_locked(struct zd_chip *chip, | |
1647 | const u32* values, unsigned int count, u8 bits) | |
1648 | { | |
1649 | int r; | |
1650 | unsigned int i; | |
1651 | ||
1652 | for (i = 0; i < count; i++) { | |
1653 | r = zd_rfwrite_locked(chip, values[i], bits); | |
1654 | if (r) | |
1655 | return r; | |
1656 | } | |
1657 | ||
1658 | return 0; | |
1659 | } | |
20fe2176 DD |
1660 | |
1661 | /* | |
1662 | * We can optionally program the RF directly through CR regs, if supported by | |
1663 | * the hardware. This is much faster than the older method. | |
1664 | */ | |
ec62bd91 | 1665 | int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value) |
20fe2176 DD |
1666 | { |
1667 | struct zd_ioreq16 ioreqs[] = { | |
1668 | { CR244, (value >> 16) & 0xff }, | |
1669 | { CR243, (value >> 8) & 0xff }, | |
1670 | { CR242, value & 0xff }, | |
1671 | }; | |
1672 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1673 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
1674 | } | |
1675 | ||
1676 | int zd_rfwritev_cr_locked(struct zd_chip *chip, | |
1677 | const u32 *values, unsigned int count) | |
1678 | { | |
1679 | int r; | |
1680 | unsigned int i; | |
1681 | ||
1682 | for (i = 0; i < count; i++) { | |
1683 | r = zd_rfwrite_cr_locked(chip, values[i]); | |
1684 | if (r) | |
1685 | return r; | |
1686 | } | |
1687 | ||
1688 | return 0; | |
1689 | } | |
9cdac965 UK |
1690 | |
1691 | int zd_chip_set_multicast_hash(struct zd_chip *chip, | |
1692 | struct zd_mc_hash *hash) | |
1693 | { | |
1694 | struct zd_ioreq32 ioreqs[] = { | |
1695 | { CR_GROUP_HASH_P1, hash->low }, | |
1696 | { CR_GROUP_HASH_P2, hash->high }, | |
1697 | }; | |
1698 | ||
1699 | dev_dbg_f(zd_chip_dev(chip), "hash l 0x%08x h 0x%08x\n", | |
1700 | ioreqs[0].value, ioreqs[1].value); | |
1701 | return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
1702 | } |