]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/wireless/zd1211rw/zd_chip.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[RT2x00]: add driver for Ralink wireless hardware
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / zd1211rw / zd_chip.c
CommitLineData
e85d0918
DD		 1/* zd_chip.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18/* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
21 */
22
23#include <linux/kernel.h>
24#include <linux/errno.h>
25
26#include "zd_def.h"
27#include "zd_chip.h"
28#include "zd_ieee80211.h"
29#include "zd_mac.h"
30#include "zd_rf.h"
31#include "zd_util.h"
32
33void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
36{
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
41}
42
43void zd_chip_clear(struct zd_chip *chip)
44{
c48cf125 45 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
e85d0918
DD		 46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
e85d0918 48 mutex_destroy(&chip->mutex);
c48cf125 49 ZD_MEMCLEAR(chip, sizeof(*chip));
e85d0918
DD		 50}
51
74553aed 52static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
e85d0918 53{
74553aed 54 u8 *addr = zd_usb_to_netdev(&chip->usb)->dev_addr;
e85d0918
DD		 55 return scnprintf(buffer, size, "%02x-%02x-%02x",
56 addr[0], addr[1], addr[2]);
57}
58
59/* Prints an identifier line, which will support debugging. */
60static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
61{
62 int i = 0;
63
64 i = scnprintf(buffer, size, "zd1211%s chip ",
74553aed 65 zd_chip_is_zd1211b(chip) ? "b" : "");
e85d0918
DD		 66 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
67 i += scnprintf(buffer+i, size-i, " ");
74553aed 68 i += scnprint_mac_oui(chip, buffer+i, size-i);
e85d0918
DD		 69 i += scnprintf(buffer+i, size-i, " ");
70 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
f2a81a16 71 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
e85d0918
DD		 72 chip->patch_cck_gain ? 'g' : '-',
73 chip->patch_cr157 ? '7' : '-',
20fe2176 74 chip->patch_6m_band_edge ? '6' : '-',
f2a81a16
DD		 75 chip->new_phy_layout ? 'N' : '-',
76 chip->al2230s_bit ? 'S' : '-');
e85d0918
DD		 77 return i;
78}
79
80static void print_id(struct zd_chip *chip)
81{
82 char buffer[80];
83
84 scnprint_id(chip, buffer, sizeof(buffer));
85 buffer[sizeof(buffer)-1] = 0;
86 dev_info(zd_chip_dev(chip), "%s\n", buffer);
87}
88
0ce34bc8
DD		 89static zd_addr_t inc_addr(zd_addr_t addr)
90{
91 u16 a = (u16)addr;
92 /* Control registers use byte addressing, but everything else uses word
93 * addressing. */
94 if ((a & 0xf000) == CR_START)
95 a += 2;
96 else
97 a += 1;
98 return (zd_addr_t)a;
99}
100
e85d0918
DD		 101/* Read a variable number of 32-bit values. Parameter count is not allowed to
102 * exceed USB_MAX_IOREAD32_COUNT.
103 */
104int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
105 unsigned int count)
106{
107 int r;
108 int i;
109 zd_addr_t *a16 = (zd_addr_t *)NULL;
110 u16 *v16;
111 unsigned int count16;
112
113 if (count > USB_MAX_IOREAD32_COUNT)
114 return -EINVAL;
115
116 /* Allocate a single memory block for values and addresses. */
117 count16 = 2*count;
44956855 118 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
35c3404e 119 GFP_KERNEL);
e85d0918
DD		 120 if (!a16) {
121 dev_dbg_f(zd_chip_dev(chip),
122 "error ENOMEM in allocation of a16\n");
123 r = -ENOMEM;
124 goto out;
125 }
126 v16 = (u16 *)(a16 + count16);
127
128 for (i = 0; i < count; i++) {
129 int j = 2*i;
130 /* We read the high word always first. */
0ce34bc8 131 a16[j] = inc_addr(addr[i]);
e85d0918
DD		 132 a16[j+1] = addr[i];
133 }
134
135 r = zd_ioread16v_locked(chip, v16, a16, count16);
136 if (r) {
137 dev_dbg_f(zd_chip_dev(chip),
138 "error: zd_ioread16v_locked. Error number %d\n", r);
139 goto out;
140 }
141
142 for (i = 0; i < count; i++) {
143 int j = 2*i;
144 values[i] = (v16[j] << 16) | v16[j+1];
145 }
146
147out:
148 kfree((void *)a16);
149 return r;
150}
151
152int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
153 unsigned int count)
154{
155 int i, j, r;
156 struct zd_ioreq16 *ioreqs16;
157 unsigned int count16;
158
159 ZD_ASSERT(mutex_is_locked(&chip->mutex));
160
161 if (count == 0)
162 return 0;
163 if (count > USB_MAX_IOWRITE32_COUNT)
164 return -EINVAL;
165
166 /* Allocate a single memory block for values and addresses. */
167 count16 = 2*count;
35c3404e 168 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL);
e85d0918
DD		 169 if (!ioreqs16) {
170 r = -ENOMEM;
171 dev_dbg_f(zd_chip_dev(chip),
172 "error %d in ioreqs16 allocation\n", r);
173 goto out;
174 }
175
176 for (i = 0; i < count; i++) {
177 j = 2*i;
178 /* We write the high word always first. */
179 ioreqs16[j].value = ioreqs[i].value >> 16;
0ce34bc8 180 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
e85d0918
DD		 181 ioreqs16[j+1].value = ioreqs[i].value;
182 ioreqs16[j+1].addr = ioreqs[i].addr;
183 }
184
185 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
186#ifdef DEBUG
187 if (r) {
188 dev_dbg_f(zd_chip_dev(chip),
189 "error %d in zd_usb_write16v\n", r);
190 }
191#endif /* DEBUG */
192out:
193 kfree(ioreqs16);
194 return r;
195}
196
197int zd_iowrite16a_locked(struct zd_chip *chip,
198 const struct zd_ioreq16 *ioreqs, unsigned int count)
199{
200 int r;
201 unsigned int i, j, t, max;
202
203 ZD_ASSERT(mutex_is_locked(&chip->mutex));
204 for (i = 0; i < count; i += j + t) {
205 t = 0;
206 max = count-i;
207 if (max > USB_MAX_IOWRITE16_COUNT)
208 max = USB_MAX_IOWRITE16_COUNT;
209 for (j = 0; j < max; j++) {
210 if (!ioreqs[i+j].addr) {
211 t = 1;
212 break;
213 }
214 }
215
216 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
217 if (r) {
218 dev_dbg_f(zd_chip_dev(chip),
219 "error zd_usb_iowrite16v. Error number %d\n",
220 r);
221 return r;
222 }
223 }
224
225 return 0;
226}
227
228/* Writes a variable number of 32 bit registers. The functions will split
229 * that in several USB requests. A split can be forced by inserting an IO
230 * request with an zero address field.
231 */
232int zd_iowrite32a_locked(struct zd_chip *chip,
233 const struct zd_ioreq32 *ioreqs, unsigned int count)
234{
235 int r;
236 unsigned int i, j, t, max;
237
238 for (i = 0; i < count; i += j + t) {
239 t = 0;
240 max = count-i;
241 if (max > USB_MAX_IOWRITE32_COUNT)
242 max = USB_MAX_IOWRITE32_COUNT;
243 for (j = 0; j < max; j++) {
244 if (!ioreqs[i+j].addr) {
245 t = 1;
246 break;
247 }
248 }
249
250 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
251 if (r) {
252 dev_dbg_f(zd_chip_dev(chip),
253 "error _zd_iowrite32v_locked."
254 " Error number %d\n", r);
255 return r;
256 }
257 }
258
259 return 0;
260}
261
262int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
263{
264 int r;
265
e85d0918
DD		 266 mutex_lock(&chip->mutex);
267 r = zd_ioread16_locked(chip, value, addr);
268 mutex_unlock(&chip->mutex);
269 return r;
270}
271
272int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
273{
274 int r;
275
e85d0918
DD		 276 mutex_lock(&chip->mutex);
277 r = zd_ioread32_locked(chip, value, addr);
278 mutex_unlock(&chip->mutex);
279 return r;
280}
281
282int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
283{
284 int r;
285
e85d0918
DD		 286 mutex_lock(&chip->mutex);
287 r = zd_iowrite16_locked(chip, value, addr);
288 mutex_unlock(&chip->mutex);
289 return r;
290}
291
292int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
293{
294 int r;
295
e85d0918
DD		 296 mutex_lock(&chip->mutex);
297 r = zd_iowrite32_locked(chip, value, addr);
298 mutex_unlock(&chip->mutex);
299 return r;
300}
301
302int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
303 u32 *values, unsigned int count)
304{
305 int r;
306
e85d0918
DD		 307 mutex_lock(&chip->mutex);
308 r = zd_ioread32v_locked(chip, values, addresses, count);
309 mutex_unlock(&chip->mutex);
310 return r;
311}
312
313int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
314 unsigned int count)
315{
316 int r;
317
e85d0918
DD		 318 mutex_lock(&chip->mutex);
319 r = zd_iowrite32a_locked(chip, ioreqs, count);
320 mutex_unlock(&chip->mutex);
321 return r;
322}
323
324static int read_pod(struct zd_chip *chip, u8 *rf_type)
325{
326 int r;
327 u32 value;
328
329 ZD_ASSERT(mutex_is_locked(&chip->mutex));
330 r = zd_ioread32_locked(chip, &value, E2P_POD);
331 if (r)
332 goto error;
333 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
334
335 /* FIXME: AL2230 handling (Bit 7 in POD) */
336 *rf_type = value & 0x0f;
337 chip->pa_type = (value >> 16) & 0x0f;
338 chip->patch_cck_gain = (value >> 8) & 0x1;
339 chip->patch_cr157 = (value >> 13) & 0x1;
340 chip->patch_6m_band_edge = (value >> 21) & 0x1;
20fe2176 341 chip->new_phy_layout = (value >> 31) & 0x1;
ae6ead46 342 chip->al2230s_bit = (value >> 7) & 0x1;
583afd1e
UK		 343 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
344 chip->supports_tx_led = 1;
345 if (value & (1 << 24)) { /* LED scenario */
346 if (value & (1 << 29))
347 chip->supports_tx_led = 0;
348 }
e85d0918
DD		 349
350 dev_dbg_f(zd_chip_dev(chip),
351 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
583afd1e 352 "patch 6M %d new PHY %d link LED%d tx led %d\n",
e85d0918
DD		 353 zd_rf_name(*rf_type), *rf_type,
354 chip->pa_type, chip->patch_cck_gain,
583afd1e
UK		 355 chip->patch_cr157, chip->patch_6m_band_edge,
356 chip->new_phy_layout,
357 chip->link_led == LED1 ? 1 : 2,
358 chip->supports_tx_led);
e85d0918
DD		 359 return 0;
360error:
361 *rf_type = 0;
362 chip->pa_type = 0;
363 chip->patch_cck_gain = 0;
364 chip->patch_cr157 = 0;
365 chip->patch_6m_band_edge = 0;
20fe2176 366 chip->new_phy_layout = 0;
e85d0918
DD		 367 return r;
368}
369
e85d0918
DD		 370/* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
371 * CR_MAC_ADDR_P2 must be overwritten
372 */
e85d0918
DD		 373int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
374{
375 int r;
376 struct zd_ioreq32 reqs[2] = {
377 [0] = { .addr = CR_MAC_ADDR_P1 },
378 [1] = { .addr = CR_MAC_ADDR_P2 },
379 };
380
381 reqs[0].value = (mac_addr[3] << 24)
382 | (mac_addr[2] << 16)
383 | (mac_addr[1] << 8)
384 | mac_addr[0];
385 reqs[1].value = (mac_addr[5] << 8)
386 | mac_addr[4];
387
388 dev_dbg_f(zd_chip_dev(chip),
389 "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
390
391 mutex_lock(&chip->mutex);
392 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
e85d0918
DD		 393 mutex_unlock(&chip->mutex);
394 return r;
395}
396
397int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
398{
399 int r;
400 u32 value;
401
402 mutex_lock(&chip->mutex);
403 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
404 mutex_unlock(&chip->mutex);
405 if (r)
406 return r;
407
408 *regdomain = value >> 16;
409 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
410
411 return 0;
412}
413
414static int read_values(struct zd_chip *chip, u8 *values, size_t count,
415 zd_addr_t e2p_addr, u32 guard)
416{
417 int r;
418 int i;
419 u32 v;
420
421 ZD_ASSERT(mutex_is_locked(&chip->mutex));
422 for (i = 0;;) {
0ce34bc8
DD		 423 r = zd_ioread32_locked(chip, &v,
424 (zd_addr_t)((u16)e2p_addr+i/2));
e85d0918
DD		 425 if (r)
426 return r;
427 v -= guard;
428 if (i+4 < count) {
429 values[i++] = v;
430 values[i++] = v >> 8;
431 values[i++] = v >> 16;
432 values[i++] = v >> 24;
433 continue;
434 }
435 for (;i < count; i++)
436 values[i] = v >> (8*(i%3));
437 return 0;
438 }
439}
440
441static int read_pwr_cal_values(struct zd_chip *chip)
442{
443 return read_values(chip, chip->pwr_cal_values,
444 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
445 0);
446}
447
448static int read_pwr_int_values(struct zd_chip *chip)
449{
450 return read_values(chip, chip->pwr_int_values,
451 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
452 E2P_PWR_INT_GUARD);
453}
454
455static int read_ofdm_cal_values(struct zd_chip *chip)
456{
457 int r;
458 int i;
459 static const zd_addr_t addresses[] = {
460 E2P_36M_CAL_VALUE1,
461 E2P_48M_CAL_VALUE1,
462 E2P_54M_CAL_VALUE1,
463 };
464
465 for (i = 0; i < 3; i++) {
466 r = read_values(chip, chip->ofdm_cal_values[i],
467 E2P_CHANNEL_COUNT, addresses[i], 0);
468 if (r)
469 return r;
470 }
471 return 0;
472}
473
474static int read_cal_int_tables(struct zd_chip *chip)
475{
476 int r;
477
478 r = read_pwr_cal_values(chip);
479 if (r)
480 return r;
481 r = read_pwr_int_values(chip);
482 if (r)
483 return r;
484 r = read_ofdm_cal_values(chip);
485 if (r)
486 return r;
487 return 0;
488}
489
490/* phy means physical registers */
491int zd_chip_lock_phy_regs(struct zd_chip *chip)
492{
493 int r;
494 u32 tmp;
495
496 ZD_ASSERT(mutex_is_locked(&chip->mutex));
497 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
498 if (r) {
499 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
500 return r;
501 }
502
e85d0918
DD		 503 tmp &= ~UNLOCK_PHY_REGS;
504
505 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
506 if (r)
507 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
508 return r;
509}
510
511int zd_chip_unlock_phy_regs(struct zd_chip *chip)
512{
513 int r;
514 u32 tmp;
515
516 ZD_ASSERT(mutex_is_locked(&chip->mutex));
517 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
518 if (r) {
519 dev_err(zd_chip_dev(chip),
520 "error ioread32(CR_REG1): %d\n", r);
521 return r;
522 }
523
e85d0918
DD		 524 tmp |= UNLOCK_PHY_REGS;
525
526 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
527 if (r)
528 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
529 return r;
530}
531
92b3e2e9 532/* CR157 can be optionally patched by the EEPROM for original ZD1211 */
e85d0918
DD		 533static int patch_cr157(struct zd_chip *chip)
534{
535 int r;
92b3e2e9 536 u16 value;
e85d0918
DD		 537
538 if (!chip->patch_cr157)
539 return 0;
540
92b3e2e9 541 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
e85d0918
DD		 542 if (r)
543 return r;
544
545 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
546 return zd_iowrite32_locked(chip, value >> 8, CR157);
547}
548
549/*
550 * 6M band edge can be optionally overwritten for certain RF's
551 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
552 * bit (for AL2230, AL2230S)
553 */
72018b22
DD		 554static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
555{
556 ZD_ASSERT(mutex_is_locked(&chip->mutex));
557 if (!chip->patch_6m_band_edge)
558 return 0;
559
560 return zd_rf_patch_6m_band_edge(&chip->rf, channel);
561}
562
563/* Generic implementation of 6M band edge patching, used by most RFs via
564 * zd_rf_generic_patch_6m() */
565int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
e85d0918
DD		 566{
567 struct zd_ioreq16 ioreqs[] = {
568 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
569 { CR47, 0x1e },
570 };
571
e85d0918
DD		 572 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
573 if (channel == 1 || channel == 11)
574 ioreqs[0].value = 0x12;
575
576 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
577 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
578}
579
580static int zd1211_hw_reset_phy(struct zd_chip *chip)
581{
582 static const struct zd_ioreq16 ioreqs[] = {
583 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
584 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
585 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
586 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
587 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
588 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
589 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
590 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
591 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
592 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
593 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
594 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
595 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
596 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
597 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
598 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
599 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
600 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
601 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
602 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
603 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
604 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
605 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
606 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
607 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
608 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
609 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
610 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
611 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
612 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
613 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
614 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
615 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
616 { },
617 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
618 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
619 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
620 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
621 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
622 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
623 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
624 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
625 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
626 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
627 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
628 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
629 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
630 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
dc536a70
DD		 631 { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
632 { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
633 { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
634 { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
635 { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
636 { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
637 { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
638 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
639 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
640 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
641 { CR170, 0xba }, { CR171, 0xba },
e85d0918
DD		 642 /* Note: CR204 must lead the CR203 */
643 { CR204, 0x7d },
644 { },
645 { CR203, 0x30 },
646 };
647
648 int r, t;
649
650 dev_dbg_f(zd_chip_dev(chip), "\n");
651
652 r = zd_chip_lock_phy_regs(chip);
653 if (r)
654 goto out;
655
656 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
657 if (r)
658 goto unlock;
659
660 r = patch_cr157(chip);
661unlock:
662 t = zd_chip_unlock_phy_regs(chip);
663 if (t && !r)
664 r = t;
665out:
666 return r;
667}
668
669static int zd1211b_hw_reset_phy(struct zd_chip *chip)
670{
671 static const struct zd_ioreq16 ioreqs[] = {
672 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
673 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
674 { CR10, 0x81 },
675 /* power control { { CR11, 1 << 6 }, */
676 { CR11, 0x00 },
677 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
678 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
679 { CR18, 0x0a }, { CR19, 0x48 },
680 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
681 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
682 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
683 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
fe7215ca 684 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
e85d0918
DD		 685 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
686 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
687 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
688 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
689 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
690 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
691 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
692 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
693 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
694 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
695 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
696 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
697 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
698 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
699 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
700 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
701 { CR94, 0x01 },
702 { CR95, 0x20 }, /* ZD1211B */
703 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
704 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
705 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
706 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
707 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
708 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
709 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
710 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
711 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
712 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
713 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
714 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
715 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
716 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
717 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
718 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
719 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
720 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
721 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
722 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
723 { CR170, 0xba }, { CR171, 0xba },
724 /* Note: CR204 must lead the CR203 */
725 { CR204, 0x7d },
726 {},
727 { CR203, 0x30 },
728 };
729
730 int r, t;
731
732 dev_dbg_f(zd_chip_dev(chip), "\n");
733
734 r = zd_chip_lock_phy_regs(chip);
735 if (r)
736 goto out;
737
738 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 739 t = zd_chip_unlock_phy_regs(chip);
740 if (t && !r)
741 r = t;
742out:
743 return r;
744}
745
746static int hw_reset_phy(struct zd_chip *chip)
747{
74553aed 748 return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
e85d0918
DD		 749 zd1211_hw_reset_phy(chip);
750}
751
752static int zd1211_hw_init_hmac(struct zd_chip *chip)
753{
754 static const struct zd_ioreq32 ioreqs[] = {
e85d0918 755 { CR_ZD1211_RETRY_MAX, 0x2 },
e85d0918 756 { CR_RX_THRESHOLD, 0x000c0640 },
e85d0918
DD		 757 };
758
e85d0918
DD		 759 dev_dbg_f(zd_chip_dev(chip), "\n");
760 ZD_ASSERT(mutex_is_locked(&chip->mutex));
34c44912 761 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 762}
763
764static int zd1211b_hw_init_hmac(struct zd_chip *chip)
765{
766 static const struct zd_ioreq32 ioreqs[] = {
e85d0918
DD		 767 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
768 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
769 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
770 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
771 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
772 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
773 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
774 { CR_ZD1211B_TXOP, 0x01800824 },
34c44912
DD		 775 { CR_RX_THRESHOLD, 0x000c0eff, },
776 };
777
778 dev_dbg_f(zd_chip_dev(chip), "\n");
779 ZD_ASSERT(mutex_is_locked(&chip->mutex));
780 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
781}
782
783static int hw_init_hmac(struct zd_chip *chip)
784{
785 int r;
786 static const struct zd_ioreq32 ioreqs[] = {
787 { CR_ACK_TIMEOUT_EXT, 0x20 },
788 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
e85d0918 789 { CR_SNIFFER_ON, 0 },
fde627b5 790 { CR_RX_FILTER, STA_RX_FILTER },
e85d0918
DD		 791 { CR_GROUP_HASH_P1, 0x00 },
792 { CR_GROUP_HASH_P2, 0x80000000 },
793 { CR_REG1, 0xa4 },
794 { CR_ADDA_PWR_DWN, 0x7f },
795 { CR_BCN_PLCP_CFG, 0x00f00401 },
796 { CR_PHY_DELAY, 0x00 },
797 { CR_ACK_TIMEOUT_EXT, 0x80 },
798 { CR_ADDA_PWR_DWN, 0x00 },
799 { CR_ACK_TIME_80211, 0x100 },
e85d0918
DD		 800 { CR_RX_PE_DELAY, 0x70 },
801 { CR_PS_CTRL, 0x10000000 },
802 { CR_RTS_CTS_RATE, 0x02030203 },
e85d0918
DD		 803 { CR_AFTER_PNP, 0x1 },
804 { CR_WEP_PROTECT, 0x114 },
34c44912 805 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
e85d0918
DD		 806 };
807
e85d0918
DD		 808 ZD_ASSERT(mutex_is_locked(&chip->mutex));
809 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
34c44912
DD		 810 if (r)
811 return r;
e85d0918 812
74553aed 813 return zd_chip_is_zd1211b(chip) ?
e85d0918
DD		 814 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
815}
816
817struct aw_pt_bi {
818 u32 atim_wnd_period;
819 u32 pre_tbtt;
820 u32 beacon_interval;
821};
822
823static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
824{
825 int r;
826 static const zd_addr_t aw_pt_bi_addr[] =
827 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
828 u32 values[3];
829
830 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
831 ARRAY_SIZE(aw_pt_bi_addr));
832 if (r) {
833 memset(s, 0, sizeof(*s));
834 return r;
835 }
836
837 s->atim_wnd_period = values[0];
838 s->pre_tbtt = values[1];
839 s->beacon_interval = values[2];
e85d0918
DD		 840 return 0;
841}
842
843static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
844{
845 struct zd_ioreq32 reqs[3];
846
847 if (s->beacon_interval <= 5)
848 s->beacon_interval = 5;
849 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
850 s->pre_tbtt = s->beacon_interval - 1;
851 if (s->atim_wnd_period >= s->pre_tbtt)
852 s->atim_wnd_period = s->pre_tbtt - 1;
853
854 reqs[0].addr = CR_ATIM_WND_PERIOD;
855 reqs[0].value = s->atim_wnd_period;
856 reqs[1].addr = CR_PRE_TBTT;
857 reqs[1].value = s->pre_tbtt;
858 reqs[2].addr = CR_BCN_INTERVAL;
859 reqs[2].value = s->beacon_interval;
860
e85d0918
DD		 861 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
862}
863
864
865static int set_beacon_interval(struct zd_chip *chip, u32 interval)
866{
867 int r;
868 struct aw_pt_bi s;
869
870 ZD_ASSERT(mutex_is_locked(&chip->mutex));
871 r = get_aw_pt_bi(chip, &s);
872 if (r)
873 return r;
874 s.beacon_interval = interval;
875 return set_aw_pt_bi(chip, &s);
876}
877
878int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
879{
880 int r;
881
882 mutex_lock(&chip->mutex);
883 r = set_beacon_interval(chip, interval);
884 mutex_unlock(&chip->mutex);
885 return r;
886}
887
888static int hw_init(struct zd_chip *chip)
889{
890 int r;
891
892 dev_dbg_f(zd_chip_dev(chip), "\n");
893 ZD_ASSERT(mutex_is_locked(&chip->mutex));
894 r = hw_reset_phy(chip);
895 if (r)
896 return r;
897
898 r = hw_init_hmac(chip);
899 if (r)
900 return r;
98227a90 901
98227a90 902 return set_beacon_interval(chip, 100);
e85d0918
DD		 903}
904
0ce34bc8
DD		 905static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
906{
907 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
908}
909
e85d0918
DD		 910#ifdef DEBUG
911static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
912 const char *addr_string)
913{
914 int r;
915 u32 value;
916
917 r = zd_ioread32_locked(chip, &value, addr);
918 if (r) {
919 dev_dbg_f(zd_chip_dev(chip),
920 "error reading %s. Error number %d\n", addr_string, r);
921 return r;
922 }
923
924 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
925 addr_string, (unsigned int)value);
926 return 0;
927}
928
929static int test_init(struct zd_chip *chip)
930{
931 int r;
932
933 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
934 if (r)
935 return r;
936 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
937 if (r)
938 return r;
939 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
940}
941
942static void dump_fw_registers(struct zd_chip *chip)
943{
0ce34bc8
DD		 944 const zd_addr_t addr[4] = {
945 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
946 fw_reg_addr(chip, FW_REG_USB_SPEED),
947 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
948 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
e85d0918
DD		 949 };
950
951 int r;
952 u16 values[4];
953
954 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
955 ARRAY_SIZE(addr));
956 if (r) {
957 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
958 r);
959 return;
960 }
961
962 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
963 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
964 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
965 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
966}
967#endif /* DEBUG */
968
969static int print_fw_version(struct zd_chip *chip)
970{
971 int r;
972 u16 version;
973
0ce34bc8
DD		 974 r = zd_ioread16_locked(chip, &version,
975 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
e85d0918
DD		 976 if (r)
977 return r;
978
979 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
980 return 0;
981}
982
983static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
984{
985 u32 rates;
986 ZD_ASSERT(mutex_is_locked(&chip->mutex));
987 /* This sets the mandatory rates, which only depend from the standard
988 * that the device is supporting. Until further notice we should try
989 * to support 802.11g also for full speed USB.
990 */
991 switch (std) {
992 case IEEE80211B:
993 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
994 break;
995 case IEEE80211G:
996 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
997 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
998 break;
999 default:
1000 return -EINVAL;
1001 }
1002 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1003}
1004
b1382ede
DD		 1005int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1006 u8 rts_rate, int preamble)
1007{
1008 int rts_mod = ZD_RX_CCK;
1009 u32 value = 0;
1010
1011 /* Modulation bit */
64f222cc 1012 if (ZD_MODULATION_TYPE(rts_rate) == ZD_OFDM)
b1382ede
DD		 1013 rts_mod = ZD_RX_OFDM;
1014
1015 dev_dbg_f(zd_chip_dev(chip), "rts_rate=%x preamble=%x\n",
1016 rts_rate, preamble);
1017
64f222cc 1018 value |= ZD_PURE_RATE(rts_rate) << RTSCTS_SH_RTS_RATE;
b1382ede
DD		 1019 value |= rts_mod << RTSCTS_SH_RTS_MOD_TYPE;
1020 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1021 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1022
1023 /* We always send 11M self-CTS messages, like the vendor driver. */
64f222cc 1024 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE;
b1382ede
DD		 1025 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1026
1027 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1028}
1029
e85d0918
DD		 1030int zd_chip_enable_hwint(struct zd_chip *chip)
1031{
1032 int r;
1033
1034 mutex_lock(&chip->mutex);
1035 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1036 mutex_unlock(&chip->mutex);
1037 return r;
1038}
1039
1040static int disable_hwint(struct zd_chip *chip)
1041{
1042 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1043}
1044
1045int zd_chip_disable_hwint(struct zd_chip *chip)
1046{
1047 int r;
1048
1049 mutex_lock(&chip->mutex);
1050 r = disable_hwint(chip);
1051 mutex_unlock(&chip->mutex);
1052 return r;
1053}
1054
0ce34bc8
DD		 1055static int read_fw_regs_offset(struct zd_chip *chip)
1056{
1057 int r;
1058
1059 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1060 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1061 FWRAW_REGS_ADDR);
1062 if (r)
1063 return r;
1064 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1065 (u16)chip->fw_regs_base);
1066
1067 return 0;
1068}
1069
74553aed
DD		 1070/* Read mac address using pre-firmware interface */
1071int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1072{
1073 dev_dbg_f(zd_chip_dev(chip), "\n");
1074 return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
1075 ETH_ALEN);
1076}
0ce34bc8 1077
74553aed 1078int zd_chip_init_hw(struct zd_chip *chip)
e85d0918
DD		 1079{
1080 int r;
1081 u8 rf_type;
1082
1083 dev_dbg_f(zd_chip_dev(chip), "\n");
1084
1085 mutex_lock(&chip->mutex);
e85d0918
DD		 1086
1087#ifdef DEBUG
1088 r = test_init(chip);
1089 if (r)
1090 goto out;
1091#endif
1092 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1093 if (r)
1094 goto out;
1095
0ce34bc8 1096 r = read_fw_regs_offset(chip);
e85d0918
DD		 1097 if (r)
1098 goto out;
1099
1100 /* GPI is always disabled, also in the other driver.
1101 */
1102 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1103 if (r)
1104 goto out;
1105 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1106 if (r)
1107 goto out;
1108 /* Currently we support IEEE 802.11g for full and high speed USB.
1109 * It might be discussed, whether we should suppport pure b mode for
1110 * full speed USB.
1111 */
1112 r = set_mandatory_rates(chip, IEEE80211G);
1113 if (r)
1114 goto out;
1115 /* Disabling interrupts is certainly a smart thing here.
1116 */
1117 r = disable_hwint(chip);
1118 if (r)
1119 goto out;
1120 r = read_pod(chip, &rf_type);
1121 if (r)
1122 goto out;
1123 r = hw_init(chip);
1124 if (r)
1125 goto out;
1126 r = zd_rf_init_hw(&chip->rf, rf_type);
1127 if (r)
1128 goto out;
1129
1130 r = print_fw_version(chip);
1131 if (r)
1132 goto out;
1133
1134#ifdef DEBUG
1135 dump_fw_registers(chip);
1136 r = test_init(chip);
1137 if (r)
1138 goto out;
1139#endif /* DEBUG */
1140
e85d0918
DD		 1141 r = read_cal_int_tables(chip);
1142 if (r)
1143 goto out;
1144
1145 print_id(chip);
1146out:
1147 mutex_unlock(&chip->mutex);
1148 return r;
1149}
1150
1151static int update_pwr_int(struct zd_chip *chip, u8 channel)
1152{
1153 u8 value = chip->pwr_int_values[channel - 1];
cbb5e6bb 1154 return zd_iowrite16_locked(chip, value, CR31);
e85d0918
DD		 1155}
1156
1157static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1158{
1159 u8 value = chip->pwr_cal_values[channel-1];
cbb5e6bb 1160 return zd_iowrite16_locked(chip, value, CR68);
e85d0918
DD		 1161}
1162
1163static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1164{
cbb5e6bb 1165 struct zd_ioreq16 ioreqs[3];
e85d0918
DD		 1166
1167 ioreqs[0].addr = CR67;
1168 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1169 ioreqs[1].addr = CR66;
1170 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1171 ioreqs[2].addr = CR65;
1172 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1173
cbb5e6bb 1174 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 1175}
1176
1177static int update_channel_integration_and_calibration(struct zd_chip *chip,
1178 u8 channel)
1179{
1180 int r;
1181
9c8fc71d
DD		 1182 if (!zd_rf_should_update_pwr_int(&chip->rf))
1183 return 0;
1184
e85d0918
DD		 1185 r = update_pwr_int(chip, channel);
1186 if (r)
1187 return r;
74553aed 1188 if (zd_chip_is_zd1211b(chip)) {
cbb5e6bb 1189 static const struct zd_ioreq16 ioreqs[] = {
e85d0918
DD		 1190 { CR69, 0x28 },
1191 {},
1192 { CR69, 0x2a },
1193 };
1194
1195 r = update_ofdm_cal(chip, channel);
1196 if (r)
1197 return r;
1198 r = update_pwr_cal(chip, channel);
1199 if (r)
1200 return r;
cbb5e6bb 1201 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 1202 if (r)
1203 return r;
1204 }
1205
1206 return 0;
1207}
1208
1209/* The CCK baseband gain can be optionally patched by the EEPROM */
1210static int patch_cck_gain(struct zd_chip *chip)
1211{
1212 int r;
1213 u32 value;
1214
aaf83d4f 1215 if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
e85d0918
DD		 1216 return 0;
1217
1218 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1219 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1220 if (r)
1221 return r;
1222 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
cbb5e6bb 1223 return zd_iowrite16_locked(chip, value & 0xff, CR47);
e85d0918
DD		 1224}
1225
1226int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1227{
1228 int r, t;
1229
1230 mutex_lock(&chip->mutex);
1231 r = zd_chip_lock_phy_regs(chip);
1232 if (r)
1233 goto out;
1234 r = zd_rf_set_channel(&chip->rf, channel);
1235 if (r)
1236 goto unlock;
1237 r = update_channel_integration_and_calibration(chip, channel);
1238 if (r)
1239 goto unlock;
1240 r = patch_cck_gain(chip);
1241 if (r)
1242 goto unlock;
1243 r = patch_6m_band_edge(chip, channel);
1244 if (r)
1245 goto unlock;
1246 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1247unlock:
1248 t = zd_chip_unlock_phy_regs(chip);
1249 if (t && !r)
1250 r = t;
1251out:
1252 mutex_unlock(&chip->mutex);
1253 return r;
1254}
1255
1256u8 zd_chip_get_channel(struct zd_chip *chip)
1257{
1258 u8 channel;
1259
1260 mutex_lock(&chip->mutex);
1261 channel = chip->rf.channel;
1262 mutex_unlock(&chip->mutex);
1263 return channel;
1264}
1265
583afd1e 1266int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
e85d0918 1267{
0ce34bc8
DD		 1268 const zd_addr_t a[] = {
1269 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
583afd1e
UK		 1270 CR_LED,
1271 };
e85d0918 1272
583afd1e
UK		 1273 int r;
1274 u16 v[ARRAY_SIZE(a)];
1275 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
0ce34bc8 1276 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
583afd1e
UK		 1277 [1] = { CR_LED },
1278 };
1279 u16 other_led;
e85d0918 1280
e85d0918 1281 mutex_lock(&chip->mutex);
583afd1e 1282 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
e85d0918 1283 if (r)
583afd1e
UK		 1284 goto out;
1285
1286 other_led = chip->link_led == LED1 ? LED2 : LED1;
1287
e85d0918 1288 switch (status) {
e85d0918 1289 case LED_OFF:
583afd1e
UK		 1290 ioreqs[0].value = FW_LINK_OFF;
1291 ioreqs[1].value = v[1] & ~(LED1|LED2);
e85d0918 1292 break;
583afd1e
UK		 1293 case LED_SCANNING:
1294 ioreqs[0].value = FW_LINK_OFF;
1295 ioreqs[1].value = v[1] & ~other_led;
1296 if (get_seconds() % 3 == 0) {
1297 ioreqs[1].value &= ~chip->link_led;
1298 } else {
1299 ioreqs[1].value |= chip->link_led;
1300 }
e85d0918 1301 break;
583afd1e
UK		 1302 case LED_ASSOCIATED:
1303 ioreqs[0].value = FW_LINK_TX;
1304 ioreqs[1].value = v[1] & ~other_led;
1305 ioreqs[1].value |= chip->link_led;
e85d0918
DD		 1306 break;
1307 default:
583afd1e 1308 r = -EINVAL;
e85d0918
DD		 1309 goto out;
1310 }
e85d0918 1311
583afd1e
UK		 1312 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1313 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1314 if (r)
e85d0918 1315 goto out;
e85d0918 1316 }
583afd1e 1317 r = 0;
e85d0918 1318out:
583afd1e 1319 mutex_unlock(&chip->mutex);
e85d0918
DD		 1320 return r;
1321}
1322
b1382ede 1323int zd_chip_set_basic_rates_locked(struct zd_chip *chip, u16 cr_rates)
e85d0918 1324{
b1382ede
DD		 1325 ZD_ASSERT((cr_rates & ~(CR_RATES_80211B | CR_RATES_80211G)) == 0);
1326 dev_dbg_f(zd_chip_dev(chip), "%x\n", cr_rates);
e85d0918 1327
b1382ede 1328 return zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
e85d0918
DD		 1329}
1330
64f222cc 1331static int ofdm_qual_db(u8 status_quality, u8 zd_rate, unsigned int size)
e85d0918
DD		 1332{
1333 static const u16 constants[] = {
1334 715, 655, 585, 540, 470, 410, 360, 315,
1335 270, 235, 205, 175, 150, 125, 105, 85,
1336 65, 50, 40, 25, 15
1337 };
1338
1339 int i;
1340 u32 x;
1341
1342 /* It seems that their quality parameter is somehow per signal
1343 * and is now transferred per bit.
1344 */
64f222cc 1345 switch (zd_rate) {
e85d0918
DD		 1346 case ZD_OFDM_RATE_6M:
1347 case ZD_OFDM_RATE_12M:
1348 case ZD_OFDM_RATE_24M:
1349 size *= 2;
1350 break;
1351 case ZD_OFDM_RATE_9M:
1352 case ZD_OFDM_RATE_18M:
1353 case ZD_OFDM_RATE_36M:
1354 case ZD_OFDM_RATE_54M:
1355 size *= 4;
1356 size /= 3;
1357 break;
1358 case ZD_OFDM_RATE_48M:
1359 size *= 3;
1360 size /= 2;
1361 break;
1362 default:
1363 return -EINVAL;
1364 }
1365
1366 x = (10000 * status_quality)/size;
1367 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1368 if (x > constants[i])
1369 break;
1370 }
1371
64f222cc 1372 switch (zd_rate) {
db888aed
UK		 1373 case ZD_OFDM_RATE_6M:
1374 case ZD_OFDM_RATE_9M:
1375 i += 3;
1376 break;
1377 case ZD_OFDM_RATE_12M:
1378 case ZD_OFDM_RATE_18M:
1379 i += 5;
1380 break;
1381 case ZD_OFDM_RATE_24M:
1382 case ZD_OFDM_RATE_36M:
1383 i += 9;
1384 break;
1385 case ZD_OFDM_RATE_48M:
1386 case ZD_OFDM_RATE_54M:
1387 i += 15;
1388 break;
1389 default:
1390 return -EINVAL;
1391 }
1392
e85d0918
DD		 1393 return i;
1394}
1395
64f222cc 1396static int ofdm_qual_percent(u8 status_quality, u8 zd_rate, unsigned int size)
db888aed
UK		 1397{
1398 int r;
1399
64f222cc 1400 r = ofdm_qual_db(status_quality, zd_rate, size);
db888aed
UK		 1401 ZD_ASSERT(r >= 0);
1402 if (r < 0)
1403 r = 0;
1404
1405 r = (r * 100)/29;
1406 return r <= 100 ? r : 100;
1407}
1408
e85d0918
DD		 1409static unsigned int log10times100(unsigned int x)
1410{
1411 static const u8 log10[] = {
1412 0,
1413 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1414 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1415 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1416 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1417 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1418 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1419 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1420 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1421 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1422 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1423 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1424 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1425 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1426 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1427 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1428 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1429 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1430 223, 223, 223, 224, 224, 224, 224,
1431 };
1432
1433 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1434}
1435
1436enum {
1437 MAX_CCK_EVM_DB = 45,
1438};
1439
1440static int cck_evm_db(u8 status_quality)
1441{
1442 return (20 * log10times100(status_quality)) / 100;
1443}
1444
1445static int cck_snr_db(u8 status_quality)
1446{
1447 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1448 ZD_ASSERT(r >= 0);
1449 return r;
1450}
1451
db888aed 1452static int cck_qual_percent(u8 status_quality)
e85d0918 1453{
db888aed
UK		 1454 int r;
1455
1456 r = cck_snr_db(status_quality);
1457 r = (100*r)/17;
1458 return r <= 100 ? r : 100;
e85d0918
DD		 1459}
1460
64f222cc
UK		 1461static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame)
1462{
1463 return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame);
1464}
1465
e85d0918
DD		 1466u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1467 const struct rx_status *status)
1468{
db888aed
UK		 1469 return (status->frame_status&ZD_RX_OFDM) ?
1470 ofdm_qual_percent(status->signal_quality_ofdm,
64f222cc 1471 zd_rate_from_ofdm_plcp_header(rx_frame),
db888aed
UK		 1472 size) :
1473 cck_qual_percent(status->signal_quality_cck);
e85d0918
DD		 1474}
1475
1476u8 zd_rx_strength_percent(u8 rssi)
1477{
db888aed 1478 int r = (rssi*100) / 41;
e85d0918
DD		 1479 if (r > 100)
1480 r = 100;
1481 return (u8) r;
1482}
1483
1484u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1485{
1486 static const u16 ofdm_rates[] = {
64f222cc
UK		 1487 [ZD_OFDM_PLCP_RATE_6M] = 60,
1488 [ZD_OFDM_PLCP_RATE_9M] = 90,
1489 [ZD_OFDM_PLCP_RATE_12M] = 120,
1490 [ZD_OFDM_PLCP_RATE_18M] = 180,
1491 [ZD_OFDM_PLCP_RATE_24M] = 240,
1492 [ZD_OFDM_PLCP_RATE_36M] = 360,
1493 [ZD_OFDM_PLCP_RATE_48M] = 480,
1494 [ZD_OFDM_PLCP_RATE_54M] = 540,
e85d0918
DD		 1495 };
1496 u16 rate;
1497 if (status->frame_status & ZD_RX_OFDM) {
64f222cc 1498 /* Deals with PLCP OFDM rate (not zd_rates) */
e85d0918
DD		 1499 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1500 rate = ofdm_rates[ofdm_rate & 0xf];
1501 } else {
64f222cc
UK		 1502 switch (zd_cck_plcp_header_signal(rx_frame)) {
1503 case ZD_CCK_PLCP_SIGNAL_1M:
e85d0918
DD		 1504 rate = 10;
1505 break;
64f222cc 1506 case ZD_CCK_PLCP_SIGNAL_2M:
e85d0918
DD		 1507 rate = 20;
1508 break;
64f222cc 1509 case ZD_CCK_PLCP_SIGNAL_5M5:
e85d0918
DD		 1510 rate = 55;
1511 break;
64f222cc 1512 case ZD_CCK_PLCP_SIGNAL_11M:
e85d0918
DD		 1513 rate = 110;
1514 break;
1515 default:
1516 rate = 0;
1517 }
1518 }
1519
1520 return rate;
1521}
1522
1523int zd_chip_switch_radio_on(struct zd_chip *chip)
1524{
1525 int r;
1526
1527 mutex_lock(&chip->mutex);
1528 r = zd_switch_radio_on(&chip->rf);
1529 mutex_unlock(&chip->mutex);
1530 return r;
1531}
1532
1533int zd_chip_switch_radio_off(struct zd_chip *chip)
1534{
1535 int r;
1536
1537 mutex_lock(&chip->mutex);
1538 r = zd_switch_radio_off(&chip->rf);
1539 mutex_unlock(&chip->mutex);
1540 return r;
1541}
1542
1543int zd_chip_enable_int(struct zd_chip *chip)
1544{
1545 int r;
1546
1547 mutex_lock(&chip->mutex);
1548 r = zd_usb_enable_int(&chip->usb);
1549 mutex_unlock(&chip->mutex);
1550 return r;
1551}
1552
1553void zd_chip_disable_int(struct zd_chip *chip)
1554{
1555 mutex_lock(&chip->mutex);
1556 zd_usb_disable_int(&chip->usb);
1557 mutex_unlock(&chip->mutex);
1558}
1559
1560int zd_chip_enable_rx(struct zd_chip *chip)
1561{
1562 int r;
1563
1564 mutex_lock(&chip->mutex);
1565 r = zd_usb_enable_rx(&chip->usb);
1566 mutex_unlock(&chip->mutex);
1567 return r;
1568}
1569
1570void zd_chip_disable_rx(struct zd_chip *chip)
1571{
1572 mutex_lock(&chip->mutex);
1573 zd_usb_disable_rx(&chip->usb);
1574 mutex_unlock(&chip->mutex);
1575}
1576
1577int zd_rfwritev_locked(struct zd_chip *chip,
1578 const u32* values, unsigned int count, u8 bits)
1579{
1580 int r;
1581 unsigned int i;
1582
1583 for (i = 0; i < count; i++) {
1584 r = zd_rfwrite_locked(chip, values[i], bits);
1585 if (r)
1586 return r;
1587 }
1588
1589 return 0;
1590}
20fe2176
DD		 1591
1592/*
1593 * We can optionally program the RF directly through CR regs, if supported by
1594 * the hardware. This is much faster than the older method.
1595 */
ec62bd91 1596int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
20fe2176
DD		 1597{
1598 struct zd_ioreq16 ioreqs[] = {
1599 { CR244, (value >> 16) & 0xff },
1600 { CR243, (value >> 8) & 0xff },
1601 { CR242, value & 0xff },
1602 };
1603 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1604 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1605}
1606
1607int zd_rfwritev_cr_locked(struct zd_chip *chip,
1608 const u32 *values, unsigned int count)
1609{
1610 int r;
1611 unsigned int i;
1612
1613 for (i = 0; i < count; i++) {
1614 r = zd_rfwrite_cr_locked(chip, values[i]);
1615 if (r)
1616 return r;
1617 }
1618
1619 return 0;
1620}
9cdac965
UK		 1621
1622int zd_chip_set_multicast_hash(struct zd_chip *chip,
1623 struct zd_mc_hash *hash)
1624{
1625 struct zd_ioreq32 ioreqs[] = {
1626 { CR_GROUP_HASH_P1, hash->low },
1627 { CR_GROUP_HASH_P2, hash->high },
1628 };
1629
9cdac965
UK		 1630 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1631}
ubuntu-bionic-kernel mirror