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1 | /* zd_chip.h |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License as published by | |
5 | * the Free Software Foundation; either version 2 of the License, or | |
6 | * (at your option) any later version. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
16 | */ | |
17 | ||
18 | #ifndef _ZD_CHIP_H | |
19 | #define _ZD_CHIP_H | |
20 | ||
e85d0918 DD |
21 | #include "zd_rf.h" |
22 | #include "zd_usb.h" | |
23 | ||
24 | /* Header for the Media Access Controller (MAC) and the Baseband Processor | |
25 | * (BBP). It appears that the ZD1211 wraps the old ZD1205 with USB glue and | |
26 | * adds a processor for handling the USB protocol. | |
27 | */ | |
28 | ||
0ce34bc8 DD |
29 | /* Address space */ |
30 | enum { | |
31 | /* CONTROL REGISTERS */ | |
32 | CR_START = 0x9000, | |
33 | ||
34 | ||
35 | /* FIRMWARE */ | |
36 | FW_START = 0xee00, | |
37 | ||
38 | ||
39 | /* EEPROM */ | |
40 | E2P_START = 0xf800, | |
41 | E2P_LEN = 0x800, | |
42 | ||
43 | /* EEPROM layout */ | |
44 | E2P_LOAD_CODE_LEN = 0xe, /* base 0xf800 */ | |
45 | E2P_LOAD_VECT_LEN = 0x9, /* base 0xf80e */ | |
46 | /* E2P_DATA indexes into this */ | |
47 | E2P_DATA_LEN = 0x7e, /* base 0xf817 */ | |
48 | E2P_BOOT_CODE_LEN = 0x760, /* base 0xf895 */ | |
49 | E2P_INTR_VECT_LEN = 0xb, /* base 0xfff5 */ | |
50 | ||
51 | /* Some precomputed offsets into the EEPROM */ | |
52 | E2P_DATA_OFFSET = E2P_LOAD_CODE_LEN + E2P_LOAD_VECT_LEN, | |
53 | E2P_BOOT_CODE_OFFSET = E2P_DATA_OFFSET + E2P_DATA_LEN, | |
54 | }; | |
55 | ||
56 | #define CTL_REG(offset) ((zd_addr_t)(CR_START + (offset))) | |
57 | #define E2P_DATA(offset) ((zd_addr_t)(E2P_START + E2P_DATA_OFFSET + (offset))) | |
58 | #define FWRAW_DATA(offset) ((zd_addr_t)(FW_START + (offset))) | |
59 | ||
e85d0918 DD |
60 | /* 8-bit hardware registers */ |
61 | #define CR0 CTL_REG(0x0000) | |
62 | #define CR1 CTL_REG(0x0004) | |
63 | #define CR2 CTL_REG(0x0008) | |
64 | #define CR3 CTL_REG(0x000C) | |
65 | ||
66 | #define CR5 CTL_REG(0x0010) | |
67 | /* bit 5: if set short preamble used | |
68 | * bit 6: filter band - Japan channel 14 on, else off | |
69 | */ | |
70 | #define CR6 CTL_REG(0x0014) | |
71 | #define CR7 CTL_REG(0x0018) | |
72 | #define CR8 CTL_REG(0x001C) | |
73 | ||
74 | #define CR4 CTL_REG(0x0020) | |
75 | ||
76 | #define CR9 CTL_REG(0x0024) | |
77 | /* bit 2: antenna switch (together with CR10) */ | |
78 | #define CR10 CTL_REG(0x0028) | |
79 | /* bit 1: antenna switch (together with CR9) | |
80 | * RF2959 controls with CR11 radion on and off | |
81 | */ | |
82 | #define CR11 CTL_REG(0x002C) | |
83 | /* bit 6: TX power control for OFDM | |
84 | * RF2959 controls with CR10 radio on and off | |
85 | */ | |
86 | #define CR12 CTL_REG(0x0030) | |
87 | #define CR13 CTL_REG(0x0034) | |
88 | #define CR14 CTL_REG(0x0038) | |
89 | #define CR15 CTL_REG(0x003C) | |
90 | #define CR16 CTL_REG(0x0040) | |
91 | #define CR17 CTL_REG(0x0044) | |
92 | #define CR18 CTL_REG(0x0048) | |
93 | #define CR19 CTL_REG(0x004C) | |
94 | #define CR20 CTL_REG(0x0050) | |
95 | #define CR21 CTL_REG(0x0054) | |
96 | #define CR22 CTL_REG(0x0058) | |
97 | #define CR23 CTL_REG(0x005C) | |
98 | #define CR24 CTL_REG(0x0060) /* CCA threshold */ | |
99 | #define CR25 CTL_REG(0x0064) | |
100 | #define CR26 CTL_REG(0x0068) | |
101 | #define CR27 CTL_REG(0x006C) | |
102 | #define CR28 CTL_REG(0x0070) | |
103 | #define CR29 CTL_REG(0x0074) | |
104 | #define CR30 CTL_REG(0x0078) | |
105 | #define CR31 CTL_REG(0x007C) /* TX power control for RF in CCK mode */ | |
106 | #define CR32 CTL_REG(0x0080) | |
107 | #define CR33 CTL_REG(0x0084) | |
108 | #define CR34 CTL_REG(0x0088) | |
109 | #define CR35 CTL_REG(0x008C) | |
110 | #define CR36 CTL_REG(0x0090) | |
111 | #define CR37 CTL_REG(0x0094) | |
112 | #define CR38 CTL_REG(0x0098) | |
113 | #define CR39 CTL_REG(0x009C) | |
114 | #define CR40 CTL_REG(0x00A0) | |
115 | #define CR41 CTL_REG(0x00A4) | |
116 | #define CR42 CTL_REG(0x00A8) | |
117 | #define CR43 CTL_REG(0x00AC) | |
118 | #define CR44 CTL_REG(0x00B0) | |
119 | #define CR45 CTL_REG(0x00B4) | |
120 | #define CR46 CTL_REG(0x00B8) | |
121 | #define CR47 CTL_REG(0x00BC) /* CCK baseband gain | |
122 | * (patch value might be in EEPROM) | |
123 | */ | |
124 | #define CR48 CTL_REG(0x00C0) | |
125 | #define CR49 CTL_REG(0x00C4) | |
126 | #define CR50 CTL_REG(0x00C8) | |
127 | #define CR51 CTL_REG(0x00CC) /* TX power control for RF in 6-36M modes */ | |
128 | #define CR52 CTL_REG(0x00D0) /* TX power control for RF in 48M mode */ | |
129 | #define CR53 CTL_REG(0x00D4) /* TX power control for RF in 54M mode */ | |
130 | #define CR54 CTL_REG(0x00D8) | |
131 | #define CR55 CTL_REG(0x00DC) | |
132 | #define CR56 CTL_REG(0x00E0) | |
133 | #define CR57 CTL_REG(0x00E4) | |
134 | #define CR58 CTL_REG(0x00E8) | |
135 | #define CR59 CTL_REG(0x00EC) | |
136 | #define CR60 CTL_REG(0x00F0) | |
137 | #define CR61 CTL_REG(0x00F4) | |
138 | #define CR62 CTL_REG(0x00F8) | |
139 | #define CR63 CTL_REG(0x00FC) | |
140 | #define CR64 CTL_REG(0x0100) | |
141 | #define CR65 CTL_REG(0x0104) /* OFDM 54M calibration */ | |
142 | #define CR66 CTL_REG(0x0108) /* OFDM 48M calibration */ | |
143 | #define CR67 CTL_REG(0x010C) /* OFDM 36M calibration */ | |
144 | #define CR68 CTL_REG(0x0110) /* CCK calibration */ | |
145 | #define CR69 CTL_REG(0x0114) | |
146 | #define CR70 CTL_REG(0x0118) | |
147 | #define CR71 CTL_REG(0x011C) | |
148 | #define CR72 CTL_REG(0x0120) | |
149 | #define CR73 CTL_REG(0x0124) | |
150 | #define CR74 CTL_REG(0x0128) | |
151 | #define CR75 CTL_REG(0x012C) | |
152 | #define CR76 CTL_REG(0x0130) | |
153 | #define CR77 CTL_REG(0x0134) | |
154 | #define CR78 CTL_REG(0x0138) | |
155 | #define CR79 CTL_REG(0x013C) | |
156 | #define CR80 CTL_REG(0x0140) | |
157 | #define CR81 CTL_REG(0x0144) | |
158 | #define CR82 CTL_REG(0x0148) | |
159 | #define CR83 CTL_REG(0x014C) | |
160 | #define CR84 CTL_REG(0x0150) | |
161 | #define CR85 CTL_REG(0x0154) | |
162 | #define CR86 CTL_REG(0x0158) | |
163 | #define CR87 CTL_REG(0x015C) | |
164 | #define CR88 CTL_REG(0x0160) | |
165 | #define CR89 CTL_REG(0x0164) | |
166 | #define CR90 CTL_REG(0x0168) | |
167 | #define CR91 CTL_REG(0x016C) | |
168 | #define CR92 CTL_REG(0x0170) | |
169 | #define CR93 CTL_REG(0x0174) | |
170 | #define CR94 CTL_REG(0x0178) | |
171 | #define CR95 CTL_REG(0x017C) | |
172 | #define CR96 CTL_REG(0x0180) | |
173 | #define CR97 CTL_REG(0x0184) | |
174 | #define CR98 CTL_REG(0x0188) | |
175 | #define CR99 CTL_REG(0x018C) | |
176 | #define CR100 CTL_REG(0x0190) | |
177 | #define CR101 CTL_REG(0x0194) | |
178 | #define CR102 CTL_REG(0x0198) | |
179 | #define CR103 CTL_REG(0x019C) | |
180 | #define CR104 CTL_REG(0x01A0) | |
181 | #define CR105 CTL_REG(0x01A4) | |
182 | #define CR106 CTL_REG(0x01A8) | |
183 | #define CR107 CTL_REG(0x01AC) | |
184 | #define CR108 CTL_REG(0x01B0) | |
185 | #define CR109 CTL_REG(0x01B4) | |
186 | #define CR110 CTL_REG(0x01B8) | |
187 | #define CR111 CTL_REG(0x01BC) | |
188 | #define CR112 CTL_REG(0x01C0) | |
189 | #define CR113 CTL_REG(0x01C4) | |
190 | #define CR114 CTL_REG(0x01C8) | |
191 | #define CR115 CTL_REG(0x01CC) | |
192 | #define CR116 CTL_REG(0x01D0) | |
193 | #define CR117 CTL_REG(0x01D4) | |
194 | #define CR118 CTL_REG(0x01D8) | |
195 | #define CR119 CTL_REG(0x01DC) | |
196 | #define CR120 CTL_REG(0x01E0) | |
197 | #define CR121 CTL_REG(0x01E4) | |
198 | #define CR122 CTL_REG(0x01E8) | |
199 | #define CR123 CTL_REG(0x01EC) | |
200 | #define CR124 CTL_REG(0x01F0) | |
201 | #define CR125 CTL_REG(0x01F4) | |
202 | #define CR126 CTL_REG(0x01F8) | |
203 | #define CR127 CTL_REG(0x01FC) | |
204 | #define CR128 CTL_REG(0x0200) | |
205 | #define CR129 CTL_REG(0x0204) | |
206 | #define CR130 CTL_REG(0x0208) | |
207 | #define CR131 CTL_REG(0x020C) | |
208 | #define CR132 CTL_REG(0x0210) | |
209 | #define CR133 CTL_REG(0x0214) | |
210 | #define CR134 CTL_REG(0x0218) | |
211 | #define CR135 CTL_REG(0x021C) | |
212 | #define CR136 CTL_REG(0x0220) | |
213 | #define CR137 CTL_REG(0x0224) | |
214 | #define CR138 CTL_REG(0x0228) | |
215 | #define CR139 CTL_REG(0x022C) | |
216 | #define CR140 CTL_REG(0x0230) | |
217 | #define CR141 CTL_REG(0x0234) | |
218 | #define CR142 CTL_REG(0x0238) | |
219 | #define CR143 CTL_REG(0x023C) | |
220 | #define CR144 CTL_REG(0x0240) | |
221 | #define CR145 CTL_REG(0x0244) | |
222 | #define CR146 CTL_REG(0x0248) | |
223 | #define CR147 CTL_REG(0x024C) | |
224 | #define CR148 CTL_REG(0x0250) | |
225 | #define CR149 CTL_REG(0x0254) | |
226 | #define CR150 CTL_REG(0x0258) | |
227 | #define CR151 CTL_REG(0x025C) | |
228 | #define CR152 CTL_REG(0x0260) | |
229 | #define CR153 CTL_REG(0x0264) | |
230 | #define CR154 CTL_REG(0x0268) | |
231 | #define CR155 CTL_REG(0x026C) | |
232 | #define CR156 CTL_REG(0x0270) | |
233 | #define CR157 CTL_REG(0x0274) | |
234 | #define CR158 CTL_REG(0x0278) | |
235 | #define CR159 CTL_REG(0x027C) | |
236 | #define CR160 CTL_REG(0x0280) | |
237 | #define CR161 CTL_REG(0x0284) | |
238 | #define CR162 CTL_REG(0x0288) | |
239 | #define CR163 CTL_REG(0x028C) | |
240 | #define CR164 CTL_REG(0x0290) | |
241 | #define CR165 CTL_REG(0x0294) | |
242 | #define CR166 CTL_REG(0x0298) | |
243 | #define CR167 CTL_REG(0x029C) | |
244 | #define CR168 CTL_REG(0x02A0) | |
245 | #define CR169 CTL_REG(0x02A4) | |
246 | #define CR170 CTL_REG(0x02A8) | |
247 | #define CR171 CTL_REG(0x02AC) | |
248 | #define CR172 CTL_REG(0x02B0) | |
249 | #define CR173 CTL_REG(0x02B4) | |
250 | #define CR174 CTL_REG(0x02B8) | |
251 | #define CR175 CTL_REG(0x02BC) | |
252 | #define CR176 CTL_REG(0x02C0) | |
253 | #define CR177 CTL_REG(0x02C4) | |
254 | #define CR178 CTL_REG(0x02C8) | |
255 | #define CR179 CTL_REG(0x02CC) | |
256 | #define CR180 CTL_REG(0x02D0) | |
257 | #define CR181 CTL_REG(0x02D4) | |
258 | #define CR182 CTL_REG(0x02D8) | |
259 | #define CR183 CTL_REG(0x02DC) | |
260 | #define CR184 CTL_REG(0x02E0) | |
261 | #define CR185 CTL_REG(0x02E4) | |
262 | #define CR186 CTL_REG(0x02E8) | |
263 | #define CR187 CTL_REG(0x02EC) | |
264 | #define CR188 CTL_REG(0x02F0) | |
265 | #define CR189 CTL_REG(0x02F4) | |
266 | #define CR190 CTL_REG(0x02F8) | |
267 | #define CR191 CTL_REG(0x02FC) | |
268 | #define CR192 CTL_REG(0x0300) | |
269 | #define CR193 CTL_REG(0x0304) | |
270 | #define CR194 CTL_REG(0x0308) | |
271 | #define CR195 CTL_REG(0x030C) | |
272 | #define CR196 CTL_REG(0x0310) | |
273 | #define CR197 CTL_REG(0x0314) | |
274 | #define CR198 CTL_REG(0x0318) | |
275 | #define CR199 CTL_REG(0x031C) | |
276 | #define CR200 CTL_REG(0x0320) | |
277 | #define CR201 CTL_REG(0x0324) | |
278 | #define CR202 CTL_REG(0x0328) | |
279 | #define CR203 CTL_REG(0x032C) /* I2C bus template value & flash control */ | |
280 | #define CR204 CTL_REG(0x0330) | |
281 | #define CR205 CTL_REG(0x0334) | |
282 | #define CR206 CTL_REG(0x0338) | |
283 | #define CR207 CTL_REG(0x033C) | |
284 | #define CR208 CTL_REG(0x0340) | |
285 | #define CR209 CTL_REG(0x0344) | |
286 | #define CR210 CTL_REG(0x0348) | |
287 | #define CR211 CTL_REG(0x034C) | |
288 | #define CR212 CTL_REG(0x0350) | |
289 | #define CR213 CTL_REG(0x0354) | |
290 | #define CR214 CTL_REG(0x0358) | |
291 | #define CR215 CTL_REG(0x035C) | |
292 | #define CR216 CTL_REG(0x0360) | |
293 | #define CR217 CTL_REG(0x0364) | |
294 | #define CR218 CTL_REG(0x0368) | |
295 | #define CR219 CTL_REG(0x036C) | |
296 | #define CR220 CTL_REG(0x0370) | |
297 | #define CR221 CTL_REG(0x0374) | |
298 | #define CR222 CTL_REG(0x0378) | |
299 | #define CR223 CTL_REG(0x037C) | |
300 | #define CR224 CTL_REG(0x0380) | |
301 | #define CR225 CTL_REG(0x0384) | |
302 | #define CR226 CTL_REG(0x0388) | |
303 | #define CR227 CTL_REG(0x038C) | |
304 | #define CR228 CTL_REG(0x0390) | |
305 | #define CR229 CTL_REG(0x0394) | |
306 | #define CR230 CTL_REG(0x0398) | |
307 | #define CR231 CTL_REG(0x039C) | |
308 | #define CR232 CTL_REG(0x03A0) | |
309 | #define CR233 CTL_REG(0x03A4) | |
310 | #define CR234 CTL_REG(0x03A8) | |
311 | #define CR235 CTL_REG(0x03AC) | |
312 | #define CR236 CTL_REG(0x03B0) | |
313 | ||
314 | #define CR240 CTL_REG(0x03C0) | |
315 | /* bit 7: host-controlled RF register writes | |
316 | * CR241-CR245: for hardware controlled writing of RF bits, not needed for | |
317 | * USB | |
318 | */ | |
319 | #define CR241 CTL_REG(0x03C4) | |
320 | #define CR242 CTL_REG(0x03C8) | |
321 | #define CR243 CTL_REG(0x03CC) | |
322 | #define CR244 CTL_REG(0x03D0) | |
323 | #define CR245 CTL_REG(0x03D4) | |
324 | ||
325 | #define CR251 CTL_REG(0x03EC) /* only used for activation and deactivation of | |
326 | * Airoha RFs AL2230 and AL7230B | |
327 | */ | |
328 | #define CR252 CTL_REG(0x03F0) | |
329 | #define CR253 CTL_REG(0x03F4) | |
330 | #define CR254 CTL_REG(0x03F8) | |
331 | #define CR255 CTL_REG(0x03FC) | |
332 | ||
333 | #define CR_MAX_PHY_REG 255 | |
334 | ||
0ce34bc8 | 335 | /* Taken from the ZYDAS driver, not all of them are relevant for the ZD1211 |
e85d0918 DD |
336 | * driver. |
337 | */ | |
338 | ||
339 | #define CR_RF_IF_CLK CTL_REG(0x0400) | |
340 | #define CR_RF_IF_DATA CTL_REG(0x0404) | |
341 | #define CR_PE1_PE2 CTL_REG(0x0408) | |
342 | #define CR_PE2_DLY CTL_REG(0x040C) | |
343 | #define CR_LE1 CTL_REG(0x0410) | |
344 | #define CR_LE2 CTL_REG(0x0414) | |
345 | /* Seems to enable/disable GPI (General Purpose IO?) */ | |
346 | #define CR_GPI_EN CTL_REG(0x0418) | |
347 | #define CR_RADIO_PD CTL_REG(0x042C) | |
348 | #define CR_RF2948_PD CTL_REG(0x042C) | |
349 | #define CR_ENABLE_PS_MANUAL_AGC CTL_REG(0x043C) | |
350 | #define CR_CONFIG_PHILIPS CTL_REG(0x0440) | |
351 | #define CR_SA2400_SER_AP CTL_REG(0x0444) | |
352 | #define CR_I2C_WRITE CTL_REG(0x0444) | |
353 | #define CR_SA2400_SER_RP CTL_REG(0x0448) | |
354 | #define CR_RADIO_PE CTL_REG(0x0458) | |
355 | #define CR_RST_BUS_MASTER CTL_REG(0x045C) | |
356 | #define CR_RFCFG CTL_REG(0x0464) | |
357 | #define CR_HSTSCHG CTL_REG(0x046C) | |
358 | #define CR_PHY_ON CTL_REG(0x0474) | |
359 | #define CR_RX_DELAY CTL_REG(0x0478) | |
360 | #define CR_RX_PE_DELAY CTL_REG(0x047C) | |
361 | #define CR_GPIO_1 CTL_REG(0x0490) | |
362 | #define CR_GPIO_2 CTL_REG(0x0494) | |
363 | #define CR_EncryBufMux CTL_REG(0x04A8) | |
364 | #define CR_PS_CTRL CTL_REG(0x0500) | |
365 | #define CR_ADDA_PWR_DWN CTL_REG(0x0504) | |
366 | #define CR_ADDA_MBIAS_WARMTIME CTL_REG(0x0508) | |
367 | #define CR_MAC_PS_STATE CTL_REG(0x050C) | |
368 | ||
369 | #define CR_INTERRUPT CTL_REG(0x0510) | |
741fec53 UK |
370 | #define INT_TX_COMPLETE (1 << 0) |
371 | #define INT_RX_COMPLETE (1 << 1) | |
372 | #define INT_RETRY_FAIL (1 << 2) | |
373 | #define INT_WAKEUP (1 << 3) | |
374 | #define INT_DTIM_NOTIFY (1 << 5) | |
375 | #define INT_CFG_NEXT_BCN (1 << 6) | |
376 | #define INT_BUS_ABORT (1 << 7) | |
377 | #define INT_TX_FIFO_READY (1 << 8) | |
378 | #define INT_UART (1 << 9) | |
379 | #define INT_TX_COMPLETE_EN (1 << 16) | |
380 | #define INT_RX_COMPLETE_EN (1 << 17) | |
381 | #define INT_RETRY_FAIL_EN (1 << 18) | |
382 | #define INT_WAKEUP_EN (1 << 19) | |
383 | #define INT_DTIM_NOTIFY_EN (1 << 21) | |
384 | #define INT_CFG_NEXT_BCN_EN (1 << 22) | |
385 | #define INT_BUS_ABORT_EN (1 << 23) | |
386 | #define INT_TX_FIFO_READY_EN (1 << 24) | |
387 | #define INT_UART_EN (1 << 25) | |
e85d0918 DD |
388 | |
389 | #define CR_TSF_LOW_PART CTL_REG(0x0514) | |
390 | #define CR_TSF_HIGH_PART CTL_REG(0x0518) | |
391 | ||
392 | /* Following three values are in time units (1024us) | |
393 | * Following condition must be met: | |
394 | * atim < tbtt < bcn | |
395 | */ | |
396 | #define CR_ATIM_WND_PERIOD CTL_REG(0x051C) | |
397 | #define CR_BCN_INTERVAL CTL_REG(0x0520) | |
398 | #define CR_PRE_TBTT CTL_REG(0x0524) | |
399 | /* in units of TU(1024us) */ | |
400 | ||
401 | /* for UART support */ | |
402 | #define CR_UART_RBR_THR_DLL CTL_REG(0x0540) | |
403 | #define CR_UART_DLM_IER CTL_REG(0x0544) | |
404 | #define CR_UART_IIR_FCR CTL_REG(0x0548) | |
405 | #define CR_UART_LCR CTL_REG(0x054c) | |
406 | #define CR_UART_MCR CTL_REG(0x0550) | |
407 | #define CR_UART_LSR CTL_REG(0x0554) | |
408 | #define CR_UART_MSR CTL_REG(0x0558) | |
409 | #define CR_UART_ECR CTL_REG(0x055c) | |
410 | #define CR_UART_STATUS CTL_REG(0x0560) | |
411 | ||
412 | #define CR_PCI_TX_ADDR_P1 CTL_REG(0x0600) | |
413 | #define CR_PCI_TX_AddR_P2 CTL_REG(0x0604) | |
414 | #define CR_PCI_RX_AddR_P1 CTL_REG(0x0608) | |
415 | #define CR_PCI_RX_AddR_P2 CTL_REG(0x060C) | |
416 | ||
417 | /* must be overwritten if custom MAC address will be used */ | |
418 | #define CR_MAC_ADDR_P1 CTL_REG(0x0610) | |
419 | #define CR_MAC_ADDR_P2 CTL_REG(0x0614) | |
420 | #define CR_BSSID_P1 CTL_REG(0x0618) | |
421 | #define CR_BSSID_P2 CTL_REG(0x061C) | |
422 | #define CR_BCN_PLCP_CFG CTL_REG(0x0620) | |
9cdac965 UK |
423 | |
424 | /* Group hash table for filtering incoming packets. | |
425 | * | |
426 | * The group hash table is 64 bit large and split over two parts. The first | |
427 | * part is the lower part. The upper 6 bits of the last byte of the target | |
428 | * address are used as index. Packets are received if the hash table bit is | |
429 | * set. This is used for multicast handling, but for broadcasts (address | |
430 | * ff:ff:ff:ff:ff:ff) the highest bit in the second table must also be set. | |
431 | */ | |
e85d0918 DD |
432 | #define CR_GROUP_HASH_P1 CTL_REG(0x0624) |
433 | #define CR_GROUP_HASH_P2 CTL_REG(0x0628) | |
e85d0918 | 434 | |
9cdac965 | 435 | #define CR_RX_TIMEOUT CTL_REG(0x062C) |
e85d0918 DD |
436 | /* Basic rates supported by the BSS. When producing ACK or CTS messages, the |
437 | * device will use a rate in this table that is less than or equal to the rate | |
438 | * of the incoming frame which prompted the response */ | |
439 | #define CR_BASIC_RATE_TBL CTL_REG(0x0630) | |
741fec53 UK |
440 | #define CR_RATE_1M (1 << 0) /* 802.11b */ |
441 | #define CR_RATE_2M (1 << 1) /* 802.11b */ | |
442 | #define CR_RATE_5_5M (1 << 2) /* 802.11b */ | |
443 | #define CR_RATE_11M (1 << 3) /* 802.11b */ | |
444 | #define CR_RATE_6M (1 << 8) /* 802.11g */ | |
445 | #define CR_RATE_9M (1 << 9) /* 802.11g */ | |
446 | #define CR_RATE_12M (1 << 10) /* 802.11g */ | |
447 | #define CR_RATE_18M (1 << 11) /* 802.11g */ | |
448 | #define CR_RATE_24M (1 << 12) /* 802.11g */ | |
449 | #define CR_RATE_36M (1 << 13) /* 802.11g */ | |
450 | #define CR_RATE_48M (1 << 14) /* 802.11g */ | |
451 | #define CR_RATE_54M (1 << 15) /* 802.11g */ | |
e85d0918 DD |
452 | #define CR_RATES_80211G 0xff00 |
453 | #define CR_RATES_80211B 0x000f | |
454 | ||
455 | /* Mandatory rates required in the BSS. When producing ACK or CTS messages, if | |
456 | * the device could not find an appropriate rate in CR_BASIC_RATE_TBL, it will | |
457 | * look for a rate in this table that is less than or equal to the rate of | |
458 | * the incoming frame. */ | |
459 | #define CR_MANDATORY_RATE_TBL CTL_REG(0x0634) | |
460 | #define CR_RTS_CTS_RATE CTL_REG(0x0638) | |
461 | ||
b1382ede DD |
462 | /* These are all bit indexes in CR_RTS_CTS_RATE, so remember to shift. */ |
463 | #define RTSCTS_SH_RTS_RATE 0 | |
464 | #define RTSCTS_SH_EXP_CTS_RATE 4 | |
465 | #define RTSCTS_SH_RTS_MOD_TYPE 8 | |
466 | #define RTSCTS_SH_RTS_PMB_TYPE 9 | |
467 | #define RTSCTS_SH_CTS_RATE 16 | |
468 | #define RTSCTS_SH_CTS_MOD_TYPE 24 | |
469 | #define RTSCTS_SH_CTS_PMB_TYPE 25 | |
470 | ||
e85d0918 DD |
471 | #define CR_WEP_PROTECT CTL_REG(0x063C) |
472 | #define CR_RX_THRESHOLD CTL_REG(0x0640) | |
473 | ||
474 | /* register for controlling the LEDS */ | |
475 | #define CR_LED CTL_REG(0x0644) | |
476 | /* masks for controlling LEDs */ | |
741fec53 UK |
477 | #define LED1 (1 << 8) |
478 | #define LED2 (1 << 9) | |
479 | #define LED_SW (1 << 10) | |
e85d0918 DD |
480 | |
481 | /* Seems to indicate that the configuration is over. | |
482 | */ | |
483 | #define CR_AFTER_PNP CTL_REG(0x0648) | |
484 | #define CR_ACK_TIME_80211 CTL_REG(0x0658) | |
485 | ||
486 | #define CR_RX_OFFSET CTL_REG(0x065c) | |
487 | ||
488 | #define CR_PHY_DELAY CTL_REG(0x066C) | |
489 | #define CR_BCN_FIFO CTL_REG(0x0670) | |
490 | #define CR_SNIFFER_ON CTL_REG(0x0674) | |
491 | ||
492 | #define CR_ENCRYPTION_TYPE CTL_REG(0x0678) | |
493 | #define NO_WEP 0 | |
494 | #define WEP64 1 | |
495 | #define WEP128 5 | |
496 | #define WEP256 6 | |
497 | #define ENC_SNIFFER 8 | |
498 | ||
499 | #define CR_ZD1211_RETRY_MAX CTL_REG(0x067C) | |
500 | ||
501 | #define CR_REG1 CTL_REG(0x0680) | |
502 | /* Setting the bit UNLOCK_PHY_REGS disallows the write access to physical | |
503 | * registers, so one could argue it is a LOCK bit. But calling it | |
504 | * LOCK_PHY_REGS makes it confusing. | |
505 | */ | |
741fec53 | 506 | #define UNLOCK_PHY_REGS (1 << 7) |
e85d0918 DD |
507 | |
508 | #define CR_DEVICE_STATE CTL_REG(0x0684) | |
509 | #define CR_UNDERRUN_CNT CTL_REG(0x0688) | |
510 | ||
511 | #define CR_RX_FILTER CTL_REG(0x068c) | |
741fec53 UK |
512 | #define RX_FILTER_ASSOC_RESPONSE (1 << 1) |
513 | #define RX_FILTER_REASSOC_RESPONSE (1 << 3) | |
514 | #define RX_FILTER_PROBE_RESPONSE (1 << 5) | |
515 | #define RX_FILTER_BEACON (1 << 8) | |
516 | #define RX_FILTER_DISASSOC (1 << 10) | |
517 | #define RX_FILTER_AUTH (1 << 11) | |
fde627b5 UK |
518 | #define AP_RX_FILTER 0x0400feff |
519 | #define STA_RX_FILTER 0x0000ffff | |
520 | ||
71eae25e | 521 | /* Monitor mode sets filter to 0xfffff */ |
e85d0918 DD |
522 | |
523 | #define CR_ACK_TIMEOUT_EXT CTL_REG(0x0690) | |
524 | #define CR_BCN_FIFO_SEMAPHORE CTL_REG(0x0694) | |
98227a90 | 525 | |
e85d0918 | 526 | #define CR_IFS_VALUE CTL_REG(0x0698) |
98227a90 DD |
527 | #define IFS_VALUE_DIFS_SH 0 |
528 | #define IFS_VALUE_EIFS_SH 12 | |
529 | #define IFS_VALUE_SIFS_SH 24 | |
530 | #define IFS_VALUE_DEFAULT (( 50 << IFS_VALUE_DIFS_SH) | \ | |
531 | (1148 << IFS_VALUE_EIFS_SH) | \ | |
532 | ( 10 << IFS_VALUE_SIFS_SH)) | |
533 | ||
e85d0918 DD |
534 | #define CR_RX_TIME_OUT CTL_REG(0x069C) |
535 | #define CR_TOTAL_RX_FRM CTL_REG(0x06A0) | |
536 | #define CR_CRC32_CNT CTL_REG(0x06A4) | |
537 | #define CR_CRC16_CNT CTL_REG(0x06A8) | |
538 | #define CR_DECRYPTION_ERR_UNI CTL_REG(0x06AC) | |
539 | #define CR_RX_FIFO_OVERRUN CTL_REG(0x06B0) | |
540 | ||
541 | #define CR_DECRYPTION_ERR_MUL CTL_REG(0x06BC) | |
542 | ||
543 | #define CR_NAV_CNT CTL_REG(0x06C4) | |
544 | #define CR_NAV_CCA CTL_REG(0x06C8) | |
545 | #define CR_RETRY_CNT CTL_REG(0x06CC) | |
546 | ||
547 | #define CR_READ_TCB_ADDR CTL_REG(0x06E8) | |
548 | #define CR_READ_RFD_ADDR CTL_REG(0x06EC) | |
549 | #define CR_CWMIN_CWMAX CTL_REG(0x06F0) | |
550 | #define CR_TOTAL_TX_FRM CTL_REG(0x06F4) | |
551 | ||
552 | /* CAM: Continuous Access Mode (power management) */ | |
553 | #define CR_CAM_MODE CTL_REG(0x0700) | |
554 | #define CR_CAM_ROLL_TB_LOW CTL_REG(0x0704) | |
555 | #define CR_CAM_ROLL_TB_HIGH CTL_REG(0x0708) | |
556 | #define CR_CAM_ADDRESS CTL_REG(0x070C) | |
557 | #define CR_CAM_DATA CTL_REG(0x0710) | |
558 | ||
559 | #define CR_ROMDIR CTL_REG(0x0714) | |
560 | ||
561 | #define CR_DECRY_ERR_FLG_LOW CTL_REG(0x0714) | |
562 | #define CR_DECRY_ERR_FLG_HIGH CTL_REG(0x0718) | |
563 | ||
564 | #define CR_WEPKEY0 CTL_REG(0x0720) | |
565 | #define CR_WEPKEY1 CTL_REG(0x0724) | |
566 | #define CR_WEPKEY2 CTL_REG(0x0728) | |
567 | #define CR_WEPKEY3 CTL_REG(0x072C) | |
568 | #define CR_WEPKEY4 CTL_REG(0x0730) | |
569 | #define CR_WEPKEY5 CTL_REG(0x0734) | |
570 | #define CR_WEPKEY6 CTL_REG(0x0738) | |
571 | #define CR_WEPKEY7 CTL_REG(0x073C) | |
572 | #define CR_WEPKEY8 CTL_REG(0x0740) | |
573 | #define CR_WEPKEY9 CTL_REG(0x0744) | |
574 | #define CR_WEPKEY10 CTL_REG(0x0748) | |
575 | #define CR_WEPKEY11 CTL_REG(0x074C) | |
576 | #define CR_WEPKEY12 CTL_REG(0x0750) | |
577 | #define CR_WEPKEY13 CTL_REG(0x0754) | |
578 | #define CR_WEPKEY14 CTL_REG(0x0758) | |
579 | #define CR_WEPKEY15 CTL_REG(0x075c) | |
580 | #define CR_TKIP_MODE CTL_REG(0x0760) | |
581 | ||
582 | #define CR_EEPROM_PROTECT0 CTL_REG(0x0758) | |
583 | #define CR_EEPROM_PROTECT1 CTL_REG(0x075C) | |
584 | ||
585 | #define CR_DBG_FIFO_RD CTL_REG(0x0800) | |
586 | #define CR_DBG_SELECT CTL_REG(0x0804) | |
587 | #define CR_FIFO_Length CTL_REG(0x0808) | |
588 | ||
589 | ||
590 | #define CR_RSSI_MGC CTL_REG(0x0810) | |
591 | ||
592 | #define CR_PON CTL_REG(0x0818) | |
593 | #define CR_RX_ON CTL_REG(0x081C) | |
594 | #define CR_TX_ON CTL_REG(0x0820) | |
595 | #define CR_CHIP_EN CTL_REG(0x0824) | |
596 | #define CR_LO_SW CTL_REG(0x0828) | |
597 | #define CR_TXRX_SW CTL_REG(0x082C) | |
598 | #define CR_S_MD CTL_REG(0x0830) | |
599 | ||
600 | #define CR_USB_DEBUG_PORT CTL_REG(0x0888) | |
601 | ||
602 | #define CR_ZD1211B_TX_PWR_CTL1 CTL_REG(0x0b00) | |
603 | #define CR_ZD1211B_TX_PWR_CTL2 CTL_REG(0x0b04) | |
604 | #define CR_ZD1211B_TX_PWR_CTL3 CTL_REG(0x0b08) | |
605 | #define CR_ZD1211B_TX_PWR_CTL4 CTL_REG(0x0b0c) | |
606 | #define CR_ZD1211B_AIFS_CTL1 CTL_REG(0x0b10) | |
607 | #define CR_ZD1211B_AIFS_CTL2 CTL_REG(0x0b14) | |
608 | #define CR_ZD1211B_TXOP CTL_REG(0x0b20) | |
609 | #define CR_ZD1211B_RETRY_MAX CTL_REG(0x0b28) | |
610 | ||
4481d609 DD |
611 | /* Used to detect PLL lock */ |
612 | #define UW2453_INTR_REG ((zd_addr_t)0x85c1) | |
613 | ||
e85d0918 DD |
614 | #define CWIN_SIZE 0x007f043f |
615 | ||
616 | ||
617 | #define HWINT_ENABLED 0x004f0000 | |
618 | #define HWINT_DISABLED 0 | |
619 | ||
620 | #define E2P_PWR_INT_GUARD 8 | |
621 | #define E2P_CHANNEL_COUNT 14 | |
622 | ||
623 | /* If you compare this addresses with the ZYDAS orignal driver, please notify | |
624 | * that we use word mapping for the EEPROM. | |
625 | */ | |
626 | ||
627 | /* | |
628 | * Upper 16 bit contains the regulatory domain. | |
629 | */ | |
ee302767 DD |
630 | #define E2P_SUBID E2P_DATA(0x00) |
631 | #define E2P_POD E2P_DATA(0x02) | |
632 | #define E2P_MAC_ADDR_P1 E2P_DATA(0x04) | |
633 | #define E2P_MAC_ADDR_P2 E2P_DATA(0x06) | |
634 | #define E2P_PWR_CAL_VALUE1 E2P_DATA(0x08) | |
635 | #define E2P_PWR_CAL_VALUE2 E2P_DATA(0x0a) | |
636 | #define E2P_PWR_CAL_VALUE3 E2P_DATA(0x0c) | |
637 | #define E2P_PWR_CAL_VALUE4 E2P_DATA(0x0e) | |
638 | #define E2P_PWR_INT_VALUE1 E2P_DATA(0x10) | |
639 | #define E2P_PWR_INT_VALUE2 E2P_DATA(0x12) | |
640 | #define E2P_PWR_INT_VALUE3 E2P_DATA(0x14) | |
641 | #define E2P_PWR_INT_VALUE4 E2P_DATA(0x16) | |
e85d0918 DD |
642 | |
643 | /* Contains a bit for each allowed channel. It gives for Europe (ETSI 0x30) | |
644 | * also only 11 channels. */ | |
ee302767 DD |
645 | #define E2P_ALLOWED_CHANNEL E2P_DATA(0x18) |
646 | ||
ee302767 | 647 | #define E2P_DEVICE_VER E2P_DATA(0x20) |
92b3e2e9 | 648 | #define E2P_PHY_REG E2P_DATA(0x25) |
ee302767 DD |
649 | #define E2P_36M_CAL_VALUE1 E2P_DATA(0x28) |
650 | #define E2P_36M_CAL_VALUE2 E2P_DATA(0x2a) | |
651 | #define E2P_36M_CAL_VALUE3 E2P_DATA(0x2c) | |
652 | #define E2P_36M_CAL_VALUE4 E2P_DATA(0x2e) | |
653 | #define E2P_11A_INT_VALUE1 E2P_DATA(0x30) | |
654 | #define E2P_11A_INT_VALUE2 E2P_DATA(0x32) | |
655 | #define E2P_11A_INT_VALUE3 E2P_DATA(0x34) | |
656 | #define E2P_11A_INT_VALUE4 E2P_DATA(0x36) | |
657 | #define E2P_48M_CAL_VALUE1 E2P_DATA(0x38) | |
658 | #define E2P_48M_CAL_VALUE2 E2P_DATA(0x3a) | |
659 | #define E2P_48M_CAL_VALUE3 E2P_DATA(0x3c) | |
660 | #define E2P_48M_CAL_VALUE4 E2P_DATA(0x3e) | |
661 | #define E2P_48M_INT_VALUE1 E2P_DATA(0x40) | |
662 | #define E2P_48M_INT_VALUE2 E2P_DATA(0x42) | |
663 | #define E2P_48M_INT_VALUE3 E2P_DATA(0x44) | |
664 | #define E2P_48M_INT_VALUE4 E2P_DATA(0x46) | |
665 | #define E2P_54M_CAL_VALUE1 E2P_DATA(0x48) /* ??? */ | |
666 | #define E2P_54M_CAL_VALUE2 E2P_DATA(0x4a) | |
667 | #define E2P_54M_CAL_VALUE3 E2P_DATA(0x4c) | |
668 | #define E2P_54M_CAL_VALUE4 E2P_DATA(0x4e) | |
669 | #define E2P_54M_INT_VALUE1 E2P_DATA(0x50) | |
670 | #define E2P_54M_INT_VALUE2 E2P_DATA(0x52) | |
671 | #define E2P_54M_INT_VALUE3 E2P_DATA(0x54) | |
672 | #define E2P_54M_INT_VALUE4 E2P_DATA(0x56) | |
e85d0918 | 673 | |
0ce34bc8 DD |
674 | /* This word contains the base address of the FW_REG_ registers below */ |
675 | #define FWRAW_REGS_ADDR FWRAW_DATA(0x1d) | |
676 | ||
677 | /* All 16 bit values, offset from the address in FWRAW_REGS_ADDR */ | |
678 | enum { | |
679 | FW_REG_FIRMWARE_VER = 0, | |
680 | /* non-zero if USB high speed connection */ | |
681 | FW_REG_USB_SPEED = 1, | |
682 | FW_REG_FIX_TX_RATE = 2, | |
683 | /* Seems to be able to control LEDs over the firmware */ | |
684 | FW_REG_LED_LINK_STATUS = 3, | |
685 | FW_REG_SOFT_RESET = 4, | |
686 | FW_REG_FLASH_CHK = 5, | |
687 | }; | |
e85d0918 | 688 | |
0ce34bc8 | 689 | /* Values for FW_LINK_STATUS */ |
583afd1e UK |
690 | #define FW_LINK_OFF 0x0 |
691 | #define FW_LINK_TX 0x1 | |
692 | /* 0x2 - link led on? */ | |
693 | ||
e85d0918 DD |
694 | enum { |
695 | /* indices for ofdm_cal_values */ | |
696 | OFDM_36M_INDEX = 0, | |
697 | OFDM_48M_INDEX = 1, | |
698 | OFDM_54M_INDEX = 2, | |
699 | }; | |
700 | ||
701 | struct zd_chip { | |
702 | struct zd_usb usb; | |
703 | struct zd_rf rf; | |
704 | struct mutex mutex; | |
0ce34bc8 DD |
705 | /* Base address of FW_REG_ registers */ |
706 | zd_addr_t fw_regs_base; | |
e85d0918 DD |
707 | /* EepSetPoint in the vendor driver */ |
708 | u8 pwr_cal_values[E2P_CHANNEL_COUNT]; | |
709 | /* integration values in the vendor driver */ | |
710 | u8 pwr_int_values[E2P_CHANNEL_COUNT]; | |
711 | /* SetPointOFDM in the vendor driver */ | |
712 | u8 ofdm_cal_values[3][E2P_CHANNEL_COUNT]; | |
583afd1e UK |
713 | u16 link_led; |
714 | unsigned int pa_type:4, | |
715 | patch_cck_gain:1, patch_cr157:1, patch_6m_band_edge:1, | |
ae6ead46 | 716 | new_phy_layout:1, al2230s_bit:1, |
74553aed | 717 | supports_tx_led:1; |
e85d0918 DD |
718 | }; |
719 | ||
720 | static inline struct zd_chip *zd_usb_to_chip(struct zd_usb *usb) | |
721 | { | |
722 | return container_of(usb, struct zd_chip, usb); | |
723 | } | |
724 | ||
725 | static inline struct zd_chip *zd_rf_to_chip(struct zd_rf *rf) | |
726 | { | |
727 | return container_of(rf, struct zd_chip, rf); | |
728 | } | |
729 | ||
730 | #define zd_chip_dev(chip) (&(chip)->usb.intf->dev) | |
731 | ||
732 | void zd_chip_init(struct zd_chip *chip, | |
733 | struct net_device *netdev, | |
734 | struct usb_interface *intf); | |
735 | void zd_chip_clear(struct zd_chip *chip); | |
74553aed DD |
736 | int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr); |
737 | int zd_chip_init_hw(struct zd_chip *chip); | |
e85d0918 DD |
738 | int zd_chip_reset(struct zd_chip *chip); |
739 | ||
74553aed DD |
740 | static inline int zd_chip_is_zd1211b(struct zd_chip *chip) |
741 | { | |
742 | return chip->usb.is_zd1211b; | |
743 | } | |
744 | ||
e85d0918 DD |
745 | static inline int zd_ioread16v_locked(struct zd_chip *chip, u16 *values, |
746 | const zd_addr_t *addresses, | |
747 | unsigned int count) | |
748 | { | |
749 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
750 | return zd_usb_ioread16v(&chip->usb, values, addresses, count); | |
751 | } | |
752 | ||
753 | static inline int zd_ioread16_locked(struct zd_chip *chip, u16 *value, | |
754 | const zd_addr_t addr) | |
755 | { | |
756 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
757 | return zd_usb_ioread16(&chip->usb, value, addr); | |
758 | } | |
759 | ||
760 | int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, | |
761 | const zd_addr_t *addresses, unsigned int count); | |
762 | ||
763 | static inline int zd_ioread32_locked(struct zd_chip *chip, u32 *value, | |
764 | const zd_addr_t addr) | |
765 | { | |
766 | return zd_ioread32v_locked(chip, value, (const zd_addr_t *)&addr, 1); | |
767 | } | |
768 | ||
769 | static inline int zd_iowrite16_locked(struct zd_chip *chip, u16 value, | |
770 | zd_addr_t addr) | |
771 | { | |
772 | struct zd_ioreq16 ioreq; | |
773 | ||
774 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
775 | ioreq.addr = addr; | |
776 | ioreq.value = value; | |
777 | ||
778 | return zd_usb_iowrite16v(&chip->usb, &ioreq, 1); | |
779 | } | |
780 | ||
781 | int zd_iowrite16a_locked(struct zd_chip *chip, | |
782 | const struct zd_ioreq16 *ioreqs, unsigned int count); | |
783 | ||
784 | int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
785 | unsigned int count); | |
786 | ||
787 | static inline int zd_iowrite32_locked(struct zd_chip *chip, u32 value, | |
788 | zd_addr_t addr) | |
789 | { | |
790 | struct zd_ioreq32 ioreq; | |
791 | ||
792 | ioreq.addr = addr; | |
793 | ioreq.value = value; | |
794 | ||
795 | return _zd_iowrite32v_locked(chip, &ioreq, 1); | |
796 | } | |
797 | ||
798 | int zd_iowrite32a_locked(struct zd_chip *chip, | |
799 | const struct zd_ioreq32 *ioreqs, unsigned int count); | |
800 | ||
801 | static inline int zd_rfwrite_locked(struct zd_chip *chip, u32 value, u8 bits) | |
802 | { | |
803 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
804 | return zd_usb_rfwrite(&chip->usb, value, bits); | |
805 | } | |
806 | ||
ec62bd91 DD |
807 | int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value); |
808 | ||
e85d0918 DD |
809 | int zd_rfwritev_locked(struct zd_chip *chip, |
810 | const u32* values, unsigned int count, u8 bits); | |
20fe2176 DD |
811 | int zd_rfwritev_cr_locked(struct zd_chip *chip, |
812 | const u32* values, unsigned int count); | |
e85d0918 DD |
813 | |
814 | /* Locking functions for reading and writing registers. | |
815 | * The different parameters are intentional. | |
816 | */ | |
817 | int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value); | |
818 | int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value); | |
819 | int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value); | |
820 | int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value); | |
821 | int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, | |
822 | u32 *values, unsigned int count); | |
823 | int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
824 | unsigned int count); | |
825 | ||
826 | int zd_chip_set_channel(struct zd_chip *chip, u8 channel); | |
827 | static inline u8 _zd_chip_get_channel(struct zd_chip *chip) | |
828 | { | |
829 | return chip->rf.channel; | |
830 | } | |
831 | u8 zd_chip_get_channel(struct zd_chip *chip); | |
832 | int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain); | |
e85d0918 DD |
833 | int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr); |
834 | int zd_chip_switch_radio_on(struct zd_chip *chip); | |
835 | int zd_chip_switch_radio_off(struct zd_chip *chip); | |
836 | int zd_chip_enable_int(struct zd_chip *chip); | |
837 | void zd_chip_disable_int(struct zd_chip *chip); | |
838 | int zd_chip_enable_rx(struct zd_chip *chip); | |
839 | void zd_chip_disable_rx(struct zd_chip *chip); | |
840 | int zd_chip_enable_hwint(struct zd_chip *chip); | |
841 | int zd_chip_disable_hwint(struct zd_chip *chip); | |
72018b22 | 842 | int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel); |
e85d0918 | 843 | |
b1382ede DD |
844 | int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, |
845 | u8 rts_rate, int preamble); | |
846 | ||
e85d0918 DD |
847 | static inline int zd_get_encryption_type(struct zd_chip *chip, u32 *type) |
848 | { | |
849 | return zd_ioread32(chip, CR_ENCRYPTION_TYPE, type); | |
850 | } | |
851 | ||
852 | static inline int zd_set_encryption_type(struct zd_chip *chip, u32 type) | |
853 | { | |
854 | return zd_iowrite32(chip, CR_ENCRYPTION_TYPE, type); | |
855 | } | |
856 | ||
857 | static inline int zd_chip_get_basic_rates(struct zd_chip *chip, u16 *cr_rates) | |
858 | { | |
859 | return zd_ioread16(chip, CR_BASIC_RATE_TBL, cr_rates); | |
860 | } | |
861 | ||
b1382ede DD |
862 | int zd_chip_set_basic_rates_locked(struct zd_chip *chip, u16 cr_rates); |
863 | ||
864 | static inline int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates) | |
865 | { | |
866 | int r; | |
867 | ||
868 | mutex_lock(&chip->mutex); | |
869 | r = zd_chip_set_basic_rates_locked(chip, cr_rates); | |
870 | mutex_unlock(&chip->mutex); | |
871 | return r; | |
872 | } | |
e85d0918 DD |
873 | |
874 | static inline int zd_chip_set_rx_filter(struct zd_chip *chip, u32 filter) | |
875 | { | |
876 | return zd_iowrite32(chip, CR_RX_FILTER, filter); | |
877 | } | |
878 | ||
879 | int zd_chip_lock_phy_regs(struct zd_chip *chip); | |
880 | int zd_chip_unlock_phy_regs(struct zd_chip *chip); | |
881 | ||
882 | enum led_status { | |
583afd1e UK |
883 | LED_OFF = 0, |
884 | LED_SCANNING = 1, | |
885 | LED_ASSOCIATED = 2, | |
e85d0918 DD |
886 | }; |
887 | ||
583afd1e | 888 | int zd_chip_control_leds(struct zd_chip *chip, enum led_status status); |
e85d0918 DD |
889 | |
890 | int zd_set_beacon_interval(struct zd_chip *chip, u32 interval); | |
891 | ||
892 | static inline int zd_get_beacon_interval(struct zd_chip *chip, u32 *interval) | |
893 | { | |
894 | return zd_ioread32(chip, CR_BCN_INTERVAL, interval); | |
895 | } | |
896 | ||
897 | struct rx_status; | |
898 | ||
899 | u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size, | |
900 | const struct rx_status *status); | |
901 | u8 zd_rx_strength_percent(u8 rssi); | |
902 | ||
903 | u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status); | |
904 | ||
9cdac965 UK |
905 | struct zd_mc_hash { |
906 | u32 low; | |
907 | u32 high; | |
908 | }; | |
909 | ||
910 | static inline void zd_mc_clear(struct zd_mc_hash *hash) | |
911 | { | |
912 | hash->low = 0; | |
913 | /* The interfaces must always received broadcasts. | |
914 | * The hash of the broadcast address ff:ff:ff:ff:ff:ff is 63. | |
915 | */ | |
916 | hash->high = 0x80000000; | |
917 | } | |
918 | ||
919 | static inline void zd_mc_add_all(struct zd_mc_hash *hash) | |
920 | { | |
921 | hash->low = hash->high = 0xffffffff; | |
922 | } | |
923 | ||
924 | static inline void zd_mc_add_addr(struct zd_mc_hash *hash, u8 *addr) | |
925 | { | |
926 | unsigned int i = addr[5] >> 2; | |
927 | if (i < 32) { | |
928 | hash->low |= 1 << i; | |
929 | } else { | |
930 | hash->high |= 1 << (i-32); | |
931 | } | |
932 | } | |
933 | ||
934 | int zd_chip_set_multicast_hash(struct zd_chip *chip, | |
935 | struct zd_mc_hash *hash); | |
936 | ||
e85d0918 | 937 | #endif /* _ZD_CHIP_H */ |