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1da177e4 LT |
1 | /* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */ |
2 | /* | |
3 | Written 1997-2001 by Donald Becker. | |
4 | ||
5 | This software may be used and distributed according to the terms of | |
6 | the GNU General Public License (GPL), incorporated herein by reference. | |
7 | Drivers based on or derived from this code fall under the GPL and must | |
8 | retain the authorship, copyright and license notice. This file is not | |
9 | a complete program and may only be used when the entire operating | |
10 | system is licensed under the GPL. | |
11 | ||
12 | This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter. | |
13 | It also supports the Symbios Logic version of the same chip core. | |
14 | ||
15 | The author may be reached as becker@scyld.com, or C/O | |
16 | Scyld Computing Corporation | |
17 | 410 Severn Ave., Suite 210 | |
18 | Annapolis MD 21403 | |
19 | ||
20 | Support and updates available at | |
21 | http://www.scyld.com/network/yellowfin.html | |
03a8c661 | 22 | [link no longer provides useful info -jgarzik] |
1da177e4 | 23 | |
1da177e4 LT |
24 | */ |
25 | ||
26 | #define DRV_NAME "yellowfin" | |
d5b20697 AG |
27 | #define DRV_VERSION "2.1" |
28 | #define DRV_RELDATE "Sep 11, 2006" | |
1da177e4 LT |
29 | |
30 | #define PFX DRV_NAME ": " | |
31 | ||
32 | /* The user-configurable values. | |
33 | These may be modified when a driver module is loaded.*/ | |
34 | ||
35 | static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
36 | /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ | |
37 | static int max_interrupt_work = 20; | |
38 | static int mtu; | |
39 | #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */ | |
40 | /* System-wide count of bogus-rx frames. */ | |
41 | static int bogus_rx; | |
42 | static int dma_ctrl = 0x004A0263; /* Constrained by errata */ | |
43 | static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */ | |
44 | #elif defined(YF_NEW) /* A future perfect board :->. */ | |
45 | static int dma_ctrl = 0x00CAC277; /* Override when loading module! */ | |
46 | static int fifo_cfg = 0x0028; | |
47 | #else | |
f71e1309 AV |
48 | static const int dma_ctrl = 0x004A0263; /* Constrained by errata */ |
49 | static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */ | |
1da177e4 LT |
50 | #endif |
51 | ||
52 | /* Set the copy breakpoint for the copy-only-tiny-frames scheme. | |
53 | Setting to > 1514 effectively disables this feature. */ | |
54 | static int rx_copybreak; | |
55 | ||
56 | /* Used to pass the media type, etc. | |
57 | No media types are currently defined. These exist for driver | |
58 | interoperability. | |
59 | */ | |
60 | #define MAX_UNITS 8 /* More are supported, limit only on options */ | |
61 | static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; | |
62 | static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; | |
63 | ||
64 | /* Do ugly workaround for GX server chipset errata. */ | |
65 | static int gx_fix; | |
66 | ||
67 | /* Operational parameters that are set at compile time. */ | |
68 | ||
69 | /* Keep the ring sizes a power of two for efficiency. | |
70 | Making the Tx ring too long decreases the effectiveness of channel | |
71 | bonding and packet priority. | |
72 | There are no ill effects from too-large receive rings. */ | |
73 | #define TX_RING_SIZE 16 | |
74 | #define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */ | |
75 | #define RX_RING_SIZE 64 | |
76 | #define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words) | |
77 | #define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc) | |
78 | #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc) | |
79 | ||
80 | /* Operational parameters that usually are not changed. */ | |
81 | /* Time in jiffies before concluding the transmitter is hung. */ | |
82 | #define TX_TIMEOUT (2*HZ) | |
83 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
84 | ||
85 | #define yellowfin_debug debug | |
86 | ||
87 | #include <linux/module.h> | |
88 | #include <linux/kernel.h> | |
89 | #include <linux/string.h> | |
90 | #include <linux/timer.h> | |
91 | #include <linux/errno.h> | |
92 | #include <linux/ioport.h> | |
93 | #include <linux/slab.h> | |
94 | #include <linux/interrupt.h> | |
95 | #include <linux/pci.h> | |
96 | #include <linux/init.h> | |
97 | #include <linux/mii.h> | |
98 | #include <linux/netdevice.h> | |
99 | #include <linux/etherdevice.h> | |
100 | #include <linux/skbuff.h> | |
101 | #include <linux/ethtool.h> | |
102 | #include <linux/crc32.h> | |
103 | #include <linux/bitops.h> | |
104 | #include <asm/uaccess.h> | |
105 | #include <asm/processor.h> /* Processor type for cache alignment. */ | |
106 | #include <asm/unaligned.h> | |
107 | #include <asm/io.h> | |
108 | ||
109 | /* These identify the driver base version and may not be removed. */ | |
110 | static char version[] __devinitdata = | |
111 | KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n" | |
112 | KERN_INFO " http://www.scyld.com/network/yellowfin.html\n" | |
113 | KERN_INFO " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n"; | |
114 | ||
115 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
116 | MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver"); | |
117 | MODULE_LICENSE("GPL"); | |
118 | ||
119 | module_param(max_interrupt_work, int, 0); | |
120 | module_param(mtu, int, 0); | |
121 | module_param(debug, int, 0); | |
122 | module_param(rx_copybreak, int, 0); | |
123 | module_param_array(options, int, NULL, 0); | |
124 | module_param_array(full_duplex, int, NULL, 0); | |
125 | module_param(gx_fix, int, 0); | |
126 | MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt"); | |
127 | MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)"); | |
128 | MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)"); | |
129 | MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames"); | |
130 | MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex"); | |
131 | MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)"); | |
132 | MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)"); | |
133 | ||
134 | /* | |
135 | Theory of Operation | |
136 | ||
137 | I. Board Compatibility | |
138 | ||
139 | This device driver is designed for the Packet Engines "Yellowfin" Gigabit | |
6aa20a22 | 140 | Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the |
1da177e4 LT |
141 | Symbios 53C885E dual function chip. |
142 | ||
143 | II. Board-specific settings | |
144 | ||
145 | PCI bus devices are configured by the system at boot time, so no jumpers | |
146 | need to be set on the board. The system BIOS preferably should assign the | |
147 | PCI INTA signal to an otherwise unused system IRQ line. | |
148 | Note: Kernel versions earlier than 1.3.73 do not support shared PCI | |
149 | interrupt lines. | |
150 | ||
151 | III. Driver operation | |
152 | ||
153 | IIIa. Ring buffers | |
154 | ||
155 | The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple. | |
156 | This is a descriptor list scheme similar to that used by the EEPro100 and | |
157 | Tulip. This driver uses two statically allocated fixed-size descriptor lists | |
158 | formed into rings by a branch from the final descriptor to the beginning of | |
159 | the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. | |
160 | ||
161 | The driver allocates full frame size skbuffs for the Rx ring buffers at | |
162 | open() time and passes the skb->data field to the Yellowfin as receive data | |
163 | buffers. When an incoming frame is less than RX_COPYBREAK bytes long, | |
164 | a fresh skbuff is allocated and the frame is copied to the new skbuff. | |
165 | When the incoming frame is larger, the skbuff is passed directly up the | |
166 | protocol stack and replaced by a newly allocated skbuff. | |
167 | ||
168 | The RX_COPYBREAK value is chosen to trade-off the memory wasted by | |
169 | using a full-sized skbuff for small frames vs. the copying costs of larger | |
170 | frames. For small frames the copying cost is negligible (esp. considering | |
171 | that we are pre-loading the cache with immediately useful header | |
172 | information). For large frames the copying cost is non-trivial, and the | |
173 | larger copy might flush the cache of useful data. | |
174 | ||
175 | IIIC. Synchronization | |
176 | ||
177 | The driver runs as two independent, single-threaded flows of control. One | |
178 | is the send-packet routine, which enforces single-threaded use by the | |
179 | dev->tbusy flag. The other thread is the interrupt handler, which is single | |
180 | threaded by the hardware and other software. | |
181 | ||
182 | The send packet thread has partial control over the Tx ring and 'dev->tbusy' | |
183 | flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next | |
184 | queue slot is empty, it clears the tbusy flag when finished otherwise it sets | |
185 | the 'yp->tx_full' flag. | |
186 | ||
187 | The interrupt handler has exclusive control over the Rx ring and records stats | |
188 | from the Tx ring. After reaping the stats, it marks the Tx queue entry as | |
189 | empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it | |
190 | clears both the tx_full and tbusy flags. | |
191 | ||
192 | IV. Notes | |
193 | ||
194 | Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards. | |
195 | Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board | |
196 | and an AlphaStation to verifty the Alpha port! | |
197 | ||
198 | IVb. References | |
199 | ||
200 | Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential | |
201 | Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary | |
202 | Data Manual v3.0 | |
203 | http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html | |
204 | http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html | |
205 | ||
206 | IVc. Errata | |
207 | ||
208 | See Packet Engines confidential appendix (prototype chips only). | |
209 | */ | |
210 | ||
6aa20a22 | 211 | |
1da177e4 | 212 | |
1da177e4 LT |
213 | enum capability_flags { |
214 | HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16, | |
215 | HasMACAddrBug=32, /* Only on early revs. */ | |
216 | DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */ | |
217 | }; | |
c3d8e682 | 218 | |
1da177e4 | 219 | /* The PCI I/O space extent. */ |
c3d8e682 JG |
220 | enum { |
221 | YELLOWFIN_SIZE = 0x100, | |
222 | }; | |
1da177e4 LT |
223 | |
224 | struct pci_id_info { | |
225 | const char *name; | |
226 | struct match_info { | |
227 | int pci, pci_mask, subsystem, subsystem_mask; | |
228 | int revision, revision_mask; /* Only 8 bits. */ | |
229 | } id; | |
1da177e4 LT |
230 | int drv_flags; /* Driver use, intended as capability flags. */ |
231 | }; | |
232 | ||
f71e1309 | 233 | static const struct pci_id_info pci_id_tbl[] = { |
1da177e4 | 234 | {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff}, |
1da177e4 LT |
235 | FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom}, |
236 | {"Symbios SYM83C885", { 0x07011000, 0xffffffff}, | |
c3d8e682 | 237 | HasMII | DontUseEeprom }, |
1f1bd5fc | 238 | { } |
1da177e4 LT |
239 | }; |
240 | ||
1f1bd5fc | 241 | static const struct pci_device_id yellowfin_pci_tbl[] = { |
1da177e4 LT |
242 | { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
243 | { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, | |
1f1bd5fc | 244 | { } |
1da177e4 LT |
245 | }; |
246 | MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl); | |
247 | ||
248 | ||
249 | /* Offsets to the Yellowfin registers. Various sizes and alignments. */ | |
250 | enum yellowfin_offsets { | |
251 | TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C, | |
252 | TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18, | |
253 | RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C, | |
254 | RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58, | |
255 | EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86, | |
256 | ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94, | |
257 | Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4, | |
258 | MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC, | |
259 | MII_Status=0xAE, | |
260 | RxDepth=0xB8, FlowCtrl=0xBC, | |
261 | AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8, | |
262 | EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4, | |
263 | EEFeature=0xF5, | |
264 | }; | |
265 | ||
266 | /* The Yellowfin Rx and Tx buffer descriptors. | |
267 | Elements are written as 32 bit for endian portability. */ | |
268 | struct yellowfin_desc { | |
269 | u32 dbdma_cmd; | |
270 | u32 addr; | |
271 | u32 branch_addr; | |
272 | u32 result_status; | |
273 | }; | |
274 | ||
275 | struct tx_status_words { | |
276 | #ifdef __BIG_ENDIAN | |
277 | u16 tx_errs; | |
278 | u16 tx_cnt; | |
279 | u16 paused; | |
280 | u16 total_tx_cnt; | |
281 | #else /* Little endian chips. */ | |
282 | u16 tx_cnt; | |
283 | u16 tx_errs; | |
284 | u16 total_tx_cnt; | |
285 | u16 paused; | |
286 | #endif /* __BIG_ENDIAN */ | |
287 | }; | |
288 | ||
289 | /* Bits in yellowfin_desc.cmd */ | |
290 | enum desc_cmd_bits { | |
291 | CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000, | |
292 | CMD_NOP=0x60000000, CMD_STOP=0x70000000, | |
293 | BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000, | |
294 | BRANCH_IFTRUE=0x040000, | |
295 | }; | |
296 | ||
297 | /* Bits in yellowfin_desc.status */ | |
298 | enum desc_status_bits { RX_EOP=0x0040, }; | |
299 | ||
300 | /* Bits in the interrupt status/mask registers. */ | |
301 | enum intr_status_bits { | |
302 | IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08, | |
303 | IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80, | |
304 | IntrEarlyRx=0x100, IntrWakeup=0x200, }; | |
305 | ||
306 | #define PRIV_ALIGN 31 /* Required alignment mask */ | |
307 | #define MII_CNT 4 | |
308 | struct yellowfin_private { | |
309 | /* Descriptor rings first for alignment. | |
310 | Tx requires a second descriptor for status. */ | |
311 | struct yellowfin_desc *rx_ring; | |
312 | struct yellowfin_desc *tx_ring; | |
313 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; | |
314 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
315 | dma_addr_t rx_ring_dma; | |
316 | dma_addr_t tx_ring_dma; | |
317 | ||
318 | struct tx_status_words *tx_status; | |
319 | dma_addr_t tx_status_dma; | |
320 | ||
321 | struct timer_list timer; /* Media selection timer. */ | |
322 | struct net_device_stats stats; | |
323 | /* Frequently used and paired value: keep adjacent for cache effect. */ | |
324 | int chip_id, drv_flags; | |
325 | struct pci_dev *pci_dev; | |
326 | unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ | |
327 | unsigned int rx_buf_sz; /* Based on MTU+slack. */ | |
328 | struct tx_status_words *tx_tail_desc; | |
329 | unsigned int cur_tx, dirty_tx; | |
330 | int tx_threshold; | |
331 | unsigned int tx_full:1; /* The Tx queue is full. */ | |
332 | unsigned int full_duplex:1; /* Full-duplex operation requested. */ | |
333 | unsigned int duplex_lock:1; | |
334 | unsigned int medialock:1; /* Do not sense media. */ | |
335 | unsigned int default_port:4; /* Last dev->if_port value. */ | |
336 | /* MII transceiver section. */ | |
337 | int mii_cnt; /* MII device addresses. */ | |
338 | u16 advertising; /* NWay media advertisement */ | |
339 | unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */ | |
340 | spinlock_t lock; | |
341 | void __iomem *base; | |
342 | }; | |
343 | ||
344 | static int read_eeprom(void __iomem *ioaddr, int location); | |
345 | static int mdio_read(void __iomem *ioaddr, int phy_id, int location); | |
346 | static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value); | |
347 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
348 | static int yellowfin_open(struct net_device *dev); | |
349 | static void yellowfin_timer(unsigned long data); | |
350 | static void yellowfin_tx_timeout(struct net_device *dev); | |
351 | static void yellowfin_init_ring(struct net_device *dev); | |
352 | static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
353 | static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance, struct pt_regs *regs); | |
354 | static int yellowfin_rx(struct net_device *dev); | |
355 | static void yellowfin_error(struct net_device *dev, int intr_status); | |
356 | static int yellowfin_close(struct net_device *dev); | |
357 | static struct net_device_stats *yellowfin_get_stats(struct net_device *dev); | |
358 | static void set_rx_mode(struct net_device *dev); | |
359 | static struct ethtool_ops ethtool_ops; | |
360 | ||
361 | ||
362 | static int __devinit yellowfin_init_one(struct pci_dev *pdev, | |
363 | const struct pci_device_id *ent) | |
364 | { | |
365 | struct net_device *dev; | |
366 | struct yellowfin_private *np; | |
367 | int irq; | |
368 | int chip_idx = ent->driver_data; | |
369 | static int find_cnt; | |
370 | void __iomem *ioaddr; | |
371 | int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0; | |
372 | int drv_flags = pci_id_tbl[chip_idx].drv_flags; | |
373 | void *ring_space; | |
374 | dma_addr_t ring_dma; | |
375 | #ifdef USE_IO_OPS | |
376 | int bar = 0; | |
377 | #else | |
378 | int bar = 1; | |
379 | #endif | |
6aa20a22 | 380 | |
1da177e4 LT |
381 | /* when built into the kernel, we only print version if device is found */ |
382 | #ifndef MODULE | |
383 | static int printed_version; | |
384 | if (!printed_version++) | |
385 | printk(version); | |
386 | #endif | |
387 | ||
388 | i = pci_enable_device(pdev); | |
389 | if (i) return i; | |
390 | ||
391 | dev = alloc_etherdev(sizeof(*np)); | |
392 | if (!dev) { | |
393 | printk (KERN_ERR PFX "cannot allocate ethernet device\n"); | |
394 | return -ENOMEM; | |
395 | } | |
396 | SET_MODULE_OWNER(dev); | |
397 | SET_NETDEV_DEV(dev, &pdev->dev); | |
398 | ||
399 | np = netdev_priv(dev); | |
400 | ||
401 | if (pci_request_regions(pdev, DRV_NAME)) | |
402 | goto err_out_free_netdev; | |
403 | ||
404 | pci_set_master (pdev); | |
405 | ||
406 | ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE); | |
407 | if (!ioaddr) | |
408 | goto err_out_free_res; | |
409 | ||
410 | irq = pdev->irq; | |
411 | ||
412 | if (drv_flags & DontUseEeprom) | |
413 | for (i = 0; i < 6; i++) | |
414 | dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i); | |
415 | else { | |
416 | int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0); | |
417 | for (i = 0; i < 6; i++) | |
418 | dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i); | |
419 | } | |
420 | ||
421 | /* Reset the chip. */ | |
422 | iowrite32(0x80000000, ioaddr + DMACtrl); | |
423 | ||
424 | dev->base_addr = (unsigned long)ioaddr; | |
425 | dev->irq = irq; | |
426 | ||
427 | pci_set_drvdata(pdev, dev); | |
428 | spin_lock_init(&np->lock); | |
429 | ||
430 | np->pci_dev = pdev; | |
431 | np->chip_id = chip_idx; | |
432 | np->drv_flags = drv_flags; | |
433 | np->base = ioaddr; | |
434 | ||
435 | ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma); | |
436 | if (!ring_space) | |
437 | goto err_out_cleardev; | |
438 | np->tx_ring = (struct yellowfin_desc *)ring_space; | |
439 | np->tx_ring_dma = ring_dma; | |
440 | ||
441 | ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma); | |
442 | if (!ring_space) | |
443 | goto err_out_unmap_tx; | |
444 | np->rx_ring = (struct yellowfin_desc *)ring_space; | |
445 | np->rx_ring_dma = ring_dma; | |
446 | ||
447 | ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma); | |
448 | if (!ring_space) | |
449 | goto err_out_unmap_rx; | |
450 | np->tx_status = (struct tx_status_words *)ring_space; | |
451 | np->tx_status_dma = ring_dma; | |
452 | ||
453 | if (dev->mem_start) | |
454 | option = dev->mem_start; | |
455 | ||
456 | /* The lower four bits are the media type. */ | |
457 | if (option > 0) { | |
458 | if (option & 0x200) | |
459 | np->full_duplex = 1; | |
460 | np->default_port = option & 15; | |
461 | if (np->default_port) | |
462 | np->medialock = 1; | |
463 | } | |
464 | if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0) | |
465 | np->full_duplex = 1; | |
466 | ||
467 | if (np->full_duplex) | |
468 | np->duplex_lock = 1; | |
469 | ||
470 | /* The Yellowfin-specific entries in the device structure. */ | |
471 | dev->open = &yellowfin_open; | |
472 | dev->hard_start_xmit = &yellowfin_start_xmit; | |
473 | dev->stop = &yellowfin_close; | |
474 | dev->get_stats = &yellowfin_get_stats; | |
475 | dev->set_multicast_list = &set_rx_mode; | |
476 | dev->do_ioctl = &netdev_ioctl; | |
477 | SET_ETHTOOL_OPS(dev, ðtool_ops); | |
478 | dev->tx_timeout = yellowfin_tx_timeout; | |
479 | dev->watchdog_timeo = TX_TIMEOUT; | |
480 | ||
481 | if (mtu) | |
482 | dev->mtu = mtu; | |
483 | ||
484 | i = register_netdev(dev); | |
485 | if (i) | |
486 | goto err_out_unmap_status; | |
487 | ||
488 | printk(KERN_INFO "%s: %s type %8x at %p, ", | |
489 | dev->name, pci_id_tbl[chip_idx].name, | |
490 | ioread32(ioaddr + ChipRev), ioaddr); | |
491 | for (i = 0; i < 5; i++) | |
492 | printk("%2.2x:", dev->dev_addr[i]); | |
493 | printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq); | |
494 | ||
495 | if (np->drv_flags & HasMII) { | |
496 | int phy, phy_idx = 0; | |
497 | for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) { | |
498 | int mii_status = mdio_read(ioaddr, phy, 1); | |
499 | if (mii_status != 0xffff && mii_status != 0x0000) { | |
500 | np->phys[phy_idx++] = phy; | |
501 | np->advertising = mdio_read(ioaddr, phy, 4); | |
502 | printk(KERN_INFO "%s: MII PHY found at address %d, status " | |
503 | "0x%4.4x advertising %4.4x.\n", | |
504 | dev->name, phy, mii_status, np->advertising); | |
505 | } | |
506 | } | |
507 | np->mii_cnt = phy_idx; | |
508 | } | |
509 | ||
510 | find_cnt++; | |
6aa20a22 | 511 | |
1da177e4 LT |
512 | return 0; |
513 | ||
514 | err_out_unmap_status: | |
6aa20a22 | 515 | pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status, |
1da177e4 LT |
516 | np->tx_status_dma); |
517 | err_out_unmap_rx: | |
518 | pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma); | |
519 | err_out_unmap_tx: | |
520 | pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma); | |
521 | err_out_cleardev: | |
522 | pci_set_drvdata(pdev, NULL); | |
523 | pci_iounmap(pdev, ioaddr); | |
524 | err_out_free_res: | |
525 | pci_release_regions(pdev); | |
526 | err_out_free_netdev: | |
527 | free_netdev (dev); | |
528 | return -ENODEV; | |
529 | } | |
530 | ||
531 | static int __devinit read_eeprom(void __iomem *ioaddr, int location) | |
532 | { | |
533 | int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */ | |
534 | ||
535 | iowrite8(location, ioaddr + EEAddr); | |
536 | iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl); | |
537 | while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0) | |
538 | ; | |
539 | return ioread8(ioaddr + EERead); | |
540 | } | |
541 | ||
542 | /* MII Managemen Data I/O accesses. | |
543 | These routines assume the MDIO controller is idle, and do not exit until | |
544 | the command is finished. */ | |
545 | ||
546 | static int mdio_read(void __iomem *ioaddr, int phy_id, int location) | |
547 | { | |
548 | int i; | |
549 | ||
550 | iowrite16((phy_id<<8) + location, ioaddr + MII_Addr); | |
551 | iowrite16(1, ioaddr + MII_Cmd); | |
552 | for (i = 10000; i >= 0; i--) | |
553 | if ((ioread16(ioaddr + MII_Status) & 1) == 0) | |
554 | break; | |
555 | return ioread16(ioaddr + MII_Rd_Data); | |
556 | } | |
557 | ||
558 | static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value) | |
559 | { | |
560 | int i; | |
561 | ||
562 | iowrite16((phy_id<<8) + location, ioaddr + MII_Addr); | |
563 | iowrite16(value, ioaddr + MII_Wr_Data); | |
564 | ||
565 | /* Wait for the command to finish. */ | |
566 | for (i = 10000; i >= 0; i--) | |
567 | if ((ioread16(ioaddr + MII_Status) & 1) == 0) | |
568 | break; | |
569 | return; | |
570 | } | |
571 | ||
6aa20a22 | 572 | |
1da177e4 LT |
573 | static int yellowfin_open(struct net_device *dev) |
574 | { | |
575 | struct yellowfin_private *yp = netdev_priv(dev); | |
576 | void __iomem *ioaddr = yp->base; | |
577 | int i; | |
578 | ||
579 | /* Reset the chip. */ | |
580 | iowrite32(0x80000000, ioaddr + DMACtrl); | |
581 | ||
1fb9df5d | 582 | i = request_irq(dev->irq, &yellowfin_interrupt, IRQF_SHARED, dev->name, dev); |
1da177e4 LT |
583 | if (i) return i; |
584 | ||
585 | if (yellowfin_debug > 1) | |
586 | printk(KERN_DEBUG "%s: yellowfin_open() irq %d.\n", | |
587 | dev->name, dev->irq); | |
588 | ||
589 | yellowfin_init_ring(dev); | |
590 | ||
591 | iowrite32(yp->rx_ring_dma, ioaddr + RxPtr); | |
592 | iowrite32(yp->tx_ring_dma, ioaddr + TxPtr); | |
593 | ||
594 | for (i = 0; i < 6; i++) | |
595 | iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i); | |
596 | ||
597 | /* Set up various condition 'select' registers. | |
598 | There are no options here. */ | |
599 | iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */ | |
600 | iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */ | |
601 | iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */ | |
602 | iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */ | |
603 | iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */ | |
604 | iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */ | |
605 | ||
606 | /* Initialize other registers: with so many this eventually this will | |
607 | converted to an offset/value list. */ | |
608 | iowrite32(dma_ctrl, ioaddr + DMACtrl); | |
609 | iowrite16(fifo_cfg, ioaddr + FIFOcfg); | |
610 | /* Enable automatic generation of flow control frames, period 0xffff. */ | |
611 | iowrite32(0x0030FFFF, ioaddr + FlowCtrl); | |
612 | ||
613 | yp->tx_threshold = 32; | |
614 | iowrite32(yp->tx_threshold, ioaddr + TxThreshold); | |
615 | ||
616 | if (dev->if_port == 0) | |
617 | dev->if_port = yp->default_port; | |
618 | ||
619 | netif_start_queue(dev); | |
620 | ||
621 | /* Setting the Rx mode will start the Rx process. */ | |
622 | if (yp->drv_flags & IsGigabit) { | |
623 | /* We are always in full-duplex mode with gigabit! */ | |
624 | yp->full_duplex = 1; | |
625 | iowrite16(0x01CF, ioaddr + Cnfg); | |
626 | } else { | |
627 | iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */ | |
628 | iowrite16(0x1018, ioaddr + FrameGap1); | |
629 | iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg); | |
630 | } | |
631 | set_rx_mode(dev); | |
632 | ||
633 | /* Enable interrupts by setting the interrupt mask. */ | |
634 | iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */ | |
635 | iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */ | |
636 | iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */ | |
637 | iowrite32(0x80008000, ioaddr + TxCtrl); | |
638 | ||
639 | if (yellowfin_debug > 2) { | |
640 | printk(KERN_DEBUG "%s: Done yellowfin_open().\n", | |
641 | dev->name); | |
642 | } | |
643 | ||
644 | /* Set the timer to check for link beat. */ | |
645 | init_timer(&yp->timer); | |
646 | yp->timer.expires = jiffies + 3*HZ; | |
647 | yp->timer.data = (unsigned long)dev; | |
648 | yp->timer.function = &yellowfin_timer; /* timer handler */ | |
649 | add_timer(&yp->timer); | |
650 | ||
651 | return 0; | |
652 | } | |
653 | ||
654 | static void yellowfin_timer(unsigned long data) | |
655 | { | |
656 | struct net_device *dev = (struct net_device *)data; | |
657 | struct yellowfin_private *yp = netdev_priv(dev); | |
658 | void __iomem *ioaddr = yp->base; | |
659 | int next_tick = 60*HZ; | |
660 | ||
661 | if (yellowfin_debug > 3) { | |
662 | printk(KERN_DEBUG "%s: Yellowfin timer tick, status %8.8x.\n", | |
663 | dev->name, ioread16(ioaddr + IntrStatus)); | |
664 | } | |
665 | ||
666 | if (yp->mii_cnt) { | |
667 | int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR); | |
668 | int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA); | |
669 | int negotiated = lpa & yp->advertising; | |
670 | if (yellowfin_debug > 1) | |
671 | printk(KERN_DEBUG "%s: MII #%d status register is %4.4x, " | |
672 | "link partner capability %4.4x.\n", | |
673 | dev->name, yp->phys[0], bmsr, lpa); | |
674 | ||
675 | yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated); | |
6aa20a22 | 676 | |
1da177e4 LT |
677 | iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg); |
678 | ||
679 | if (bmsr & BMSR_LSTATUS) | |
680 | next_tick = 60*HZ; | |
681 | else | |
682 | next_tick = 3*HZ; | |
683 | } | |
684 | ||
685 | yp->timer.expires = jiffies + next_tick; | |
686 | add_timer(&yp->timer); | |
687 | } | |
688 | ||
689 | static void yellowfin_tx_timeout(struct net_device *dev) | |
690 | { | |
691 | struct yellowfin_private *yp = netdev_priv(dev); | |
692 | void __iomem *ioaddr = yp->base; | |
693 | ||
694 | printk(KERN_WARNING "%s: Yellowfin transmit timed out at %d/%d Tx " | |
695 | "status %4.4x, Rx status %4.4x, resetting...\n", | |
696 | dev->name, yp->cur_tx, yp->dirty_tx, | |
697 | ioread32(ioaddr + TxStatus), ioread32(ioaddr + RxStatus)); | |
698 | ||
699 | /* Note: these should be KERN_DEBUG. */ | |
700 | if (yellowfin_debug) { | |
701 | int i; | |
702 | printk(KERN_WARNING " Rx ring %p: ", yp->rx_ring); | |
703 | for (i = 0; i < RX_RING_SIZE; i++) | |
704 | printk(" %8.8x", yp->rx_ring[i].result_status); | |
705 | printk("\n"KERN_WARNING" Tx ring %p: ", yp->tx_ring); | |
706 | for (i = 0; i < TX_RING_SIZE; i++) | |
707 | printk(" %4.4x /%8.8x", yp->tx_status[i].tx_errs, | |
708 | yp->tx_ring[i].result_status); | |
709 | printk("\n"); | |
710 | } | |
711 | ||
712 | /* If the hardware is found to hang regularly, we will update the code | |
713 | to reinitialize the chip here. */ | |
714 | dev->if_port = 0; | |
715 | ||
716 | /* Wake the potentially-idle transmit channel. */ | |
717 | iowrite32(0x10001000, yp->base + TxCtrl); | |
718 | if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE) | |
719 | netif_wake_queue (dev); /* Typical path */ | |
720 | ||
721 | dev->trans_start = jiffies; | |
722 | yp->stats.tx_errors++; | |
723 | } | |
724 | ||
725 | /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ | |
726 | static void yellowfin_init_ring(struct net_device *dev) | |
727 | { | |
728 | struct yellowfin_private *yp = netdev_priv(dev); | |
729 | int i; | |
730 | ||
731 | yp->tx_full = 0; | |
732 | yp->cur_rx = yp->cur_tx = 0; | |
733 | yp->dirty_tx = 0; | |
734 | ||
735 | yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); | |
736 | ||
737 | for (i = 0; i < RX_RING_SIZE; i++) { | |
738 | yp->rx_ring[i].dbdma_cmd = | |
739 | cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz); | |
740 | yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma + | |
741 | ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc)); | |
742 | } | |
743 | ||
744 | for (i = 0; i < RX_RING_SIZE; i++) { | |
745 | struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz); | |
746 | yp->rx_skbuff[i] = skb; | |
747 | if (skb == NULL) | |
748 | break; | |
749 | skb->dev = dev; /* Mark as being used by this device. */ | |
750 | skb_reserve(skb, 2); /* 16 byte align the IP header. */ | |
751 | yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev, | |
689be439 | 752 | skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE)); |
1da177e4 LT |
753 | } |
754 | yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP); | |
755 | yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE); | |
756 | ||
757 | #define NO_TXSTATS | |
758 | #ifdef NO_TXSTATS | |
759 | /* In this mode the Tx ring needs only a single descriptor. */ | |
760 | for (i = 0; i < TX_RING_SIZE; i++) { | |
761 | yp->tx_skbuff[i] = NULL; | |
762 | yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP); | |
763 | yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma + | |
764 | ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc)); | |
765 | } | |
766 | /* Wrap ring */ | |
767 | yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS); | |
768 | #else | |
769 | { | |
770 | int j; | |
771 | ||
772 | /* Tx ring needs a pair of descriptors, the second for the status. */ | |
773 | for (i = 0; i < TX_RING_SIZE; i++) { | |
774 | j = 2*i; | |
775 | yp->tx_skbuff[i] = 0; | |
776 | /* Branch on Tx error. */ | |
777 | yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP); | |
778 | yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma + | |
779 | (j+1)*sizeof(struct yellowfin_desc); | |
780 | j++; | |
781 | if (yp->flags & FullTxStatus) { | |
782 | yp->tx_ring[j].dbdma_cmd = | |
783 | cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status)); | |
784 | yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status); | |
785 | yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma + | |
786 | i*sizeof(struct tx_status_words); | |
787 | } else { | |
788 | /* Symbios chips write only tx_errs word. */ | |
789 | yp->tx_ring[j].dbdma_cmd = | |
790 | cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2); | |
791 | yp->tx_ring[j].request_cnt = 2; | |
792 | /* Om pade ummmmm... */ | |
793 | yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma + | |
794 | i*sizeof(struct tx_status_words) + | |
6aa20a22 | 795 | &(yp->tx_status[0].tx_errs) - |
1da177e4 LT |
796 | &(yp->tx_status[0])); |
797 | } | |
6aa20a22 | 798 | yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma + |
1da177e4 LT |
799 | ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc)); |
800 | } | |
801 | /* Wrap ring */ | |
802 | yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS); | |
803 | } | |
804 | #endif | |
805 | yp->tx_tail_desc = &yp->tx_status[0]; | |
806 | return; | |
807 | } | |
808 | ||
809 | static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
810 | { | |
811 | struct yellowfin_private *yp = netdev_priv(dev); | |
812 | unsigned entry; | |
813 | int len = skb->len; | |
814 | ||
815 | netif_stop_queue (dev); | |
816 | ||
817 | /* Note: Ordering is important here, set the field with the | |
818 | "ownership" bit last, and only then increment cur_tx. */ | |
819 | ||
820 | /* Calculate the next Tx descriptor entry. */ | |
821 | entry = yp->cur_tx % TX_RING_SIZE; | |
822 | ||
823 | if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */ | |
824 | int cacheline_end = ((unsigned long)skb->data + skb->len) % 32; | |
825 | /* Fix GX chipset errata. */ | |
826 | if (cacheline_end > 24 || cacheline_end == 0) { | |
827 | len = skb->len + 32 - cacheline_end + 1; | |
5b057c6b HX |
828 | if (skb_padto(skb, len)) { |
829 | yp->tx_skbuff[entry] = NULL; | |
830 | netif_wake_queue(dev); | |
831 | return 0; | |
832 | } | |
1da177e4 LT |
833 | } |
834 | } | |
835 | yp->tx_skbuff[entry] = skb; | |
836 | ||
837 | #ifdef NO_TXSTATS | |
6aa20a22 | 838 | yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev, |
1da177e4 LT |
839 | skb->data, len, PCI_DMA_TODEVICE)); |
840 | yp->tx_ring[entry].result_status = 0; | |
841 | if (entry >= TX_RING_SIZE-1) { | |
842 | /* New stop command. */ | |
843 | yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP); | |
844 | yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd = | |
845 | cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len); | |
846 | } else { | |
847 | yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP); | |
848 | yp->tx_ring[entry].dbdma_cmd = | |
849 | cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len); | |
850 | } | |
851 | yp->cur_tx++; | |
852 | #else | |
853 | yp->tx_ring[entry<<1].request_cnt = len; | |
6aa20a22 | 854 | yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev, |
1da177e4 | 855 | skb->data, len, PCI_DMA_TODEVICE)); |
6aa20a22 | 856 | /* The input_last (status-write) command is constant, but we must |
1da177e4 LT |
857 | rewrite the subsequent 'stop' command. */ |
858 | ||
859 | yp->cur_tx++; | |
860 | { | |
861 | unsigned next_entry = yp->cur_tx % TX_RING_SIZE; | |
862 | yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP); | |
863 | } | |
864 | /* Final step -- overwrite the old 'stop' command. */ | |
865 | ||
866 | yp->tx_ring[entry<<1].dbdma_cmd = | |
867 | cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE : | |
868 | CMD_TX_PKT | BRANCH_IFTRUE) | len); | |
869 | #endif | |
870 | ||
871 | /* Non-x86 Todo: explicitly flush cache lines here. */ | |
872 | ||
873 | /* Wake the potentially-idle transmit channel. */ | |
874 | iowrite32(0x10001000, yp->base + TxCtrl); | |
875 | ||
876 | if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE) | |
877 | netif_start_queue (dev); /* Typical path */ | |
878 | else | |
879 | yp->tx_full = 1; | |
880 | dev->trans_start = jiffies; | |
881 | ||
882 | if (yellowfin_debug > 4) { | |
883 | printk(KERN_DEBUG "%s: Yellowfin transmit frame #%d queued in slot %d.\n", | |
884 | dev->name, yp->cur_tx, entry); | |
885 | } | |
886 | return 0; | |
887 | } | |
888 | ||
889 | /* The interrupt handler does all of the Rx thread work and cleans up | |
890 | after the Tx thread. */ | |
891 | static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance, struct pt_regs *regs) | |
892 | { | |
893 | struct net_device *dev = dev_instance; | |
894 | struct yellowfin_private *yp; | |
895 | void __iomem *ioaddr; | |
896 | int boguscnt = max_interrupt_work; | |
897 | unsigned int handled = 0; | |
898 | ||
899 | #ifndef final_version /* Can never occur. */ | |
900 | if (dev == NULL) { | |
901 | printk (KERN_ERR "yellowfin_interrupt(): irq %d for unknown device.\n", irq); | |
902 | return IRQ_NONE; | |
903 | } | |
904 | #endif | |
905 | ||
906 | yp = netdev_priv(dev); | |
907 | ioaddr = yp->base; | |
6aa20a22 | 908 | |
1da177e4 LT |
909 | spin_lock (&yp->lock); |
910 | ||
911 | do { | |
912 | u16 intr_status = ioread16(ioaddr + IntrClear); | |
913 | ||
914 | if (yellowfin_debug > 4) | |
915 | printk(KERN_DEBUG "%s: Yellowfin interrupt, status %4.4x.\n", | |
916 | dev->name, intr_status); | |
917 | ||
918 | if (intr_status == 0) | |
919 | break; | |
920 | handled = 1; | |
921 | ||
922 | if (intr_status & (IntrRxDone | IntrEarlyRx)) { | |
923 | yellowfin_rx(dev); | |
924 | iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */ | |
925 | } | |
926 | ||
927 | #ifdef NO_TXSTATS | |
928 | for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) { | |
929 | int entry = yp->dirty_tx % TX_RING_SIZE; | |
930 | struct sk_buff *skb; | |
931 | ||
932 | if (yp->tx_ring[entry].result_status == 0) | |
933 | break; | |
934 | skb = yp->tx_skbuff[entry]; | |
935 | yp->stats.tx_packets++; | |
936 | yp->stats.tx_bytes += skb->len; | |
937 | /* Free the original skb. */ | |
938 | pci_unmap_single(yp->pci_dev, yp->tx_ring[entry].addr, | |
939 | skb->len, PCI_DMA_TODEVICE); | |
940 | dev_kfree_skb_irq(skb); | |
941 | yp->tx_skbuff[entry] = NULL; | |
942 | } | |
943 | if (yp->tx_full | |
944 | && yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) { | |
945 | /* The ring is no longer full, clear tbusy. */ | |
946 | yp->tx_full = 0; | |
947 | netif_wake_queue(dev); | |
948 | } | |
949 | #else | |
950 | if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) { | |
951 | unsigned dirty_tx = yp->dirty_tx; | |
952 | ||
953 | for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0; | |
954 | dirty_tx++) { | |
955 | /* Todo: optimize this. */ | |
956 | int entry = dirty_tx % TX_RING_SIZE; | |
957 | u16 tx_errs = yp->tx_status[entry].tx_errs; | |
958 | struct sk_buff *skb; | |
959 | ||
960 | #ifndef final_version | |
961 | if (yellowfin_debug > 5) | |
962 | printk(KERN_DEBUG "%s: Tx queue %d check, Tx status " | |
963 | "%4.4x %4.4x %4.4x %4.4x.\n", | |
964 | dev->name, entry, | |
965 | yp->tx_status[entry].tx_cnt, | |
966 | yp->tx_status[entry].tx_errs, | |
967 | yp->tx_status[entry].total_tx_cnt, | |
968 | yp->tx_status[entry].paused); | |
969 | #endif | |
970 | if (tx_errs == 0) | |
971 | break; /* It still hasn't been Txed */ | |
972 | skb = yp->tx_skbuff[entry]; | |
973 | if (tx_errs & 0xF810) { | |
974 | /* There was an major error, log it. */ | |
975 | #ifndef final_version | |
976 | if (yellowfin_debug > 1) | |
977 | printk(KERN_DEBUG "%s: Transmit error, Tx status %4.4x.\n", | |
978 | dev->name, tx_errs); | |
979 | #endif | |
980 | yp->stats.tx_errors++; | |
981 | if (tx_errs & 0xF800) yp->stats.tx_aborted_errors++; | |
982 | if (tx_errs & 0x0800) yp->stats.tx_carrier_errors++; | |
983 | if (tx_errs & 0x2000) yp->stats.tx_window_errors++; | |
984 | if (tx_errs & 0x8000) yp->stats.tx_fifo_errors++; | |
985 | } else { | |
986 | #ifndef final_version | |
987 | if (yellowfin_debug > 4) | |
988 | printk(KERN_DEBUG "%s: Normal transmit, Tx status %4.4x.\n", | |
989 | dev->name, tx_errs); | |
990 | #endif | |
991 | yp->stats.tx_bytes += skb->len; | |
992 | yp->stats.collisions += tx_errs & 15; | |
993 | yp->stats.tx_packets++; | |
994 | } | |
995 | /* Free the original skb. */ | |
6aa20a22 JG |
996 | pci_unmap_single(yp->pci_dev, |
997 | yp->tx_ring[entry<<1].addr, skb->len, | |
1da177e4 LT |
998 | PCI_DMA_TODEVICE); |
999 | dev_kfree_skb_irq(skb); | |
1000 | yp->tx_skbuff[entry] = 0; | |
1001 | /* Mark status as empty. */ | |
1002 | yp->tx_status[entry].tx_errs = 0; | |
1003 | } | |
1004 | ||
1005 | #ifndef final_version | |
1006 | if (yp->cur_tx - dirty_tx > TX_RING_SIZE) { | |
1007 | printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n", | |
1008 | dev->name, dirty_tx, yp->cur_tx, yp->tx_full); | |
1009 | dirty_tx += TX_RING_SIZE; | |
1010 | } | |
1011 | #endif | |
1012 | ||
1013 | if (yp->tx_full | |
1014 | && yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) { | |
1015 | /* The ring is no longer full, clear tbusy. */ | |
1016 | yp->tx_full = 0; | |
1017 | netif_wake_queue(dev); | |
1018 | } | |
1019 | ||
1020 | yp->dirty_tx = dirty_tx; | |
1021 | yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE]; | |
1022 | } | |
1023 | #endif | |
1024 | ||
1025 | /* Log errors and other uncommon events. */ | |
1026 | if (intr_status & 0x2ee) /* Abnormal error summary. */ | |
1027 | yellowfin_error(dev, intr_status); | |
1028 | ||
1029 | if (--boguscnt < 0) { | |
1030 | printk(KERN_WARNING "%s: Too much work at interrupt, " | |
1031 | "status=0x%4.4x.\n", | |
1032 | dev->name, intr_status); | |
1033 | break; | |
1034 | } | |
1035 | } while (1); | |
1036 | ||
1037 | if (yellowfin_debug > 3) | |
1038 | printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n", | |
1039 | dev->name, ioread16(ioaddr + IntrStatus)); | |
1040 | ||
1041 | spin_unlock (&yp->lock); | |
1042 | return IRQ_RETVAL(handled); | |
1043 | } | |
1044 | ||
1045 | /* This routine is logically part of the interrupt handler, but separated | |
1046 | for clarity and better register allocation. */ | |
1047 | static int yellowfin_rx(struct net_device *dev) | |
1048 | { | |
1049 | struct yellowfin_private *yp = netdev_priv(dev); | |
1050 | int entry = yp->cur_rx % RX_RING_SIZE; | |
1051 | int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx; | |
1052 | ||
1053 | if (yellowfin_debug > 4) { | |
1054 | printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %8.8x.\n", | |
1055 | entry, yp->rx_ring[entry].result_status); | |
1056 | printk(KERN_DEBUG " #%d desc. %8.8x %8.8x %8.8x.\n", | |
1057 | entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr, | |
1058 | yp->rx_ring[entry].result_status); | |
1059 | } | |
1060 | ||
1061 | /* If EOP is set on the next entry, it's a new packet. Send it up. */ | |
1062 | while (1) { | |
1063 | struct yellowfin_desc *desc = &yp->rx_ring[entry]; | |
1064 | struct sk_buff *rx_skb = yp->rx_skbuff[entry]; | |
1065 | s16 frame_status; | |
1066 | u16 desc_status; | |
1067 | int data_size; | |
1068 | u8 *buf_addr; | |
1069 | ||
1070 | if(!desc->result_status) | |
1071 | break; | |
1072 | pci_dma_sync_single_for_cpu(yp->pci_dev, desc->addr, | |
1073 | yp->rx_buf_sz, PCI_DMA_FROMDEVICE); | |
1074 | desc_status = le32_to_cpu(desc->result_status) >> 16; | |
689be439 | 1075 | buf_addr = rx_skb->data; |
6aa20a22 | 1076 | data_size = (le32_to_cpu(desc->dbdma_cmd) - |
1da177e4 LT |
1077 | le32_to_cpu(desc->result_status)) & 0xffff; |
1078 | frame_status = le16_to_cpu(get_unaligned((s16*)&(buf_addr[data_size - 2]))); | |
1079 | if (yellowfin_debug > 4) | |
1080 | printk(KERN_DEBUG " yellowfin_rx() status was %4.4x.\n", | |
1081 | frame_status); | |
1082 | if (--boguscnt < 0) | |
1083 | break; | |
1084 | if ( ! (desc_status & RX_EOP)) { | |
1085 | if (data_size != 0) | |
1086 | printk(KERN_WARNING "%s: Oversized Ethernet frame spanned multiple buffers," | |
1087 | " status %4.4x, data_size %d!\n", dev->name, desc_status, data_size); | |
1088 | yp->stats.rx_length_errors++; | |
1089 | } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) { | |
1090 | /* There was a error. */ | |
1091 | if (yellowfin_debug > 3) | |
1092 | printk(KERN_DEBUG " yellowfin_rx() Rx error was %4.4x.\n", | |
1093 | frame_status); | |
1094 | yp->stats.rx_errors++; | |
1095 | if (frame_status & 0x0060) yp->stats.rx_length_errors++; | |
1096 | if (frame_status & 0x0008) yp->stats.rx_frame_errors++; | |
1097 | if (frame_status & 0x0010) yp->stats.rx_crc_errors++; | |
1098 | if (frame_status < 0) yp->stats.rx_dropped++; | |
1099 | } else if ( !(yp->drv_flags & IsGigabit) && | |
1100 | ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) { | |
1101 | u8 status1 = buf_addr[data_size-2]; | |
1102 | u8 status2 = buf_addr[data_size-1]; | |
1103 | yp->stats.rx_errors++; | |
1104 | if (status1 & 0xC0) yp->stats.rx_length_errors++; | |
1105 | if (status2 & 0x03) yp->stats.rx_frame_errors++; | |
1106 | if (status2 & 0x04) yp->stats.rx_crc_errors++; | |
1107 | if (status2 & 0x80) yp->stats.rx_dropped++; | |
1108 | #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */ | |
1109 | } else if ((yp->flags & HasMACAddrBug) && | |
1110 | memcmp(le32_to_cpu(yp->rx_ring_dma + | |
1111 | entry*sizeof(struct yellowfin_desc)), | |
6aa20a22 | 1112 | dev->dev_addr, 6) != 0 && |
1da177e4 LT |
1113 | memcmp(le32_to_cpu(yp->rx_ring_dma + |
1114 | entry*sizeof(struct yellowfin_desc)), | |
1115 | "\377\377\377\377\377\377", 6) != 0) { | |
1116 | if (bogus_rx++ == 0) | |
1117 | printk(KERN_WARNING "%s: Bad frame to %2.2x:%2.2x:%2.2x:%2.2x:" | |
1118 | "%2.2x:%2.2x.\n", | |
1119 | dev->name, buf_addr[0], buf_addr[1], buf_addr[2], | |
1120 | buf_addr[3], buf_addr[4], buf_addr[5]); | |
1121 | #endif | |
1122 | } else { | |
1123 | struct sk_buff *skb; | |
1124 | int pkt_len = data_size - | |
1125 | (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]); | |
1126 | /* To verify: Yellowfin Length should omit the CRC! */ | |
1127 | ||
1128 | #ifndef final_version | |
1129 | if (yellowfin_debug > 4) | |
1130 | printk(KERN_DEBUG " yellowfin_rx() normal Rx pkt length %d" | |
1131 | " of %d, bogus_cnt %d.\n", | |
1132 | pkt_len, data_size, boguscnt); | |
1133 | #endif | |
1134 | /* Check if the packet is long enough to just pass up the skbuff | |
1135 | without copying to a properly sized skbuff. */ | |
1136 | if (pkt_len > rx_copybreak) { | |
1137 | skb_put(skb = rx_skb, pkt_len); | |
6aa20a22 JG |
1138 | pci_unmap_single(yp->pci_dev, |
1139 | yp->rx_ring[entry].addr, | |
1140 | yp->rx_buf_sz, | |
1da177e4 LT |
1141 | PCI_DMA_FROMDEVICE); |
1142 | yp->rx_skbuff[entry] = NULL; | |
1143 | } else { | |
1144 | skb = dev_alloc_skb(pkt_len + 2); | |
1145 | if (skb == NULL) | |
1146 | break; | |
1147 | skb->dev = dev; | |
1148 | skb_reserve(skb, 2); /* 16 byte align the IP header */ | |
689be439 | 1149 | eth_copy_and_sum(skb, rx_skb->data, pkt_len, 0); |
1da177e4 LT |
1150 | skb_put(skb, pkt_len); |
1151 | pci_dma_sync_single_for_device(yp->pci_dev, desc->addr, | |
1152 | yp->rx_buf_sz, | |
1153 | PCI_DMA_FROMDEVICE); | |
1154 | } | |
1155 | skb->protocol = eth_type_trans(skb, dev); | |
1156 | netif_rx(skb); | |
1157 | dev->last_rx = jiffies; | |
1158 | yp->stats.rx_packets++; | |
1159 | yp->stats.rx_bytes += pkt_len; | |
1160 | } | |
1161 | entry = (++yp->cur_rx) % RX_RING_SIZE; | |
1162 | } | |
1163 | ||
1164 | /* Refill the Rx ring buffers. */ | |
1165 | for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) { | |
1166 | entry = yp->dirty_rx % RX_RING_SIZE; | |
1167 | if (yp->rx_skbuff[entry] == NULL) { | |
1168 | struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz); | |
1169 | if (skb == NULL) | |
1170 | break; /* Better luck next round. */ | |
1171 | yp->rx_skbuff[entry] = skb; | |
1172 | skb->dev = dev; /* Mark as being used by this device. */ | |
1173 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ | |
1174 | yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev, | |
689be439 | 1175 | skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE)); |
1da177e4 LT |
1176 | } |
1177 | yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP); | |
1178 | yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */ | |
1179 | if (entry != 0) | |
1180 | yp->rx_ring[entry - 1].dbdma_cmd = | |
1181 | cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz); | |
1182 | else | |
1183 | yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd = | |
1184 | cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS | |
1185 | | yp->rx_buf_sz); | |
1186 | } | |
1187 | ||
1188 | return 0; | |
1189 | } | |
1190 | ||
1191 | static void yellowfin_error(struct net_device *dev, int intr_status) | |
1192 | { | |
1193 | struct yellowfin_private *yp = netdev_priv(dev); | |
1194 | ||
1195 | printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n", | |
1196 | dev->name, intr_status); | |
1197 | /* Hmmmmm, it's not clear what to do here. */ | |
1198 | if (intr_status & (IntrTxPCIErr | IntrTxPCIFault)) | |
1199 | yp->stats.tx_errors++; | |
1200 | if (intr_status & (IntrRxPCIErr | IntrRxPCIFault)) | |
1201 | yp->stats.rx_errors++; | |
1202 | } | |
1203 | ||
1204 | static int yellowfin_close(struct net_device *dev) | |
1205 | { | |
1206 | struct yellowfin_private *yp = netdev_priv(dev); | |
1207 | void __iomem *ioaddr = yp->base; | |
1208 | int i; | |
1209 | ||
1210 | netif_stop_queue (dev); | |
1211 | ||
1212 | if (yellowfin_debug > 1) { | |
1213 | printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x " | |
1214 | "Rx %4.4x Int %2.2x.\n", | |
1215 | dev->name, ioread16(ioaddr + TxStatus), | |
1216 | ioread16(ioaddr + RxStatus), | |
1217 | ioread16(ioaddr + IntrStatus)); | |
1218 | printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n", | |
1219 | dev->name, yp->cur_tx, yp->dirty_tx, yp->cur_rx, yp->dirty_rx); | |
1220 | } | |
1221 | ||
1222 | /* Disable interrupts by clearing the interrupt mask. */ | |
1223 | iowrite16(0x0000, ioaddr + IntrEnb); | |
1224 | ||
1225 | /* Stop the chip's Tx and Rx processes. */ | |
1226 | iowrite32(0x80000000, ioaddr + RxCtrl); | |
1227 | iowrite32(0x80000000, ioaddr + TxCtrl); | |
1228 | ||
1229 | del_timer(&yp->timer); | |
1230 | ||
1231 | #if defined(__i386__) | |
1232 | if (yellowfin_debug > 2) { | |
1233 | printk("\n"KERN_DEBUG" Tx ring at %8.8llx:\n", | |
1234 | (unsigned long long)yp->tx_ring_dma); | |
1235 | for (i = 0; i < TX_RING_SIZE*2; i++) | |
1236 | printk(" %c #%d desc. %8.8x %8.8x %8.8x %8.8x.\n", | |
1237 | ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ', | |
1238 | i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr, | |
1239 | yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status); | |
1240 | printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status); | |
1241 | for (i = 0; i < TX_RING_SIZE; i++) | |
1242 | printk(" #%d status %4.4x %4.4x %4.4x %4.4x.\n", | |
1243 | i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs, | |
1244 | yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused); | |
1245 | ||
1246 | printk("\n"KERN_DEBUG " Rx ring %8.8llx:\n", | |
1247 | (unsigned long long)yp->rx_ring_dma); | |
1248 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1249 | printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x %8.8x\n", | |
1250 | ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ', | |
1251 | i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr, | |
1252 | yp->rx_ring[i].result_status); | |
1253 | if (yellowfin_debug > 6) { | |
1254 | if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) { | |
1255 | int j; | |
1256 | for (j = 0; j < 0x50; j++) | |
1257 | printk(" %4.4x", | |
1258 | get_unaligned(((u16*)yp->rx_ring[i].addr) + j)); | |
1259 | printk("\n"); | |
1260 | } | |
1261 | } | |
1262 | } | |
1263 | } | |
1264 | #endif /* __i386__ debugging only */ | |
1265 | ||
1266 | free_irq(dev->irq, dev); | |
1267 | ||
1268 | /* Free all the skbuffs in the Rx queue. */ | |
1269 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1270 | yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP); | |
1271 | yp->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */ | |
1272 | if (yp->rx_skbuff[i]) { | |
1273 | dev_kfree_skb(yp->rx_skbuff[i]); | |
1274 | } | |
1275 | yp->rx_skbuff[i] = NULL; | |
1276 | } | |
1277 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1278 | if (yp->tx_skbuff[i]) | |
1279 | dev_kfree_skb(yp->tx_skbuff[i]); | |
1280 | yp->tx_skbuff[i] = NULL; | |
1281 | } | |
1282 | ||
1283 | #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */ | |
1284 | if (yellowfin_debug > 0) { | |
1285 | printk(KERN_DEBUG "%s: Received %d frames that we should not have.\n", | |
1286 | dev->name, bogus_rx); | |
1287 | } | |
1288 | #endif | |
1289 | ||
1290 | return 0; | |
1291 | } | |
1292 | ||
1293 | static struct net_device_stats *yellowfin_get_stats(struct net_device *dev) | |
1294 | { | |
1295 | struct yellowfin_private *yp = netdev_priv(dev); | |
1296 | return &yp->stats; | |
1297 | } | |
1298 | ||
1299 | /* Set or clear the multicast filter for this adaptor. */ | |
1300 | ||
1301 | static void set_rx_mode(struct net_device *dev) | |
1302 | { | |
1303 | struct yellowfin_private *yp = netdev_priv(dev); | |
1304 | void __iomem *ioaddr = yp->base; | |
1305 | u16 cfg_value = ioread16(ioaddr + Cnfg); | |
1306 | ||
1307 | /* Stop the Rx process to change any value. */ | |
1308 | iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg); | |
1309 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1da177e4 LT |
1310 | iowrite16(0x000F, ioaddr + AddrMode); |
1311 | } else if ((dev->mc_count > 64) || (dev->flags & IFF_ALLMULTI)) { | |
1312 | /* Too many to filter well, or accept all multicasts. */ | |
1313 | iowrite16(0x000B, ioaddr + AddrMode); | |
1314 | } else if (dev->mc_count > 0) { /* Must use the multicast hash table. */ | |
1315 | struct dev_mc_list *mclist; | |
1316 | u16 hash_table[4]; | |
1317 | int i; | |
1318 | memset(hash_table, 0, sizeof(hash_table)); | |
1319 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
1320 | i++, mclist = mclist->next) { | |
1321 | unsigned int bit; | |
1322 | ||
1323 | /* Due to a bug in the early chip versions, multiple filter | |
1324 | slots must be set for each address. */ | |
1325 | if (yp->drv_flags & HasMulticastBug) { | |
1326 | bit = (ether_crc_le(3, mclist->dmi_addr) >> 3) & 0x3f; | |
1327 | hash_table[bit >> 4] |= (1 << bit); | |
1328 | bit = (ether_crc_le(4, mclist->dmi_addr) >> 3) & 0x3f; | |
1329 | hash_table[bit >> 4] |= (1 << bit); | |
1330 | bit = (ether_crc_le(5, mclist->dmi_addr) >> 3) & 0x3f; | |
1331 | hash_table[bit >> 4] |= (1 << bit); | |
1332 | } | |
1333 | bit = (ether_crc_le(6, mclist->dmi_addr) >> 3) & 0x3f; | |
1334 | hash_table[bit >> 4] |= (1 << bit); | |
1335 | } | |
1336 | /* Copy the hash table to the chip. */ | |
1337 | for (i = 0; i < 4; i++) | |
1338 | iowrite16(hash_table[i], ioaddr + HashTbl + i*2); | |
1339 | iowrite16(0x0003, ioaddr + AddrMode); | |
1340 | } else { /* Normal, unicast/broadcast-only mode. */ | |
1341 | iowrite16(0x0001, ioaddr + AddrMode); | |
1342 | } | |
1343 | /* Restart the Rx process. */ | |
1344 | iowrite16(cfg_value | 0x1000, ioaddr + Cnfg); | |
1345 | } | |
1346 | ||
1347 | static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
1348 | { | |
1349 | struct yellowfin_private *np = netdev_priv(dev); | |
1350 | strcpy(info->driver, DRV_NAME); | |
1351 | strcpy(info->version, DRV_VERSION); | |
1352 | strcpy(info->bus_info, pci_name(np->pci_dev)); | |
1353 | } | |
1354 | ||
1355 | static struct ethtool_ops ethtool_ops = { | |
1356 | .get_drvinfo = yellowfin_get_drvinfo | |
1357 | }; | |
1358 | ||
1359 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1360 | { | |
1361 | struct yellowfin_private *np = netdev_priv(dev); | |
1362 | void __iomem *ioaddr = np->base; | |
1363 | struct mii_ioctl_data *data = if_mii(rq); | |
1364 | ||
1365 | switch(cmd) { | |
1366 | case SIOCGMIIPHY: /* Get address of MII PHY in use. */ | |
1367 | data->phy_id = np->phys[0] & 0x1f; | |
1368 | /* Fall Through */ | |
1369 | ||
1370 | case SIOCGMIIREG: /* Read MII PHY register. */ | |
1371 | data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f); | |
1372 | return 0; | |
1373 | ||
1374 | case SIOCSMIIREG: /* Write MII PHY register. */ | |
1375 | if (!capable(CAP_NET_ADMIN)) | |
1376 | return -EPERM; | |
1377 | if (data->phy_id == np->phys[0]) { | |
1378 | u16 value = data->val_in; | |
1379 | switch (data->reg_num) { | |
1380 | case 0: | |
1381 | /* Check for autonegotiation on or reset. */ | |
1382 | np->medialock = (value & 0x9000) ? 0 : 1; | |
1383 | if (np->medialock) | |
1384 | np->full_duplex = (value & 0x0100) ? 1 : 0; | |
1385 | break; | |
1386 | case 4: np->advertising = value; break; | |
1387 | } | |
1388 | /* Perhaps check_duplex(dev), depending on chip semantics. */ | |
1389 | } | |
1390 | mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in); | |
1391 | return 0; | |
1392 | default: | |
1393 | return -EOPNOTSUPP; | |
1394 | } | |
1395 | } | |
1396 | ||
1397 | ||
1398 | static void __devexit yellowfin_remove_one (struct pci_dev *pdev) | |
1399 | { | |
1400 | struct net_device *dev = pci_get_drvdata(pdev); | |
1401 | struct yellowfin_private *np; | |
1402 | ||
5d9428de | 1403 | BUG_ON(!dev); |
1da177e4 LT |
1404 | np = netdev_priv(dev); |
1405 | ||
6aa20a22 | 1406 | pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status, |
1da177e4 LT |
1407 | np->tx_status_dma); |
1408 | pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma); | |
1409 | pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma); | |
1410 | unregister_netdev (dev); | |
1411 | ||
1412 | pci_iounmap(pdev, np->base); | |
1413 | ||
1414 | pci_release_regions (pdev); | |
1415 | ||
1416 | free_netdev (dev); | |
1417 | pci_set_drvdata(pdev, NULL); | |
1418 | } | |
1419 | ||
1420 | ||
1421 | static struct pci_driver yellowfin_driver = { | |
1422 | .name = DRV_NAME, | |
1423 | .id_table = yellowfin_pci_tbl, | |
1424 | .probe = yellowfin_init_one, | |
1425 | .remove = __devexit_p(yellowfin_remove_one), | |
1426 | }; | |
1427 | ||
1428 | ||
1429 | static int __init yellowfin_init (void) | |
1430 | { | |
1431 | /* when a module, this is printed whether or not devices are found in probe */ | |
1432 | #ifdef MODULE | |
1433 | printk(version); | |
1434 | #endif | |
29917620 | 1435 | return pci_register_driver(&yellowfin_driver); |
1da177e4 LT |
1436 | } |
1437 | ||
1438 | ||
1439 | static void __exit yellowfin_cleanup (void) | |
1440 | { | |
1441 | pci_unregister_driver (&yellowfin_driver); | |
1442 | } | |
1443 | ||
1444 | ||
1445 | module_init(yellowfin_init); | |
1446 | module_exit(yellowfin_cleanup); | |
6aa20a22 | 1447 | |
1da177e4 LT |
1448 | /* |
1449 | * Local variables: | |
1450 | * compile-command: "gcc -DMODULE -Wall -Wstrict-prototypes -O6 -c yellowfin.c" | |
1451 | * compile-command-alphaLX: "gcc -DMODULE -Wall -Wstrict-prototypes -O2 -c yellowfin.c -fomit-frame-pointer -fno-strength-reduce -mno-fp-regs -Wa,-m21164a -DBWX_USABLE -DBWIO_ENABLED" | |
1452 | * simple-compile-command: "gcc -DMODULE -O6 -c yellowfin.c" | |
1453 | * c-indent-level: 4 | |
1454 | * c-basic-offset: 4 | |
1455 | * tab-width: 4 | |
1456 | * End: | |
1457 | */ |