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97f18414 EL |
1 | /* |
2 | * I2C Link Layer for PN544 HCI based Driver | |
3 | * | |
4 | * Copyright (C) 2012 Intel Corporation. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
98b32dec | 16 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
97f18414 EL |
17 | */ |
18 | ||
17936b43 JP |
19 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
20 | ||
97f18414 EL |
21 | #include <linux/crc-ccitt.h> |
22 | #include <linux/module.h> | |
23 | #include <linux/i2c.h> | |
24 | #include <linux/gpio.h> | |
eda8565a CP |
25 | #include <linux/of_gpio.h> |
26 | #include <linux/of_irq.h> | |
97f18414 EL |
27 | #include <linux/miscdevice.h> |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/delay.h> | |
06c66034 EL |
30 | #include <linux/nfc.h> |
31 | #include <linux/firmware.h> | |
61cdb018 | 32 | #include <linux/platform_data/pn544.h> |
db083bcb | 33 | #include <asm/unaligned.h> |
97f18414 EL |
34 | |
35 | #include <net/nfc/hci.h> | |
36 | #include <net/nfc/llc.h> | |
06c66034 | 37 | #include <net/nfc/nfc.h> |
97f18414 EL |
38 | |
39 | #include "pn544.h" | |
40 | ||
41 | #define PN544_I2C_FRAME_HEADROOM 1 | |
42 | #define PN544_I2C_FRAME_TAILROOM 2 | |
43 | ||
44 | /* framing in HCI mode */ | |
45 | #define PN544_HCI_I2C_LLC_LEN 1 | |
46 | #define PN544_HCI_I2C_LLC_CRC 2 | |
47 | #define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \ | |
48 | PN544_HCI_I2C_LLC_CRC) | |
49 | #define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC) | |
50 | #define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29 | |
51 | #define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \ | |
52 | PN544_HCI_I2C_LLC_MAX_PAYLOAD) | |
53 | ||
54 | static struct i2c_device_id pn544_hci_i2c_id_table[] = { | |
55 | {"pn544", 0}, | |
56 | {} | |
57 | }; | |
58 | ||
59 | MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table); | |
60 | ||
61 | #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c" | |
62 | ||
971d63cf AW |
63 | /* |
64 | * Exposed through the 4 most significant bytes | |
65 | * from the HCI SW_VERSION first byte, a.k.a. | |
66 | * SW RomLib. | |
67 | */ | |
68 | #define PN544_HW_VARIANT_C2 0xa | |
69 | #define PN544_HW_VARIANT_C3 0xb | |
70 | ||
f1dd56fd | 71 | #define PN544_FW_CMD_RESET 0x01 |
06c66034 EL |
72 | #define PN544_FW_CMD_WRITE 0x08 |
73 | #define PN544_FW_CMD_CHECK 0x06 | |
f1dd56fd AW |
74 | #define PN544_FW_CMD_SECURE_WRITE 0x0C |
75 | #define PN544_FW_CMD_SECURE_CHUNK_WRITE 0x0D | |
06c66034 EL |
76 | |
77 | struct pn544_i2c_fw_frame_write { | |
78 | u8 cmd; | |
79 | u16 be_length; | |
80 | u8 be_dest_addr[3]; | |
81 | u16 be_datalen; | |
82 | u8 data[]; | |
83 | } __packed; | |
84 | ||
85 | struct pn544_i2c_fw_frame_check { | |
86 | u8 cmd; | |
87 | u16 be_length; | |
88 | u8 be_start_addr[3]; | |
89 | u16 be_datalen; | |
90 | u16 be_crc; | |
91 | } __packed; | |
92 | ||
93 | struct pn544_i2c_fw_frame_response { | |
94 | u8 status; | |
95 | u16 be_length; | |
96 | } __packed; | |
97 | ||
98 | struct pn544_i2c_fw_blob { | |
99 | u32 be_size; | |
100 | u32 be_destaddr; | |
101 | u8 data[]; | |
102 | }; | |
103 | ||
f1dd56fd AW |
104 | struct pn544_i2c_fw_secure_frame { |
105 | u8 cmd; | |
106 | u16 be_datalen; | |
107 | u8 data[]; | |
108 | } __packed; | |
109 | ||
110 | struct pn544_i2c_fw_secure_blob { | |
111 | u64 header; | |
112 | u8 data[]; | |
113 | }; | |
114 | ||
06c66034 EL |
115 | #define PN544_FW_CMD_RESULT_TIMEOUT 0x01 |
116 | #define PN544_FW_CMD_RESULT_BAD_CRC 0x02 | |
117 | #define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08 | |
118 | #define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B | |
119 | #define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11 | |
f1dd56fd | 120 | #define PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND 0x13 |
06c66034 | 121 | #define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18 |
f1dd56fd AW |
122 | #define PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR 0x19 |
123 | #define PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR 0x1D | |
124 | #define PN544_FW_CMD_RESULT_MEMORY_ERROR 0x20 | |
125 | #define PN544_FW_CMD_RESULT_CHUNK_OK 0x21 | |
06c66034 | 126 | #define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74 |
f1dd56fd AW |
127 | #define PN544_FW_CMD_RESULT_COMMAND_REJECTED 0xE0 |
128 | #define PN544_FW_CMD_RESULT_CHUNK_ERROR 0xE6 | |
06c66034 EL |
129 | |
130 | #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) | |
131 | ||
132 | #define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7 | |
133 | #define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE | |
134 | #define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8 | |
135 | #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\ | |
136 | PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\ | |
137 | PN544_FW_WRITE_BUFFER_MAX_LEN) | |
f1dd56fd AW |
138 | #define PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN 3 |
139 | #define PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN (PN544_FW_I2C_MAX_PAYLOAD -\ | |
140 | PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN) | |
141 | #define PN544_FW_SECURE_FRAME_HEADER_LEN 3 | |
142 | #define PN544_FW_SECURE_BLOB_HEADER_LEN 8 | |
06c66034 EL |
143 | |
144 | #define FW_WORK_STATE_IDLE 1 | |
145 | #define FW_WORK_STATE_START 2 | |
146 | #define FW_WORK_STATE_WAIT_WRITE_ANSWER 3 | |
147 | #define FW_WORK_STATE_WAIT_CHECK_ANSWER 4 | |
f1dd56fd | 148 | #define FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER 5 |
06c66034 | 149 | |
97f18414 EL |
150 | struct pn544_i2c_phy { |
151 | struct i2c_client *i2c_dev; | |
152 | struct nfc_hci_dev *hdev; | |
153 | ||
154 | unsigned int gpio_en; | |
155 | unsigned int gpio_irq; | |
156 | unsigned int gpio_fw; | |
157 | unsigned int en_polarity; | |
158 | ||
971d63cf AW |
159 | u8 hw_variant; |
160 | ||
06c66034 EL |
161 | struct work_struct fw_work; |
162 | int fw_work_state; | |
163 | char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1]; | |
164 | const struct firmware *fw; | |
165 | u32 fw_blob_dest_addr; | |
166 | size_t fw_blob_size; | |
167 | const u8 *fw_blob_data; | |
168 | size_t fw_written; | |
f1dd56fd AW |
169 | size_t fw_size; |
170 | ||
06c66034 EL |
171 | int fw_cmd_result; |
172 | ||
97f18414 | 173 | int powered; |
eab10b71 | 174 | int run_mode; |
97f18414 EL |
175 | |
176 | int hard_fault; /* | |
177 | * < 0 if hardware error occured (e.g. i2c err) | |
178 | * and prevents normal operation. | |
179 | */ | |
180 | }; | |
181 | ||
182 | #define I2C_DUMP_SKB(info, skb) \ | |
183 | do { \ | |
184 | pr_debug("%s:\n", info); \ | |
185 | print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \ | |
186 | 16, 1, (skb)->data, (skb)->len, 0); \ | |
187 | } while (0) | |
188 | ||
189 | static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy) | |
190 | { | |
191 | int polarity, retry, ret; | |
192 | char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 }; | |
193 | int count = sizeof(rset_cmd); | |
194 | ||
17936b43 | 195 | nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n"); |
97f18414 EL |
196 | |
197 | /* Disable fw download */ | |
75dda421 | 198 | gpio_set_value_cansleep(phy->gpio_fw, 0); |
97f18414 EL |
199 | |
200 | for (polarity = 0; polarity < 2; polarity++) { | |
201 | phy->en_polarity = polarity; | |
202 | retry = 3; | |
203 | while (retry--) { | |
204 | /* power off */ | |
75dda421 RD |
205 | gpio_set_value_cansleep(phy->gpio_en, |
206 | !phy->en_polarity); | |
97f18414 EL |
207 | usleep_range(10000, 15000); |
208 | ||
209 | /* power on */ | |
75dda421 | 210 | gpio_set_value_cansleep(phy->gpio_en, phy->en_polarity); |
97f18414 EL |
211 | usleep_range(10000, 15000); |
212 | ||
213 | /* send reset */ | |
214 | dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n"); | |
215 | ret = i2c_master_send(phy->i2c_dev, rset_cmd, count); | |
216 | if (ret == count) { | |
17936b43 | 217 | nfc_info(&phy->i2c_dev->dev, |
97f18414 EL |
218 | "nfc_en polarity : active %s\n", |
219 | (polarity == 0 ? "low" : "high")); | |
220 | goto out; | |
221 | } | |
222 | } | |
223 | } | |
224 | ||
17936b43 | 225 | nfc_err(&phy->i2c_dev->dev, |
97f18414 EL |
226 | "Could not detect nfc_en polarity, fallback to active high\n"); |
227 | ||
228 | out: | |
75dda421 | 229 | gpio_set_value_cansleep(phy->gpio_en, !phy->en_polarity); |
97f18414 EL |
230 | } |
231 | ||
eab10b71 EL |
232 | static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode) |
233 | { | |
75dda421 RD |
234 | gpio_set_value_cansleep(phy->gpio_fw, |
235 | run_mode == PN544_FW_MODE ? 1 : 0); | |
236 | gpio_set_value_cansleep(phy->gpio_en, phy->en_polarity); | |
eab10b71 EL |
237 | usleep_range(10000, 15000); |
238 | ||
239 | phy->run_mode = run_mode; | |
240 | } | |
241 | ||
97f18414 EL |
242 | static int pn544_hci_i2c_enable(void *phy_id) |
243 | { | |
244 | struct pn544_i2c_phy *phy = phy_id; | |
245 | ||
17936b43 | 246 | pr_info("%s\n", __func__); |
97f18414 | 247 | |
eab10b71 | 248 | pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE); |
97f18414 EL |
249 | |
250 | phy->powered = 1; | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
255 | static void pn544_hci_i2c_disable(void *phy_id) | |
256 | { | |
257 | struct pn544_i2c_phy *phy = phy_id; | |
258 | ||
75dda421 RD |
259 | gpio_set_value_cansleep(phy->gpio_fw, 0); |
260 | gpio_set_value_cansleep(phy->gpio_en, !phy->en_polarity); | |
97f18414 EL |
261 | usleep_range(10000, 15000); |
262 | ||
75dda421 | 263 | gpio_set_value_cansleep(phy->gpio_en, phy->en_polarity); |
97f18414 EL |
264 | usleep_range(10000, 15000); |
265 | ||
75dda421 | 266 | gpio_set_value_cansleep(phy->gpio_en, !phy->en_polarity); |
97f18414 EL |
267 | usleep_range(10000, 15000); |
268 | ||
269 | phy->powered = 0; | |
270 | } | |
271 | ||
272 | static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb) | |
273 | { | |
274 | u16 crc; | |
275 | int len; | |
276 | ||
277 | len = skb->len + 2; | |
278 | *skb_push(skb, 1) = len; | |
279 | ||
280 | crc = crc_ccitt(0xffff, skb->data, skb->len); | |
281 | crc = ~crc; | |
282 | *skb_put(skb, 1) = crc & 0xff; | |
283 | *skb_put(skb, 1) = crc >> 8; | |
284 | } | |
285 | ||
286 | static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb) | |
287 | { | |
288 | skb_pull(skb, PN544_I2C_FRAME_HEADROOM); | |
289 | skb_trim(skb, PN544_I2C_FRAME_TAILROOM); | |
290 | } | |
291 | ||
292 | /* | |
293 | * Writing a frame must not return the number of written bytes. | |
294 | * It must return either zero for success, or <0 for error. | |
295 | * In addition, it must not alter the skb | |
296 | */ | |
297 | static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb) | |
298 | { | |
299 | int r; | |
300 | struct pn544_i2c_phy *phy = phy_id; | |
301 | struct i2c_client *client = phy->i2c_dev; | |
302 | ||
303 | if (phy->hard_fault != 0) | |
304 | return phy->hard_fault; | |
305 | ||
306 | usleep_range(3000, 6000); | |
307 | ||
308 | pn544_hci_i2c_add_len_crc(skb); | |
309 | ||
310 | I2C_DUMP_SKB("i2c frame written", skb); | |
311 | ||
312 | r = i2c_master_send(client, skb->data, skb->len); | |
313 | ||
314 | if (r == -EREMOTEIO) { /* Retry, chip was in standby */ | |
315 | usleep_range(6000, 10000); | |
316 | r = i2c_master_send(client, skb->data, skb->len); | |
317 | } | |
318 | ||
319 | if (r >= 0) { | |
320 | if (r != skb->len) | |
321 | r = -EREMOTEIO; | |
322 | else | |
323 | r = 0; | |
324 | } | |
325 | ||
326 | pn544_hci_i2c_remove_len_crc(skb); | |
327 | ||
328 | return r; | |
329 | } | |
330 | ||
331 | static int check_crc(u8 *buf, int buflen) | |
332 | { | |
333 | int len; | |
334 | u16 crc; | |
335 | ||
336 | len = buf[0] + 1; | |
337 | crc = crc_ccitt(0xffff, buf, len - 2); | |
338 | crc = ~crc; | |
339 | ||
340 | if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) { | |
17936b43 | 341 | pr_err("CRC error 0x%x != 0x%x 0x%x\n", |
97f18414 | 342 | crc, buf[len - 1], buf[len - 2]); |
17936b43 | 343 | pr_info("%s: BAD CRC\n", __func__); |
97f18414 EL |
344 | print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE, |
345 | 16, 2, buf, buflen, false); | |
346 | return -EPERM; | |
347 | } | |
348 | return 0; | |
349 | } | |
350 | ||
351 | /* | |
352 | * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees | |
353 | * that i2c bus will be flushed and that next read will start on a new frame. | |
354 | * returned skb contains only LLC header and payload. | |
355 | * returns: | |
356 | * -EREMOTEIO : i2c read error (fatal) | |
357 | * -EBADMSG : frame was incorrect and discarded | |
358 | * -ENOMEM : cannot allocate skb, frame dropped | |
359 | */ | |
360 | static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb) | |
361 | { | |
362 | int r; | |
363 | u8 len; | |
364 | u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1]; | |
365 | struct i2c_client *client = phy->i2c_dev; | |
366 | ||
367 | r = i2c_master_recv(client, &len, 1); | |
368 | if (r != 1) { | |
17936b43 | 369 | nfc_err(&client->dev, "cannot read len byte\n"); |
97f18414 EL |
370 | return -EREMOTEIO; |
371 | } | |
372 | ||
373 | if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) || | |
374 | (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) { | |
17936b43 | 375 | nfc_err(&client->dev, "invalid len byte\n"); |
97f18414 EL |
376 | r = -EBADMSG; |
377 | goto flush; | |
378 | } | |
379 | ||
380 | *skb = alloc_skb(1 + len, GFP_KERNEL); | |
381 | if (*skb == NULL) { | |
382 | r = -ENOMEM; | |
383 | goto flush; | |
384 | } | |
385 | ||
386 | *skb_put(*skb, 1) = len; | |
387 | ||
388 | r = i2c_master_recv(client, skb_put(*skb, len), len); | |
389 | if (r != len) { | |
390 | kfree_skb(*skb); | |
391 | return -EREMOTEIO; | |
392 | } | |
393 | ||
394 | I2C_DUMP_SKB("i2c frame read", *skb); | |
395 | ||
396 | r = check_crc((*skb)->data, (*skb)->len); | |
397 | if (r != 0) { | |
398 | kfree_skb(*skb); | |
399 | r = -EBADMSG; | |
400 | goto flush; | |
401 | } | |
402 | ||
403 | skb_pull(*skb, 1); | |
404 | skb_trim(*skb, (*skb)->len - 2); | |
405 | ||
406 | usleep_range(3000, 6000); | |
407 | ||
408 | return 0; | |
409 | ||
410 | flush: | |
411 | if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0) | |
412 | r = -EREMOTEIO; | |
413 | ||
414 | usleep_range(3000, 6000); | |
415 | ||
416 | return r; | |
417 | } | |
418 | ||
06c66034 EL |
419 | static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy) |
420 | { | |
421 | int r; | |
422 | struct pn544_i2c_fw_frame_response response; | |
423 | struct i2c_client *client = phy->i2c_dev; | |
424 | ||
425 | r = i2c_master_recv(client, (char *) &response, sizeof(response)); | |
426 | if (r != sizeof(response)) { | |
17936b43 | 427 | nfc_err(&client->dev, "cannot read fw status\n"); |
06c66034 EL |
428 | return -EIO; |
429 | } | |
430 | ||
431 | usleep_range(3000, 6000); | |
432 | ||
433 | switch (response.status) { | |
434 | case 0: | |
435 | return 0; | |
f1dd56fd AW |
436 | case PN544_FW_CMD_RESULT_CHUNK_OK: |
437 | return response.status; | |
06c66034 EL |
438 | case PN544_FW_CMD_RESULT_TIMEOUT: |
439 | return -ETIMEDOUT; | |
440 | case PN544_FW_CMD_RESULT_BAD_CRC: | |
441 | return -ENODATA; | |
442 | case PN544_FW_CMD_RESULT_ACCESS_DENIED: | |
443 | return -EACCES; | |
444 | case PN544_FW_CMD_RESULT_PROTOCOL_ERROR: | |
445 | return -EPROTO; | |
446 | case PN544_FW_CMD_RESULT_INVALID_PARAMETER: | |
447 | return -EINVAL; | |
f1dd56fd AW |
448 | case PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND: |
449 | return -ENOTSUPP; | |
06c66034 EL |
450 | case PN544_FW_CMD_RESULT_INVALID_LENGTH: |
451 | return -EBADMSG; | |
f1dd56fd AW |
452 | case PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR: |
453 | return -ENOKEY; | |
454 | case PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR: | |
455 | return -EINVAL; | |
456 | case PN544_FW_CMD_RESULT_MEMORY_ERROR: | |
457 | return -ENOMEM; | |
458 | case PN544_FW_CMD_RESULT_COMMAND_REJECTED: | |
459 | return -EACCES; | |
06c66034 | 460 | case PN544_FW_CMD_RESULT_WRITE_FAILED: |
f1dd56fd | 461 | case PN544_FW_CMD_RESULT_CHUNK_ERROR: |
06c66034 EL |
462 | return -EIO; |
463 | default: | |
464 | return -EIO; | |
465 | } | |
466 | } | |
467 | ||
97f18414 EL |
468 | /* |
469 | * Reads an shdlc frame from the chip. This is not as straightforward as it | |
470 | * seems. There are cases where we could loose the frame start synchronization. | |
471 | * The frame format is len-data-crc, and corruption can occur anywhere while | |
472 | * transiting on i2c bus, such that we could read an invalid len. | |
473 | * In order to recover synchronization with the next frame, we must be sure | |
474 | * to read the real amount of data without using the len byte. We do this by | |
475 | * assuming the following: | |
476 | * - the chip will always present only one single complete frame on the bus | |
477 | * before triggering the interrupt | |
478 | * - the chip will not present a new frame until we have completely read | |
479 | * the previous one (or until we have handled the interrupt). | |
480 | * The tricky case is when we read a corrupted len that is less than the real | |
481 | * len. We must detect this here in order to determine that we need to flush | |
482 | * the bus. This is the reason why we check the crc here. | |
483 | */ | |
484 | static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id) | |
485 | { | |
486 | struct pn544_i2c_phy *phy = phy_id; | |
487 | struct i2c_client *client; | |
488 | struct sk_buff *skb = NULL; | |
489 | int r; | |
490 | ||
491 | if (!phy || irq != phy->i2c_dev->irq) { | |
492 | WARN_ON_ONCE(1); | |
493 | return IRQ_NONE; | |
494 | } | |
495 | ||
496 | client = phy->i2c_dev; | |
497 | dev_dbg(&client->dev, "IRQ\n"); | |
498 | ||
499 | if (phy->hard_fault != 0) | |
500 | return IRQ_HANDLED; | |
501 | ||
06c66034 EL |
502 | if (phy->run_mode == PN544_FW_MODE) { |
503 | phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy); | |
504 | schedule_work(&phy->fw_work); | |
505 | } else { | |
506 | r = pn544_hci_i2c_read(phy, &skb); | |
507 | if (r == -EREMOTEIO) { | |
508 | phy->hard_fault = r; | |
97f18414 | 509 | |
06c66034 | 510 | nfc_hci_recv_frame(phy->hdev, NULL); |
97f18414 | 511 | |
06c66034 EL |
512 | return IRQ_HANDLED; |
513 | } else if ((r == -ENOMEM) || (r == -EBADMSG)) { | |
514 | return IRQ_HANDLED; | |
515 | } | |
97f18414 | 516 | |
06c66034 EL |
517 | nfc_hci_recv_frame(phy->hdev, skb); |
518 | } | |
97f18414 EL |
519 | return IRQ_HANDLED; |
520 | } | |
521 | ||
522 | static struct nfc_phy_ops i2c_phy_ops = { | |
523 | .write = pn544_hci_i2c_write, | |
524 | .enable = pn544_hci_i2c_enable, | |
525 | .disable = pn544_hci_i2c_disable, | |
526 | }; | |
527 | ||
971d63cf AW |
528 | static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name, |
529 | u8 hw_variant) | |
06c66034 EL |
530 | { |
531 | struct pn544_i2c_phy *phy = phy_id; | |
532 | ||
17936b43 | 533 | pr_info("Starting Firmware Download (%s)\n", firmware_name); |
06c66034 EL |
534 | |
535 | strcpy(phy->firmware_name, firmware_name); | |
536 | ||
971d63cf | 537 | phy->hw_variant = hw_variant; |
06c66034 EL |
538 | phy->fw_work_state = FW_WORK_STATE_START; |
539 | ||
540 | schedule_work(&phy->fw_work); | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
545 | static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy, | |
546 | int result) | |
547 | { | |
17936b43 | 548 | pr_info("Firmware Download Complete, result=%d\n", result); |
06c66034 EL |
549 | |
550 | pn544_hci_i2c_disable(phy); | |
551 | ||
552 | phy->fw_work_state = FW_WORK_STATE_IDLE; | |
553 | ||
554 | if (phy->fw) { | |
555 | release_firmware(phy->fw); | |
556 | phy->fw = NULL; | |
557 | } | |
558 | ||
559 | nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result); | |
560 | } | |
561 | ||
562 | static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr, | |
563 | const u8 *data, u16 datalen) | |
564 | { | |
565 | u8 frame[PN544_FW_I2C_MAX_PAYLOAD]; | |
566 | struct pn544_i2c_fw_frame_write *framep; | |
567 | u16 params_len; | |
568 | int framelen; | |
569 | int r; | |
570 | ||
571 | if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN) | |
572 | datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN; | |
573 | ||
574 | framep = (struct pn544_i2c_fw_frame_write *) frame; | |
575 | ||
576 | params_len = sizeof(framep->be_dest_addr) + | |
577 | sizeof(framep->be_datalen) + datalen; | |
578 | framelen = params_len + sizeof(framep->cmd) + | |
579 | sizeof(framep->be_length); | |
580 | ||
581 | framep->cmd = PN544_FW_CMD_WRITE; | |
582 | ||
583 | put_unaligned_be16(params_len, &framep->be_length); | |
584 | ||
585 | framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16; | |
586 | framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8; | |
587 | framep->be_dest_addr[2] = dest_addr & 0xff; | |
588 | ||
589 | put_unaligned_be16(datalen, &framep->be_datalen); | |
590 | ||
591 | memcpy(framep->data, data, datalen); | |
592 | ||
593 | r = i2c_master_send(client, frame, framelen); | |
594 | ||
595 | if (r == framelen) | |
596 | return datalen; | |
597 | else if (r < 0) | |
598 | return r; | |
599 | else | |
600 | return -EIO; | |
601 | } | |
602 | ||
603 | static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr, | |
604 | const u8 *data, u16 datalen) | |
605 | { | |
606 | struct pn544_i2c_fw_frame_check frame; | |
607 | int r; | |
608 | u16 crc; | |
609 | ||
610 | /* calculate local crc for the data we want to check */ | |
611 | crc = crc_ccitt(0xffff, data, datalen); | |
612 | ||
613 | frame.cmd = PN544_FW_CMD_CHECK; | |
614 | ||
615 | put_unaligned_be16(sizeof(frame.be_start_addr) + | |
616 | sizeof(frame.be_datalen) + sizeof(frame.be_crc), | |
617 | &frame.be_length); | |
618 | ||
619 | /* tell the chip the memory region to which our crc applies */ | |
620 | frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16; | |
621 | frame.be_start_addr[1] = (start_addr & 0xff00) >> 8; | |
622 | frame.be_start_addr[2] = start_addr & 0xff; | |
623 | ||
624 | put_unaligned_be16(datalen, &frame.be_datalen); | |
625 | ||
626 | /* | |
627 | * and give our local crc. Chip will calculate its own crc for the | |
628 | * region and compare with ours. | |
629 | */ | |
630 | put_unaligned_be16(crc, &frame.be_crc); | |
631 | ||
632 | r = i2c_master_send(client, (const char *) &frame, sizeof(frame)); | |
633 | ||
634 | if (r == sizeof(frame)) | |
635 | return 0; | |
636 | else if (r < 0) | |
637 | return r; | |
638 | else | |
639 | return -EIO; | |
640 | } | |
641 | ||
642 | static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy) | |
643 | { | |
644 | int r; | |
645 | ||
646 | r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev, | |
647 | phy->fw_blob_dest_addr + phy->fw_written, | |
648 | phy->fw_blob_data + phy->fw_written, | |
649 | phy->fw_blob_size - phy->fw_written); | |
650 | if (r < 0) | |
651 | return r; | |
652 | ||
653 | phy->fw_written += r; | |
654 | phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER; | |
655 | ||
656 | return 0; | |
657 | } | |
658 | ||
f1dd56fd AW |
659 | static int pn544_hci_i2c_fw_secure_write_frame_cmd(struct pn544_i2c_phy *phy, |
660 | const u8 *data, u16 datalen) | |
661 | { | |
662 | u8 buf[PN544_FW_I2C_MAX_PAYLOAD]; | |
663 | struct pn544_i2c_fw_secure_frame *chunk; | |
664 | int chunklen; | |
665 | int r; | |
666 | ||
667 | if (datalen > PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN) | |
668 | datalen = PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN; | |
669 | ||
670 | chunk = (struct pn544_i2c_fw_secure_frame *) buf; | |
671 | ||
672 | chunk->cmd = PN544_FW_CMD_SECURE_CHUNK_WRITE; | |
673 | ||
674 | put_unaligned_be16(datalen, &chunk->be_datalen); | |
675 | ||
676 | memcpy(chunk->data, data, datalen); | |
677 | ||
678 | chunklen = sizeof(chunk->cmd) + sizeof(chunk->be_datalen) + datalen; | |
679 | ||
680 | r = i2c_master_send(phy->i2c_dev, buf, chunklen); | |
681 | ||
682 | if (r == chunklen) | |
683 | return datalen; | |
684 | else if (r < 0) | |
685 | return r; | |
686 | else | |
687 | return -EIO; | |
688 | ||
689 | } | |
690 | ||
691 | static int pn544_hci_i2c_fw_secure_write_frame(struct pn544_i2c_phy *phy) | |
692 | { | |
693 | struct pn544_i2c_fw_secure_frame *framep; | |
694 | int r; | |
695 | ||
696 | framep = (struct pn544_i2c_fw_secure_frame *) phy->fw_blob_data; | |
697 | if (phy->fw_written == 0) | |
698 | phy->fw_blob_size = get_unaligned_be16(&framep->be_datalen) | |
699 | + PN544_FW_SECURE_FRAME_HEADER_LEN; | |
700 | ||
701 | /* Only secure write command can be chunked*/ | |
702 | if (phy->fw_blob_size > PN544_FW_I2C_MAX_PAYLOAD && | |
703 | framep->cmd != PN544_FW_CMD_SECURE_WRITE) | |
704 | return -EINVAL; | |
705 | ||
706 | /* The firmware also have other commands, we just send them directly */ | |
707 | if (phy->fw_blob_size < PN544_FW_I2C_MAX_PAYLOAD) { | |
708 | r = i2c_master_send(phy->i2c_dev, | |
709 | (const char *) phy->fw_blob_data, phy->fw_blob_size); | |
710 | ||
711 | if (r == phy->fw_blob_size) | |
712 | goto exit; | |
713 | else if (r < 0) | |
714 | return r; | |
715 | else | |
716 | return -EIO; | |
717 | } | |
718 | ||
719 | r = pn544_hci_i2c_fw_secure_write_frame_cmd(phy, | |
720 | phy->fw_blob_data + phy->fw_written, | |
721 | phy->fw_blob_size - phy->fw_written); | |
722 | if (r < 0) | |
723 | return r; | |
724 | ||
725 | exit: | |
726 | phy->fw_written += r; | |
727 | phy->fw_work_state = FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER; | |
728 | ||
729 | /* SW reset command will not trig any response from PN544 */ | |
730 | if (framep->cmd == PN544_FW_CMD_RESET) { | |
731 | pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); | |
732 | phy->fw_cmd_result = 0; | |
733 | schedule_work(&phy->fw_work); | |
734 | } | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
06c66034 EL |
739 | static void pn544_hci_i2c_fw_work(struct work_struct *work) |
740 | { | |
741 | struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy, | |
742 | fw_work); | |
743 | int r; | |
744 | struct pn544_i2c_fw_blob *blob; | |
f1dd56fd | 745 | struct pn544_i2c_fw_secure_blob *secure_blob; |
06c66034 EL |
746 | |
747 | switch (phy->fw_work_state) { | |
748 | case FW_WORK_STATE_START: | |
749 | pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); | |
750 | ||
751 | r = request_firmware(&phy->fw, phy->firmware_name, | |
752 | &phy->i2c_dev->dev); | |
753 | if (r < 0) | |
754 | goto exit_state_start; | |
755 | ||
06c66034 | 756 | phy->fw_written = 0; |
f1dd56fd AW |
757 | |
758 | switch (phy->hw_variant) { | |
759 | case PN544_HW_VARIANT_C2: | |
760 | blob = (struct pn544_i2c_fw_blob *) phy->fw->data; | |
761 | phy->fw_blob_size = get_unaligned_be32(&blob->be_size); | |
762 | phy->fw_blob_dest_addr = get_unaligned_be32( | |
763 | &blob->be_destaddr); | |
764 | phy->fw_blob_data = blob->data; | |
765 | ||
766 | r = pn544_hci_i2c_fw_write_chunk(phy); | |
767 | break; | |
768 | case PN544_HW_VARIANT_C3: | |
769 | secure_blob = (struct pn544_i2c_fw_secure_blob *) | |
770 | phy->fw->data; | |
771 | phy->fw_blob_data = secure_blob->data; | |
772 | phy->fw_size = phy->fw->size; | |
773 | r = pn544_hci_i2c_fw_secure_write_frame(phy); | |
774 | break; | |
775 | default: | |
776 | r = -ENOTSUPP; | |
777 | break; | |
778 | } | |
06c66034 EL |
779 | |
780 | exit_state_start: | |
781 | if (r < 0) | |
782 | pn544_hci_i2c_fw_work_complete(phy, r); | |
783 | break; | |
784 | ||
785 | case FW_WORK_STATE_WAIT_WRITE_ANSWER: | |
786 | r = phy->fw_cmd_result; | |
787 | if (r < 0) | |
788 | goto exit_state_wait_write_answer; | |
789 | ||
790 | if (phy->fw_written == phy->fw_blob_size) { | |
791 | r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev, | |
792 | phy->fw_blob_dest_addr, | |
793 | phy->fw_blob_data, | |
794 | phy->fw_blob_size); | |
795 | if (r < 0) | |
796 | goto exit_state_wait_write_answer; | |
797 | phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER; | |
798 | break; | |
799 | } | |
800 | ||
801 | r = pn544_hci_i2c_fw_write_chunk(phy); | |
802 | ||
803 | exit_state_wait_write_answer: | |
804 | if (r < 0) | |
805 | pn544_hci_i2c_fw_work_complete(phy, r); | |
806 | break; | |
807 | ||
808 | case FW_WORK_STATE_WAIT_CHECK_ANSWER: | |
809 | r = phy->fw_cmd_result; | |
810 | if (r < 0) | |
811 | goto exit_state_wait_check_answer; | |
812 | ||
813 | blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data + | |
814 | phy->fw_blob_size); | |
815 | phy->fw_blob_size = get_unaligned_be32(&blob->be_size); | |
816 | if (phy->fw_blob_size != 0) { | |
817 | phy->fw_blob_dest_addr = | |
818 | get_unaligned_be32(&blob->be_destaddr); | |
819 | phy->fw_blob_data = blob->data; | |
820 | ||
821 | phy->fw_written = 0; | |
822 | r = pn544_hci_i2c_fw_write_chunk(phy); | |
823 | } | |
824 | ||
825 | exit_state_wait_check_answer: | |
826 | if (r < 0 || phy->fw_blob_size == 0) | |
827 | pn544_hci_i2c_fw_work_complete(phy, r); | |
828 | break; | |
829 | ||
f1dd56fd AW |
830 | case FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER: |
831 | r = phy->fw_cmd_result; | |
832 | if (r < 0) | |
833 | goto exit_state_wait_secure_write_answer; | |
834 | ||
835 | if (r == PN544_FW_CMD_RESULT_CHUNK_OK) { | |
836 | r = pn544_hci_i2c_fw_secure_write_frame(phy); | |
837 | goto exit_state_wait_secure_write_answer; | |
838 | } | |
839 | ||
840 | if (phy->fw_written == phy->fw_blob_size) { | |
841 | secure_blob = (struct pn544_i2c_fw_secure_blob *) | |
842 | (phy->fw_blob_data + phy->fw_blob_size); | |
843 | phy->fw_size -= phy->fw_blob_size + | |
844 | PN544_FW_SECURE_BLOB_HEADER_LEN; | |
845 | if (phy->fw_size >= PN544_FW_SECURE_BLOB_HEADER_LEN | |
846 | + PN544_FW_SECURE_FRAME_HEADER_LEN) { | |
847 | phy->fw_blob_data = secure_blob->data; | |
848 | ||
849 | phy->fw_written = 0; | |
850 | r = pn544_hci_i2c_fw_secure_write_frame(phy); | |
851 | } | |
852 | } | |
853 | ||
854 | exit_state_wait_secure_write_answer: | |
855 | if (r < 0 || phy->fw_size == 0) | |
856 | pn544_hci_i2c_fw_work_complete(phy, r); | |
857 | break; | |
858 | ||
06c66034 EL |
859 | default: |
860 | break; | |
861 | } | |
862 | } | |
863 | ||
eda8565a CP |
864 | #ifdef CONFIG_OF |
865 | ||
866 | static int pn544_hci_i2c_of_request_resources(struct i2c_client *client) | |
867 | { | |
868 | struct pn544_i2c_phy *phy = i2c_get_clientdata(client); | |
869 | struct device_node *pp; | |
870 | int ret; | |
871 | ||
872 | pp = client->dev.of_node; | |
873 | if (!pp) { | |
874 | ret = -ENODEV; | |
875 | goto err_dt; | |
876 | } | |
877 | ||
878 | /* Obtention of EN GPIO from device tree */ | |
879 | ret = of_get_named_gpio(pp, "enable-gpios", 0); | |
880 | if (ret < 0) { | |
881 | if (ret != -EPROBE_DEFER) | |
882 | nfc_err(&client->dev, | |
883 | "Failed to get EN gpio, error: %d\n", ret); | |
884 | goto err_dt; | |
885 | } | |
886 | phy->gpio_en = ret; | |
887 | ||
888 | /* Configuration of EN GPIO */ | |
889 | ret = gpio_request(phy->gpio_en, "pn544_en"); | |
890 | if (ret) { | |
891 | nfc_err(&client->dev, "Fail EN pin\n"); | |
892 | goto err_dt; | |
893 | } | |
894 | ret = gpio_direction_output(phy->gpio_en, 0); | |
895 | if (ret) { | |
896 | nfc_err(&client->dev, "Fail EN pin direction\n"); | |
897 | goto err_gpio_en; | |
898 | } | |
899 | ||
900 | /* Obtention of FW GPIO from device tree */ | |
901 | ret = of_get_named_gpio(pp, "firmware-gpios", 0); | |
902 | if (ret < 0) { | |
903 | if (ret != -EPROBE_DEFER) | |
904 | nfc_err(&client->dev, | |
905 | "Failed to get FW gpio, error: %d\n", ret); | |
906 | goto err_gpio_en; | |
907 | } | |
908 | phy->gpio_fw = ret; | |
909 | ||
910 | /* Configuration of FW GPIO */ | |
911 | ret = gpio_request(phy->gpio_fw, "pn544_fw"); | |
912 | if (ret) { | |
913 | nfc_err(&client->dev, "Fail FW pin\n"); | |
914 | goto err_gpio_en; | |
915 | } | |
916 | ret = gpio_direction_output(phy->gpio_fw, 0); | |
917 | if (ret) { | |
918 | nfc_err(&client->dev, "Fail FW pin direction\n"); | |
919 | goto err_gpio_fw; | |
920 | } | |
921 | ||
922 | /* IRQ */ | |
923 | ret = irq_of_parse_and_map(pp, 0); | |
924 | if (ret < 0) { | |
925 | nfc_err(&client->dev, | |
926 | "Unable to get irq, error: %d\n", ret); | |
927 | goto err_gpio_fw; | |
928 | } | |
929 | client->irq = ret; | |
930 | ||
931 | return 0; | |
932 | ||
933 | err_gpio_fw: | |
934 | gpio_free(phy->gpio_fw); | |
935 | err_gpio_en: | |
936 | gpio_free(phy->gpio_en); | |
937 | err_dt: | |
938 | return ret; | |
939 | } | |
940 | ||
941 | #else | |
942 | ||
943 | static int pn544_hci_i2c_of_request_resources(struct i2c_client *client) | |
944 | { | |
945 | return -ENODEV; | |
946 | } | |
947 | ||
948 | #endif | |
949 | ||
0fe763c5 GKH |
950 | static int pn544_hci_i2c_probe(struct i2c_client *client, |
951 | const struct i2c_device_id *id) | |
97f18414 EL |
952 | { |
953 | struct pn544_i2c_phy *phy; | |
954 | struct pn544_nfc_platform_data *pdata; | |
955 | int r = 0; | |
956 | ||
957 | dev_dbg(&client->dev, "%s\n", __func__); | |
958 | dev_dbg(&client->dev, "IRQ: %d\n", client->irq); | |
959 | ||
960 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { | |
17936b43 | 961 | nfc_err(&client->dev, "Need I2C_FUNC_I2C\n"); |
97f18414 EL |
962 | return -ENODEV; |
963 | } | |
964 | ||
a0f36536 SO |
965 | phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy), |
966 | GFP_KERNEL); | |
97f18414 | 967 | if (!phy) { |
17936b43 | 968 | nfc_err(&client->dev, |
97f18414 | 969 | "Cannot allocate memory for pn544 i2c phy.\n"); |
a0f36536 | 970 | return -ENOMEM; |
97f18414 EL |
971 | } |
972 | ||
06c66034 EL |
973 | INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work); |
974 | phy->fw_work_state = FW_WORK_STATE_IDLE; | |
975 | ||
97f18414 EL |
976 | phy->i2c_dev = client; |
977 | i2c_set_clientdata(client, phy); | |
978 | ||
979 | pdata = client->dev.platform_data; | |
97f18414 | 980 | |
eda8565a CP |
981 | /* No platform data, using device tree. */ |
982 | if (!pdata && client->dev.of_node) { | |
983 | r = pn544_hci_i2c_of_request_resources(client); | |
984 | if (r) { | |
985 | nfc_err(&client->dev, "No DT data\n"); | |
986 | return r; | |
987 | } | |
988 | /* Using platform data. */ | |
989 | } else if (pdata) { | |
97f18414 | 990 | |
eda8565a CP |
991 | if (pdata->request_resources == NULL) { |
992 | nfc_err(&client->dev, "request_resources() missing\n"); | |
993 | return -EINVAL; | |
994 | } | |
995 | ||
996 | r = pdata->request_resources(client); | |
997 | if (r) { | |
998 | nfc_err(&client->dev, | |
999 | "Cannot get platform resources\n"); | |
1000 | return r; | |
1001 | } | |
97f18414 | 1002 | |
eda8565a CP |
1003 | phy->gpio_en = pdata->get_gpio(NFC_GPIO_ENABLE); |
1004 | phy->gpio_fw = pdata->get_gpio(NFC_GPIO_FW_RESET); | |
1005 | phy->gpio_irq = pdata->get_gpio(NFC_GPIO_IRQ); | |
1006 | } else { | |
1007 | nfc_err(&client->dev, "No platform data\n"); | |
1008 | return -EINVAL; | |
1009 | } | |
97f18414 EL |
1010 | |
1011 | pn544_hci_i2c_platform_init(phy); | |
1012 | ||
1013 | r = request_threaded_irq(client->irq, NULL, pn544_hci_i2c_irq_thread_fn, | |
1014 | IRQF_TRIGGER_RISING | IRQF_ONESHOT, | |
1015 | PN544_HCI_I2C_DRIVER_NAME, phy); | |
1016 | if (r < 0) { | |
17936b43 | 1017 | nfc_err(&client->dev, "Unable to register IRQ handler\n"); |
97f18414 EL |
1018 | goto err_rti; |
1019 | } | |
1020 | ||
1021 | r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME, | |
1022 | PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM, | |
06c66034 EL |
1023 | PN544_HCI_I2C_LLC_MAX_PAYLOAD, |
1024 | pn544_hci_i2c_fw_download, &phy->hdev); | |
97f18414 EL |
1025 | if (r < 0) |
1026 | goto err_hci; | |
1027 | ||
1028 | return 0; | |
1029 | ||
1030 | err_hci: | |
1031 | free_irq(client->irq, phy); | |
1032 | ||
1033 | err_rti: | |
12b25dbf CP |
1034 | if (!pdata) { |
1035 | gpio_free(phy->gpio_en); | |
1036 | gpio_free(phy->gpio_fw); | |
1037 | } else if (pdata->free_resources) { | |
97f18414 | 1038 | pdata->free_resources(); |
12b25dbf | 1039 | } |
97f18414 | 1040 | |
97f18414 EL |
1041 | return r; |
1042 | } | |
1043 | ||
0fe763c5 | 1044 | static int pn544_hci_i2c_remove(struct i2c_client *client) |
97f18414 EL |
1045 | { |
1046 | struct pn544_i2c_phy *phy = i2c_get_clientdata(client); | |
1047 | struct pn544_nfc_platform_data *pdata = client->dev.platform_data; | |
1048 | ||
1049 | dev_dbg(&client->dev, "%s\n", __func__); | |
1050 | ||
06c66034 EL |
1051 | cancel_work_sync(&phy->fw_work); |
1052 | if (phy->fw_work_state != FW_WORK_STATE_IDLE) | |
1053 | pn544_hci_i2c_fw_work_complete(phy, -ENODEV); | |
1054 | ||
97f18414 EL |
1055 | pn544_hci_remove(phy->hdev); |
1056 | ||
1057 | if (phy->powered) | |
1058 | pn544_hci_i2c_disable(phy); | |
1059 | ||
1060 | free_irq(client->irq, phy); | |
eda8565a CP |
1061 | |
1062 | /* No platform data, GPIOs have been requested by this driver */ | |
1063 | if (!pdata) { | |
1064 | gpio_free(phy->gpio_en); | |
1065 | gpio_free(phy->gpio_fw); | |
1066 | /* Using platform data */ | |
1067 | } else if (pdata->free_resources) { | |
97f18414 | 1068 | pdata->free_resources(); |
eda8565a | 1069 | } |
97f18414 | 1070 | |
97f18414 EL |
1071 | return 0; |
1072 | } | |
1073 | ||
eda8565a CP |
1074 | static const struct of_device_id of_pn544_i2c_match[] = { |
1075 | { .compatible = "nxp,pn544-i2c", }, | |
1076 | {}, | |
1077 | }; | |
1078 | MODULE_DEVICE_TABLE(of, of_pn544_i2c_match); | |
1079 | ||
97f18414 EL |
1080 | static struct i2c_driver pn544_hci_i2c_driver = { |
1081 | .driver = { | |
1082 | .name = PN544_HCI_I2C_DRIVER_NAME, | |
eda8565a CP |
1083 | .owner = THIS_MODULE, |
1084 | .of_match_table = of_match_ptr(of_pn544_i2c_match), | |
97f18414 EL |
1085 | }, |
1086 | .probe = pn544_hci_i2c_probe, | |
1087 | .id_table = pn544_hci_i2c_id_table, | |
0fe763c5 | 1088 | .remove = pn544_hci_i2c_remove, |
97f18414 EL |
1089 | }; |
1090 | ||
234d4d6b | 1091 | module_i2c_driver(pn544_hci_i2c_driver); |
97f18414 EL |
1092 | |
1093 | MODULE_LICENSE("GPL"); | |
1094 | MODULE_DESCRIPTION(DRIVER_DESC); |