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97f18414 EL |
1 | /* |
2 | * I2C Link Layer for PN544 HCI based Driver | |
3 | * | |
4 | * Copyright (C) 2012 Intel Corporation. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
98b32dec | 16 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
97f18414 EL |
17 | */ |
18 | ||
17936b43 JP |
19 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
20 | ||
97f18414 EL |
21 | #include <linux/crc-ccitt.h> |
22 | #include <linux/module.h> | |
23 | #include <linux/i2c.h> | |
24 | #include <linux/gpio.h> | |
eda8565a CP |
25 | #include <linux/of_gpio.h> |
26 | #include <linux/of_irq.h> | |
0a5942c8 | 27 | #include <linux/acpi.h> |
97f18414 EL |
28 | #include <linux/interrupt.h> |
29 | #include <linux/delay.h> | |
06c66034 EL |
30 | #include <linux/nfc.h> |
31 | #include <linux/firmware.h> | |
0a5942c8 | 32 | #include <linux/gpio/consumer.h> |
e7f6ccaa | 33 | |
db083bcb | 34 | #include <asm/unaligned.h> |
97f18414 EL |
35 | |
36 | #include <net/nfc/hci.h> | |
37 | #include <net/nfc/llc.h> | |
06c66034 | 38 | #include <net/nfc/nfc.h> |
97f18414 EL |
39 | |
40 | #include "pn544.h" | |
41 | ||
42 | #define PN544_I2C_FRAME_HEADROOM 1 | |
43 | #define PN544_I2C_FRAME_TAILROOM 2 | |
44 | ||
0a5942c8 RD |
45 | /* GPIO names */ |
46 | #define PN544_GPIO_NAME_IRQ "pn544_irq" | |
47 | #define PN544_GPIO_NAME_FW "pn544_fw" | |
48 | #define PN544_GPIO_NAME_EN "pn544_en" | |
49 | ||
97f18414 EL |
50 | /* framing in HCI mode */ |
51 | #define PN544_HCI_I2C_LLC_LEN 1 | |
52 | #define PN544_HCI_I2C_LLC_CRC 2 | |
53 | #define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \ | |
54 | PN544_HCI_I2C_LLC_CRC) | |
55 | #define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC) | |
56 | #define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29 | |
57 | #define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \ | |
58 | PN544_HCI_I2C_LLC_MAX_PAYLOAD) | |
59 | ||
60 | static struct i2c_device_id pn544_hci_i2c_id_table[] = { | |
61 | {"pn544", 0}, | |
62 | {} | |
63 | }; | |
64 | ||
65 | MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table); | |
66 | ||
0a5942c8 RD |
67 | static const struct acpi_device_id pn544_hci_i2c_acpi_match[] = { |
68 | {"NXP5440", 0}, | |
69 | {} | |
70 | }; | |
71 | ||
72 | MODULE_DEVICE_TABLE(acpi, pn544_hci_i2c_acpi_match); | |
73 | ||
97f18414 EL |
74 | #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c" |
75 | ||
971d63cf AW |
76 | /* |
77 | * Exposed through the 4 most significant bytes | |
78 | * from the HCI SW_VERSION first byte, a.k.a. | |
79 | * SW RomLib. | |
80 | */ | |
81 | #define PN544_HW_VARIANT_C2 0xa | |
82 | #define PN544_HW_VARIANT_C3 0xb | |
83 | ||
f1dd56fd | 84 | #define PN544_FW_CMD_RESET 0x01 |
06c66034 EL |
85 | #define PN544_FW_CMD_WRITE 0x08 |
86 | #define PN544_FW_CMD_CHECK 0x06 | |
f1dd56fd AW |
87 | #define PN544_FW_CMD_SECURE_WRITE 0x0C |
88 | #define PN544_FW_CMD_SECURE_CHUNK_WRITE 0x0D | |
06c66034 EL |
89 | |
90 | struct pn544_i2c_fw_frame_write { | |
91 | u8 cmd; | |
92 | u16 be_length; | |
93 | u8 be_dest_addr[3]; | |
94 | u16 be_datalen; | |
95 | u8 data[]; | |
96 | } __packed; | |
97 | ||
98 | struct pn544_i2c_fw_frame_check { | |
99 | u8 cmd; | |
100 | u16 be_length; | |
101 | u8 be_start_addr[3]; | |
102 | u16 be_datalen; | |
103 | u16 be_crc; | |
104 | } __packed; | |
105 | ||
106 | struct pn544_i2c_fw_frame_response { | |
107 | u8 status; | |
108 | u16 be_length; | |
109 | } __packed; | |
110 | ||
111 | struct pn544_i2c_fw_blob { | |
112 | u32 be_size; | |
113 | u32 be_destaddr; | |
114 | u8 data[]; | |
115 | }; | |
116 | ||
f1dd56fd AW |
117 | struct pn544_i2c_fw_secure_frame { |
118 | u8 cmd; | |
119 | u16 be_datalen; | |
120 | u8 data[]; | |
121 | } __packed; | |
122 | ||
123 | struct pn544_i2c_fw_secure_blob { | |
124 | u64 header; | |
125 | u8 data[]; | |
126 | }; | |
127 | ||
06c66034 EL |
128 | #define PN544_FW_CMD_RESULT_TIMEOUT 0x01 |
129 | #define PN544_FW_CMD_RESULT_BAD_CRC 0x02 | |
130 | #define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08 | |
131 | #define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B | |
132 | #define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11 | |
f1dd56fd | 133 | #define PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND 0x13 |
06c66034 | 134 | #define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18 |
f1dd56fd AW |
135 | #define PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR 0x19 |
136 | #define PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR 0x1D | |
137 | #define PN544_FW_CMD_RESULT_MEMORY_ERROR 0x20 | |
138 | #define PN544_FW_CMD_RESULT_CHUNK_OK 0x21 | |
06c66034 | 139 | #define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74 |
f1dd56fd AW |
140 | #define PN544_FW_CMD_RESULT_COMMAND_REJECTED 0xE0 |
141 | #define PN544_FW_CMD_RESULT_CHUNK_ERROR 0xE6 | |
06c66034 EL |
142 | |
143 | #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) | |
144 | ||
145 | #define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7 | |
146 | #define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE | |
147 | #define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8 | |
148 | #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\ | |
149 | PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\ | |
150 | PN544_FW_WRITE_BUFFER_MAX_LEN) | |
f1dd56fd AW |
151 | #define PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN 3 |
152 | #define PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN (PN544_FW_I2C_MAX_PAYLOAD -\ | |
153 | PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN) | |
154 | #define PN544_FW_SECURE_FRAME_HEADER_LEN 3 | |
155 | #define PN544_FW_SECURE_BLOB_HEADER_LEN 8 | |
06c66034 EL |
156 | |
157 | #define FW_WORK_STATE_IDLE 1 | |
158 | #define FW_WORK_STATE_START 2 | |
159 | #define FW_WORK_STATE_WAIT_WRITE_ANSWER 3 | |
160 | #define FW_WORK_STATE_WAIT_CHECK_ANSWER 4 | |
f1dd56fd | 161 | #define FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER 5 |
06c66034 | 162 | |
97f18414 EL |
163 | struct pn544_i2c_phy { |
164 | struct i2c_client *i2c_dev; | |
165 | struct nfc_hci_dev *hdev; | |
166 | ||
167 | unsigned int gpio_en; | |
97f18414 EL |
168 | unsigned int gpio_fw; |
169 | unsigned int en_polarity; | |
170 | ||
971d63cf AW |
171 | u8 hw_variant; |
172 | ||
06c66034 EL |
173 | struct work_struct fw_work; |
174 | int fw_work_state; | |
175 | char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1]; | |
176 | const struct firmware *fw; | |
177 | u32 fw_blob_dest_addr; | |
178 | size_t fw_blob_size; | |
179 | const u8 *fw_blob_data; | |
180 | size_t fw_written; | |
f1dd56fd AW |
181 | size_t fw_size; |
182 | ||
06c66034 EL |
183 | int fw_cmd_result; |
184 | ||
97f18414 | 185 | int powered; |
eab10b71 | 186 | int run_mode; |
97f18414 EL |
187 | |
188 | int hard_fault; /* | |
189 | * < 0 if hardware error occured (e.g. i2c err) | |
190 | * and prevents normal operation. | |
191 | */ | |
192 | }; | |
193 | ||
194 | #define I2C_DUMP_SKB(info, skb) \ | |
195 | do { \ | |
196 | pr_debug("%s:\n", info); \ | |
197 | print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \ | |
198 | 16, 1, (skb)->data, (skb)->len, 0); \ | |
199 | } while (0) | |
200 | ||
201 | static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy) | |
202 | { | |
203 | int polarity, retry, ret; | |
204 | char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 }; | |
205 | int count = sizeof(rset_cmd); | |
206 | ||
17936b43 | 207 | nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n"); |
97f18414 EL |
208 | |
209 | /* Disable fw download */ | |
75dda421 | 210 | gpio_set_value_cansleep(phy->gpio_fw, 0); |
97f18414 EL |
211 | |
212 | for (polarity = 0; polarity < 2; polarity++) { | |
213 | phy->en_polarity = polarity; | |
214 | retry = 3; | |
215 | while (retry--) { | |
216 | /* power off */ | |
75dda421 RD |
217 | gpio_set_value_cansleep(phy->gpio_en, |
218 | !phy->en_polarity); | |
97f18414 EL |
219 | usleep_range(10000, 15000); |
220 | ||
221 | /* power on */ | |
75dda421 | 222 | gpio_set_value_cansleep(phy->gpio_en, phy->en_polarity); |
97f18414 EL |
223 | usleep_range(10000, 15000); |
224 | ||
225 | /* send reset */ | |
226 | dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n"); | |
227 | ret = i2c_master_send(phy->i2c_dev, rset_cmd, count); | |
228 | if (ret == count) { | |
17936b43 | 229 | nfc_info(&phy->i2c_dev->dev, |
97f18414 EL |
230 | "nfc_en polarity : active %s\n", |
231 | (polarity == 0 ? "low" : "high")); | |
232 | goto out; | |
233 | } | |
234 | } | |
235 | } | |
236 | ||
17936b43 | 237 | nfc_err(&phy->i2c_dev->dev, |
97f18414 EL |
238 | "Could not detect nfc_en polarity, fallback to active high\n"); |
239 | ||
240 | out: | |
75dda421 | 241 | gpio_set_value_cansleep(phy->gpio_en, !phy->en_polarity); |
97f18414 EL |
242 | } |
243 | ||
eab10b71 EL |
244 | static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode) |
245 | { | |
75dda421 RD |
246 | gpio_set_value_cansleep(phy->gpio_fw, |
247 | run_mode == PN544_FW_MODE ? 1 : 0); | |
248 | gpio_set_value_cansleep(phy->gpio_en, phy->en_polarity); | |
eab10b71 EL |
249 | usleep_range(10000, 15000); |
250 | ||
251 | phy->run_mode = run_mode; | |
252 | } | |
253 | ||
97f18414 EL |
254 | static int pn544_hci_i2c_enable(void *phy_id) |
255 | { | |
256 | struct pn544_i2c_phy *phy = phy_id; | |
257 | ||
17936b43 | 258 | pr_info("%s\n", __func__); |
97f18414 | 259 | |
eab10b71 | 260 | pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE); |
97f18414 EL |
261 | |
262 | phy->powered = 1; | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
267 | static void pn544_hci_i2c_disable(void *phy_id) | |
268 | { | |
269 | struct pn544_i2c_phy *phy = phy_id; | |
270 | ||
75dda421 RD |
271 | gpio_set_value_cansleep(phy->gpio_fw, 0); |
272 | gpio_set_value_cansleep(phy->gpio_en, !phy->en_polarity); | |
97f18414 EL |
273 | usleep_range(10000, 15000); |
274 | ||
75dda421 | 275 | gpio_set_value_cansleep(phy->gpio_en, phy->en_polarity); |
97f18414 EL |
276 | usleep_range(10000, 15000); |
277 | ||
75dda421 | 278 | gpio_set_value_cansleep(phy->gpio_en, !phy->en_polarity); |
97f18414 EL |
279 | usleep_range(10000, 15000); |
280 | ||
281 | phy->powered = 0; | |
282 | } | |
283 | ||
284 | static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb) | |
285 | { | |
286 | u16 crc; | |
287 | int len; | |
288 | ||
289 | len = skb->len + 2; | |
290 | *skb_push(skb, 1) = len; | |
291 | ||
292 | crc = crc_ccitt(0xffff, skb->data, skb->len); | |
293 | crc = ~crc; | |
294 | *skb_put(skb, 1) = crc & 0xff; | |
295 | *skb_put(skb, 1) = crc >> 8; | |
296 | } | |
297 | ||
298 | static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb) | |
299 | { | |
300 | skb_pull(skb, PN544_I2C_FRAME_HEADROOM); | |
301 | skb_trim(skb, PN544_I2C_FRAME_TAILROOM); | |
302 | } | |
303 | ||
304 | /* | |
305 | * Writing a frame must not return the number of written bytes. | |
306 | * It must return either zero for success, or <0 for error. | |
307 | * In addition, it must not alter the skb | |
308 | */ | |
309 | static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb) | |
310 | { | |
311 | int r; | |
312 | struct pn544_i2c_phy *phy = phy_id; | |
313 | struct i2c_client *client = phy->i2c_dev; | |
314 | ||
315 | if (phy->hard_fault != 0) | |
316 | return phy->hard_fault; | |
317 | ||
318 | usleep_range(3000, 6000); | |
319 | ||
320 | pn544_hci_i2c_add_len_crc(skb); | |
321 | ||
322 | I2C_DUMP_SKB("i2c frame written", skb); | |
323 | ||
324 | r = i2c_master_send(client, skb->data, skb->len); | |
325 | ||
326 | if (r == -EREMOTEIO) { /* Retry, chip was in standby */ | |
327 | usleep_range(6000, 10000); | |
328 | r = i2c_master_send(client, skb->data, skb->len); | |
329 | } | |
330 | ||
331 | if (r >= 0) { | |
332 | if (r != skb->len) | |
333 | r = -EREMOTEIO; | |
334 | else | |
335 | r = 0; | |
336 | } | |
337 | ||
338 | pn544_hci_i2c_remove_len_crc(skb); | |
339 | ||
340 | return r; | |
341 | } | |
342 | ||
343 | static int check_crc(u8 *buf, int buflen) | |
344 | { | |
345 | int len; | |
346 | u16 crc; | |
347 | ||
348 | len = buf[0] + 1; | |
349 | crc = crc_ccitt(0xffff, buf, len - 2); | |
350 | crc = ~crc; | |
351 | ||
352 | if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) { | |
17936b43 | 353 | pr_err("CRC error 0x%x != 0x%x 0x%x\n", |
97f18414 | 354 | crc, buf[len - 1], buf[len - 2]); |
17936b43 | 355 | pr_info("%s: BAD CRC\n", __func__); |
97f18414 EL |
356 | print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE, |
357 | 16, 2, buf, buflen, false); | |
358 | return -EPERM; | |
359 | } | |
360 | return 0; | |
361 | } | |
362 | ||
363 | /* | |
364 | * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees | |
365 | * that i2c bus will be flushed and that next read will start on a new frame. | |
366 | * returned skb contains only LLC header and payload. | |
367 | * returns: | |
368 | * -EREMOTEIO : i2c read error (fatal) | |
369 | * -EBADMSG : frame was incorrect and discarded | |
370 | * -ENOMEM : cannot allocate skb, frame dropped | |
371 | */ | |
372 | static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb) | |
373 | { | |
374 | int r; | |
375 | u8 len; | |
376 | u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1]; | |
377 | struct i2c_client *client = phy->i2c_dev; | |
378 | ||
379 | r = i2c_master_recv(client, &len, 1); | |
380 | if (r != 1) { | |
17936b43 | 381 | nfc_err(&client->dev, "cannot read len byte\n"); |
97f18414 EL |
382 | return -EREMOTEIO; |
383 | } | |
384 | ||
385 | if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) || | |
386 | (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) { | |
17936b43 | 387 | nfc_err(&client->dev, "invalid len byte\n"); |
97f18414 EL |
388 | r = -EBADMSG; |
389 | goto flush; | |
390 | } | |
391 | ||
392 | *skb = alloc_skb(1 + len, GFP_KERNEL); | |
393 | if (*skb == NULL) { | |
394 | r = -ENOMEM; | |
395 | goto flush; | |
396 | } | |
397 | ||
398 | *skb_put(*skb, 1) = len; | |
399 | ||
400 | r = i2c_master_recv(client, skb_put(*skb, len), len); | |
401 | if (r != len) { | |
402 | kfree_skb(*skb); | |
403 | return -EREMOTEIO; | |
404 | } | |
405 | ||
406 | I2C_DUMP_SKB("i2c frame read", *skb); | |
407 | ||
408 | r = check_crc((*skb)->data, (*skb)->len); | |
409 | if (r != 0) { | |
410 | kfree_skb(*skb); | |
411 | r = -EBADMSG; | |
412 | goto flush; | |
413 | } | |
414 | ||
415 | skb_pull(*skb, 1); | |
416 | skb_trim(*skb, (*skb)->len - 2); | |
417 | ||
418 | usleep_range(3000, 6000); | |
419 | ||
420 | return 0; | |
421 | ||
422 | flush: | |
423 | if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0) | |
424 | r = -EREMOTEIO; | |
425 | ||
426 | usleep_range(3000, 6000); | |
427 | ||
428 | return r; | |
429 | } | |
430 | ||
06c66034 EL |
431 | static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy) |
432 | { | |
433 | int r; | |
434 | struct pn544_i2c_fw_frame_response response; | |
435 | struct i2c_client *client = phy->i2c_dev; | |
436 | ||
437 | r = i2c_master_recv(client, (char *) &response, sizeof(response)); | |
438 | if (r != sizeof(response)) { | |
17936b43 | 439 | nfc_err(&client->dev, "cannot read fw status\n"); |
06c66034 EL |
440 | return -EIO; |
441 | } | |
442 | ||
443 | usleep_range(3000, 6000); | |
444 | ||
445 | switch (response.status) { | |
446 | case 0: | |
447 | return 0; | |
f1dd56fd AW |
448 | case PN544_FW_CMD_RESULT_CHUNK_OK: |
449 | return response.status; | |
06c66034 EL |
450 | case PN544_FW_CMD_RESULT_TIMEOUT: |
451 | return -ETIMEDOUT; | |
452 | case PN544_FW_CMD_RESULT_BAD_CRC: | |
453 | return -ENODATA; | |
454 | case PN544_FW_CMD_RESULT_ACCESS_DENIED: | |
455 | return -EACCES; | |
456 | case PN544_FW_CMD_RESULT_PROTOCOL_ERROR: | |
457 | return -EPROTO; | |
458 | case PN544_FW_CMD_RESULT_INVALID_PARAMETER: | |
459 | return -EINVAL; | |
f1dd56fd AW |
460 | case PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND: |
461 | return -ENOTSUPP; | |
06c66034 EL |
462 | case PN544_FW_CMD_RESULT_INVALID_LENGTH: |
463 | return -EBADMSG; | |
f1dd56fd AW |
464 | case PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR: |
465 | return -ENOKEY; | |
466 | case PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR: | |
467 | return -EINVAL; | |
468 | case PN544_FW_CMD_RESULT_MEMORY_ERROR: | |
469 | return -ENOMEM; | |
470 | case PN544_FW_CMD_RESULT_COMMAND_REJECTED: | |
471 | return -EACCES; | |
06c66034 | 472 | case PN544_FW_CMD_RESULT_WRITE_FAILED: |
f1dd56fd | 473 | case PN544_FW_CMD_RESULT_CHUNK_ERROR: |
06c66034 EL |
474 | return -EIO; |
475 | default: | |
476 | return -EIO; | |
477 | } | |
478 | } | |
479 | ||
97f18414 EL |
480 | /* |
481 | * Reads an shdlc frame from the chip. This is not as straightforward as it | |
482 | * seems. There are cases where we could loose the frame start synchronization. | |
483 | * The frame format is len-data-crc, and corruption can occur anywhere while | |
484 | * transiting on i2c bus, such that we could read an invalid len. | |
485 | * In order to recover synchronization with the next frame, we must be sure | |
486 | * to read the real amount of data without using the len byte. We do this by | |
487 | * assuming the following: | |
488 | * - the chip will always present only one single complete frame on the bus | |
489 | * before triggering the interrupt | |
490 | * - the chip will not present a new frame until we have completely read | |
491 | * the previous one (or until we have handled the interrupt). | |
492 | * The tricky case is when we read a corrupted len that is less than the real | |
493 | * len. We must detect this here in order to determine that we need to flush | |
494 | * the bus. This is the reason why we check the crc here. | |
495 | */ | |
496 | static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id) | |
497 | { | |
498 | struct pn544_i2c_phy *phy = phy_id; | |
499 | struct i2c_client *client; | |
500 | struct sk_buff *skb = NULL; | |
501 | int r; | |
502 | ||
503 | if (!phy || irq != phy->i2c_dev->irq) { | |
504 | WARN_ON_ONCE(1); | |
505 | return IRQ_NONE; | |
506 | } | |
507 | ||
508 | client = phy->i2c_dev; | |
509 | dev_dbg(&client->dev, "IRQ\n"); | |
510 | ||
511 | if (phy->hard_fault != 0) | |
512 | return IRQ_HANDLED; | |
513 | ||
06c66034 EL |
514 | if (phy->run_mode == PN544_FW_MODE) { |
515 | phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy); | |
516 | schedule_work(&phy->fw_work); | |
517 | } else { | |
518 | r = pn544_hci_i2c_read(phy, &skb); | |
519 | if (r == -EREMOTEIO) { | |
520 | phy->hard_fault = r; | |
97f18414 | 521 | |
06c66034 | 522 | nfc_hci_recv_frame(phy->hdev, NULL); |
97f18414 | 523 | |
06c66034 EL |
524 | return IRQ_HANDLED; |
525 | } else if ((r == -ENOMEM) || (r == -EBADMSG)) { | |
526 | return IRQ_HANDLED; | |
527 | } | |
97f18414 | 528 | |
06c66034 EL |
529 | nfc_hci_recv_frame(phy->hdev, skb); |
530 | } | |
97f18414 EL |
531 | return IRQ_HANDLED; |
532 | } | |
533 | ||
534 | static struct nfc_phy_ops i2c_phy_ops = { | |
535 | .write = pn544_hci_i2c_write, | |
536 | .enable = pn544_hci_i2c_enable, | |
537 | .disable = pn544_hci_i2c_disable, | |
538 | }; | |
539 | ||
971d63cf AW |
540 | static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name, |
541 | u8 hw_variant) | |
06c66034 EL |
542 | { |
543 | struct pn544_i2c_phy *phy = phy_id; | |
544 | ||
17936b43 | 545 | pr_info("Starting Firmware Download (%s)\n", firmware_name); |
06c66034 EL |
546 | |
547 | strcpy(phy->firmware_name, firmware_name); | |
548 | ||
971d63cf | 549 | phy->hw_variant = hw_variant; |
06c66034 EL |
550 | phy->fw_work_state = FW_WORK_STATE_START; |
551 | ||
552 | schedule_work(&phy->fw_work); | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
557 | static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy, | |
558 | int result) | |
559 | { | |
17936b43 | 560 | pr_info("Firmware Download Complete, result=%d\n", result); |
06c66034 EL |
561 | |
562 | pn544_hci_i2c_disable(phy); | |
563 | ||
564 | phy->fw_work_state = FW_WORK_STATE_IDLE; | |
565 | ||
566 | if (phy->fw) { | |
567 | release_firmware(phy->fw); | |
568 | phy->fw = NULL; | |
569 | } | |
570 | ||
571 | nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result); | |
572 | } | |
573 | ||
574 | static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr, | |
575 | const u8 *data, u16 datalen) | |
576 | { | |
577 | u8 frame[PN544_FW_I2C_MAX_PAYLOAD]; | |
578 | struct pn544_i2c_fw_frame_write *framep; | |
579 | u16 params_len; | |
580 | int framelen; | |
581 | int r; | |
582 | ||
583 | if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN) | |
584 | datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN; | |
585 | ||
586 | framep = (struct pn544_i2c_fw_frame_write *) frame; | |
587 | ||
588 | params_len = sizeof(framep->be_dest_addr) + | |
589 | sizeof(framep->be_datalen) + datalen; | |
590 | framelen = params_len + sizeof(framep->cmd) + | |
591 | sizeof(framep->be_length); | |
592 | ||
593 | framep->cmd = PN544_FW_CMD_WRITE; | |
594 | ||
595 | put_unaligned_be16(params_len, &framep->be_length); | |
596 | ||
597 | framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16; | |
598 | framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8; | |
599 | framep->be_dest_addr[2] = dest_addr & 0xff; | |
600 | ||
601 | put_unaligned_be16(datalen, &framep->be_datalen); | |
602 | ||
603 | memcpy(framep->data, data, datalen); | |
604 | ||
605 | r = i2c_master_send(client, frame, framelen); | |
606 | ||
607 | if (r == framelen) | |
608 | return datalen; | |
609 | else if (r < 0) | |
610 | return r; | |
611 | else | |
612 | return -EIO; | |
613 | } | |
614 | ||
615 | static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr, | |
616 | const u8 *data, u16 datalen) | |
617 | { | |
618 | struct pn544_i2c_fw_frame_check frame; | |
619 | int r; | |
620 | u16 crc; | |
621 | ||
622 | /* calculate local crc for the data we want to check */ | |
623 | crc = crc_ccitt(0xffff, data, datalen); | |
624 | ||
625 | frame.cmd = PN544_FW_CMD_CHECK; | |
626 | ||
627 | put_unaligned_be16(sizeof(frame.be_start_addr) + | |
628 | sizeof(frame.be_datalen) + sizeof(frame.be_crc), | |
629 | &frame.be_length); | |
630 | ||
631 | /* tell the chip the memory region to which our crc applies */ | |
632 | frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16; | |
633 | frame.be_start_addr[1] = (start_addr & 0xff00) >> 8; | |
634 | frame.be_start_addr[2] = start_addr & 0xff; | |
635 | ||
636 | put_unaligned_be16(datalen, &frame.be_datalen); | |
637 | ||
638 | /* | |
639 | * and give our local crc. Chip will calculate its own crc for the | |
640 | * region and compare with ours. | |
641 | */ | |
642 | put_unaligned_be16(crc, &frame.be_crc); | |
643 | ||
644 | r = i2c_master_send(client, (const char *) &frame, sizeof(frame)); | |
645 | ||
646 | if (r == sizeof(frame)) | |
647 | return 0; | |
648 | else if (r < 0) | |
649 | return r; | |
650 | else | |
651 | return -EIO; | |
652 | } | |
653 | ||
654 | static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy) | |
655 | { | |
656 | int r; | |
657 | ||
658 | r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev, | |
659 | phy->fw_blob_dest_addr + phy->fw_written, | |
660 | phy->fw_blob_data + phy->fw_written, | |
661 | phy->fw_blob_size - phy->fw_written); | |
662 | if (r < 0) | |
663 | return r; | |
664 | ||
665 | phy->fw_written += r; | |
666 | phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER; | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
f1dd56fd AW |
671 | static int pn544_hci_i2c_fw_secure_write_frame_cmd(struct pn544_i2c_phy *phy, |
672 | const u8 *data, u16 datalen) | |
673 | { | |
674 | u8 buf[PN544_FW_I2C_MAX_PAYLOAD]; | |
675 | struct pn544_i2c_fw_secure_frame *chunk; | |
676 | int chunklen; | |
677 | int r; | |
678 | ||
679 | if (datalen > PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN) | |
680 | datalen = PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN; | |
681 | ||
682 | chunk = (struct pn544_i2c_fw_secure_frame *) buf; | |
683 | ||
684 | chunk->cmd = PN544_FW_CMD_SECURE_CHUNK_WRITE; | |
685 | ||
686 | put_unaligned_be16(datalen, &chunk->be_datalen); | |
687 | ||
688 | memcpy(chunk->data, data, datalen); | |
689 | ||
690 | chunklen = sizeof(chunk->cmd) + sizeof(chunk->be_datalen) + datalen; | |
691 | ||
692 | r = i2c_master_send(phy->i2c_dev, buf, chunklen); | |
693 | ||
694 | if (r == chunklen) | |
695 | return datalen; | |
696 | else if (r < 0) | |
697 | return r; | |
698 | else | |
699 | return -EIO; | |
700 | ||
701 | } | |
702 | ||
703 | static int pn544_hci_i2c_fw_secure_write_frame(struct pn544_i2c_phy *phy) | |
704 | { | |
705 | struct pn544_i2c_fw_secure_frame *framep; | |
706 | int r; | |
707 | ||
708 | framep = (struct pn544_i2c_fw_secure_frame *) phy->fw_blob_data; | |
709 | if (phy->fw_written == 0) | |
710 | phy->fw_blob_size = get_unaligned_be16(&framep->be_datalen) | |
711 | + PN544_FW_SECURE_FRAME_HEADER_LEN; | |
712 | ||
713 | /* Only secure write command can be chunked*/ | |
714 | if (phy->fw_blob_size > PN544_FW_I2C_MAX_PAYLOAD && | |
715 | framep->cmd != PN544_FW_CMD_SECURE_WRITE) | |
716 | return -EINVAL; | |
717 | ||
718 | /* The firmware also have other commands, we just send them directly */ | |
719 | if (phy->fw_blob_size < PN544_FW_I2C_MAX_PAYLOAD) { | |
720 | r = i2c_master_send(phy->i2c_dev, | |
721 | (const char *) phy->fw_blob_data, phy->fw_blob_size); | |
722 | ||
723 | if (r == phy->fw_blob_size) | |
724 | goto exit; | |
725 | else if (r < 0) | |
726 | return r; | |
727 | else | |
728 | return -EIO; | |
729 | } | |
730 | ||
731 | r = pn544_hci_i2c_fw_secure_write_frame_cmd(phy, | |
732 | phy->fw_blob_data + phy->fw_written, | |
733 | phy->fw_blob_size - phy->fw_written); | |
734 | if (r < 0) | |
735 | return r; | |
736 | ||
737 | exit: | |
738 | phy->fw_written += r; | |
739 | phy->fw_work_state = FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER; | |
740 | ||
741 | /* SW reset command will not trig any response from PN544 */ | |
742 | if (framep->cmd == PN544_FW_CMD_RESET) { | |
743 | pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); | |
744 | phy->fw_cmd_result = 0; | |
745 | schedule_work(&phy->fw_work); | |
746 | } | |
747 | ||
748 | return 0; | |
749 | } | |
750 | ||
06c66034 EL |
751 | static void pn544_hci_i2c_fw_work(struct work_struct *work) |
752 | { | |
753 | struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy, | |
754 | fw_work); | |
755 | int r; | |
756 | struct pn544_i2c_fw_blob *blob; | |
f1dd56fd | 757 | struct pn544_i2c_fw_secure_blob *secure_blob; |
06c66034 EL |
758 | |
759 | switch (phy->fw_work_state) { | |
760 | case FW_WORK_STATE_START: | |
761 | pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); | |
762 | ||
763 | r = request_firmware(&phy->fw, phy->firmware_name, | |
764 | &phy->i2c_dev->dev); | |
765 | if (r < 0) | |
766 | goto exit_state_start; | |
767 | ||
06c66034 | 768 | phy->fw_written = 0; |
f1dd56fd AW |
769 | |
770 | switch (phy->hw_variant) { | |
771 | case PN544_HW_VARIANT_C2: | |
772 | blob = (struct pn544_i2c_fw_blob *) phy->fw->data; | |
773 | phy->fw_blob_size = get_unaligned_be32(&blob->be_size); | |
774 | phy->fw_blob_dest_addr = get_unaligned_be32( | |
775 | &blob->be_destaddr); | |
776 | phy->fw_blob_data = blob->data; | |
777 | ||
778 | r = pn544_hci_i2c_fw_write_chunk(phy); | |
779 | break; | |
780 | case PN544_HW_VARIANT_C3: | |
781 | secure_blob = (struct pn544_i2c_fw_secure_blob *) | |
782 | phy->fw->data; | |
783 | phy->fw_blob_data = secure_blob->data; | |
784 | phy->fw_size = phy->fw->size; | |
785 | r = pn544_hci_i2c_fw_secure_write_frame(phy); | |
786 | break; | |
787 | default: | |
788 | r = -ENOTSUPP; | |
789 | break; | |
790 | } | |
06c66034 EL |
791 | |
792 | exit_state_start: | |
793 | if (r < 0) | |
794 | pn544_hci_i2c_fw_work_complete(phy, r); | |
795 | break; | |
796 | ||
797 | case FW_WORK_STATE_WAIT_WRITE_ANSWER: | |
798 | r = phy->fw_cmd_result; | |
799 | if (r < 0) | |
800 | goto exit_state_wait_write_answer; | |
801 | ||
802 | if (phy->fw_written == phy->fw_blob_size) { | |
803 | r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev, | |
804 | phy->fw_blob_dest_addr, | |
805 | phy->fw_blob_data, | |
806 | phy->fw_blob_size); | |
807 | if (r < 0) | |
808 | goto exit_state_wait_write_answer; | |
809 | phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER; | |
810 | break; | |
811 | } | |
812 | ||
813 | r = pn544_hci_i2c_fw_write_chunk(phy); | |
814 | ||
815 | exit_state_wait_write_answer: | |
816 | if (r < 0) | |
817 | pn544_hci_i2c_fw_work_complete(phy, r); | |
818 | break; | |
819 | ||
820 | case FW_WORK_STATE_WAIT_CHECK_ANSWER: | |
821 | r = phy->fw_cmd_result; | |
822 | if (r < 0) | |
823 | goto exit_state_wait_check_answer; | |
824 | ||
825 | blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data + | |
826 | phy->fw_blob_size); | |
827 | phy->fw_blob_size = get_unaligned_be32(&blob->be_size); | |
828 | if (phy->fw_blob_size != 0) { | |
829 | phy->fw_blob_dest_addr = | |
830 | get_unaligned_be32(&blob->be_destaddr); | |
831 | phy->fw_blob_data = blob->data; | |
832 | ||
833 | phy->fw_written = 0; | |
834 | r = pn544_hci_i2c_fw_write_chunk(phy); | |
835 | } | |
836 | ||
837 | exit_state_wait_check_answer: | |
838 | if (r < 0 || phy->fw_blob_size == 0) | |
839 | pn544_hci_i2c_fw_work_complete(phy, r); | |
840 | break; | |
841 | ||
f1dd56fd AW |
842 | case FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER: |
843 | r = phy->fw_cmd_result; | |
844 | if (r < 0) | |
845 | goto exit_state_wait_secure_write_answer; | |
846 | ||
847 | if (r == PN544_FW_CMD_RESULT_CHUNK_OK) { | |
848 | r = pn544_hci_i2c_fw_secure_write_frame(phy); | |
849 | goto exit_state_wait_secure_write_answer; | |
850 | } | |
851 | ||
852 | if (phy->fw_written == phy->fw_blob_size) { | |
853 | secure_blob = (struct pn544_i2c_fw_secure_blob *) | |
854 | (phy->fw_blob_data + phy->fw_blob_size); | |
855 | phy->fw_size -= phy->fw_blob_size + | |
856 | PN544_FW_SECURE_BLOB_HEADER_LEN; | |
857 | if (phy->fw_size >= PN544_FW_SECURE_BLOB_HEADER_LEN | |
858 | + PN544_FW_SECURE_FRAME_HEADER_LEN) { | |
859 | phy->fw_blob_data = secure_blob->data; | |
860 | ||
861 | phy->fw_written = 0; | |
862 | r = pn544_hci_i2c_fw_secure_write_frame(phy); | |
863 | } | |
864 | } | |
865 | ||
866 | exit_state_wait_secure_write_answer: | |
867 | if (r < 0 || phy->fw_size == 0) | |
868 | pn544_hci_i2c_fw_work_complete(phy, r); | |
869 | break; | |
870 | ||
06c66034 EL |
871 | default: |
872 | break; | |
873 | } | |
874 | } | |
875 | ||
0a5942c8 RD |
876 | static int pn544_hci_i2c_acpi_request_resources(struct i2c_client *client) |
877 | { | |
878 | struct pn544_i2c_phy *phy = i2c_get_clientdata(client); | |
97b69788 | 879 | struct gpio_desc *gpiod_en, *gpiod_fw; |
dd215430 | 880 | struct device *dev = &client->dev; |
0a5942c8 RD |
881 | |
882 | /* Get EN GPIO from ACPI */ | |
8a2151c5 UKK |
883 | gpiod_en = devm_gpiod_get_index(dev, PN544_GPIO_NAME_EN, 1, |
884 | GPIOD_OUT_LOW); | |
0a5942c8 | 885 | if (IS_ERR(gpiod_en)) { |
8a2151c5 | 886 | nfc_err(dev, "Unable to get EN GPIO\n"); |
0a5942c8 RD |
887 | return -ENODEV; |
888 | } | |
889 | ||
8a2151c5 | 890 | phy->gpio_en = desc_to_gpio(gpiod_en); |
0a5942c8 RD |
891 | |
892 | /* Get FW GPIO from ACPI */ | |
8a2151c5 UKK |
893 | gpiod_fw = devm_gpiod_get_index(dev, PN544_GPIO_NAME_FW, 2, |
894 | GPIOD_OUT_LOW); | |
0a5942c8 | 895 | if (IS_ERR(gpiod_fw)) { |
8a2151c5 | 896 | nfc_err(dev, "Unable to get FW GPIO\n"); |
0a5942c8 RD |
897 | return -ENODEV; |
898 | } | |
899 | ||
8a2151c5 | 900 | phy->gpio_fw = desc_to_gpio(gpiod_fw); |
0a5942c8 | 901 | |
0a5942c8 RD |
902 | return 0; |
903 | } | |
904 | ||
eda8565a CP |
905 | static int pn544_hci_i2c_of_request_resources(struct i2c_client *client) |
906 | { | |
907 | struct pn544_i2c_phy *phy = i2c_get_clientdata(client); | |
908 | struct device_node *pp; | |
909 | int ret; | |
910 | ||
911 | pp = client->dev.of_node; | |
912 | if (!pp) { | |
913 | ret = -ENODEV; | |
914 | goto err_dt; | |
915 | } | |
916 | ||
917 | /* Obtention of EN GPIO from device tree */ | |
918 | ret = of_get_named_gpio(pp, "enable-gpios", 0); | |
919 | if (ret < 0) { | |
920 | if (ret != -EPROBE_DEFER) | |
921 | nfc_err(&client->dev, | |
922 | "Failed to get EN gpio, error: %d\n", ret); | |
923 | goto err_dt; | |
924 | } | |
925 | phy->gpio_en = ret; | |
926 | ||
927 | /* Configuration of EN GPIO */ | |
0a5942c8 | 928 | ret = gpio_request(phy->gpio_en, PN544_GPIO_NAME_EN); |
eda8565a CP |
929 | if (ret) { |
930 | nfc_err(&client->dev, "Fail EN pin\n"); | |
931 | goto err_dt; | |
932 | } | |
933 | ret = gpio_direction_output(phy->gpio_en, 0); | |
934 | if (ret) { | |
935 | nfc_err(&client->dev, "Fail EN pin direction\n"); | |
936 | goto err_gpio_en; | |
937 | } | |
938 | ||
939 | /* Obtention of FW GPIO from device tree */ | |
940 | ret = of_get_named_gpio(pp, "firmware-gpios", 0); | |
941 | if (ret < 0) { | |
942 | if (ret != -EPROBE_DEFER) | |
943 | nfc_err(&client->dev, | |
944 | "Failed to get FW gpio, error: %d\n", ret); | |
945 | goto err_gpio_en; | |
946 | } | |
947 | phy->gpio_fw = ret; | |
948 | ||
949 | /* Configuration of FW GPIO */ | |
0a5942c8 | 950 | ret = gpio_request(phy->gpio_fw, PN544_GPIO_NAME_FW); |
eda8565a CP |
951 | if (ret) { |
952 | nfc_err(&client->dev, "Fail FW pin\n"); | |
953 | goto err_gpio_en; | |
954 | } | |
955 | ret = gpio_direction_output(phy->gpio_fw, 0); | |
956 | if (ret) { | |
957 | nfc_err(&client->dev, "Fail FW pin direction\n"); | |
958 | goto err_gpio_fw; | |
959 | } | |
960 | ||
eda8565a CP |
961 | return 0; |
962 | ||
963 | err_gpio_fw: | |
964 | gpio_free(phy->gpio_fw); | |
965 | err_gpio_en: | |
966 | gpio_free(phy->gpio_en); | |
967 | err_dt: | |
968 | return ret; | |
969 | } | |
970 | ||
0fe763c5 GKH |
971 | static int pn544_hci_i2c_probe(struct i2c_client *client, |
972 | const struct i2c_device_id *id) | |
97f18414 EL |
973 | { |
974 | struct pn544_i2c_phy *phy; | |
97f18414 EL |
975 | int r = 0; |
976 | ||
977 | dev_dbg(&client->dev, "%s\n", __func__); | |
978 | dev_dbg(&client->dev, "IRQ: %d\n", client->irq); | |
979 | ||
980 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { | |
17936b43 | 981 | nfc_err(&client->dev, "Need I2C_FUNC_I2C\n"); |
97f18414 EL |
982 | return -ENODEV; |
983 | } | |
984 | ||
a0f36536 SO |
985 | phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy), |
986 | GFP_KERNEL); | |
3590ebc0 | 987 | if (!phy) |
a0f36536 | 988 | return -ENOMEM; |
97f18414 | 989 | |
06c66034 EL |
990 | INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work); |
991 | phy->fw_work_state = FW_WORK_STATE_IDLE; | |
992 | ||
97f18414 EL |
993 | phy->i2c_dev = client; |
994 | i2c_set_clientdata(client, phy); | |
995 | ||
eda8565a | 996 | /* No platform data, using device tree. */ |
e7f6ccaa | 997 | if (client->dev.of_node) { |
eda8565a CP |
998 | r = pn544_hci_i2c_of_request_resources(client); |
999 | if (r) { | |
1000 | nfc_err(&client->dev, "No DT data\n"); | |
1001 | return r; | |
1002 | } | |
0a5942c8 RD |
1003 | /* Using ACPI */ |
1004 | } else if (ACPI_HANDLE(&client->dev)) { | |
1005 | r = pn544_hci_i2c_acpi_request_resources(client); | |
1006 | if (r) { | |
1007 | nfc_err(&client->dev, | |
1008 | "Cannot get ACPI data\n"); | |
1009 | return r; | |
1010 | } | |
eda8565a CP |
1011 | } else { |
1012 | nfc_err(&client->dev, "No platform data\n"); | |
1013 | return -EINVAL; | |
1014 | } | |
97f18414 EL |
1015 | |
1016 | pn544_hci_i2c_platform_init(phy); | |
1017 | ||
1018 | r = request_threaded_irq(client->irq, NULL, pn544_hci_i2c_irq_thread_fn, | |
1019 | IRQF_TRIGGER_RISING | IRQF_ONESHOT, | |
1020 | PN544_HCI_I2C_DRIVER_NAME, phy); | |
1021 | if (r < 0) { | |
17936b43 | 1022 | nfc_err(&client->dev, "Unable to register IRQ handler\n"); |
97f18414 EL |
1023 | goto err_rti; |
1024 | } | |
1025 | ||
1026 | r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME, | |
1027 | PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM, | |
06c66034 EL |
1028 | PN544_HCI_I2C_LLC_MAX_PAYLOAD, |
1029 | pn544_hci_i2c_fw_download, &phy->hdev); | |
97f18414 EL |
1030 | if (r < 0) |
1031 | goto err_hci; | |
1032 | ||
1033 | return 0; | |
1034 | ||
1035 | err_hci: | |
1036 | free_irq(client->irq, phy); | |
1037 | ||
1038 | err_rti: | |
e7f6ccaa AS |
1039 | gpio_free(phy->gpio_en); |
1040 | gpio_free(phy->gpio_fw); | |
97f18414 | 1041 | |
97f18414 EL |
1042 | return r; |
1043 | } | |
1044 | ||
0fe763c5 | 1045 | static int pn544_hci_i2c_remove(struct i2c_client *client) |
97f18414 EL |
1046 | { |
1047 | struct pn544_i2c_phy *phy = i2c_get_clientdata(client); | |
97f18414 EL |
1048 | |
1049 | dev_dbg(&client->dev, "%s\n", __func__); | |
1050 | ||
06c66034 EL |
1051 | cancel_work_sync(&phy->fw_work); |
1052 | if (phy->fw_work_state != FW_WORK_STATE_IDLE) | |
1053 | pn544_hci_i2c_fw_work_complete(phy, -ENODEV); | |
1054 | ||
97f18414 EL |
1055 | pn544_hci_remove(phy->hdev); |
1056 | ||
1057 | if (phy->powered) | |
1058 | pn544_hci_i2c_disable(phy); | |
1059 | ||
1060 | free_irq(client->irq, phy); | |
eda8565a | 1061 | |
e7f6ccaa AS |
1062 | gpio_free(phy->gpio_en); |
1063 | gpio_free(phy->gpio_fw); | |
97f18414 | 1064 | |
97f18414 EL |
1065 | return 0; |
1066 | } | |
1067 | ||
eda8565a CP |
1068 | static const struct of_device_id of_pn544_i2c_match[] = { |
1069 | { .compatible = "nxp,pn544-i2c", }, | |
1070 | {}, | |
1071 | }; | |
1072 | MODULE_DEVICE_TABLE(of, of_pn544_i2c_match); | |
1073 | ||
97f18414 EL |
1074 | static struct i2c_driver pn544_hci_i2c_driver = { |
1075 | .driver = { | |
1076 | .name = PN544_HCI_I2C_DRIVER_NAME, | |
eda8565a | 1077 | .of_match_table = of_match_ptr(of_pn544_i2c_match), |
0a5942c8 | 1078 | .acpi_match_table = ACPI_PTR(pn544_hci_i2c_acpi_match), |
97f18414 EL |
1079 | }, |
1080 | .probe = pn544_hci_i2c_probe, | |
1081 | .id_table = pn544_hci_i2c_id_table, | |
0fe763c5 | 1082 | .remove = pn544_hci_i2c_remove, |
97f18414 EL |
1083 | }; |
1084 | ||
234d4d6b | 1085 | module_i2c_driver(pn544_hci_i2c_driver); |
97f18414 EL |
1086 | |
1087 | MODULE_LICENSE("GPL"); | |
1088 | MODULE_DESCRIPTION(DRIVER_DESC); |