[mirror_ubuntu-artful-kernel.git] / drivers / ntb / ntb_regs.h

/*
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 *   redistributing this file, you may do so under either license.
 *
 *   GPL LICENSE SUMMARY
 *
 *   Copyright(c) 2012 Intel Corporation. All rights reserved.
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of version 2 of the GNU General Public License as
 *   published by the Free Software Foundation.
 *
 *   BSD LICENSE
 *
 *   Copyright(c) 2012 Intel Corporation. All rights reserved.
 *
 *   Redistribution and use in source and binary forms, with or without
 *   modification, are permitted provided that the following conditions
 *   are met:
 *
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copy
 *       notice, this list of conditions and the following disclaimer in
 *       the documentation and/or other materials provided with the
 *       distribution.
 *     * Neither the name of Intel Corporation nor the names of its
 *       contributors may be used to endorse or promote products derived
 *       from this software without specific prior written permission.
 *
 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Intel PCIe NTB Linux driver
 *
 * Contact Information:
 * Jon Mason <jon.mason@intel.com>
 */

#define NTB_LINK_STATUS_ACTIVE	0x2000
#define NTB_LINK_SPEED_MASK	0x000f
#define NTB_LINK_WIDTH_MASK	0x03f0

#define SNB_MSIX_CNT		4
#define SNB_MAX_B2B_SPADS	16
#define SNB_MAX_COMPAT_SPADS	16
/* Reserve the uppermost bit for link interrupt */
#define SNB_MAX_DB_BITS		15
#define SNB_LINK_DB		15
#define SNB_DB_BITS_PER_VEC	5
#define HSX_SPLITBAR_MAX_MW	3
#define SNB_MAX_MW		2
#define SNB_ERRATA_MAX_MW	1

#define SNB_DB_HW_LINK		0x8000

#define SNB_UNCERRSTS_OFFSET	0x014C
#define SNB_CORERRSTS_OFFSET	0x0158
#define SNB_LINK_STATUS_OFFSET	0x01A2
#define SNB_PCICMD_OFFSET	0x0504
#define SNB_DEVCTRL_OFFSET	0x0598
#define SNB_DEVSTS_OFFSET	0x059A
#define SNB_SLINK_STATUS_OFFSET	0x05A2

#define SNB_PBAR2LMT_OFFSET	0x0000
#define SNB_PBAR4LMT_OFFSET	0x0008
#define SNB_PBAR5LMT_OFFSET	0x000C
#define SNB_PBAR2XLAT_OFFSET	0x0010
#define SNB_PBAR4XLAT_OFFSET	0x0018
#define SNB_PBAR5XLAT_OFFSET	0x001C
#define SNB_SBAR2LMT_OFFSET	0x0020
#define SNB_SBAR4LMT_OFFSET	0x0028
#define SNB_SBAR5LMT_OFFSET	0x002C
#define SNB_SBAR2XLAT_OFFSET	0x0030
#define SNB_SBAR4XLAT_OFFSET	0x0038
#define SNB_SBAR5XLAT_OFFSET	0x003C
#define SNB_SBAR0BASE_OFFSET	0x0040
#define SNB_SBAR2BASE_OFFSET	0x0048
#define SNB_SBAR4BASE_OFFSET	0x0050
#define SNB_SBAR5BASE_OFFSET	0x0054
#define SNB_NTBCNTL_OFFSET	0x0058
#define SNB_SBDF_OFFSET		0x005C
#define SNB_PDOORBELL_OFFSET	0x0060
#define SNB_PDBMSK_OFFSET	0x0062
#define SNB_SDOORBELL_OFFSET	0x0064
#define SNB_SDBMSK_OFFSET	0x0066
#define SNB_USMEMMISS_OFFSET	0x0070
#define SNB_SPAD_OFFSET		0x0080
#define SNB_SPADSEMA4_OFFSET	0x00c0
#define SNB_WCCNTRL_OFFSET	0x00e0
#define SNB_B2B_SPAD_OFFSET	0x0100
#define SNB_B2B_DOORBELL_OFFSET	0x0140
#define SNB_B2B_XLAT_OFFSETL	0x0144
#define SNB_B2B_XLAT_OFFSETU	0x0148

/*
 * The addresses are setup so the 32bit BARs can function. Thus
 * the addresses are all in 32bit space
 */
#define SNB_MBAR01_USD_ADDR	0x000000002100000CULL
#define SNB_MBAR23_USD_ADDR	0x000000004100000CULL
#define SNB_MBAR4_USD_ADDR	0x000000008100000CULL
#define SNB_MBAR5_USD_ADDR	0x00000000A100000CULL
#define SNB_MBAR01_DSD_ADDR	0x000000002000000CULL
#define SNB_MBAR23_DSD_ADDR	0x000000004000000CULL
#define SNB_MBAR4_DSD_ADDR	0x000000008000000CULL
#define SNB_MBAR5_DSD_ADDR	0x00000000A000000CULL

#define BWD_MSIX_CNT		34
#define BWD_MAX_SPADS		16
#define BWD_MAX_DB_BITS		34
#define BWD_DB_BITS_PER_VEC	1
#define BWD_MAX_MW		2

#define BWD_PCICMD_OFFSET	0xb004
#define BWD_MBAR23_OFFSET	0xb018
#define BWD_MBAR45_OFFSET	0xb020
#define BWD_DEVCTRL_OFFSET	0xb048
#define BWD_LINK_STATUS_OFFSET	0xb052
#define BWD_ERRCORSTS_OFFSET	0xb110

#define BWD_SBAR2XLAT_OFFSET	0x0008
#define BWD_SBAR4XLAT_OFFSET	0x0010
#define BWD_PDOORBELL_OFFSET	0x0020
#define BWD_PDBMSK_OFFSET	0x0028
#define BWD_NTBCNTL_OFFSET	0x0060
#define BWD_EBDF_OFFSET		0x0064
#define BWD_SPAD_OFFSET		0x0080
#define BWD_SPADSEMA_OFFSET	0x00c0
#define BWD_STKYSPAD_OFFSET	0x00c4
#define BWD_PBAR2XLAT_OFFSET	0x8008
#define BWD_PBAR4XLAT_OFFSET	0x8010
#define BWD_B2B_DOORBELL_OFFSET	0x8020
#define BWD_B2B_SPAD_OFFSET	0x8080
#define BWD_B2B_SPADSEMA_OFFSET	0x80c0
#define BWD_B2B_STKYSPAD_OFFSET	0x80c4

#define BWD_MODPHY_PCSREG4	0x1c004
#define BWD_MODPHY_PCSREG6	0x1c006

#define BWD_IP_BASE		0xC000
#define BWD_DESKEWSTS_OFFSET	(BWD_IP_BASE + 0x3024)
#define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180)
#define BWD_LTSSMSTATEJMP_OFFSET	(BWD_IP_BASE + 0x3040)
#define BWD_IBSTERRRCRVSTS0_OFFSET	(BWD_IP_BASE + 0x3324)

#define BWD_DESKEWSTS_DBERR	(1 << 15)
#define BWD_LTSSMERRSTS0_UNEXPECTEDEI	(1 << 20)
#define BWD_LTSSMSTATEJMP_FORCEDETECT	(1 << 2)
#define BWD_IBIST_ERR_OFLOW	0x7FFF7FFF

#define NTB_CNTL_CFG_LOCK		(1 << 0)
#define NTB_CNTL_LINK_DISABLE		(1 << 1)
#define NTB_CNTL_S2P_BAR23_SNOOP	(1 << 2)
#define NTB_CNTL_P2S_BAR23_SNOOP	(1 << 4)
#define NTB_CNTL_S2P_BAR4_SNOOP	(1 << 6)
#define NTB_CNTL_P2S_BAR4_SNOOP	(1 << 8)
#define NTB_CNTL_S2P_BAR5_SNOOP	(1 << 12)
#define NTB_CNTL_P2S_BAR5_SNOOP	(1 << 14)
#define BWD_CNTL_LINK_DOWN		(1 << 16)

#define NTB_PPD_OFFSET		0x00D4
#define SNB_PPD_CONN_TYPE	0x0003
#define SNB_PPD_DEV_TYPE	0x0010
#define SNB_PPD_SPLIT_BAR	(1 << 6)
#define BWD_PPD_INIT_LINK	0x0008
#define BWD_PPD_CONN_TYPE	0x0300
#define BWD_PPD_DEV_TYPE	0x1000
Commit	Line	Data
fce8a7bb JM	1	/*
	2	* This file is provided under a dual BSD/GPLv2 license. When using or
	3	* redistributing this file, you may do so under either license.
	4	*
	5	* GPL LICENSE SUMMARY
	6	*
	7	* Copyright(c) 2012 Intel Corporation. All rights reserved.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of version 2 of the GNU General Public License as
	11	* published by the Free Software Foundation.
	12	*
	13	* BSD LICENSE
	14	*
	15	* Copyright(c) 2012 Intel Corporation. All rights reserved.
	16	*
	17	* Redistribution and use in source and binary forms, with or without
	18	* modification, are permitted provided that the following conditions
	19	* are met:
	20	*
	21	* * Redistributions of source code must retain the above copyright
	22	* notice, this list of conditions and the following disclaimer.
	23	* * Redistributions in binary form must reproduce the above copy
	24	* notice, this list of conditions and the following disclaimer in
	25	* the documentation and/or other materials provided with the
	26	* distribution.
	27	* * Neither the name of Intel Corporation nor the names of its
	28	* contributors may be used to endorse or promote products derived
	29	* from this software without specific prior written permission.
	30	*
	31	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	32	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	33	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	34	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	35	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	36	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	37	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	38	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	39	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	40	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	42	*
	43	* Intel PCIe NTB Linux driver
	44	*
	45	* Contact Information:
	46	* Jon Mason <jon.mason@intel.com>
	47	*/
	48
fce8a7bb JM	49	#define NTB_LINK_STATUS_ACTIVE 0x2000
	50	#define NTB_LINK_SPEED_MASK 0x000f
	51	#define NTB_LINK_WIDTH_MASK 0x03f0
	52
	53	#define SNB_MSIX_CNT 4
87034511 JM	54	#define SNB_MAX_B2B_SPADS 16
87034511 JM	55	#define SNB_MAX_COMPAT_SPADS 16
fce8a7bb JM	56	/* Reserve the uppermost bit for link interrupt */
fce8a7bb JM	57	#define SNB_MAX_DB_BITS 15
c529aa30	58	#define SNB_LINK_DB 15
fce8a7bb	59	#define SNB_DB_BITS_PER_VEC 5
ab760a0c	60	#define HSX_SPLITBAR_MAX_MW 3
948d3a65 JM	61	#define SNB_MAX_MW 2
948d3a65 JM	62	#define SNB_ERRATA_MAX_MW 1
fce8a7bb JM	63
	64	#define SNB_DB_HW_LINK 0x8000
	65
6465d02e JM	66	#define SNB_UNCERRSTS_OFFSET 0x014C
	67	#define SNB_CORERRSTS_OFFSET 0x0158
	68	#define SNB_LINK_STATUS_OFFSET 0x01A2
fce8a7bb JM	69	#define SNB_PCICMD_OFFSET 0x0504
fce8a7bb JM	70	#define SNB_DEVCTRL_OFFSET 0x0598
6465d02e	71	#define SNB_DEVSTS_OFFSET 0x059A
ed6c24ed	72	#define SNB_SLINK_STATUS_OFFSET 0x05A2
fce8a7bb JM	73
	74	#define SNB_PBAR2LMT_OFFSET 0x0000
	75	#define SNB_PBAR4LMT_OFFSET 0x0008
ab760a0c	76	#define SNB_PBAR5LMT_OFFSET 0x000C
fce8a7bb JM	77	#define SNB_PBAR2XLAT_OFFSET 0x0010
fce8a7bb JM	78	#define SNB_PBAR4XLAT_OFFSET 0x0018
ab760a0c	79	#define SNB_PBAR5XLAT_OFFSET 0x001C
fce8a7bb JM	80	#define SNB_SBAR2LMT_OFFSET 0x0020
fce8a7bb JM	81	#define SNB_SBAR4LMT_OFFSET 0x0028
ab760a0c	82	#define SNB_SBAR5LMT_OFFSET 0x002C
fce8a7bb JM	83	#define SNB_SBAR2XLAT_OFFSET 0x0030
fce8a7bb JM	84	#define SNB_SBAR4XLAT_OFFSET 0x0038
ab760a0c	85	#define SNB_SBAR5XLAT_OFFSET 0x003C
fce8a7bb JM	86	#define SNB_SBAR0BASE_OFFSET 0x0040
	87	#define SNB_SBAR2BASE_OFFSET 0x0048
	88	#define SNB_SBAR4BASE_OFFSET 0x0050
ab760a0c	89	#define SNB_SBAR5BASE_OFFSET 0x0054
fce8a7bb JM	90	#define SNB_NTBCNTL_OFFSET 0x0058
	91	#define SNB_SBDF_OFFSET 0x005C
	92	#define SNB_PDOORBELL_OFFSET 0x0060
	93	#define SNB_PDBMSK_OFFSET 0x0062
	94	#define SNB_SDOORBELL_OFFSET 0x0064
	95	#define SNB_SDBMSK_OFFSET 0x0066
6465d02e	96	#define SNB_USMEMMISS_OFFSET 0x0070
fce8a7bb JM	97	#define SNB_SPAD_OFFSET 0x0080
	98	#define SNB_SPADSEMA4_OFFSET 0x00c0
	99	#define SNB_WCCNTRL_OFFSET 0x00e0
	100	#define SNB_B2B_SPAD_OFFSET 0x0100
	101	#define SNB_B2B_DOORBELL_OFFSET 0x0140
948d3a65 JM	102	#define SNB_B2B_XLAT_OFFSETL 0x0144
	103	#define SNB_B2B_XLAT_OFFSETU 0x0148
	104
ab760a0c DJ	105	/*
	106	* The addresses are setup so the 32bit BARs can function. Thus
	107	* the addresses are all in 32bit space
	108	*/
	109	#define SNB_MBAR01_USD_ADDR 0x000000002100000CULL
	110	#define SNB_MBAR23_USD_ADDR 0x000000004100000CULL
	111	#define SNB_MBAR4_USD_ADDR 0x000000008100000CULL
	112	#define SNB_MBAR5_USD_ADDR 0x00000000A100000CULL
	113	#define SNB_MBAR01_DSD_ADDR 0x000000002000000CULL
	114	#define SNB_MBAR23_DSD_ADDR 0x000000004000000CULL
	115	#define SNB_MBAR4_DSD_ADDR 0x000000008000000CULL
	116	#define SNB_MBAR5_DSD_ADDR 0x00000000A000000CULL
fce8a7bb JM	117
	118	#define BWD_MSIX_CNT 34
	119	#define BWD_MAX_SPADS 16
fce8a7bb JM	120	#define BWD_MAX_DB_BITS 34
fce8a7bb JM	121	#define BWD_DB_BITS_PER_VEC 1
948d3a65	122	#define BWD_MAX_MW 2
fce8a7bb JM	123
	124	#define BWD_PCICMD_OFFSET 0xb004
	125	#define BWD_MBAR23_OFFSET 0xb018
	126	#define BWD_MBAR45_OFFSET 0xb020
	127	#define BWD_DEVCTRL_OFFSET 0xb048
	128	#define BWD_LINK_STATUS_OFFSET 0xb052
113bf1c9	129	#define BWD_ERRCORSTS_OFFSET 0xb110
fce8a7bb JM	130
	131	#define BWD_SBAR2XLAT_OFFSET 0x0008
	132	#define BWD_SBAR4XLAT_OFFSET 0x0010
	133	#define BWD_PDOORBELL_OFFSET 0x0020
	134	#define BWD_PDBMSK_OFFSET 0x0028
	135	#define BWD_NTBCNTL_OFFSET 0x0060
	136	#define BWD_EBDF_OFFSET 0x0064
	137	#define BWD_SPAD_OFFSET 0x0080
	138	#define BWD_SPADSEMA_OFFSET 0x00c0
	139	#define BWD_STKYSPAD_OFFSET 0x00c4
	140	#define BWD_PBAR2XLAT_OFFSET 0x8008
	141	#define BWD_PBAR4XLAT_OFFSET 0x8010
	142	#define BWD_B2B_DOORBELL_OFFSET 0x8020
	143	#define BWD_B2B_SPAD_OFFSET 0x8080
	144	#define BWD_B2B_SPADSEMA_OFFSET 0x80c0
	145	#define BWD_B2B_STKYSPAD_OFFSET 0x80c4
	146
113bf1c9 JM	147	#define BWD_MODPHY_PCSREG4 0x1c004
	148	#define BWD_MODPHY_PCSREG6 0x1c006
	149
	150	#define BWD_IP_BASE 0xC000
	151	#define BWD_DESKEWSTS_OFFSET (BWD_IP_BASE + 0x3024)
	152	#define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180)
	153	#define BWD_LTSSMSTATEJMP_OFFSET (BWD_IP_BASE + 0x3040)
	154	#define BWD_IBSTERRRCRVSTS0_OFFSET (BWD_IP_BASE + 0x3324)
	155
	156	#define BWD_DESKEWSTS_DBERR (1 << 15)
	157	#define BWD_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20)
	158	#define BWD_LTSSMSTATEJMP_FORCEDETECT (1 << 2)
	159	#define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF
	160
78958433 JM	161	#define NTB_CNTL_CFG_LOCK (1 << 0)
	162	#define NTB_CNTL_LINK_DISABLE (1 << 1)
	163	#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2)
	164	#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4)
ab760a0c DJ	165	#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6)
	166	#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8)
	167	#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12)
	168	#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14)
78958433	169	#define BWD_CNTL_LINK_DOWN (1 << 16)
fce8a7bb JM	170
	171	#define NTB_PPD_OFFSET 0x00D4
	172	#define SNB_PPD_CONN_TYPE 0x0003
	173	#define SNB_PPD_DEV_TYPE 0x0010
ab760a0c	174	#define SNB_PPD_SPLIT_BAR (1 << 6)
fce8a7bb JM	175	#define BWD_PPD_INIT_LINK 0x0008
	176	#define BWD_PPD_CONN_TYPE 0x0300
	177	#define BWD_PPD_DEV_TYPE 0x1000