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5b497af4 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
4d88a97a DW |
2 | /* |
3 | * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. | |
4d88a97a DW |
4 | */ |
5 | #ifndef __ND_H__ | |
6 | #define __ND_H__ | |
1f7df6f8 | 7 | #include <linux/libnvdimm.h> |
200c79da | 8 | #include <linux/badblocks.h> |
f0dc089c | 9 | #include <linux/blkdev.h> |
4d88a97a DW |
10 | #include <linux/device.h> |
11 | #include <linux/mutex.h> | |
12 | #include <linux/ndctl.h> | |
bf9bccc1 | 13 | #include <linux/types.h> |
71999466 | 14 | #include <linux/nd.h> |
4a826c83 | 15 | #include "label.h" |
4d88a97a | 16 | |
8c2f7e86 | 17 | enum { |
5212e11f VV |
18 | /* |
19 | * Limits the maximum number of block apertures a dimm can | |
20 | * support and is an input to the geometry/on-disk-format of a | |
21 | * BTT instance | |
22 | */ | |
23 | ND_MAX_LANES = 256, | |
fcae6957 | 24 | INT_LBASIZE_ALIGNMENT = 64, |
3ae3d67b | 25 | NVDIMM_IO_ATOMIC = 1, |
8c2f7e86 DW |
26 | }; |
27 | ||
4d88a97a DW |
28 | struct nvdimm_drvdata { |
29 | struct device *dev; | |
02881768 | 30 | int nslabel_size; |
4d88a97a DW |
31 | struct nd_cmd_get_config_size nsarea; |
32 | void *data; | |
4a826c83 DW |
33 | int ns_current, ns_next; |
34 | struct resource dpa; | |
bf9bccc1 | 35 | struct kref kref; |
4d88a97a DW |
36 | }; |
37 | ||
e5ae3b25 DW |
38 | struct nd_region_data { |
39 | int ns_count; | |
40 | int ns_active; | |
595c7307 DW |
41 | unsigned int hints_shift; |
42 | void __iomem *flush_wpq[0]; | |
3d88002e DW |
43 | }; |
44 | ||
595c7307 DW |
45 | static inline void __iomem *ndrd_get_flush_wpq(struct nd_region_data *ndrd, |
46 | int dimm, int hint) | |
47 | { | |
48 | unsigned int num = 1 << ndrd->hints_shift; | |
49 | unsigned int mask = num - 1; | |
50 | ||
51 | return ndrd->flush_wpq[dimm * num + (hint & mask)]; | |
52 | } | |
53 | ||
54 | static inline void ndrd_set_flush_wpq(struct nd_region_data *ndrd, int dimm, | |
55 | int hint, void __iomem *flush) | |
56 | { | |
57 | unsigned int num = 1 << ndrd->hints_shift; | |
58 | unsigned int mask = num - 1; | |
59 | ||
60 | ndrd->flush_wpq[dimm * num + (hint & mask)] = flush; | |
61 | } | |
62 | ||
4a826c83 DW |
63 | static inline struct nd_namespace_index *to_namespace_index( |
64 | struct nvdimm_drvdata *ndd, int i) | |
65 | { | |
66 | if (i < 0) | |
67 | return NULL; | |
68 | ||
69 | return ndd->data + sizeof_namespace_index(ndd) * i; | |
70 | } | |
71 | ||
72 | static inline struct nd_namespace_index *to_current_namespace_index( | |
73 | struct nvdimm_drvdata *ndd) | |
74 | { | |
75 | return to_namespace_index(ndd, ndd->ns_current); | |
76 | } | |
77 | ||
78 | static inline struct nd_namespace_index *to_next_namespace_index( | |
79 | struct nvdimm_drvdata *ndd) | |
80 | { | |
81 | return to_namespace_index(ndd, ndd->ns_next); | |
82 | } | |
83 | ||
564e871a DW |
84 | unsigned sizeof_namespace_label(struct nvdimm_drvdata *ndd); |
85 | ||
86 | #define namespace_label_has(ndd, field) \ | |
87 | (offsetof(struct nd_namespace_label, field) \ | |
88 | < sizeof_namespace_label(ndd)) | |
89 | ||
4a826c83 DW |
90 | #define nd_dbg_dpa(r, d, res, fmt, arg...) \ |
91 | dev_dbg((r) ? &(r)->dev : (d)->dev, "%s: %.13s: %#llx @ %#llx " fmt, \ | |
92 | (r) ? dev_name((d)->dev) : "", res ? res->name : "null", \ | |
93 | (unsigned long long) (res ? resource_size(res) : 0), \ | |
94 | (unsigned long long) (res ? res->start : 0), ##arg) | |
95 | ||
bf9bccc1 DW |
96 | #define for_each_dpa_resource(ndd, res) \ |
97 | for (res = (ndd)->dpa.child; res; res = res->sibling) | |
98 | ||
4a826c83 DW |
99 | #define for_each_dpa_resource_safe(ndd, res, next) \ |
100 | for (res = (ndd)->dpa.child, next = res ? res->sibling : NULL; \ | |
101 | res; res = next, next = next ? next->sibling : NULL) | |
102 | ||
5212e11f VV |
103 | struct nd_percpu_lane { |
104 | int count; | |
105 | spinlock_t lock; | |
106 | }; | |
107 | ||
c4703ce1 DW |
108 | enum nd_label_flags { |
109 | ND_LABEL_REAP, | |
110 | }; | |
ae8219f1 DW |
111 | struct nd_label_ent { |
112 | struct list_head list; | |
c4703ce1 | 113 | unsigned long flags; |
ae8219f1 DW |
114 | struct nd_namespace_label *label; |
115 | }; | |
116 | ||
117 | enum nd_mapping_lock_class { | |
118 | ND_MAPPING_CLASS0, | |
119 | ND_MAPPING_UUID_SCAN, | |
120 | }; | |
121 | ||
44c462eb DW |
122 | struct nd_mapping { |
123 | struct nvdimm *nvdimm; | |
44c462eb DW |
124 | u64 start; |
125 | u64 size; | |
401c0a19 | 126 | int position; |
ae8219f1 DW |
127 | struct list_head labels; |
128 | struct mutex lock; | |
44c462eb DW |
129 | /* |
130 | * @ndd is for private use at region enable / disable time for | |
131 | * get_ndd() + put_ndd(), all other nd_mapping to ndd | |
132 | * conversions use to_ndd() which respects enabled state of the | |
133 | * nvdimm. | |
134 | */ | |
135 | struct nvdimm_drvdata *ndd; | |
136 | }; | |
137 | ||
1f7df6f8 DW |
138 | struct nd_region { |
139 | struct device dev; | |
1b40e09a | 140 | struct ida ns_ida; |
8c2f7e86 | 141 | struct ida btt_ida; |
e1455744 | 142 | struct ida pfn_ida; |
cd03412a | 143 | struct ida dax_ida; |
004f1afb | 144 | unsigned long flags; |
bf9bccc1 | 145 | struct device *ns_seed; |
8c2f7e86 | 146 | struct device *btt_seed; |
e1455744 | 147 | struct device *pfn_seed; |
cd03412a | 148 | struct device *dax_seed; |
1f7df6f8 DW |
149 | u16 ndr_mappings; |
150 | u64 ndr_size; | |
151 | u64 ndr_start; | |
8fc5c735 | 152 | int id, num_lanes, ro, numa_node, target_node; |
1f7df6f8 | 153 | void *provider_data; |
975750a9 | 154 | struct kernfs_node *bb_state; |
6a6bef90 | 155 | struct badblocks bb; |
eaf96153 | 156 | struct nd_interleave_set *nd_set; |
5212e11f | 157 | struct nd_percpu_lane __percpu *lane; |
c5d4355d | 158 | int (*flush)(struct nd_region *nd_region, struct bio *bio); |
1f7df6f8 DW |
159 | struct nd_mapping mapping[0]; |
160 | }; | |
161 | ||
047fc8a1 RZ |
162 | struct nd_blk_region { |
163 | int (*enable)(struct nvdimm_bus *nvdimm_bus, struct device *dev); | |
047fc8a1 RZ |
164 | int (*do_io)(struct nd_blk_region *ndbr, resource_size_t dpa, |
165 | void *iobuf, u64 len, int rw); | |
166 | void *blk_provider_data; | |
167 | struct nd_region nd_region; | |
168 | }; | |
169 | ||
4a826c83 DW |
170 | /* |
171 | * Lookup next in the repeating sequence of 01, 10, and 11. | |
172 | */ | |
173 | static inline unsigned nd_inc_seq(unsigned seq) | |
174 | { | |
175 | static const unsigned next[] = { 0, 2, 3, 1 }; | |
176 | ||
177 | return next[seq & 3]; | |
178 | } | |
f524bf27 | 179 | |
5212e11f | 180 | struct btt; |
8c2f7e86 DW |
181 | struct nd_btt { |
182 | struct device dev; | |
183 | struct nd_namespace_common *ndns; | |
5212e11f | 184 | struct btt *btt; |
8c2f7e86 | 185 | unsigned long lbasize; |
abe8b4e3 | 186 | u64 size; |
8c2f7e86 DW |
187 | u8 *uuid; |
188 | int id; | |
14e49454 VV |
189 | int initial_offset; |
190 | u16 version_major; | |
191 | u16 version_minor; | |
8c2f7e86 DW |
192 | }; |
193 | ||
e1455744 DW |
194 | enum nd_pfn_mode { |
195 | PFN_MODE_NONE, | |
196 | PFN_MODE_RAM, | |
197 | PFN_MODE_PMEM, | |
198 | }; | |
199 | ||
200 | struct nd_pfn { | |
201 | int id; | |
202 | u8 *uuid; | |
203 | struct device dev; | |
315c5625 | 204 | unsigned long align; |
e1455744 DW |
205 | unsigned long npfns; |
206 | enum nd_pfn_mode mode; | |
207 | struct nd_pfn_sb *pfn_sb; | |
208 | struct nd_namespace_common *ndns; | |
209 | }; | |
210 | ||
cd03412a DW |
211 | struct nd_dax { |
212 | struct nd_pfn nd_pfn; | |
213 | }; | |
214 | ||
8f4b01fc AK |
215 | static inline u32 nd_info_block_reserve(void) |
216 | { | |
217 | return ALIGN(SZ_8K, PAGE_SIZE); | |
218 | } | |
219 | ||
4d88a97a DW |
220 | enum nd_async_mode { |
221 | ND_SYNC, | |
222 | ND_ASYNC, | |
223 | }; | |
224 | ||
41cd8b70 | 225 | int nd_integrity_init(struct gendisk *disk, unsigned long meta_size); |
bf9bccc1 | 226 | void wait_nvdimm_bus_probe_idle(struct device *dev); |
4d88a97a DW |
227 | void nd_device_register(struct device *dev); |
228 | void nd_device_unregister(struct device *dev, enum nd_async_mode mode); | |
71999466 | 229 | void nd_device_notify(struct device *dev, enum nvdimm_event event); |
bf9bccc1 DW |
230 | int nd_uuid_store(struct device *dev, u8 **uuid_out, const char *buf, |
231 | size_t len); | |
b2c48f9f | 232 | ssize_t nd_size_select_show(unsigned long current_size, |
1b40e09a | 233 | const unsigned long *supported, char *buf); |
b2c48f9f DW |
234 | ssize_t nd_size_select_store(struct device *dev, const char *buf, |
235 | unsigned long *current_size, const unsigned long *supported); | |
4d88a97a | 236 | int __init nvdimm_init(void); |
3d88002e | 237 | int __init nd_region_init(void); |
b3fde74e | 238 | int __init nd_label_init(void); |
4d88a97a | 239 | void nvdimm_exit(void); |
3d88002e | 240 | void nd_region_exit(void); |
bf9bccc1 | 241 | struct nvdimm; |
adbb6829 | 242 | extern const struct attribute_group nd_device_attribute_group; |
e2f6a0e3 | 243 | extern const struct attribute_group nd_numa_attribute_group; |
e755799a | 244 | extern const struct attribute_group *nvdimm_bus_attribute_groups[]; |
bf9bccc1 | 245 | struct nvdimm_drvdata *to_ndd(struct nd_mapping *nd_mapping); |
aee65987 | 246 | int nvdimm_check_config_data(struct device *dev); |
4d88a97a DW |
247 | int nvdimm_init_nsarea(struct nvdimm_drvdata *ndd); |
248 | int nvdimm_init_config_data(struct nvdimm_drvdata *ndd); | |
2d657d17 AD |
249 | int nvdimm_get_config_data(struct nvdimm_drvdata *ndd, void *buf, |
250 | size_t offset, size_t len); | |
f524bf27 DW |
251 | int nvdimm_set_config_data(struct nvdimm_drvdata *ndd, size_t offset, |
252 | void *buf, size_t len); | |
59e64739 DW |
253 | long nvdimm_clear_poison(struct device *dev, phys_addr_t phys, |
254 | unsigned int len); | |
42237e39 | 255 | void nvdimm_set_aliasing(struct device *dev); |
8f078b38 | 256 | void nvdimm_set_locked(struct device *dev); |
d34cb808 | 257 | void nvdimm_clear_locked(struct device *dev); |
1cd73865 | 258 | int nvdimm_security_setup_events(struct device *dev); |
4c6926a2 DJ |
259 | #if IS_ENABLED(CONFIG_NVDIMM_KEYS) |
260 | int nvdimm_security_unlock(struct device *dev); | |
261 | #else | |
262 | static inline int nvdimm_security_unlock(struct device *dev) | |
263 | { | |
264 | return 0; | |
265 | } | |
266 | #endif | |
8c2f7e86 | 267 | struct nd_btt *to_nd_btt(struct device *dev); |
e1455744 DW |
268 | |
269 | struct nd_gen_sb { | |
270 | char reserved[SZ_4K - 8]; | |
271 | __le64 checksum; | |
272 | }; | |
273 | ||
274 | u64 nd_sb_checksum(struct nd_gen_sb *sb); | |
8c2f7e86 | 275 | #if IS_ENABLED(CONFIG_BTT) |
200c79da | 276 | int nd_btt_probe(struct device *dev, struct nd_namespace_common *ndns); |
8c2f7e86 DW |
277 | bool is_nd_btt(struct device *dev); |
278 | struct device *nd_btt_create(struct nd_region *nd_region); | |
279 | #else | |
e32bc729 | 280 | static inline int nd_btt_probe(struct device *dev, |
200c79da | 281 | struct nd_namespace_common *ndns) |
8c2f7e86 DW |
282 | { |
283 | return -ENODEV; | |
284 | } | |
285 | ||
286 | static inline bool is_nd_btt(struct device *dev) | |
287 | { | |
288 | return false; | |
289 | } | |
290 | ||
291 | static inline struct device *nd_btt_create(struct nd_region *nd_region) | |
292 | { | |
293 | return NULL; | |
294 | } | |
e1455744 | 295 | #endif |
8c2f7e86 | 296 | |
e1455744 DW |
297 | struct nd_pfn *to_nd_pfn(struct device *dev); |
298 | #if IS_ENABLED(CONFIG_NVDIMM_PFN) | |
0dd69643 | 299 | |
f5376699 | 300 | #define MAX_NVDIMM_ALIGN 4 |
0dd69643 | 301 | |
200c79da | 302 | int nd_pfn_probe(struct device *dev, struct nd_namespace_common *ndns); |
e1455744 DW |
303 | bool is_nd_pfn(struct device *dev); |
304 | struct device *nd_pfn_create(struct nd_region *nd_region); | |
cd03412a DW |
305 | struct device *nd_pfn_devinit(struct nd_pfn *nd_pfn, |
306 | struct nd_namespace_common *ndns); | |
c5ed9268 | 307 | int nd_pfn_validate(struct nd_pfn *nd_pfn, const char *sig); |
78c81cc8 | 308 | extern const struct attribute_group *nd_pfn_attribute_groups[]; |
e1455744 | 309 | #else |
200c79da DW |
310 | static inline int nd_pfn_probe(struct device *dev, |
311 | struct nd_namespace_common *ndns) | |
e1455744 DW |
312 | { |
313 | return -ENODEV; | |
314 | } | |
315 | ||
316 | static inline bool is_nd_pfn(struct device *dev) | |
317 | { | |
318 | return false; | |
319 | } | |
320 | ||
321 | static inline struct device *nd_pfn_create(struct nd_region *nd_region) | |
322 | { | |
323 | return NULL; | |
324 | } | |
32ab0a3f | 325 | |
c5ed9268 | 326 | static inline int nd_pfn_validate(struct nd_pfn *nd_pfn, const char *sig) |
32ab0a3f DW |
327 | { |
328 | return -ENODEV; | |
329 | } | |
8c2f7e86 | 330 | #endif |
e1455744 | 331 | |
cd03412a DW |
332 | struct nd_dax *to_nd_dax(struct device *dev); |
333 | #if IS_ENABLED(CONFIG_NVDIMM_DAX) | |
c5ed9268 | 334 | int nd_dax_probe(struct device *dev, struct nd_namespace_common *ndns); |
cd03412a DW |
335 | bool is_nd_dax(struct device *dev); |
336 | struct device *nd_dax_create(struct nd_region *nd_region); | |
337 | #else | |
c5ed9268 DW |
338 | static inline int nd_dax_probe(struct device *dev, |
339 | struct nd_namespace_common *ndns) | |
340 | { | |
341 | return -ENODEV; | |
342 | } | |
343 | ||
cd03412a DW |
344 | static inline bool is_nd_dax(struct device *dev) |
345 | { | |
346 | return false; | |
347 | } | |
348 | ||
349 | static inline struct device *nd_dax_create(struct nd_region *nd_region) | |
350 | { | |
351 | return NULL; | |
352 | } | |
353 | #endif | |
354 | ||
3d88002e DW |
355 | int nd_region_to_nstype(struct nd_region *nd_region); |
356 | int nd_region_register_namespaces(struct nd_region *nd_region, int *err); | |
c12c48ce DW |
357 | u64 nd_region_interleave_set_cookie(struct nd_region *nd_region, |
358 | struct nd_namespace_index *nsindex); | |
86ef58a4 | 359 | u64 nd_region_interleave_set_altcookie(struct nd_region *nd_region); |
3d88002e DW |
360 | void nvdimm_bus_lock(struct device *dev); |
361 | void nvdimm_bus_unlock(struct device *dev); | |
362 | bool is_nvdimm_bus_locked(struct device *dev); | |
58138820 | 363 | int nvdimm_revalidate_disk(struct gendisk *disk); |
bf9bccc1 DW |
364 | void nvdimm_drvdata_release(struct kref *kref); |
365 | void put_ndd(struct nvdimm_drvdata *ndd); | |
4a826c83 DW |
366 | int nd_label_reserve_dpa(struct nvdimm_drvdata *ndd); |
367 | void nvdimm_free_dpa(struct nvdimm_drvdata *ndd, struct resource *res); | |
368 | struct resource *nvdimm_allocate_dpa(struct nvdimm_drvdata *ndd, | |
369 | struct nd_label_id *label_id, resource_size_t start, | |
370 | resource_size_t n); | |
8c2f7e86 | 371 | resource_size_t nvdimm_namespace_capacity(struct nd_namespace_common *ndns); |
08e6b3c6 | 372 | bool nvdimm_namespace_locked(struct nd_namespace_common *ndns); |
8c2f7e86 | 373 | struct nd_namespace_common *nvdimm_namespace_common_probe(struct device *dev); |
5212e11f | 374 | int nvdimm_namespace_attach_btt(struct nd_namespace_common *ndns); |
298f2bc5 | 375 | int nvdimm_namespace_detach_btt(struct nd_btt *nd_btt); |
5212e11f VV |
376 | const char *nvdimm_namespace_disk_name(struct nd_namespace_common *ndns, |
377 | char *name); | |
f979b13c | 378 | unsigned int pmem_sector_size(struct nd_namespace_common *ndns); |
a3901802 DW |
379 | void nvdimm_badblocks_populate(struct nd_region *nd_region, |
380 | struct badblocks *bb, const struct resource *res); | |
8f4b01fc AK |
381 | int devm_namespace_enable(struct device *dev, struct nd_namespace_common *ndns, |
382 | resource_size_t size); | |
383 | void devm_namespace_disable(struct device *dev, | |
384 | struct nd_namespace_common *ndns); | |
200c79da | 385 | #if IS_ENABLED(CONFIG_ND_CLAIM) |
e96f0bf2 AK |
386 | /* max struct page size independent of kernel config */ |
387 | #define MAX_STRUCT_PAGE_SIZE 64 | |
e8d51348 | 388 | int nvdimm_setup_pfn(struct nd_pfn *nd_pfn, struct dev_pagemap *pgmap); |
200c79da | 389 | #else |
e8d51348 CH |
390 | static inline int nvdimm_setup_pfn(struct nd_pfn *nd_pfn, |
391 | struct dev_pagemap *pgmap) | |
ac515c08 | 392 | { |
e8d51348 | 393 | return -ENXIO; |
ac515c08 | 394 | } |
200c79da | 395 | #endif |
047fc8a1 | 396 | int nd_blk_region_init(struct nd_region *nd_region); |
e5ae3b25 | 397 | int nd_region_activate(struct nd_region *nd_region); |
f0dc089c DW |
398 | void __nd_iostat_start(struct bio *bio, unsigned long *start); |
399 | static inline bool nd_iostat_start(struct bio *bio, unsigned long *start) | |
400 | { | |
74d46992 | 401 | struct gendisk *disk = bio->bi_disk; |
f0dc089c DW |
402 | |
403 | if (!blk_queue_io_stat(disk->queue)) | |
404 | return false; | |
405 | ||
8d7c22ac | 406 | *start = jiffies; |
ddcf35d3 MC |
407 | generic_start_io_acct(disk->queue, bio_op(bio), bio_sectors(bio), |
408 | &disk->part0); | |
f0dc089c DW |
409 | return true; |
410 | } | |
8d7c22ac TK |
411 | static inline void nd_iostat_end(struct bio *bio, unsigned long start) |
412 | { | |
74d46992 | 413 | struct gendisk *disk = bio->bi_disk; |
8d7c22ac | 414 | |
ddcf35d3 | 415 | generic_end_io_acct(disk->queue, bio_op(bio), &disk->part0, start); |
8d7c22ac | 416 | } |
200c79da DW |
417 | static inline bool is_bad_pmem(struct badblocks *bb, sector_t sector, |
418 | unsigned int len) | |
419 | { | |
420 | if (bb->count) { | |
421 | sector_t first_bad; | |
422 | int num_bad; | |
423 | ||
424 | return !!badblocks_check(bb, sector, len / 512, &first_bad, | |
425 | &num_bad); | |
426 | } | |
427 | ||
428 | return false; | |
429 | } | |
047fc8a1 | 430 | resource_size_t nd_namespace_blk_validate(struct nd_namespace_blk *nsblk); |
6ec68954 | 431 | const u8 *nd_dev_to_uuid(struct device *dev); |
004f1afb | 432 | bool pmem_should_map_pages(struct device *dev); |
4d88a97a | 433 | #endif /* __ND_H__ */ |