]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/nvme/host/core.c
Merge branches 'for-4.11/upstream-fixes', 'for-4.12/accutouch', 'for-4.12/cp2112...
[mirror_ubuntu-artful-kernel.git] / drivers / nvme / host / core.c
CommitLineData
21d34711
CH
1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH
21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH
23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH
25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
29#include <scsi/sg.h>
30#include <asm/unaligned.h>
21d34711
CH
31
32#include "nvme.h"
038bd4cb 33#include "fabrics.h"
21d34711 34
f3ca80fc
CH
35#define NVME_MINORS (1U << MINORBITS)
36
ba0ba7d3
ML
37unsigned char admin_timeout = 60;
38module_param(admin_timeout, byte, 0644);
39MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 40EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3
ML
41
42unsigned char nvme_io_timeout = 30;
43module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
44MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 45EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3
ML
46
47unsigned char shutdown_timeout = 5;
48module_param(shutdown_timeout, byte, 0644);
49MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
50
f80ec966
KB
51unsigned int nvme_max_retries = 5;
52module_param_named(max_retries, nvme_max_retries, uint, 0644);
53MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
54EXPORT_SYMBOL_GPL(nvme_max_retries);
5bae7f73 55
f3ca80fc
CH
56static int nvme_char_major;
57module_param(nvme_char_major, int, 0);
58
59static LIST_HEAD(nvme_ctrl_list);
9f2482b9 60static DEFINE_SPINLOCK(dev_list_lock);
1673f1f0 61
f3ca80fc
CH
62static struct class *nvme_class;
63
c55a2fd4
ML
64void nvme_cancel_request(struct request *req, void *data, bool reserved)
65{
66 int status;
67
68 if (!blk_mq_request_started(req))
69 return;
70
71 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
72 "Cancelling I/O %d", req->tag);
73
74 status = NVME_SC_ABORT_REQ;
75 if (blk_queue_dying(req->q))
76 status |= NVME_SC_DNR;
77 blk_mq_complete_request(req, status);
78}
79EXPORT_SYMBOL_GPL(nvme_cancel_request);
80
bb8d261e
CH
81bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
82 enum nvme_ctrl_state new_state)
83{
f6b6a28e 84 enum nvme_ctrl_state old_state;
bb8d261e
CH
85 bool changed = false;
86
87 spin_lock_irq(&ctrl->lock);
f6b6a28e
GKB
88
89 old_state = ctrl->state;
bb8d261e
CH
90 switch (new_state) {
91 case NVME_CTRL_LIVE:
92 switch (old_state) {
7d2e8008 93 case NVME_CTRL_NEW:
bb8d261e 94 case NVME_CTRL_RESETTING:
def61eca 95 case NVME_CTRL_RECONNECTING:
bb8d261e
CH
96 changed = true;
97 /* FALLTHRU */
98 default:
99 break;
100 }
101 break;
102 case NVME_CTRL_RESETTING:
103 switch (old_state) {
104 case NVME_CTRL_NEW:
def61eca
CH
105 case NVME_CTRL_LIVE:
106 case NVME_CTRL_RECONNECTING:
107 changed = true;
108 /* FALLTHRU */
109 default:
110 break;
111 }
112 break;
113 case NVME_CTRL_RECONNECTING:
114 switch (old_state) {
bb8d261e
CH
115 case NVME_CTRL_LIVE:
116 changed = true;
117 /* FALLTHRU */
118 default:
119 break;
120 }
121 break;
122 case NVME_CTRL_DELETING:
123 switch (old_state) {
124 case NVME_CTRL_LIVE:
125 case NVME_CTRL_RESETTING:
def61eca 126 case NVME_CTRL_RECONNECTING:
bb8d261e
CH
127 changed = true;
128 /* FALLTHRU */
129 default:
130 break;
131 }
132 break;
0ff9d4e1
KB
133 case NVME_CTRL_DEAD:
134 switch (old_state) {
135 case NVME_CTRL_DELETING:
136 changed = true;
137 /* FALLTHRU */
138 default:
139 break;
140 }
141 break;
bb8d261e
CH
142 default:
143 break;
144 }
bb8d261e
CH
145
146 if (changed)
147 ctrl->state = new_state;
148
f6b6a28e
GKB
149 spin_unlock_irq(&ctrl->lock);
150
bb8d261e
CH
151 return changed;
152}
153EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
154
1673f1f0
CH
155static void nvme_free_ns(struct kref *kref)
156{
157 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
158
b0b4e09c
MB
159 if (ns->ndev)
160 nvme_nvm_unregister(ns);
1673f1f0 161
b0b4e09c
MB
162 if (ns->disk) {
163 spin_lock(&dev_list_lock);
164 ns->disk->private_data = NULL;
165 spin_unlock(&dev_list_lock);
166 }
1673f1f0 167
1673f1f0 168 put_disk(ns->disk);
075790eb
KB
169 ida_simple_remove(&ns->ctrl->ns_ida, ns->instance);
170 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH
171 kfree(ns);
172}
173
5bae7f73 174static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH
175{
176 kref_put(&ns->kref, nvme_free_ns);
177}
178
179static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk)
180{
181 struct nvme_ns *ns;
182
183 spin_lock(&dev_list_lock);
184 ns = disk->private_data;
e439bb12
SG
185 if (ns) {
186 if (!kref_get_unless_zero(&ns->kref))
187 goto fail;
188 if (!try_module_get(ns->ctrl->ops->module))
189 goto fail_put_ns;
190 }
1673f1f0
CH
191 spin_unlock(&dev_list_lock);
192
193 return ns;
e439bb12
SG
194
195fail_put_ns:
196 kref_put(&ns->kref, nvme_free_ns);
197fail:
198 spin_unlock(&dev_list_lock);
199 return NULL;
1673f1f0
CH
200}
201
7688faa6
CH
202void nvme_requeue_req(struct request *req)
203{
a6eaa884 204 blk_mq_requeue_request(req, !blk_mq_queue_stopped(req->q));
7688faa6 205}
576d55d6 206EXPORT_SYMBOL_GPL(nvme_requeue_req);
7688faa6 207
4160982e 208struct request *nvme_alloc_request(struct request_queue *q,
eb71f435 209 struct nvme_command *cmd, unsigned int flags, int qid)
21d34711 210{
aebf526b 211 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 212 struct request *req;
21d34711 213
eb71f435 214 if (qid == NVME_QID_ANY) {
aebf526b 215 req = blk_mq_alloc_request(q, op, flags);
eb71f435 216 } else {
aebf526b 217 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH
218 qid ? qid - 1 : 0);
219 }
21d34711 220 if (IS_ERR(req))
4160982e 221 return req;
21d34711 222
21d34711 223 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d49187e9 224 nvme_req(req)->cmd = cmd;
21d34711 225
4160982e
CH
226 return req;
227}
576d55d6 228EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 229
8093f7ca
ML
230static inline void nvme_setup_flush(struct nvme_ns *ns,
231 struct nvme_command *cmnd)
232{
233 memset(cmnd, 0, sizeof(*cmnd));
234 cmnd->common.opcode = nvme_cmd_flush;
235 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
236}
237
238static inline int nvme_setup_discard(struct nvme_ns *ns, struct request *req,
239 struct nvme_command *cmnd)
240{
b35ba01e 241 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 242 struct nvme_dsm_range *range;
b35ba01e 243 struct bio *bio;
8093f7ca 244
b35ba01e 245 range = kmalloc_array(segments, sizeof(*range), GFP_ATOMIC);
8093f7ca
ML
246 if (!range)
247 return BLK_MQ_RQ_QUEUE_BUSY;
248
b35ba01e
CH
249 __rq_for_each_bio(bio, req) {
250 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
251 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
252
253 range[n].cattr = cpu_to_le32(0);
254 range[n].nlb = cpu_to_le32(nlb);
255 range[n].slba = cpu_to_le64(slba);
256 n++;
257 }
258
259 if (WARN_ON_ONCE(n != segments)) {
260 kfree(range);
261 return BLK_MQ_RQ_QUEUE_ERROR;
262 }
8093f7ca
ML
263
264 memset(cmnd, 0, sizeof(*cmnd));
265 cmnd->dsm.opcode = nvme_cmd_dsm;
266 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
b35ba01e 267 cmnd->dsm.nr = segments - 1;
8093f7ca
ML
268 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
269
f9d03f96
CH
270 req->special_vec.bv_page = virt_to_page(range);
271 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 272 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 273 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 274
bac0000a 275 return BLK_MQ_RQ_QUEUE_OK;
8093f7ca 276}
8093f7ca 277
8093f7ca
ML
278static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req,
279 struct nvme_command *cmnd)
280{
281 u16 control = 0;
282 u32 dsmgmt = 0;
283
284 if (req->cmd_flags & REQ_FUA)
285 control |= NVME_RW_FUA;
286 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
287 control |= NVME_RW_LR;
288
289 if (req->cmd_flags & REQ_RAHEAD)
290 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
291
292 memset(cmnd, 0, sizeof(*cmnd));
293 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
8093f7ca
ML
294 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
295 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
296 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
297
298 if (ns->ms) {
299 switch (ns->pi_type) {
300 case NVME_NS_DPS_PI_TYPE3:
301 control |= NVME_RW_PRINFO_PRCHK_GUARD;
302 break;
303 case NVME_NS_DPS_PI_TYPE1:
304 case NVME_NS_DPS_PI_TYPE2:
305 control |= NVME_RW_PRINFO_PRCHK_GUARD |
306 NVME_RW_PRINFO_PRCHK_REF;
307 cmnd->rw.reftag = cpu_to_le32(
308 nvme_block_nr(ns, blk_rq_pos(req)));
309 break;
310 }
311 if (!blk_integrity_rq(req))
312 control |= NVME_RW_PRINFO_PRACT;
313 }
314
315 cmnd->rw.control = cpu_to_le16(control);
316 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
317}
318
319int nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
320 struct nvme_command *cmd)
321{
bac0000a 322 int ret = BLK_MQ_RQ_QUEUE_OK;
8093f7ca 323
aebf526b
CH
324 switch (req_op(req)) {
325 case REQ_OP_DRV_IN:
326 case REQ_OP_DRV_OUT:
d49187e9 327 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH
328 break;
329 case REQ_OP_FLUSH:
8093f7ca 330 nvme_setup_flush(ns, cmd);
aebf526b
CH
331 break;
332 case REQ_OP_DISCARD:
8093f7ca 333 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH
334 break;
335 case REQ_OP_READ:
336 case REQ_OP_WRITE:
8093f7ca 337 nvme_setup_rw(ns, req, cmd);
aebf526b
CH
338 break;
339 default:
340 WARN_ON_ONCE(1);
341 return BLK_MQ_RQ_QUEUE_ERROR;
342 }
8093f7ca 343
721b3917 344 cmd->common.command_id = req->tag;
8093f7ca
ML
345 return ret;
346}
347EXPORT_SYMBOL_GPL(nvme_setup_cmd);
348
4160982e
CH
349/*
350 * Returns 0 on success. If the result is negative, it's a Linux error code;
351 * if the result is positive, it's an NVM Express status code
352 */
353int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 354 union nvme_result *result, void *buffer, unsigned bufflen,
eb71f435 355 unsigned timeout, int qid, int at_head, int flags)
4160982e
CH
356{
357 struct request *req;
358 int ret;
359
eb71f435 360 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH
361 if (IS_ERR(req))
362 return PTR_ERR(req);
363
364 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
365
21d34711
CH
366 if (buffer && bufflen) {
367 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
368 if (ret)
369 goto out;
4160982e
CH
370 }
371
eb71f435 372 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH
373 if (result)
374 *result = nvme_req(req)->result;
4160982e
CH
375 ret = req->errors;
376 out:
377 blk_mq_free_request(req);
378 return ret;
379}
eb71f435 380EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH
381
382int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
383 void *buffer, unsigned bufflen)
384{
eb71f435
CH
385 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
386 NVME_QID_ANY, 0, 0);
4160982e 387}
576d55d6 388EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 389
0b7f1f26
KB
390int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
391 void __user *ubuffer, unsigned bufflen,
392 void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
393 u32 *result, unsigned timeout)
4160982e 394{
7a5abb4b 395 bool write = nvme_is_write(cmd);
0b7f1f26
KB
396 struct nvme_ns *ns = q->queuedata;
397 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 398 struct request *req;
0b7f1f26
KB
399 struct bio *bio = NULL;
400 void *meta = NULL;
4160982e
CH
401 int ret;
402
eb71f435 403 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH
404 if (IS_ERR(req))
405 return PTR_ERR(req);
406
407 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
408
409 if (ubuffer && bufflen) {
21d34711
CH
410 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
411 GFP_KERNEL);
412 if (ret)
413 goto out;
414 bio = req->bio;
21d34711 415
0b7f1f26
KB
416 if (!disk)
417 goto submit;
418 bio->bi_bdev = bdget_disk(disk, 0);
419 if (!bio->bi_bdev) {
420 ret = -ENODEV;
421 goto out_unmap;
422 }
423
e9fc63d6 424 if (meta_buffer && meta_len) {
0b7f1f26
KB
425 struct bio_integrity_payload *bip;
426
427 meta = kmalloc(meta_len, GFP_KERNEL);
428 if (!meta) {
429 ret = -ENOMEM;
430 goto out_unmap;
431 }
432
433 if (write) {
434 if (copy_from_user(meta, meta_buffer,
435 meta_len)) {
436 ret = -EFAULT;
437 goto out_free_meta;
438 }
439 }
440
441 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
06c1e390
KB
442 if (IS_ERR(bip)) {
443 ret = PTR_ERR(bip);
0b7f1f26
KB
444 goto out_free_meta;
445 }
446
447 bip->bip_iter.bi_size = meta_len;
448 bip->bip_iter.bi_sector = meta_seed;
449
450 ret = bio_integrity_add_page(bio, virt_to_page(meta),
451 meta_len, offset_in_page(meta));
452 if (ret != meta_len) {
453 ret = -ENOMEM;
454 goto out_free_meta;
455 }
456 }
457 }
458 submit:
459 blk_execute_rq(req->q, disk, req, 0);
460 ret = req->errors;
21d34711 461 if (result)
d49187e9 462 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB
463 if (meta && !ret && !write) {
464 if (copy_to_user(meta_buffer, meta, meta_len))
465 ret = -EFAULT;
466 }
467 out_free_meta:
468 kfree(meta);
469 out_unmap:
470 if (bio) {
471 if (disk && bio->bi_bdev)
472 bdput(bio->bi_bdev);
473 blk_rq_unmap_user(bio);
474 }
21d34711
CH
475 out:
476 blk_mq_free_request(req);
477 return ret;
478}
479
0b7f1f26
KB
480int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
481 void __user *ubuffer, unsigned bufflen, u32 *result,
482 unsigned timeout)
483{
484 return __nvme_submit_user_cmd(q, cmd, ubuffer, bufflen, NULL, 0, 0,
485 result, timeout);
486}
487
038bd4cb
SG
488static void nvme_keep_alive_end_io(struct request *rq, int error)
489{
490 struct nvme_ctrl *ctrl = rq->end_io_data;
491
492 blk_mq_free_request(rq);
493
494 if (error) {
495 dev_err(ctrl->device,
496 "failed nvme_keep_alive_end_io error=%d\n", error);
497 return;
498 }
499
500 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
501}
502
503static int nvme_keep_alive(struct nvme_ctrl *ctrl)
504{
505 struct nvme_command c;
506 struct request *rq;
507
508 memset(&c, 0, sizeof(c));
509 c.common.opcode = nvme_admin_keep_alive;
510
511 rq = nvme_alloc_request(ctrl->admin_q, &c, BLK_MQ_REQ_RESERVED,
512 NVME_QID_ANY);
513 if (IS_ERR(rq))
514 return PTR_ERR(rq);
515
516 rq->timeout = ctrl->kato * HZ;
517 rq->end_io_data = ctrl;
518
519 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
520
521 return 0;
522}
523
524static void nvme_keep_alive_work(struct work_struct *work)
525{
526 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
527 struct nvme_ctrl, ka_work);
528
529 if (nvme_keep_alive(ctrl)) {
530 /* allocation failure, reset the controller */
531 dev_err(ctrl->device, "keep-alive failed\n");
532 ctrl->ops->reset_ctrl(ctrl);
533 return;
534 }
535}
536
537void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
538{
539 if (unlikely(ctrl->kato == 0))
540 return;
541
542 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
543 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
544}
545EXPORT_SYMBOL_GPL(nvme_start_keep_alive);
546
547void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
548{
549 if (unlikely(ctrl->kato == 0))
550 return;
551
552 cancel_delayed_work_sync(&ctrl->ka_work);
553}
554EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
555
1c63dc66 556int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH
557{
558 struct nvme_command c = { };
559 int error;
560
561 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
562 c.identify.opcode = nvme_admin_identify;
fa606826 563 c.identify.cns = cpu_to_le32(NVME_ID_CNS_CTRL);
21d34711
CH
564
565 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
566 if (!*id)
567 return -ENOMEM;
568
569 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
570 sizeof(struct nvme_id_ctrl));
571 if (error)
572 kfree(*id);
573 return error;
574}
575
540c801c
KB
576static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
577{
578 struct nvme_command c = { };
579
580 c.identify.opcode = nvme_admin_identify;
fa606826 581 c.identify.cns = cpu_to_le32(NVME_ID_CNS_NS_ACTIVE_LIST);
540c801c
KB
582 c.identify.nsid = cpu_to_le32(nsid);
583 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000);
584}
585
1c63dc66 586int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
21d34711
CH
587 struct nvme_id_ns **id)
588{
589 struct nvme_command c = { };
590 int error;
591
592 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
593 c.identify.opcode = nvme_admin_identify,
594 c.identify.nsid = cpu_to_le32(nsid),
595
596 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
597 if (!*id)
598 return -ENOMEM;
599
600 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
601 sizeof(struct nvme_id_ns));
602 if (error)
603 kfree(*id);
604 return error;
605}
606
1c63dc66 607int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
1a6fe74d 608 void *buffer, size_t buflen, u32 *result)
21d34711
CH
609{
610 struct nvme_command c;
d49187e9 611 union nvme_result res;
1cb3cce5 612 int ret;
21d34711
CH
613
614 memset(&c, 0, sizeof(c));
615 c.features.opcode = nvme_admin_get_features;
616 c.features.nsid = cpu_to_le32(nsid);
21d34711
CH
617 c.features.fid = cpu_to_le32(fid);
618
d49187e9 619 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res, buffer, buflen, 0,
eb71f435 620 NVME_QID_ANY, 0, 0);
9b47f77a 621 if (ret >= 0 && result)
d49187e9 622 *result = le32_to_cpu(res.u32);
1cb3cce5 623 return ret;
21d34711
CH
624}
625
1c63dc66 626int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 627 void *buffer, size_t buflen, u32 *result)
21d34711
CH
628{
629 struct nvme_command c;
d49187e9 630 union nvme_result res;
1cb3cce5 631 int ret;
21d34711
CH
632
633 memset(&c, 0, sizeof(c));
634 c.features.opcode = nvme_admin_set_features;
21d34711
CH
635 c.features.fid = cpu_to_le32(fid);
636 c.features.dword11 = cpu_to_le32(dword11);
637
d49187e9 638 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
1a6fe74d 639 buffer, buflen, 0, NVME_QID_ANY, 0, 0);
9b47f77a 640 if (ret >= 0 && result)
d49187e9 641 *result = le32_to_cpu(res.u32);
1cb3cce5 642 return ret;
21d34711
CH
643}
644
1c63dc66 645int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log)
21d34711
CH
646{
647 struct nvme_command c = { };
648 int error;
649
650 c.common.opcode = nvme_admin_get_log_page,
651 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
652 c.common.cdw10[0] = cpu_to_le32(
653 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
654 NVME_LOG_SMART),
655
656 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
657 if (!*log)
658 return -ENOMEM;
659
660 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
661 sizeof(struct nvme_smart_log));
662 if (error)
663 kfree(*log);
664 return error;
665}
1673f1f0 666
9a0be7ab
CH
667int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
668{
669 u32 q_count = (*count - 1) | ((*count - 1) << 16);
670 u32 result;
671 int status, nr_io_queues;
672
1a6fe74d 673 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 674 &result);
f5fa90dc 675 if (status < 0)
9a0be7ab
CH
676 return status;
677
f5fa90dc
CH
678 /*
679 * Degraded controllers might return an error when setting the queue
680 * count. We still want to be able to bring them online and offer
681 * access to the admin queue, as that might be only way to fix them up.
682 */
683 if (status > 0) {
684 dev_err(ctrl->dev, "Could not set queue count (%d)\n", status);
685 *count = 0;
686 } else {
687 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
688 *count = min(*count, nr_io_queues);
689 }
690
9a0be7ab
CH
691 return 0;
692}
576d55d6 693EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 694
1673f1f0
CH
695static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
696{
697 struct nvme_user_io io;
698 struct nvme_command c;
699 unsigned length, meta_len;
700 void __user *metadata;
701
702 if (copy_from_user(&io, uio, sizeof(io)))
703 return -EFAULT;
63088ec7
KB
704 if (io.flags)
705 return -EINVAL;
1673f1f0
CH
706
707 switch (io.opcode) {
708 case nvme_cmd_write:
709 case nvme_cmd_read:
710 case nvme_cmd_compare:
711 break;
712 default:
713 return -EINVAL;
714 }
715
716 length = (io.nblocks + 1) << ns->lba_shift;
717 meta_len = (io.nblocks + 1) * ns->ms;
718 metadata = (void __user *)(uintptr_t)io.metadata;
719
720 if (ns->ext) {
721 length += meta_len;
722 meta_len = 0;
723 } else if (meta_len) {
724 if ((io.metadata & 3) || !io.metadata)
725 return -EINVAL;
726 }
727
728 memset(&c, 0, sizeof(c));
729 c.rw.opcode = io.opcode;
730 c.rw.flags = io.flags;
731 c.rw.nsid = cpu_to_le32(ns->ns_id);
732 c.rw.slba = cpu_to_le64(io.slba);
733 c.rw.length = cpu_to_le16(io.nblocks);
734 c.rw.control = cpu_to_le16(io.control);
735 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
736 c.rw.reftag = cpu_to_le32(io.reftag);
737 c.rw.apptag = cpu_to_le16(io.apptag);
738 c.rw.appmask = cpu_to_le16(io.appmask);
739
740 return __nvme_submit_user_cmd(ns->queue, &c,
741 (void __user *)(uintptr_t)io.addr, length,
742 metadata, meta_len, io.slba, NULL, 0);
743}
744
f3ca80fc 745static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH
746 struct nvme_passthru_cmd __user *ucmd)
747{
748 struct nvme_passthru_cmd cmd;
749 struct nvme_command c;
750 unsigned timeout = 0;
751 int status;
752
753 if (!capable(CAP_SYS_ADMIN))
754 return -EACCES;
755 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
756 return -EFAULT;
63088ec7
KB
757 if (cmd.flags)
758 return -EINVAL;
1673f1f0
CH
759
760 memset(&c, 0, sizeof(c));
761 c.common.opcode = cmd.opcode;
762 c.common.flags = cmd.flags;
763 c.common.nsid = cpu_to_le32(cmd.nsid);
764 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
765 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
766 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
767 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
768 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
769 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
770 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
771 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
772
773 if (cmd.timeout_ms)
774 timeout = msecs_to_jiffies(cmd.timeout_ms);
775
776 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 777 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1673f1f0
CH
778 &cmd.result, timeout);
779 if (status >= 0) {
780 if (put_user(cmd.result, &ucmd->result))
781 return -EFAULT;
782 }
783
784 return status;
785}
786
787static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
788 unsigned int cmd, unsigned long arg)
789{
790 struct nvme_ns *ns = bdev->bd_disk->private_data;
791
792 switch (cmd) {
793 case NVME_IOCTL_ID:
794 force_successful_syscall_return();
795 return ns->ns_id;
796 case NVME_IOCTL_ADMIN_CMD:
797 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
798 case NVME_IOCTL_IO_CMD:
799 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
800 case NVME_IOCTL_SUBMIT_IO:
801 return nvme_submit_io(ns, (void __user *)arg);
44907332 802#ifdef CONFIG_BLK_DEV_NVME_SCSI
1673f1f0
CH
803 case SG_GET_VERSION_NUM:
804 return nvme_sg_get_version_num((void __user *)arg);
805 case SG_IO:
806 return nvme_sg_io(ns, (void __user *)arg);
44907332 807#endif
1673f1f0 808 default:
84d4add7
MB
809#ifdef CONFIG_NVM
810 if (ns->ndev)
811 return nvme_nvm_ioctl(ns, cmd, arg);
812#endif
a98e58e5 813 if (is_sed_ioctl(cmd))
4f1244c8 814 return sed_ioctl(ns->ctrl->opal_dev, cmd,
e225c20e 815 (void __user *) arg);
1673f1f0
CH
816 return -ENOTTY;
817 }
818}
819
820#ifdef CONFIG_COMPAT
821static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
822 unsigned int cmd, unsigned long arg)
823{
824 switch (cmd) {
825 case SG_IO:
826 return -ENOIOCTLCMD;
827 }
828 return nvme_ioctl(bdev, mode, cmd, arg);
829}
830#else
831#define nvme_compat_ioctl NULL
832#endif
833
834static int nvme_open(struct block_device *bdev, fmode_t mode)
835{
836 return nvme_get_ns_from_disk(bdev->bd_disk) ? 0 : -ENXIO;
837}
838
839static void nvme_release(struct gendisk *disk, fmode_t mode)
840{
e439bb12
SG
841 struct nvme_ns *ns = disk->private_data;
842
843 module_put(ns->ctrl->ops->module);
844 nvme_put_ns(ns);
1673f1f0
CH
845}
846
847static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
848{
849 /* some standard values */
850 geo->heads = 1 << 6;
851 geo->sectors = 1 << 5;
852 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
853 return 0;
854}
855
856#ifdef CONFIG_BLK_DEV_INTEGRITY
857static void nvme_init_integrity(struct nvme_ns *ns)
858{
859 struct blk_integrity integrity;
860
fa9a89fc 861 memset(&integrity, 0, sizeof(integrity));
1673f1f0
CH
862 switch (ns->pi_type) {
863 case NVME_NS_DPS_PI_TYPE3:
864 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB
865 integrity.tag_size = sizeof(u16) + sizeof(u32);
866 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH
867 break;
868 case NVME_NS_DPS_PI_TYPE1:
869 case NVME_NS_DPS_PI_TYPE2:
870 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB
871 integrity.tag_size = sizeof(u16);
872 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH
873 break;
874 default:
875 integrity.profile = NULL;
876 break;
877 }
878 integrity.tuple_size = ns->ms;
879 blk_integrity_register(ns->disk, &integrity);
880 blk_queue_max_integrity_segments(ns->queue, 1);
881}
882#else
883static void nvme_init_integrity(struct nvme_ns *ns)
884{
885}
886#endif /* CONFIG_BLK_DEV_INTEGRITY */
887
888static void nvme_config_discard(struct nvme_ns *ns)
889{
08095e70 890 struct nvme_ctrl *ctrl = ns->ctrl;
1673f1f0 891 u32 logical_block_size = queue_logical_block_size(ns->queue);
08095e70 892
b35ba01e
CH
893 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
894 NVME_DSM_MAX_RANGES);
895
08095e70
KB
896 if (ctrl->quirks & NVME_QUIRK_DISCARD_ZEROES)
897 ns->queue->limits.discard_zeroes_data = 1;
898 else
899 ns->queue->limits.discard_zeroes_data = 0;
900
1673f1f0
CH
901 ns->queue->limits.discard_alignment = logical_block_size;
902 ns->queue->limits.discard_granularity = logical_block_size;
bd0fc288 903 blk_queue_max_discard_sectors(ns->queue, UINT_MAX);
b35ba01e 904 blk_queue_max_discard_segments(ns->queue, NVME_DSM_MAX_RANGES);
1673f1f0
CH
905 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
906}
907
ac81bfa9 908static int nvme_revalidate_ns(struct nvme_ns *ns, struct nvme_id_ns **id)
1673f1f0 909{
ac81bfa9 910 if (nvme_identify_ns(ns->ctrl, ns->ns_id, id)) {
b0b4e09c 911 dev_warn(ns->ctrl->dev, "%s: Identify failure\n", __func__);
1673f1f0
CH
912 return -ENODEV;
913 }
1673f1f0 914
ac81bfa9
MB
915 if ((*id)->ncap == 0) {
916 kfree(*id);
917 return -ENODEV;
1673f1f0
CH
918 }
919
8ef2074d 920 if (ns->ctrl->vs >= NVME_VS(1, 1, 0))
ac81bfa9 921 memcpy(ns->eui, (*id)->eui64, sizeof(ns->eui));
8ef2074d 922 if (ns->ctrl->vs >= NVME_VS(1, 2, 0))
ac81bfa9
MB
923 memcpy(ns->uuid, (*id)->nguid, sizeof(ns->uuid));
924
925 return 0;
926}
927
928static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
929{
930 struct nvme_ns *ns = disk->private_data;
931 u8 lbaf, pi_type;
932 u16 old_ms;
933 unsigned short bs;
2b9b6e86 934
1673f1f0
CH
935 old_ms = ns->ms;
936 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
937 ns->lba_shift = id->lbaf[lbaf].ds;
938 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
939 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
940
941 /*
942 * If identify namespace failed, use default 512 byte block size so
943 * block layer can use before failing read/write for 0 capacity.
944 */
945 if (ns->lba_shift == 0)
946 ns->lba_shift = 9;
947 bs = 1 << ns->lba_shift;
1673f1f0
CH
948 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
949 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
950 id->dps & NVME_NS_DPS_PI_MASK : 0;
951
952 blk_mq_freeze_queue(disk->queue);
953 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
954 ns->ms != old_ms ||
955 bs != queue_logical_block_size(disk->queue) ||
956 (ns->ms && ns->ext)))
957 blk_integrity_unregister(disk);
958
959 ns->pi_type = pi_type;
960 blk_queue_logical_block_size(ns->queue, bs);
961
4b9d5b15 962 if (ns->ms && !blk_get_integrity(disk) && !ns->ext)
1673f1f0 963 nvme_init_integrity(ns);
1673f1f0
CH
964 if (ns->ms && !(ns->ms == 8 && ns->pi_type) && !blk_get_integrity(disk))
965 set_capacity(disk, 0);
966 else
967 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
968
969 if (ns->ctrl->oncs & NVME_CTRL_ONCS_DSM)
970 nvme_config_discard(ns);
971 blk_mq_unfreeze_queue(disk->queue);
ac81bfa9 972}
1673f1f0 973
ac81bfa9
MB
974static int nvme_revalidate_disk(struct gendisk *disk)
975{
976 struct nvme_ns *ns = disk->private_data;
977 struct nvme_id_ns *id = NULL;
978 int ret;
979
980 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
981 set_capacity(disk, 0);
982 return -ENODEV;
983 }
984
985 ret = nvme_revalidate_ns(ns, &id);
986 if (ret)
987 return ret;
988
989 __nvme_revalidate_disk(disk, id);
1673f1f0 990 kfree(id);
ac81bfa9 991
1673f1f0
CH
992 return 0;
993}
994
995static char nvme_pr_type(enum pr_type type)
996{
997 switch (type) {
998 case PR_WRITE_EXCLUSIVE:
999 return 1;
1000 case PR_EXCLUSIVE_ACCESS:
1001 return 2;
1002 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1003 return 3;
1004 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1005 return 4;
1006 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1007 return 5;
1008 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1009 return 6;
1010 default:
1011 return 0;
1012 }
1013};
1014
1015static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1016 u64 key, u64 sa_key, u8 op)
1017{
1018 struct nvme_ns *ns = bdev->bd_disk->private_data;
1019 struct nvme_command c;
1020 u8 data[16] = { 0, };
1021
1022 put_unaligned_le64(key, &data[0]);
1023 put_unaligned_le64(sa_key, &data[8]);
1024
1025 memset(&c, 0, sizeof(c));
1026 c.common.opcode = op;
1027 c.common.nsid = cpu_to_le32(ns->ns_id);
1028 c.common.cdw10[0] = cpu_to_le32(cdw10);
1029
1030 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
1031}
1032
1033static int nvme_pr_register(struct block_device *bdev, u64 old,
1034 u64 new, unsigned flags)
1035{
1036 u32 cdw10;
1037
1038 if (flags & ~PR_FL_IGNORE_KEY)
1039 return -EOPNOTSUPP;
1040
1041 cdw10 = old ? 2 : 0;
1042 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1043 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1044 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1045}
1046
1047static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1048 enum pr_type type, unsigned flags)
1049{
1050 u32 cdw10;
1051
1052 if (flags & ~PR_FL_IGNORE_KEY)
1053 return -EOPNOTSUPP;
1054
1055 cdw10 = nvme_pr_type(type) << 8;
1056 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1057 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1058}
1059
1060static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1061 enum pr_type type, bool abort)
1062{
1063 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
1064 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1065}
1066
1067static int nvme_pr_clear(struct block_device *bdev, u64 key)
1068{
8c0b3915 1069 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH
1070 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1071}
1072
1073static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1074{
1075 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
1076 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1077}
1078
1079static const struct pr_ops nvme_pr_ops = {
1080 .pr_register = nvme_pr_register,
1081 .pr_reserve = nvme_pr_reserve,
1082 .pr_release = nvme_pr_release,
1083 .pr_preempt = nvme_pr_preempt,
1084 .pr_clear = nvme_pr_clear,
1085};
1086
a98e58e5 1087#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH
1088int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1089 bool send)
a98e58e5 1090{
4f1244c8 1091 struct nvme_ctrl *ctrl = data;
a98e58e5 1092 struct nvme_command cmd;
a98e58e5
SB
1093
1094 memset(&cmd, 0, sizeof(cmd));
1095 if (send)
1096 cmd.common.opcode = nvme_admin_security_send;
1097 else
1098 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5
SB
1099 cmd.common.nsid = 0;
1100 cmd.common.cdw10[0] = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1101 cmd.common.cdw10[1] = cpu_to_le32(len);
1102
1103 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
1104 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0);
1105}
1106EXPORT_SYMBOL_GPL(nvme_sec_submit);
1107#endif /* CONFIG_BLK_SED_OPAL */
1108
5bae7f73 1109static const struct block_device_operations nvme_fops = {
1673f1f0
CH
1110 .owner = THIS_MODULE,
1111 .ioctl = nvme_ioctl,
1112 .compat_ioctl = nvme_compat_ioctl,
1113 .open = nvme_open,
1114 .release = nvme_release,
1115 .getgeo = nvme_getgeo,
1116 .revalidate_disk= nvme_revalidate_disk,
1117 .pr_ops = &nvme_pr_ops,
1118};
1119
5fd4ce1b
CH
1120static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1121{
1122 unsigned long timeout =
1123 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1124 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1125 int ret;
1126
1127 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB
1128 if (csts == ~0)
1129 return -ENODEV;
5fd4ce1b
CH
1130 if ((csts & NVME_CSTS_RDY) == bit)
1131 break;
1132
1133 msleep(100);
1134 if (fatal_signal_pending(current))
1135 return -EINTR;
1136 if (time_after(jiffies, timeout)) {
1b3c47c1 1137 dev_err(ctrl->device,
5fd4ce1b
CH
1138 "Device not ready; aborting %s\n", enabled ?
1139 "initialisation" : "reset");
1140 return -ENODEV;
1141 }
1142 }
1143
1144 return ret;
1145}
1146
1147/*
1148 * If the device has been passed off to us in an enabled state, just clear
1149 * the enabled bit. The spec says we should set the 'shutdown notification
1150 * bits', but doing so may cause the device to complete commands to the
1151 * admin queue ... and we don't know what memory that might be pointing at!
1152 */
1153int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1154{
1155 int ret;
1156
1157 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1158 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1159
1160 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1161 if (ret)
1162 return ret;
54adc010 1163
b5a10c5f 1164 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP
1165 msleep(NVME_QUIRK_DELAY_AMOUNT);
1166
5fd4ce1b
CH
1167 return nvme_wait_ready(ctrl, cap, false);
1168}
576d55d6 1169EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH
1170
1171int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1172{
1173 /*
1174 * Default to a 4K page size, with the intention to update this
1175 * path in the future to accomodate architectures with differing
1176 * kernel and IO page sizes.
1177 */
1178 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1179 int ret;
1180
1181 if (page_shift < dev_page_min) {
1b3c47c1 1182 dev_err(ctrl->device,
5fd4ce1b
CH
1183 "Minimum device page size %u too large for host (%u)\n",
1184 1 << dev_page_min, 1 << page_shift);
1185 return -ENODEV;
1186 }
1187
1188 ctrl->page_size = 1 << page_shift;
1189
1190 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1191 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1192 ctrl->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1193 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1194 ctrl->ctrl_config |= NVME_CC_ENABLE;
1195
1196 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1197 if (ret)
1198 return ret;
1199 return nvme_wait_ready(ctrl, cap, true);
1200}
576d55d6 1201EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH
1202
1203int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1204{
1205 unsigned long timeout = SHUTDOWN_TIMEOUT + jiffies;
1206 u32 csts;
1207 int ret;
1208
1209 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1210 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1211
1212 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1213 if (ret)
1214 return ret;
1215
1216 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1217 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1218 break;
1219
1220 msleep(100);
1221 if (fatal_signal_pending(current))
1222 return -EINTR;
1223 if (time_after(jiffies, timeout)) {
1b3c47c1 1224 dev_err(ctrl->device,
5fd4ce1b
CH
1225 "Device shutdown incomplete; abort shutdown\n");
1226 return -ENODEV;
1227 }
1228 }
1229
1230 return ret;
1231}
576d55d6 1232EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1233
da35825d
CH
1234static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1235 struct request_queue *q)
1236{
7c88cb00
JA
1237 bool vwc = false;
1238
da35825d 1239 if (ctrl->max_hw_sectors) {
45686b61
CH
1240 u32 max_segments =
1241 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1242
da35825d 1243 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1244 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1245 }
e6282aef
KB
1246 if (ctrl->quirks & NVME_QUIRK_STRIPE_SIZE)
1247 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1248 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA
1249 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1250 vwc = true;
1251 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH
1252}
1253
7fd8930f
CH
1254/*
1255 * Initialize the cached copies of the Identify data and various controller
1256 * register in our nvme_ctrl structure. This should be called as soon as
1257 * the admin queue is fully up and running.
1258 */
1259int nvme_init_identify(struct nvme_ctrl *ctrl)
1260{
1261 struct nvme_id_ctrl *id;
1262 u64 cap;
1263 int ret, page_shift;
a229dbf6 1264 u32 max_hw_sectors;
7fd8930f 1265
f3ca80fc
CH
1266 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
1267 if (ret) {
1b3c47c1 1268 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH
1269 return ret;
1270 }
1271
7fd8930f
CH
1272 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
1273 if (ret) {
1b3c47c1 1274 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH
1275 return ret;
1276 }
1277 page_shift = NVME_CAP_MPSMIN(cap) + 12;
1278
8ef2074d 1279 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH
1280 ctrl->subsystem = NVME_CAP_NSSRC(cap);
1281
7fd8930f
CH
1282 ret = nvme_identify_ctrl(ctrl, &id);
1283 if (ret) {
1b3c47c1 1284 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH
1285 return -EIO;
1286 }
1287
8a9ae523 1288 ctrl->oacs = le16_to_cpu(id->oacs);
118472ab 1289 ctrl->vid = le16_to_cpu(id->vid);
7fd8930f 1290 ctrl->oncs = le16_to_cpup(&id->oncs);
6bf25d16 1291 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 1292 ctrl->vwc = id->vwc;
931e1c22 1293 ctrl->cntlid = le16_to_cpup(&id->cntlid);
7fd8930f
CH
1294 memcpy(ctrl->serial, id->sn, sizeof(id->sn));
1295 memcpy(ctrl->model, id->mn, sizeof(id->mn));
1296 memcpy(ctrl->firmware_rev, id->fr, sizeof(id->fr));
1297 if (id->mdts)
a229dbf6 1298 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 1299 else
a229dbf6
CH
1300 max_hw_sectors = UINT_MAX;
1301 ctrl->max_hw_sectors =
1302 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 1303
da35825d 1304 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 1305 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 1306 ctrl->kas = le16_to_cpu(id->kas);
07bfcd09
CH
1307
1308 if (ctrl->ops->is_fabrics) {
1309 ctrl->icdoff = le16_to_cpu(id->icdoff);
1310 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
1311 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
1312 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
1313
1314 /*
1315 * In fabrics we need to verify the cntlid matches the
1316 * admin connect
1317 */
1318 if (ctrl->cntlid != le16_to_cpu(id->cntlid))
1319 ret = -EINVAL;
038bd4cb
SG
1320
1321 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
1322 dev_err(ctrl->dev,
1323 "keep-alive support is mandatory for fabrics\n");
1324 ret = -EINVAL;
1325 }
07bfcd09
CH
1326 } else {
1327 ctrl->cntlid = le16_to_cpu(id->cntlid);
1328 }
da35825d 1329
7fd8930f 1330 kfree(id);
07bfcd09 1331 return ret;
7fd8930f 1332}
576d55d6 1333EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 1334
f3ca80fc 1335static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 1336{
f3ca80fc
CH
1337 struct nvme_ctrl *ctrl;
1338 int instance = iminor(inode);
1339 int ret = -ENODEV;
1673f1f0 1340
f3ca80fc
CH
1341 spin_lock(&dev_list_lock);
1342 list_for_each_entry(ctrl, &nvme_ctrl_list, node) {
1343 if (ctrl->instance != instance)
1344 continue;
1345
1346 if (!ctrl->admin_q) {
1347 ret = -EWOULDBLOCK;
1348 break;
1349 }
1350 if (!kref_get_unless_zero(&ctrl->kref))
1351 break;
1352 file->private_data = ctrl;
1353 ret = 0;
1354 break;
1355 }
1356 spin_unlock(&dev_list_lock);
1357
1358 return ret;
1673f1f0
CH
1359}
1360
f3ca80fc 1361static int nvme_dev_release(struct inode *inode, struct file *file)
1673f1f0 1362{
f3ca80fc
CH
1363 nvme_put_ctrl(file->private_data);
1364 return 0;
1365}
1366
bfd89471
CH
1367static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
1368{
1369 struct nvme_ns *ns;
1370 int ret;
1371
1372 mutex_lock(&ctrl->namespaces_mutex);
1373 if (list_empty(&ctrl->namespaces)) {
1374 ret = -ENOTTY;
1375 goto out_unlock;
1376 }
1377
1378 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
1379 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 1380 dev_warn(ctrl->device,
bfd89471
CH
1381 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
1382 ret = -EINVAL;
1383 goto out_unlock;
1384 }
1385
1b3c47c1 1386 dev_warn(ctrl->device,
bfd89471
CH
1387 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
1388 kref_get(&ns->kref);
1389 mutex_unlock(&ctrl->namespaces_mutex);
1390
1391 ret = nvme_user_cmd(ctrl, ns, argp);
1392 nvme_put_ns(ns);
1393 return ret;
1394
1395out_unlock:
1396 mutex_unlock(&ctrl->namespaces_mutex);
1397 return ret;
1398}
1399
f3ca80fc
CH
1400static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
1401 unsigned long arg)
1402{
1403 struct nvme_ctrl *ctrl = file->private_data;
1404 void __user *argp = (void __user *)arg;
f3ca80fc
CH
1405
1406 switch (cmd) {
1407 case NVME_IOCTL_ADMIN_CMD:
1408 return nvme_user_cmd(ctrl, NULL, argp);
1409 case NVME_IOCTL_IO_CMD:
bfd89471 1410 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 1411 case NVME_IOCTL_RESET:
1b3c47c1 1412 dev_warn(ctrl->device, "resetting controller\n");
f3ca80fc
CH
1413 return ctrl->ops->reset_ctrl(ctrl);
1414 case NVME_IOCTL_SUBSYS_RESET:
1415 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB
1416 case NVME_IOCTL_RESCAN:
1417 nvme_queue_scan(ctrl);
1418 return 0;
f3ca80fc
CH
1419 default:
1420 return -ENOTTY;
1421 }
1422}
1423
1424static const struct file_operations nvme_dev_fops = {
1425 .owner = THIS_MODULE,
1426 .open = nvme_dev_open,
1427 .release = nvme_dev_release,
1428 .unlocked_ioctl = nvme_dev_ioctl,
1429 .compat_ioctl = nvme_dev_ioctl,
1430};
1431
1432static ssize_t nvme_sysfs_reset(struct device *dev,
1433 struct device_attribute *attr, const char *buf,
1434 size_t count)
1435{
1436 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1437 int ret;
1438
1439 ret = ctrl->ops->reset_ctrl(ctrl);
1440 if (ret < 0)
1441 return ret;
1442 return count;
1673f1f0 1443}
f3ca80fc 1444static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 1445
9ec3bb2f
KB
1446static ssize_t nvme_sysfs_rescan(struct device *dev,
1447 struct device_attribute *attr, const char *buf,
1448 size_t count)
1449{
1450 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1451
1452 nvme_queue_scan(ctrl);
1453 return count;
1454}
1455static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
1456
118472ab
KB
1457static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
1458 char *buf)
1459{
40267efd 1460 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
118472ab
KB
1461 struct nvme_ctrl *ctrl = ns->ctrl;
1462 int serial_len = sizeof(ctrl->serial);
1463 int model_len = sizeof(ctrl->model);
1464
1465 if (memchr_inv(ns->uuid, 0, sizeof(ns->uuid)))
1466 return sprintf(buf, "eui.%16phN\n", ns->uuid);
1467
1468 if (memchr_inv(ns->eui, 0, sizeof(ns->eui)))
1469 return sprintf(buf, "eui.%8phN\n", ns->eui);
1470
1471 while (ctrl->serial[serial_len - 1] == ' ')
1472 serial_len--;
1473 while (ctrl->model[model_len - 1] == ' ')
1474 model_len--;
1475
1476 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", ctrl->vid,
1477 serial_len, ctrl->serial, model_len, ctrl->model, ns->ns_id);
1478}
1479static DEVICE_ATTR(wwid, S_IRUGO, wwid_show, NULL);
1480
2b9b6e86
KB
1481static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
1482 char *buf)
1483{
40267efd 1484 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB
1485 return sprintf(buf, "%pU\n", ns->uuid);
1486}
1487static DEVICE_ATTR(uuid, S_IRUGO, uuid_show, NULL);
1488
1489static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
1490 char *buf)
1491{
40267efd 1492 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB
1493 return sprintf(buf, "%8phd\n", ns->eui);
1494}
1495static DEVICE_ATTR(eui, S_IRUGO, eui_show, NULL);
1496
1497static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
1498 char *buf)
1499{
40267efd 1500 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB
1501 return sprintf(buf, "%d\n", ns->ns_id);
1502}
1503static DEVICE_ATTR(nsid, S_IRUGO, nsid_show, NULL);
1504
1505static struct attribute *nvme_ns_attrs[] = {
118472ab 1506 &dev_attr_wwid.attr,
2b9b6e86
KB
1507 &dev_attr_uuid.attr,
1508 &dev_attr_eui.attr,
1509 &dev_attr_nsid.attr,
1510 NULL,
1511};
1512
1a353d85 1513static umode_t nvme_ns_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB
1514 struct attribute *a, int n)
1515{
1516 struct device *dev = container_of(kobj, struct device, kobj);
40267efd 1517 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB
1518
1519 if (a == &dev_attr_uuid.attr) {
1520 if (!memchr_inv(ns->uuid, 0, sizeof(ns->uuid)))
1521 return 0;
1522 }
1523 if (a == &dev_attr_eui.attr) {
1524 if (!memchr_inv(ns->eui, 0, sizeof(ns->eui)))
1525 return 0;
1526 }
1527 return a->mode;
1528}
1529
1530static const struct attribute_group nvme_ns_attr_group = {
1531 .attrs = nvme_ns_attrs,
1a353d85 1532 .is_visible = nvme_ns_attrs_are_visible,
2b9b6e86
KB
1533};
1534
931e1c22 1535#define nvme_show_str_function(field) \
779ff756
KB
1536static ssize_t field##_show(struct device *dev, \
1537 struct device_attribute *attr, char *buf) \
1538{ \
1539 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
1540 return sprintf(buf, "%.*s\n", (int)sizeof(ctrl->field), ctrl->field); \
1541} \
1542static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
1543
931e1c22
ML
1544#define nvme_show_int_function(field) \
1545static ssize_t field##_show(struct device *dev, \
1546 struct device_attribute *attr, char *buf) \
1547{ \
1548 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
1549 return sprintf(buf, "%d\n", ctrl->field); \
1550} \
1551static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
1552
1553nvme_show_str_function(model);
1554nvme_show_str_function(serial);
1555nvme_show_str_function(firmware_rev);
1556nvme_show_int_function(cntlid);
779ff756 1557
1a353d85
ML
1558static ssize_t nvme_sysfs_delete(struct device *dev,
1559 struct device_attribute *attr, const char *buf,
1560 size_t count)
1561{
1562 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1563
1564 if (device_remove_file_self(dev, attr))
1565 ctrl->ops->delete_ctrl(ctrl);
1566 return count;
1567}
1568static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
1569
1570static ssize_t nvme_sysfs_show_transport(struct device *dev,
1571 struct device_attribute *attr,
1572 char *buf)
1573{
1574 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1575
1576 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
1577}
1578static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
1579
1580static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
1581 struct device_attribute *attr,
1582 char *buf)
1583{
1584 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1585
1586 return snprintf(buf, PAGE_SIZE, "%s\n",
1587 ctrl->ops->get_subsysnqn(ctrl));
1588}
1589static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
1590
1591static ssize_t nvme_sysfs_show_address(struct device *dev,
1592 struct device_attribute *attr,
1593 char *buf)
1594{
1595 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1596
1597 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
1598}
1599static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
1600
779ff756
KB
1601static struct attribute *nvme_dev_attrs[] = {
1602 &dev_attr_reset_controller.attr,
9ec3bb2f 1603 &dev_attr_rescan_controller.attr,
779ff756
KB
1604 &dev_attr_model.attr,
1605 &dev_attr_serial.attr,
1606 &dev_attr_firmware_rev.attr,
931e1c22 1607 &dev_attr_cntlid.attr,
1a353d85
ML
1608 &dev_attr_delete_controller.attr,
1609 &dev_attr_transport.attr,
1610 &dev_attr_subsysnqn.attr,
1611 &dev_attr_address.attr,
779ff756
KB
1612 NULL
1613};
1614
1a353d85
ML
1615#define CHECK_ATTR(ctrl, a, name) \
1616 if ((a) == &dev_attr_##name.attr && \
1617 !(ctrl)->ops->get_##name) \
1618 return 0
1619
1620static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
1621 struct attribute *a, int n)
1622{
1623 struct device *dev = container_of(kobj, struct device, kobj);
1624 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1625
1626 if (a == &dev_attr_delete_controller.attr) {
1627 if (!ctrl->ops->delete_ctrl)
1628 return 0;
1629 }
1630
1631 CHECK_ATTR(ctrl, a, subsysnqn);
1632 CHECK_ATTR(ctrl, a, address);
1633
1634 return a->mode;
1635}
1636
779ff756 1637static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML
1638 .attrs = nvme_dev_attrs,
1639 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB
1640};
1641
1642static const struct attribute_group *nvme_dev_attr_groups[] = {
1643 &nvme_dev_attrs_group,
1644 NULL,
1645};
1646
5bae7f73
CH
1647static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
1648{
1649 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
1650 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
1651
1652 return nsa->ns_id - nsb->ns_id;
1653}
1654
32f0c4af 1655static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 1656{
32f0c4af 1657 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 1658
32f0c4af 1659 mutex_lock(&ctrl->namespaces_mutex);
5bae7f73 1660 list_for_each_entry(ns, &ctrl->namespaces, list) {
32f0c4af
KB
1661 if (ns->ns_id == nsid) {
1662 kref_get(&ns->kref);
1663 ret = ns;
1664 break;
1665 }
5bae7f73
CH
1666 if (ns->ns_id > nsid)
1667 break;
1668 }
32f0c4af
KB
1669 mutex_unlock(&ctrl->namespaces_mutex);
1670 return ret;
5bae7f73
CH
1671}
1672
1673static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
1674{
1675 struct nvme_ns *ns;
1676 struct gendisk *disk;
ac81bfa9
MB
1677 struct nvme_id_ns *id;
1678 char disk_name[DISK_NAME_LEN];
5bae7f73
CH
1679 int node = dev_to_node(ctrl->dev);
1680
1681 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
1682 if (!ns)
1683 return;
1684
075790eb
KB
1685 ns->instance = ida_simple_get(&ctrl->ns_ida, 1, 0, GFP_KERNEL);
1686 if (ns->instance < 0)
1687 goto out_free_ns;
1688
5bae7f73
CH
1689 ns->queue = blk_mq_init_queue(ctrl->tagset);
1690 if (IS_ERR(ns->queue))
075790eb 1691 goto out_release_instance;
5bae7f73
CH
1692 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1693 ns->queue->queuedata = ns;
1694 ns->ctrl = ctrl;
1695
5bae7f73
CH
1696 kref_init(&ns->kref);
1697 ns->ns_id = nsid;
5bae7f73 1698 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH
1699
1700 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 1701 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73 1702
ac81bfa9 1703 sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->instance);
5bae7f73 1704
ac81bfa9
MB
1705 if (nvme_revalidate_ns(ns, &id))
1706 goto out_free_queue;
1707
3dc87dd0
MB
1708 if (nvme_nvm_ns_supported(ns, id) &&
1709 nvme_nvm_register(ns, disk_name, node)) {
1710 dev_warn(ctrl->dev, "%s: LightNVM init failure\n", __func__);
1711 goto out_free_id;
1712 }
ac81bfa9 1713
3dc87dd0
MB
1714 disk = alloc_disk_node(0, node);
1715 if (!disk)
1716 goto out_free_id;
ac81bfa9 1717
3dc87dd0
MB
1718 disk->fops = &nvme_fops;
1719 disk->private_data = ns;
1720 disk->queue = ns->queue;
1721 disk->flags = GENHD_FL_EXT_DEVT;
1722 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
1723 ns->disk = disk;
1724
1725 __nvme_revalidate_disk(disk, id);
5bae7f73 1726
32f0c4af
KB
1727 mutex_lock(&ctrl->namespaces_mutex);
1728 list_add_tail(&ns->list, &ctrl->namespaces);
1729 mutex_unlock(&ctrl->namespaces_mutex);
1730
5bae7f73 1731 kref_get(&ctrl->kref);
ac81bfa9
MB
1732
1733 kfree(id);
1734
0d52c756 1735 device_add_disk(ctrl->device, ns->disk);
2b9b6e86
KB
1736 if (sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
1737 &nvme_ns_attr_group))
1738 pr_warn("%s: failed to create sysfs group for identification\n",
1739 ns->disk->disk_name);
3dc87dd0
MB
1740 if (ns->ndev && nvme_nvm_register_sysfs(ns))
1741 pr_warn("%s: failed to register lightnvm sysfs group for identification\n",
1742 ns->disk->disk_name);
5bae7f73 1743 return;
ac81bfa9
MB
1744 out_free_id:
1745 kfree(id);
5bae7f73
CH
1746 out_free_queue:
1747 blk_cleanup_queue(ns->queue);
075790eb
KB
1748 out_release_instance:
1749 ida_simple_remove(&ctrl->ns_ida, ns->instance);
5bae7f73
CH
1750 out_free_ns:
1751 kfree(ns);
1752}
1753
1754static void nvme_ns_remove(struct nvme_ns *ns)
1755{
646017a6
KB
1756 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
1757 return;
69d3b8ac 1758
b0b4e09c 1759 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
5bae7f73
CH
1760 if (blk_get_integrity(ns->disk))
1761 blk_integrity_unregister(ns->disk);
2b9b6e86
KB
1762 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
1763 &nvme_ns_attr_group);
3dc87dd0
MB
1764 if (ns->ndev)
1765 nvme_nvm_unregister_sysfs(ns);
5bae7f73 1766 del_gendisk(ns->disk);
5bae7f73
CH
1767 blk_mq_abort_requeue_list(ns->queue);
1768 blk_cleanup_queue(ns->queue);
1769 }
32f0c4af
KB
1770
1771 mutex_lock(&ns->ctrl->namespaces_mutex);
5bae7f73 1772 list_del_init(&ns->list);
32f0c4af
KB
1773 mutex_unlock(&ns->ctrl->namespaces_mutex);
1774
5bae7f73
CH
1775 nvme_put_ns(ns);
1776}
1777
540c801c
KB
1778static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
1779{
1780 struct nvme_ns *ns;
1781
32f0c4af 1782 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 1783 if (ns) {
b0b4e09c 1784 if (ns->disk && revalidate_disk(ns->disk))
540c801c 1785 nvme_ns_remove(ns);
32f0c4af 1786 nvme_put_ns(ns);
540c801c
KB
1787 } else
1788 nvme_alloc_ns(ctrl, nsid);
1789}
1790
47b0e50a
SB
1791static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
1792 unsigned nsid)
1793{
1794 struct nvme_ns *ns, *next;
1795
1796 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
1797 if (ns->ns_id > nsid)
1798 nvme_ns_remove(ns);
1799 }
1800}
1801
540c801c
KB
1802static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
1803{
1804 struct nvme_ns *ns;
1805 __le32 *ns_list;
1806 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
1807 int ret = 0;
1808
1809 ns_list = kzalloc(0x1000, GFP_KERNEL);
1810 if (!ns_list)
1811 return -ENOMEM;
1812
1813 for (i = 0; i < num_lists; i++) {
1814 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
1815 if (ret)
47b0e50a 1816 goto free;
540c801c
KB
1817
1818 for (j = 0; j < min(nn, 1024U); j++) {
1819 nsid = le32_to_cpu(ns_list[j]);
1820 if (!nsid)
1821 goto out;
1822
1823 nvme_validate_ns(ctrl, nsid);
1824
1825 while (++prev < nsid) {
32f0c4af
KB
1826 ns = nvme_find_get_ns(ctrl, prev);
1827 if (ns) {
540c801c 1828 nvme_ns_remove(ns);
32f0c4af
KB
1829 nvme_put_ns(ns);
1830 }
540c801c
KB
1831 }
1832 }
1833 nn -= j;
1834 }
1835 out:
47b0e50a
SB
1836 nvme_remove_invalid_namespaces(ctrl, prev);
1837 free:
540c801c
KB
1838 kfree(ns_list);
1839 return ret;
1840}
1841
5955be21 1842static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 1843{
5bae7f73
CH
1844 unsigned i;
1845
540c801c
KB
1846 for (i = 1; i <= nn; i++)
1847 nvme_validate_ns(ctrl, i);
1848
47b0e50a 1849 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH
1850}
1851
5955be21 1852static void nvme_scan_work(struct work_struct *work)
5bae7f73 1853{
5955be21
CH
1854 struct nvme_ctrl *ctrl =
1855 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 1856 struct nvme_id_ctrl *id;
540c801c 1857 unsigned nn;
5bae7f73 1858
5955be21
CH
1859 if (ctrl->state != NVME_CTRL_LIVE)
1860 return;
1861
5bae7f73
CH
1862 if (nvme_identify_ctrl(ctrl, &id))
1863 return;
540c801c
KB
1864
1865 nn = le32_to_cpu(id->nn);
8ef2074d 1866 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB
1867 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
1868 if (!nvme_scan_ns_list(ctrl, nn))
1869 goto done;
1870 }
5955be21 1871 nvme_scan_ns_sequential(ctrl, nn);
540c801c 1872 done:
32f0c4af 1873 mutex_lock(&ctrl->namespaces_mutex);
540c801c 1874 list_sort(NULL, &ctrl->namespaces, ns_cmp);
69d3b8ac 1875 mutex_unlock(&ctrl->namespaces_mutex);
5bae7f73
CH
1876 kfree(id);
1877}
5955be21
CH
1878
1879void nvme_queue_scan(struct nvme_ctrl *ctrl)
1880{
1881 /*
1882 * Do not queue new scan work when a controller is reset during
1883 * removal.
1884 */
1885 if (ctrl->state == NVME_CTRL_LIVE)
1886 schedule_work(&ctrl->scan_work);
1887}
1888EXPORT_SYMBOL_GPL(nvme_queue_scan);
5bae7f73 1889
32f0c4af
KB
1890/*
1891 * This function iterates the namespace list unlocked to allow recovery from
1892 * controller failure. It is up to the caller to ensure the namespace list is
1893 * not modified by scan work while this function is executing.
1894 */
5bae7f73
CH
1895void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
1896{
1897 struct nvme_ns *ns, *next;
1898
0ff9d4e1
KB
1899 /*
1900 * The dead states indicates the controller was not gracefully
1901 * disconnected. In that case, we won't be able to flush any data while
1902 * removing the namespaces' disks; fail all the queues now to avoid
1903 * potentially having to clean up the failed sync later.
1904 */
1905 if (ctrl->state == NVME_CTRL_DEAD)
1906 nvme_kill_queues(ctrl);
1907
5bae7f73
CH
1908 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list)
1909 nvme_ns_remove(ns);
1910}
576d55d6 1911EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 1912
f866fc42
CH
1913static void nvme_async_event_work(struct work_struct *work)
1914{
1915 struct nvme_ctrl *ctrl =
1916 container_of(work, struct nvme_ctrl, async_event_work);
1917
1918 spin_lock_irq(&ctrl->lock);
1919 while (ctrl->event_limit > 0) {
1920 int aer_idx = --ctrl->event_limit;
1921
1922 spin_unlock_irq(&ctrl->lock);
1923 ctrl->ops->submit_async_event(ctrl, aer_idx);
1924 spin_lock_irq(&ctrl->lock);
1925 }
1926 spin_unlock_irq(&ctrl->lock);
1927}
1928
7bf58533
CH
1929void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
1930 union nvme_result *res)
f866fc42 1931{
7bf58533
CH
1932 u32 result = le32_to_cpu(res->u32);
1933 bool done = true;
f866fc42 1934
7bf58533
CH
1935 switch (le16_to_cpu(status) >> 1) {
1936 case NVME_SC_SUCCESS:
1937 done = false;
1938 /*FALLTHRU*/
1939 case NVME_SC_ABORT_REQ:
f866fc42
CH
1940 ++ctrl->event_limit;
1941 schedule_work(&ctrl->async_event_work);
7bf58533
CH
1942 break;
1943 default:
1944 break;
f866fc42
CH
1945 }
1946
7bf58533 1947 if (done)
f866fc42
CH
1948 return;
1949
1950 switch (result & 0xff07) {
1951 case NVME_AER_NOTICE_NS_CHANGED:
1952 dev_info(ctrl->device, "rescanning\n");
1953 nvme_queue_scan(ctrl);
1954 break;
1955 default:
1956 dev_warn(ctrl->device, "async event result %08x\n", result);
1957 }
1958}
1959EXPORT_SYMBOL_GPL(nvme_complete_async_event);
1960
1961void nvme_queue_async_events(struct nvme_ctrl *ctrl)
1962{
1963 ctrl->event_limit = NVME_NR_AERS;
1964 schedule_work(&ctrl->async_event_work);
1965}
1966EXPORT_SYMBOL_GPL(nvme_queue_async_events);
1967
f3ca80fc
CH
1968static DEFINE_IDA(nvme_instance_ida);
1969
1970static int nvme_set_instance(struct nvme_ctrl *ctrl)
1971{
1972 int instance, error;
1973
1974 do {
1975 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
1976 return -ENODEV;
1977
1978 spin_lock(&dev_list_lock);
1979 error = ida_get_new(&nvme_instance_ida, &instance);
1980 spin_unlock(&dev_list_lock);
1981 } while (error == -EAGAIN);
1982
1983 if (error)
1984 return -ENODEV;
1985
1986 ctrl->instance = instance;
1987 return 0;
1988}
1989
1990static void nvme_release_instance(struct nvme_ctrl *ctrl)
1991{
1992 spin_lock(&dev_list_lock);
1993 ida_remove(&nvme_instance_ida, ctrl->instance);
1994 spin_unlock(&dev_list_lock);
1995}
1996
53029b04 1997void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
576d55d6 1998{
f866fc42 1999 flush_work(&ctrl->async_event_work);
5955be21
CH
2000 flush_work(&ctrl->scan_work);
2001 nvme_remove_namespaces(ctrl);
2002
53029b04 2003 device_destroy(nvme_class, MKDEV(nvme_char_major, ctrl->instance));
f3ca80fc
CH
2004
2005 spin_lock(&dev_list_lock);
2006 list_del(&ctrl->node);
2007 spin_unlock(&dev_list_lock);
53029b04 2008}
576d55d6 2009EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04
KB
2010
2011static void nvme_free_ctrl(struct kref *kref)
2012{
2013 struct nvme_ctrl *ctrl = container_of(kref, struct nvme_ctrl, kref);
f3ca80fc
CH
2014
2015 put_device(ctrl->device);
2016 nvme_release_instance(ctrl);
075790eb 2017 ida_destroy(&ctrl->ns_ida);
f3ca80fc
CH
2018
2019 ctrl->ops->free_ctrl(ctrl);
2020}
2021
2022void nvme_put_ctrl(struct nvme_ctrl *ctrl)
2023{
2024 kref_put(&ctrl->kref, nvme_free_ctrl);
2025}
576d55d6 2026EXPORT_SYMBOL_GPL(nvme_put_ctrl);
f3ca80fc
CH
2027
2028/*
2029 * Initialize a NVMe controller structures. This needs to be called during
2030 * earliest initialization so that we have the initialized structured around
2031 * during probing.
2032 */
2033int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
2034 const struct nvme_ctrl_ops *ops, unsigned long quirks)
2035{
2036 int ret;
2037
bb8d261e
CH
2038 ctrl->state = NVME_CTRL_NEW;
2039 spin_lock_init(&ctrl->lock);
f3ca80fc 2040 INIT_LIST_HEAD(&ctrl->namespaces);
69d3b8ac 2041 mutex_init(&ctrl->namespaces_mutex);
f3ca80fc
CH
2042 kref_init(&ctrl->kref);
2043 ctrl->dev = dev;
2044 ctrl->ops = ops;
2045 ctrl->quirks = quirks;
5955be21 2046 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 2047 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
f3ca80fc
CH
2048
2049 ret = nvme_set_instance(ctrl);
2050 if (ret)
2051 goto out;
2052
779ff756 2053 ctrl->device = device_create_with_groups(nvme_class, ctrl->dev,
f3ca80fc 2054 MKDEV(nvme_char_major, ctrl->instance),
f4f0f63e 2055 ctrl, nvme_dev_attr_groups,
779ff756 2056 "nvme%d", ctrl->instance);
f3ca80fc
CH
2057 if (IS_ERR(ctrl->device)) {
2058 ret = PTR_ERR(ctrl->device);
2059 goto out_release_instance;
2060 }
2061 get_device(ctrl->device);
075790eb 2062 ida_init(&ctrl->ns_ida);
f3ca80fc 2063
f3ca80fc
CH
2064 spin_lock(&dev_list_lock);
2065 list_add_tail(&ctrl->node, &nvme_ctrl_list);
2066 spin_unlock(&dev_list_lock);
2067
2068 return 0;
f3ca80fc
CH
2069out_release_instance:
2070 nvme_release_instance(ctrl);
2071out:
2072 return ret;
2073}
576d55d6 2074EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 2075
69d9a99c
KB
2076/**
2077 * nvme_kill_queues(): Ends all namespace queues
2078 * @ctrl: the dead controller that needs to end
2079 *
2080 * Call this function when the driver determines it is unable to get the
2081 * controller in a state capable of servicing IO.
2082 */
2083void nvme_kill_queues(struct nvme_ctrl *ctrl)
2084{
2085 struct nvme_ns *ns;
2086
32f0c4af
KB
2087 mutex_lock(&ctrl->namespaces_mutex);
2088 list_for_each_entry(ns, &ctrl->namespaces, list) {
69d9a99c
KB
2089 /*
2090 * Revalidating a dead namespace sets capacity to 0. This will
2091 * end buffered writers dirtying pages that can't be synced.
2092 */
b0b4e09c 2093 if (ns->disk && !test_and_set_bit(NVME_NS_DEAD, &ns->flags))
69d9a99c
KB
2094 revalidate_disk(ns->disk);
2095
2096 blk_set_queue_dying(ns->queue);
2097 blk_mq_abort_requeue_list(ns->queue);
2098 blk_mq_start_stopped_hw_queues(ns->queue, true);
69d9a99c 2099 }
32f0c4af 2100 mutex_unlock(&ctrl->namespaces_mutex);
69d9a99c 2101}
237045fc 2102EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 2103
25646264 2104void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG
2105{
2106 struct nvme_ns *ns;
2107
32f0c4af 2108 mutex_lock(&ctrl->namespaces_mutex);
a6eaa884 2109 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 2110 blk_mq_quiesce_queue(ns->queue);
32f0c4af 2111 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2112}
576d55d6 2113EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 2114
25646264 2115void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG
2116{
2117 struct nvme_ns *ns;
2118
32f0c4af
KB
2119 mutex_lock(&ctrl->namespaces_mutex);
2120 list_for_each_entry(ns, &ctrl->namespaces, list) {
363c9aac
SG
2121 blk_mq_start_stopped_hw_queues(ns->queue, true);
2122 blk_mq_kick_requeue_list(ns->queue);
2123 }
32f0c4af 2124 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2125}
576d55d6 2126EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 2127
5bae7f73
CH
2128int __init nvme_core_init(void)
2129{
2130 int result;
2131
f3ca80fc
CH
2132 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
2133 &nvme_dev_fops);
2134 if (result < 0)
b09dcf58 2135 return result;
f3ca80fc
CH
2136 else if (result > 0)
2137 nvme_char_major = result;
2138
2139 nvme_class = class_create(THIS_MODULE, "nvme");
2140 if (IS_ERR(nvme_class)) {
2141 result = PTR_ERR(nvme_class);
2142 goto unregister_chrdev;
2143 }
2144
5bae7f73 2145 return 0;
f3ca80fc
CH
2146
2147 unregister_chrdev:
2148 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
f3ca80fc 2149 return result;
5bae7f73
CH
2150}
2151
2152void nvme_core_exit(void)
2153{
f3ca80fc
CH
2154 class_destroy(nvme_class);
2155 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
5bae7f73 2156}
576d55d6
ML
2157
2158MODULE_LICENSE("GPL");
2159MODULE_VERSION("1.0");
2160module_init(nvme_core_init);
2161module_exit(nvme_core_exit);